High-bandwidth memory and method for manufacturing the same.

Abstract

The present invention provides a high-bandwidth memory HBM having a structure that prevents overflowing non-conductive film (NCF) from flowing upward and downward. [Solution] The high-bandwidth memory of the present invention comprises a base die, a semiconductor stack including a plurality of core dies stacked on the base die and having a first width in the horizontal direction, a dummy die on the semiconductor stack, an insulating member between the semiconductor stack and the dummy die, and a molding material covering the semiconductor stack, the dummy die and the insulating member on the base die, wherein the dummy die includes a first portion having a second width smaller than the first width in the horizontal direction, and a second portion located on the first portion and having a third width greater than or equal to the first width in the horizontal direction.

Description

Technical Field

[0001] The present invention relates to a high-bandwidth memory and a method for manufacturing the same.

Background Art

[0002] In the field of the semiconductor industry, in accordance with the requirements for miniaturization, weight reduction of electronic devices, the semiconductor packages mounted on electronic devices are miniaturized, weight-reduced, and thinned, while pursuing high speed, multi-functionality, and large capacity. Therefore, the need for packaging technology that can store more data and transmit data at higher speeds is increasing. As such packaging technology, a high-bandwidth memory (HBM) formed by stacking a plurality of individual semiconductor chips has been developed and used.

[0003] The high-bandwidth memory HBM is manufactured by arranging a memory stack formed by stacking memory dies on a base die. In such stacking of memory dies, it is important that the memory dies have a high I / O density and be connected. When the I / O density is increased so that the electrical signal connection density becomes similar to the copper wiring density in the front end process of the semiconductor, even if the memory dies are connected in the back end process of the semiconductor, results similar to those of a single semiconductor chip made through the front end process of the semiconductor will be produced.

[0004] Thus, in order to stack memory dies coupled with a high I / O density, a hybrid bonding process is applied to the bonding between the memory dies. Hybrid bonding is a method of bonding two devices by fusing the same material of the two devices using the bonding properties of the same material. Here, "hybrid" means that two different types of bonding are performed, for example, bonding the two devices with a first type of metal-to-metal bonding and a second type of non-metal-to-non-metal bonding. However, when stacking memory dies using hybrid bonding technology, stack voids may occur at the interface between memory dies located at the top of the memory stack as a result of the accumulation of the surface topography of each memory die.

[0005] To control the occurrence of such stack voids, a dummy die with a relatively larger thickness compared to the memory die can be placed on the memory stack. Furthermore, to bond the memory stack and the dummy die, a non-conductive film (NCF) can be placed between the memory stack and the dummy die, and thermal compression (TC) bonding can be performed on the non-conductive film (NCF).

[0006] However, when performing thermocompression (TC) bonding, there is a possibility that the non-conductive film (NCF) may overflow, forming a fillet where the NCF is exposed outside the side of the memory die. Fillets formed by the downward flow of overflowed NCF may come into contact with the base die or memory die, forming an irregular interface with the molding material. This irregular interface can induce delamination between memory dies or cause crack formation, potentially making the high-bandwidth memory (HBM) structurally unstable. Furthermore, fillets formed by the upward flow of overflowed NCF may not be covered by the molding material, leading to external exposure, oxidation, or affecting the appearance of the final product and reducing its value. [Overview of the project] [Problems that the invention aims to solve]

[0007] The present invention has been made in view of the above-mentioned conventional problems, and the object of the present invention is to provide a high-bandwidth memory HBM having a structure in which overflowed non-conductive film (NCF) does not flow upward or downward. [Means for solving the problem]

[0008] A high-bandwidth memory according to one aspect of the present invention, made to achieve the above objective, comprises a base die, a semiconductor stack including a plurality of core dies stacked on the base die and having a first width in the horizontal direction, a dummy die on the semiconductor stack, an insulating member between the semiconductor stack and the dummy die, and a molding material covering the semiconductor stack, the dummy die and the insulating member on the base die, wherein the dummy die includes a first portion having a second width smaller than the first width in the horizontal direction, and a second portion located on the first portion and having a third width greater than or equal to the first width in the horizontal direction.

[0009] To achieve the above objective, another aspect of the present invention provides a high-bandwidth memory comprising: a buffer die; a memory stack including a plurality of memory dies stacked on the buffer die; a dummy structure on the memory stack; an insulating member between the memory stack and the dummy structure; and a molding material covering the memory stack, the dummy structure and the insulating member on the buffer die, wherein each side of the side of a first portion of the dummy structure is recessed horizontally with respect to a corresponding side among the sides of the plurality of memory dies, and each side of the side of a second portion on the first portion protrudes horizontally with respect to a corresponding side among the sides of the plurality of memory dies.

[0010] A high-bandwidth memory according to yet another aspect of the present invention made to achieve the above objectives comprises a base die, a semiconductor stack including a plurality of core dies and a plurality of interconnect structures, wherein the plurality of core dies and the plurality of interconnect structures are alternately stacked on the base die, an insulating member on the semiconductor stack, a dummy structure on the insulating member, and a molding material covering the semiconductor stack, the dummy structure and the insulating member on the base die, wherein each side of the dummy structure of a first structure is offset horizontally by a first length inward from the corresponding side of the plurality of core dies, and each side of the second structure on the first structure is offset by a second length outward from the corresponding side of the plurality of core dies.

[0011] A high-bandwidth memory manufacturing method according to one embodiment includes the steps of: stacking a plurality of core dies having a first width in the horizontal direction on a base die to form a semiconductor stack on the base die; attaching a dummy die to an insulating member on the semiconductor stack; and molding the semiconductor stack, the dummy die, and the insulating member on the base die with a molding material, wherein the dummy die includes a first portion having a second width smaller than the first width in the horizontal direction, and a second portion located on the first portion and having a third width greater than or equal to the first width in the horizontal direction. [Effects of the Invention]

[0012] According to the present invention, a high-bandwidth memory HBM can be provided in which a dummy die is disposed on a memory die, comprising a first portion having a second width smaller than the first width of the memory die, and a second portion disposed on the first portion having a third width larger than the first width of the memory die. Therefore, overflowing non-conductive film (NCF) is prevented from flowing downward by the memory stack first, and secondarily from flowing upward by the second portion.

[0013] Therefore, it is possible to prevent problems such as overflowed non-conductive film (NCF) flowing downwards, inducing delamination between memory dies, or generating cracks that adversely affect the internal circuitry of the base die or memory die.

[0014] Furthermore, it prevents problems such as overflowing non-conductive film (NCF) flowing upward, exposing the fillet to the outside and causing oxidation, or affecting the shape of the final product. [Brief explanation of the drawing]

[0015] [Figure 1] This is a cross-sectional view showing a first example of a high-bandwidth memory according to one embodiment. [Figure 2] Figure 1 is a plan view showing the top surface of the high-bandwidth memory. [Figure 3] This is a cross-sectional view showing a second example of a high-bandwidth memory according to one embodiment. [Figure 4] Figure 3 is a plan view showing the top surface of the high-bandwidth memory. [Figure 5] This is a cross-sectional view showing a third example of a high-bandwidth memory according to one embodiment. [Figure 6] Figure 5 is a plan view showing the top surface of the high-bandwidth memory. [Figure 7] This is a cross-sectional view shown to illustrate a method for manufacturing a first example dummy die according to one embodiment. [Figure 8]A cross-sectional view shown to explain a method of manufacturing a third example of a dummy die according to an embodiment. [Figure 9] A cross-sectional view shown to explain a method of manufacturing the high-bandwidth memory of FIG. 1. [Figure 10] A cross-sectional view shown to explain a method of manufacturing the high-bandwidth memory of FIG. 1. [Figure 11] A cross-sectional view shown to explain a method of manufacturing the high-bandwidth memory of FIG. 1. [Figure 12] A cross-sectional view shown to explain a method of manufacturing the high-bandwidth memory of FIG. 1. [Figure 13] A cross-sectional view shown to explain a method of manufacturing the high-bandwidth memory of FIG. 1. [Figure 14] A cross-sectional view shown to explain a method of manufacturing the high-bandwidth memory of FIG. 1. [Figure 15] A cross-sectional view showing a fourth example of a high-bandwidth memory according to an embodiment. [Figure 16] A cross-sectional view shown to explain a method of manufacturing the high-bandwidth memory of FIG. 15. [Figure 17] A cross-sectional view shown to explain a method of manufacturing the high-bandwidth memory of FIG. 15. [Figure 18] A cross-sectional view shown to explain a method of manufacturing the high-bandwidth memory of FIG. 15. [Figure 19] A cross-sectional view shown to explain a method of manufacturing the high-bandwidth memory of FIG. 15. [[ID=3z4]] [Figure 20] A cross-sectional view shown to explain a method of manufacturing the high-bandwidth memory of FIG. 15.

Embodiments of the Invention

[0016] Hereinafter, specific examples of embodiments for implementing the present invention will be described in detail with reference to the drawings. The present invention can be embodied in various different forms and is not limited to the embodiments described here.

[0017] In the drawings, parts that are not necessary for explaining the invention clearly have been omitted, and the same or similar components are denoted by the same reference numerals throughout the specification.

[0018] Furthermore, the dimensions and thicknesses of each component shown in the drawings are arbitrarily indicated for the sake of explanation, and the present invention is not necessarily limited to those shown.

[0019] Throughout the specification, when one part is described as being "connected" to another part, this includes not only cases where they are "directly connected" but also cases where they are "indirectly connected" through other components. Furthermore, when one part is described as "containing" a certain component, this means that, unless otherwise stated, it may contain other components rather than excluding them.

[0020] Furthermore, when a layer, membrane, region, plate, or other part is said to be "on top of" another part, this includes not only the case where it is "directly above" the other part, but also the case where the other part is in between. Conversely, when one part is said to be "directly above" another part, it means that there is no other part in between. Also, being "on top of" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" in the opposite direction of gravity.

[0021] Furthermore, throughout the specification, "on a plane" refers to a view of the subject from above, and "on a cross-section" refers to a view of a cross-section of the subject, obtained by cutting it perpendicularly, from the side.

[0022] Hereinafter, with reference to the drawings, the first to fourth examples of high-bandwidth memory (HBM) 100 (100A, 100B, 100C, 100D) and the manufacturing method of the high-bandwidth memory (HBM) 100 according to one embodiment will be described.

[0023] Figure 1 is a cross-sectional view showing a first example of a high-bandwidth memory (HBM) 100A according to one embodiment.

[0024] Referring to Figure 1, the high-bandwidth memory (HBM) 100A includes a bump structure 110, a base die (logic die, buffer die) 120, a memory stack (semiconductor stack) S, a first pad 134, an insulating member 150, a dummy die (dummy structure) 160, a second pad 161, and a molding material 170. The high-bandwidth memory (HBM) 100A is a high-performance three-dimensional (3D) stacked dynamic random-access memory (DRAM). The high-bandwidth memory (HBM) 100A has multiple memory channels through a memory stack S manufactured by vertically stacking memory dies 130, and can simultaneously achieve shorter latency and higher bandwidth compared to conventional DRAM products, reducing the total area occupied by individual DRAMs on the substrate, which is advantageous for high bandwidth relative to area, and has the advantage of reducing power consumption.

[0025] The bump structures 110 are positioned between the base die 120 and an external device. Each bump structure 110 is positioned on a corresponding wire in the wiring of the front structure 122 of the base die 120, electrically connecting the corresponding wire in the wiring of the front structure 122 of the base die 120 to the external device. Each bump structure 110 includes a bump filler 111 and a solder ball 112. In one embodiment, the bump structure 110 includes microbumps. The bump filler 111 is positioned between a corresponding wire in the wiring of the front structure 122 of the base die 120 and a solder ball 112. In one embodiment, the bump filler 111 is formed of a copper alloy or copper including silver, chromium, nickel, tin, gold, and combinations thereof. In one embodiment, the solder ball 112 includes at least one of tin, silver, lead, nickel, copper, and alloys thereof.

[0026] The base die 120 is placed between the memory stack S and the external device. The base die 120 is a buffer die. When data is exchanged between devices with different data processing speeds, processing units, and usage times, data loss may occur due to differences in data processing speed, processing unit, and usage time between each device. To prevent such loss, the base die 120 is placed between the memory die 130 and the external device, and information about data exchange between the memory die 130 and the external device is temporarily stored in the base die 120. When sending data to or receiving data from the memory die 130, the base die 120 sorts the data and then passes the data through sequentially.

[0027] The base die 120 includes a die base 121, a front side structure 122, and a first through-silicon via (TSV) 123. The die base 121 includes a front side 121F facing the bump structure 110 and a rear side 121B which is the opposite side of the front side 121F. The die base 121 is a die formed from a wafer. In one embodiment, the die base 121 includes silicon or other semiconductor material.

[0028] The front structure 122 is positioned between the die base 121 and the bump structure 110. The front structure 122 includes an active layer and a wiring layer. The active layer is positioned on the front surface of the die base 121. The active layer includes an integrated circuit structure having an integrated circuit region. In one embodiment, the integrated circuit structure includes at least one active device and a passive device. In one embodiment, the integrated circuit structure includes a gate structure, a source region, and a drain region. In one embodiment, the integrated circuit structure includes at least one transistor, a diode, a capacitor, an inductor, and a resistor. The wiring layer is positioned on the active layer. The wiring layer includes signal wiring lines, power wiring lines, contact plugs, and inter-metal dielectric (IMD).

[0029] The first through-silicon vias (TSVs) 123 are positioned within the die base 121. Each of the first through-silicon vias 123 is positioned between the wiring layer of the front structure 122 and the corresponding first bonding pad 143 in the first bonding pad 143 of the first interconnect structure 140A on the back side 121B of the die base 121. Each of the first through-silicon vias 123 electrically connects the wiring layer of the front structure 122 to the corresponding first bonding pad 143 in the first bonding pad 143 of the first interconnect structure 140A on the back side 121B of the die base 121. In one embodiment, the first through-silicon vias 123 include at least one of tungsten, aluminum, copper, and alloys thereof.

[0030] The first interconnection structure 140A is positioned between the rear surface 121B of the die base 121 and the memory stack S. The first interconnection structure 140A includes a rear silicon layer 141 on the rear surface 121B of the die base 121, a front silicon layer 142 on the front structure 132 of the memory die 130, a rear bonding pad 143 on the rear surface 121B of the die base 121, and a front bonding pad 144 on the front structure 132 of the memory die 130. The rear silicon layer 141 is directly bonded to the front silicon layer 142. The rear silicon layer 141 insulates the rear bonding pad 143. The front silicon layer 142 insulates the front bonding pad 144. In one embodiment, the rear silicon layer 141 and the front silicon layer 142 include at least one of silicon oxide and silicon nitride. In one embodiment, the rear silicon layer 141 and the front silicon layer 142 contain SiO2, SiN, or SiCN.

[0031] The rear bonding pads 143 are positioned through the rear silicon layer 141. The bonding surface level of the rear bonding pads 143 is the same as the bonding surface level of the rear silicon layer 141. The sides of the rear bonding pads 143 are surrounded and in contact with the rear silicon layer 141. Each of the rear bonding pads 143 is electrically connected to the corresponding first through-silicon via 123 in the first through-silicon via (TSV) 123. Each of the rear bonding pads 143 is directly bonded to the corresponding front bonding pad 144 in the front bonding pads 144. The front bonding pads 144 are positioned through the front silicon layer 142. The bonding surface level of the front bonding pads 144 is the same as the bonding surface level of the front silicon layer 142. The sides of the front bonding pads 144 are surrounded and in contact with the front silicon layer 142. Each of the front bonding pads 144 is electrically connected to the corresponding wiring in the wiring of the front structure 132 of the memory die 130. Direct bonding between the rear bonding pad 143 and the front bonding pads 144 enables an electrical connection between the base die 120 and the memory stack S. In one embodiment, the rear bonding pad 143 and the front bonding pad 144 include copper or a conductive material suitable for hybrid bonding.

[0032] The memory stack S is positioned on top of the base die 120. The memory stack S includes vertically stacked memory dies 130 and alternating second interconnection structures 140 with respect to the memory dies 130. Corresponding sides 130S of the memory die 130 (memory stack S) do not contact the insulating member 150. Corresponding sides 130S of the memory die 130 (memory stack S) contact the molding material 170. Although Figure 1 discloses a memory stack S containing four memory dies 130, the invention is not limited thereto, and memory stacks S containing more or fewer memory dies 130 are included in the scope of the present invention. For example, the memory stack S may contain four, eight, twelve, sixteen, or twenty memory dies 130.

[0033] The memory die (semiconductor die, core die) 130 includes a memory die base 131, a front structure 132, and a second through-silicon via (TSV) 133. The memory die 130T located at the top of the memory stack S does not include the second through-silicon via (TSV) 133. In one embodiment, the memory die 130 includes DRAM.

[0034] The memory die base 131 includes a front surface 131F facing the bump structure 110, and a rear surface 131B which is the opposite surface of the front surface 131F. The memory die base 131 is a die formed from a wafer. In one embodiment, the memory die base 131 comprises silicon or other semiconductor material.

[0035] The front structure 132 is located on the front surface 131F of the memory die base 131. The front structure 132 includes an active layer and a wiring layer. The active layer is located on the front surface of the memory die base 131. The active layer includes an integrated circuit structure having an integrated circuit region. In one embodiment, the integrated circuit structure includes at least one active device and a passive device. In one embodiment, the integrated circuit structure includes a gate structure, a source region, and a drain region. In one embodiment, the integrated circuit structure includes at least one transistor, a diode, a capacitor, an inductor, and a resistor. The wiring layer is located on the active layer. The wiring layer includes signal wiring lines, power wiring lines, contact plugs, and intermetallic dielectrics (IMDs).

[0036] The second through-silicon vias (TSVs) 133 are located within the memory die base 131. Each of the second through-silicon vias (TSVs) 133 is positioned between the wiring layer of the front structure 132 and the corresponding first bonding pad 143 in the first bonding pad 143 of the second interconnect structure 140 on the rear surface 131B of the memory die base 131. Each of the second through-silicon vias (TSVs) 133 electrically connects the wiring layer of the front structure 132 to the corresponding first bonding pad 143 in the first bonding pad 143 of the second interconnect structure 140 on the rear surface 131B of the memory die base 131. In one embodiment, the second through-silicon vias (TSVs) 133 include at least one of tungsten, aluminum, copper, and alloys thereof.

[0037] The second interconnection structures 140 are stacked alternately with the memory dies 130. Each of the second interconnection structures 140 is positioned between the rear surface 131B of the memory die base 131 of the memory die 130 and the front structure 132 of the adjacent memory die 130. Each of the second interconnection structures 140 includes a first silicon layer (rear silicon layer) 141 on the rear surface 131B of the memory die base 131, a second silicon layer (front silicon layer) 142 on the front structure 132 of the memory die 130, a first bonding pad (rear bonding pad) 143 on the rear surface 131B of the memory die base 131, and a second bonding pad (front bonding pad) 144 on the front structure 132 of the memory die 130. The first silicon layer 141 is directly bonded to the second silicon layer 142. The first silicon layer 141 surrounds and insulates the first bonding pad 143. The second silicon layer 142 surrounds and insulates the second bonding pad 144. In one embodiment, the first silicon layer 141 and the second silicon layer 142 each contain at least one of silicon oxide and silicon nitride. In one embodiment, the first silicon layer 141 and the second silicon layer 142 each contain SiO2, SiN, or SiCN.

[0038] The first bonding pads 143 are positioned through the first silicon layer 141. The bonding surface level of the first bonding pads 143 is the same as the bonding surface level of the first silicon layer 141. The sides of the first bonding pads 143 are surrounded and in contact with the first silicon layer 141. Each of the first bonding pads 143 is electrically connected to the corresponding second through-silicon via 133 in the second through-silicon via (TSV) 133. Each of the first bonding pads 143 is directly bonded to the corresponding second bonding pad 144 in the second bonding pad 144. The second bonding pads 144 are positioned through the second silicon layer 142. The bonding surface level of the second bonding pads 144 is the same as the bonding surface level of the second silicon layer 142. The sides of the second bonding pads 144 are surrounded and in contact with the second silicon layer 142. Each of the second bonding pads 144 is electrically connected to the corresponding wiring in the wiring of the memory die 130. Direct bonding between the first bonding pad 143 and the second bonding pad 144 enables electrical connection between the memory dies 130. In one embodiment, the first bonding pad 143 and the second bonding pad 144 include copper or a conductive material suitable for hybrid bonding.

[0039] The first pad 134 is positioned on the memory stack S. The first pad 134 is positioned on the memory die 130T located at the top of the memory stack S. The first pad 134 is covered by an insulating member 150. The first pad 134 is electrically isolated from other components, including the memory die 130T located at the top. The first pad 134 is thermally coupled to the memory stack S and transfers the heat generated in the memory stack S to the dummy die 160 through the insulating member 150 and the second pad 161. The first pad 134 is covered by the insulating member 150 on the memory die 130T located at the top. Each of the top and side surfaces of the first pad 134 is surrounded by the insulating member 150. In one embodiment, the first pad 134 includes a conductive material having high thermal conductivity. In one embodiment, the first pad 134 includes at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof.

[0040] The insulating member 150 is positioned between the memory stack S and the dummy die 160. The insulating member 150 surrounds and covers the first pad 134 and the second pad 161. The insulating member 150 contacts at least a portion of each side 160AS of the side 160AS of the first portion 160A of the dummy die 160. The insulating member 150 contacts at least a portion of the lower surface (second surface) 160BL of the second portion 160B of the dummy die 160. The insulating member 150 does not contact each side 160BS of the side 160BS of the second portion 160B of the dummy die 160. The insulating member 150 does not contact the corresponding side 130S within the side 130S of the memory die 130 (memory stack S).

[0041] The insulating member 150 includes a material having a high dielectric constant. The insulating member 150 is thermally connected to the memory stack S and the first pad 134 and transfers the heat generated in the memory stack S to the dummy die 160 directly or through the second pad 161. In one embodiment, the insulating member 150 includes a non-conductive film (NCF). In one embodiment, the insulating member 150 includes at least one of a thermosetting resin, a curing agent, a catalyst, a flux, a thermoplastic resin, and an inorganic filler. In one embodiment, the inorganic filler includes alumina.

[0042] The dummy die (dummy structure) 160 is placed on the memory stack S. The dummy die 160 is attached to the memory stack S by an insulating member 150. The dummy die 160 is thermally connected to the memory stack S through a first pad 134, an insulating member 150, and a second pad 161, and dissipates heat transferred from the memory stack S to the outside. In one embodiment, the dummy die 160 includes a heat dissipation structure. In one embodiment, the heat dissipation structure includes a heat slag, a heat sink, or a heat spreader. In one embodiment, the heat dissipation structure includes a conductive material having high thermal conductivity. In one embodiment, the dummy die 160 includes at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof.

[0043] The dummy die 160 includes a first part (first structure) 160A and a second part (second structure) 160B on the first part 160A. The first part 160A and the second part 160B have a single, integrated shape. The first part 160A of the dummy die 160 has a first height H1 in the vertical direction (Z direction). The second part 160B of the dummy structure has a second height H2 in the vertical direction (Z direction). In one embodiment, the ratio of the second height H2 to the first height H1 is in the range of 1:9 to 9:1.

[0044] Each side 160AS of the first part 160A is recessed horizontally (in the X and Y directions) with respect to the corresponding side 130S of the memory die 130 (memory stack S). Each side 160AS of the first part 160A is offset inward horizontally (in the X and Y directions) (OS1) from the corresponding side 130S of the memory die 130 (memory stack S). At least a portion of each side 160AS of the first part 160A is covered by an insulating member 150.

[0045] Each side 160BS of the second part 160B protrudes horizontally (in the X and Y directions) with respect to the corresponding side 130S within the side 130S of the memory die 130 (memory stack S). Each side 160BS of the second part 160B is offset outward horizontally (in the X and Y directions) (OS2) from the corresponding side 130S within the side 130S of the memory die 130 (memory stack S). Each side 160BS of the second part 160B is not entirely in contact with the insulating member 150, but is in contact with the molding material 170. The second portion 160B includes a first surface 160BU that is exposed to the outside from the molding material 170, and a second surface 160BL that is opposite to the first surface 160BU and extends between the side surface 160AS of the first portion 160A and the side surface 160BS of the second portion 160B. At least a portion of the second surface 160BL is in contact with the insulating member 150.

[0046] The second pad 161 is positioned on the surface of the dummy die 160 facing the memory stack S. The second pad 161 is covered by an insulating member 150. The second pad 161 is electrically isolated from the first pad 134 and the dummy die 160, as well as other components. The second pad 161 is separated from the first pad 134. The second pad 161 is thermally connected to the memory stack S through the first pad 134 and the insulating member 150, and transfers the heat generated in the memory stack S to the dummy die 160. Each of the lower and side surfaces of the second pad 161 is surrounded by the insulating member 150. In one embodiment, the second pad 161 includes a conductive material having high thermal conductivity. In one embodiment, the second pad 161 includes at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof.

[0047] The molding material 170 covers the memory stack S, the insulating member 150, and the dummy die 160 on the base die 120. The first surface 160BU of the dummy die 160 is exposed from the molding material 170 and is at the same level as the upper surface of the molding material 170.

[0048] Figure 2 is a plan view showing the top surface of the high-bandwidth memory (HBM) 100A shown in Figure 1.

[0049] Referring to Figure 2, the memory die 130 has a first width W1 in the horizontal direction (X and Y directions). The first part 160A of the dummy die 160 has a second width W2 in the horizontal direction (X and Y directions). The second part 160B of the dummy die 160 has a third width W3 in the horizontal direction (X and Y directions). The second width W2 is smaller than the first width W1. The third width W3 is larger than the first width W1. The first part 160A of the dummy die 160 completely overlaps the memory stack S or the memory die 130 in the vertical direction (Z direction). The footprint of the first part 160A of the dummy die 160 is included in the footprint of the memory stack S or the footprint of the memory die 130. The memory stack S or the memory die 130 completely overlaps the second part 160B of the dummy die 160 in the vertical direction (Z direction). The footprint of the memory stack S or the footprint of the memory die 130 is included in the footprint of the second part 160B of the dummy die 160.

[0050] Each side 160AS of the first portion 160A is offset horizontally (in the X and Y directions) by a first distance L1 from the corresponding side 130S within the side 130S of the memory die 130 (memory stack S). In one embodiment, the first distance L1 ranges from about 0.5 mm to about 1.3 mm. Each side 160BS of the second portion 160B is offset horizontally (in the X and Y directions) by a second length L2 from the corresponding side 130S within the side 130S of the memory die 130 (memory stack S). In one embodiment, the second length L2 ranges from about 0.5 mm to about 1.3 mm.

[0051] Figure 3 is a cross-sectional view showing a second example of a high-bandwidth memory (HBM) 100B according to one embodiment. Figure 4 is a plan view showing the top surface of the high-bandwidth memory (HBM) 100B of Figure 3.

[0052] Referring to Figures 3 and 4, each side 160AS of the first part 160A of the dummy die 160 is recessed horizontally (in the X and Y directions) with respect to the corresponding side 130S of the memory die 130 (memory stack S). Each side 160AS of the first part 160A is offset horizontally (in the X and Y directions) inward (OS) from the corresponding side 130S of the memory die 130 (memory stack S). Each side 160BS of the second part 160B of the dummy die 160 is in the same position as the corresponding side 130S of the memory die 130 (memory stack S).

[0053] The memory die 130 has a first width W1 in the horizontal direction (X and Y directions). The first portion 160A of the dummy die 160 has a second width W2 in the horizontal direction (X and Y directions). The second portion 160B of the dummy die 160 has a third width W3 in the horizontal direction (X and Y directions). The second width W2 is smaller than the first width W1. The third width W3 is the same as the first width W1. The first portion 160A of the dummy die 160 completely overlaps the memory stack S or the memory die 130 in the vertical direction (Z direction). The footprint of the first portion 160A of the dummy die 160 is included in the footprint of the memory stack S or the footprint of the memory die 130. The memory stack S or the memory die 130 completely overlaps or coincides with the second portion 160B of the dummy die 160 in the vertical direction (Z direction). The footprint of the memory stack S or the footprint of the memory die 130 is included in or matches the footprint of the second portion 160B of the dummy die 160.

[0054] Each side 160AS of the first part 160A is offset horizontally (in the X and Y directions) by a first distance L1 from the corresponding side 130S of the memory die 130 (memory stack S). In one embodiment, the first distance L1 ranges from about 0.5 mm to about 1.3 mm. Each side 160BS of the second part 160B coincides with the corresponding side 130S of the memory die 130 (memory stack S).

[0055] Except for the details described for the high-bandwidth memory (HBM) 100B according to one embodiment shown in Figures 3 and 4 above, the details described for the high-bandwidth memory (HBM) 100A shown in Figures 1 and 2 can be applied.

[0056] Figure 5 is a cross-sectional view showing a third example of a high-bandwidth memory (HBM) 100C according to one embodiment. Figure 6 is a plan view showing the top surface of the high-bandwidth memory (HBM) 100C of Figure 5.

[0057] Referring to Figures 5 and 6, each side 160AS of the side 160AS of the first portion 160A of the dummy die 160 is recessed horizontally (in the X and Y directions) with respect to the corresponding side 130S of the side 130S of the memory die 130 (memory stack S). Each side 160AS of the side 160AS of the first portion 160A has a profile that slopes from the lower surface 160A1 of the first portion 160A toward the interface surface 160A2 between the first portion 160A and the second portion 160B. The offset length of each side 160AS of the side 160AS of the first portion 160A, which is offset inward in the horizontal direction (X and Y directions) from the corresponding side 130S within the side 130S of the memory die 130 (memory stack S), decreases from the lower surface 160A1 of the first portion 160A toward the interface surface 160A2 between the first portion 160A and the second portion 160B.

[0058] The memory die 130 has a first width W1 in the horizontal direction (X and Y directions). The first part 160A of the dummy die 160 has a second width W2 in the horizontal direction (X and Y directions). The second part 160B of the dummy die 160 has a third width W3 in the horizontal direction (X and Y directions). The second width W2 is smaller than the first width W1. The second width W2 increases as the distance from the memory stack S increases. The third width W3 is larger than the first width W1. Figure 5 shows that the second width W2 increases as the distance from the memory stack S increases, but the invention is not limited to this. In one embodiment, the second width W2 of the first portion 160A of the dummy die 160 may decrease as the distance from the memory stack S increases, or the second width W2 may decrease as the distance from the memory stack S increases and then increase again, or the second width W2 may increase as the distance from the memory stack S increases and then decrease again, and combinations thereof are included within the scope of the present invention.

[0059] Each side 160AS of the side 160AS of the first portion 160A is offset horizontally (in the X and Y directions) inward by a first distance L1 from the corresponding side 130S of the side 130S of the memory die 130 (memory stack S). The first distance L1 decreases from the lower surface 160A1 of the first portion 160A toward the interface 160A2 between the first portion 160A and the second portion 160B. The first distance L1 increases from the lower surface 160A1 of the first portion 160A toward the interface 160A2 between the first portion 160A and the second portion 160B. In one embodiment, the first distance L1 has a range of about 0.5 mm to about 1.3 mm. Each side 160BS of the side 160BS of the second portion 160B is offset outward horizontally (in the X and Y directions) by a second length L2 from the corresponding side 130S of the side 130S of the memory die 130 (memory stack S). In one embodiment, the second length L2 is in the range of about 0.5 mm to about 1.3 mm.

[0060] Except for the details described for the high-bandwidth memory (HBM) 100C according to one embodiment shown in Figures 5 and 6 above, the details described for the high-bandwidth memory (HBM) 100A shown in Figures 1 and 2 can be applied.

[0061] Figure 7 is a cross-sectional view illustrating a method for manufacturing a first example dummy die 160 according to one embodiment of Figure 1. The method for manufacturing the dummy die 160 of Figure 1, as shown in Figure 7, can also be applied to the method for manufacturing the dummy die 160 of Figure 3.

[0062] Referring to Figure 7(A), a dummy wafer (dummy panel) 160W is provided, and a first singulation process 220 is performed on the dummy wafer 160W. The first singulation process 220 is not performed over the entire vertical direction (Z direction) of the dummy wafer 160W, but only on a portion of the vertical direction (Z direction). In one embodiment, the first singulation process 220 is performed using a saw blade or a laser. After the first singulation process 220, a recess (RC) is formed on the dummy wafer 160W.

[0063] Referring to Figure 7(B), a second singulation step 221 is performed on the dummy wafer 160W to form an opening (OP). The opening (OP) formed by the second singulation step 221 has a width smaller than the width of the recess (RC) in the horizontal direction (X direction and Y direction) of the recess (RC) of the dummy wafer 160W. In one embodiment, the second singulation step 221 is performed using a saw blade or a laser. After the second singulation step 221, the dummy wafer 160W is separated into dummy dies 160. Each dummy die 160 has a shape in which a first portion 160A having a second width W2 smaller than the first width W1 of the memory die 130 and a second portion 160B having a third width W3 larger than the first width W1 of the memory die 130 are integrally formed.

[0064] Figure 8 is a cross-sectional view illustrating a method for manufacturing a third example dummy die 160 according to one embodiment of Figure 5.

[0065] Referring to Figure 8(A), a dummy wafer (dummy panel) 160W is provided, and a first singulation process 220 is performed on the dummy wafer 160W. The first singulation process 220 forms a recess (RC) having an inclined side surface on the dummy wafer 160W. The first singulation process 220 is not performed over the entire vertical direction (Z direction) of the dummy wafer 160W, but only on a portion of the vertical direction (Z direction). In one embodiment, the first singulation process 220 is performed using a saw blade or a laser.

[0066] Referring to Figure 8(B), a second singulation step 221 is performed on the dummy wafer 160W to form an opening (OP). The opening (OP) formed by the second singulation step 221 has a width smaller than the width of the recess (RC) in the horizontal direction (X and Y directions) of the recess (RC) of the dummy wafer 160W. In one embodiment, the second singulation step 221 is performed using a saw blade or a laser. After the second singulation step 221, the dummy wafer 160W is separated into dummy dies 160. Each dummy die 160 has a shape in which a first portion 160A having a second width W2 smaller than the first width W1 of the memory die 130 and a second portion 160B having a third width W3 larger than the first width W1 of the memory die 130 are integrally formed. The length of the second width W2 changes progressively in the vertical direction (Z direction).

[0067] Figures 9 to 14 are cross-sectional views illustrating the method for manufacturing the high-bandwidth memory (HBM) 100A shown in Figure 1. The method for manufacturing the high-bandwidth memory (HBM) 100A shown in Figures 9 to 14 can also be applied to the method for manufacturing the high-bandwidth memory (HBM) 100B shown in Figure 3 and the method for manufacturing the high-bandwidth memory (HBM) 100C shown in Figure 5.

[0068] Figure 9 is a cross-sectional view showing the steps of sequentially stacking memory dies 130 on the base die 120.

[0069] Referring to Figure 9, the hybrid bonding process is performed sequentially to stack the memory dies 130 onto the base die 120. The hybrid bonding process between the base die 120 and the memory die 130 will be described below. The description of the hybrid bonding process between the base die 120 and the memory die 130 can also be similarly applied to the hybrid bonding process in the process of sequentially stacking the memory dies 130.

[0070] A chemical mechanical polishing (CMP) process is performed before hybrid bonding. In one embodiment, the surface roughness of each bonding surface to be hybrid bonded is approximately 10 Å or less. Subsequently, the bonding surface of the rear silicon layer 141 of the base die 120 and the bonding surface of the front silicon layer 142 of the memory die 130 are activated. In one embodiment, the bonding surface of the rear silicon layer 141 and the bonding surface of the front silicon layer 142 are surface-treated by plasma activation. After that, the first base die 120 and the memory die 130 are aligned for hybrid bonding. Subsequently, the activated bonding surface of the rear silicon layer 141 of the base die 120 and the activated bonding surface of the front silicon layer 142 of the memory die 130 come into contact and pre-bonding is performed.

[0071] Next, the base die 120 and the memory die 130 are hybrid-bonded. First, the rear silicon layer 141 of the base die 120 and the front silicon layer 142 of the memory die 130 are bonded by treatment. The treatment strengthens the bond between the pre-bonded rear silicon layer 141 of the base die 120 and the front silicon layer 142 of the memory die 130.

[0072] Subsequently, each of the rear bonding pads 143 of the base die 120 and each of the front bonding pads 144 of the memory die 130 are bonded by annealing.

[0073] After this, the same hybrid process is performed to sequentially stack the memory dies 130.

[0074] Figure 10 is a cross-sectional view showing the step of aligning the dummy die 160 on the memory stack S.

[0075] Referring to Figure 10, the dummy dies 160 are aligned on the memory stack S. The insulating member 150 is attached to the lower surface of the dummy die 160, and the second pad 161 is surrounded by the insulating member 150.

[0076] Figure 11 is a cross-sectional view showing the step of attaching a dummy die 160 onto the memory stack S.

[0077] Referring to Figure 11, a dummy die 160 is bonded onto the memory stack S. The dummy die 160 is bonded onto the memory stack S by a thermal compression (TC) process.

[0078] Figure 11(A) shows the step in which the insulating member 150 on the lower surface of the dummy die 160 comes into contact with the memory stack S before the thermocompression bonding (TC) process. The insulating member 150 comes into contact with the memory stack S and covers the first pad 134 on the memory stack S. At this time, the insulating member 150 has a first thickness T1 in the vertical direction. The insulating member 150 is in a gel state before the thermocompression bonding (TC) process.

[0079] Figure 11(B) shows the step in which the thermocompression bonding (TC) process is initiated and heat and pressure are applied to the insulating member 150 and the dummy die 160. When heat is applied to the insulating member 150, it changes from a gel state to a liquid state. Pressure P is also applied to the dummy die 160 on the insulating member 150. Due to the pressure P applied to the liquid insulating member 150, the insulating member 150 flows out from between the memory stack S and the dummy die 160. Because the second width W2 in the horizontal direction (X and Y directions) of the first portion 160A of the dummy die 160 is smaller than the first width W1 in the horizontal direction (X and Y directions) of the memory die 130T located at the top of the memory stack S, the insulating member 150 that flows out does not flow downwards but flows upwards (see F1). Due to the pressure P applied to the liquid insulating member 150, the insulating member 150 has a second thickness T2 in the vertical direction that is smaller than the first thickness T1.

[0080] Figure 11(C) shows the steps in which a thermocompression (TC) process is carried out in succession to Figure 11(B), applying heat and pressure to the insulating member 150 and the dummy die 160. Because the third width W3 in the horizontal direction (X and Y directions) of the second part 160B of the dummy die 160 is greater than the second width W2 in the horizontal direction (X and Y directions) of the first part 160A of the dummy die 160, the insulating member 150, which flowed upward (see F1), changes direction and flows laterally (see F2).

[0081] Due to the pressure P applied to the liquid insulating member 150, the insulating member 150 has a third thickness T3 in the vertical direction that is smaller than the second thickness T2.

[0082] Figure 12 is a cross-sectional view showing the steps after the thermocompression bonding (TC) process has been completed.

[0083] Referring to Figure 12, the insulating member 150 that flowed laterally (see F2) hardens after the thermocompression (TC) process is completed, becoming a fillet. The insulating member 150 is positioned and attached between the memory stack S and the dummy die 160, protecting and insulating the first pad 134 and the second pad 161, and thermally connecting the dummy die 160 to the memory stack S.

[0084] According to the present invention, the dummy die 160 includes a first portion 160A having a second width W2 smaller than the first width W1 of the memory die 130, and a second portion 160B positioned on the first portion 160A and having a third width W3 larger than the first width W1 of the memory die 130. Therefore, in the process of performing a thermocompression bonding (TC) process to attach the dummy die 160 to the memory die 130T located at the top of the memory stack S, the insulating member 150 that overflows to the outside between the memory stack S and the dummy die 160 is prevented from flowing downward by the memory stack S first, and secondarily from flowing upward by the second portion 160B. Therefore, it is possible to prevent the conventional problem in which the overflowed insulating member 150 flows downward, inducing delamination between the memory dies 130 or generating cracks that adversely affect the internal circuits of the base die 120 or the memory die 130. Furthermore, it is possible to prevent the conventional problem of the overflowing insulating material 150 flowing upward, exposing the fillet to the outside and causing oxidation, or affecting the external shape of the final product.

[0085] Figure 13 is a cross-sectional view showing the steps of molding the memory stack S, insulating member 150, and dummy die 160 on the base die 120.

[0086] Referring to Figure 13, the memory stack S, insulating member 150, and dummy die 160 are molded on the base die 120 with molding material 170. In one embodiment, the molding process with molding material 170 includes a compression molding or transfer molding process. In one embodiment, the molding material 170 includes an epoxy molding compound (EMC).

[0087] Figure 14 is a cross-sectional view showing the step of performing a chemical mechanical polishing (CMP) process on the molding material 170.

[0088] Referring to Figure 14, a chemical mechanical polishing (CMP) process is performed to level the upper surface of the molding material 170. After the chemical mechanical polishing (CMP) process, the upper surface of the dummy die 160 is exposed, and the fillet of the insulating member 150 is not exposed to the outside.

[0089] Figure 15 is a cross-sectional view showing a fourth example of a high-bandwidth memory (HBM) 100D according to one embodiment.

[0090] Referring to Figure 15, the first interconnection structure 140A is positioned between the rear surface 121B of the die base 121 and the memory stack S. The second interconnection structures 140 are stacked alternately with the memory dies 130. Each of the second interconnection structures 140 is positioned between the rear surface 131B of the memory die base 131 of the memory die 130 and the front structure 132 of the adjacent memory die 130. The first interconnection structure 140A and the second interconnection structure 140 each include a bonding pad 145, a second bump structure 146, and an insulating member 149, respectively. With the new definition of the second bump structure 146, the bump structure 110 is named the first bump structure 110.

[0091] Each bonding pad 145 of the first interconnection structure 140A is positioned between the corresponding first through-silicon via (TSV) 123 in the first through-silicon via (TSV) 123 and the corresponding second bump structure 146 in the second bump structure 146. Each bonding pad 145 of the first interconnection structure 140A electrically connects the corresponding first through-silicon via (TSV) 123 in the first through-silicon via (TSV) 123 to the corresponding second bump structure 146 in the second bump structure 146. Each bonding pad 145 of the second interconnection structure 140A is positioned between the corresponding second through-silicon via (TSV) 133 in the second through-silicon via (TSV) 133 and the corresponding second bump structure 146 in the second bump structure 146. Each bonding pad 145 of the second interconnection structure 140 electrically connects the corresponding second through silicon via (TSV) 133 in the second through silicon via (TSV) 133 to the corresponding second bump structure 146 in the second bump structure 146. In one embodiment, the bonding pad 145 includes at least one of copper, aluminum, tungsten, nickel, gold, tin, titanium, and alloys thereof.

[0092] The second bump structure 146 is positioned between the base die 120 and the memory stack S, or between one memory die 130 and another adjacent memory die 130. Each of the second bump structures 146 is positioned between the corresponding bonding pad 145 in the bonding pad 145 and the corresponding wiring in the wiring of the front structure 132 of the memory die 130. Each of the second bump structures 146 includes a bump filler 147 and solder balls 148. In one embodiment, the second bump structure 146 includes microbumps.

[0093] Each bump filler 147 is positioned between the corresponding solder ball 148 in the solder ball 148 and the corresponding wiring in the wiring of the front structure 132 of the memory die 130. Each bump filler 147 electrically connects the corresponding wiring in the wiring of the front structure 132 of the memory die 130 to the corresponding solder ball 148 in the solder ball 148. Each solder ball 148 is positioned between the corresponding bonding pad 145 in the bonding pad 145 and the corresponding bump filler 147 in the bump filler 147. Each solder ball 148 electrically connects the corresponding bump filler 147 in the bump filler 147 to the corresponding bonding pad 145 in the bonding pad 145. In one embodiment, the bump filler 147 is formed of a copper alloy or copper, including silver, chromium, nickel, tin, gold, and combinations thereof. In one embodiment, the solder ball 148 comprises at least one of tin, silver, lead, nickel, copper, and alloys thereof.

[0094] Each of the insulating members 149 is positioned between the base die 120 and the memory stack S, or between one memory die 130 and another adjacent memory die 130. Each of the insulating members 149 insulates the bonding pad 145 and the second bump structure 146. In one embodiment, the insulating member 149 includes a conductive film (NCF).

[0095] Other than the above-mentioned details, the contents of the high-bandwidth memory (HBM) 100D in Figure 15 can be applied to the contents described for the high-bandwidth memory (HBM) 100A in Figures 1 and 2, the contents described for the high-bandwidth memory (HBM) 100B in Figures 3 and 4, the contents described for the high-bandwidth memory (HBM) 100C in Figures 5 and 6, and the contents of the method for manufacturing the dummy die 160 according to one embodiment in Figures 7 and 8.

[0096] Figures 16 to 20 are cross-sectional views illustrating the method for manufacturing the high-bandwidth memory (HBM) 100D shown in Figure 15.

[0097] Figure 16 is a cross-sectional view showing the steps of sequentially stacking memory dies 130 on the base die 120.

[0098] Referring to Figure 16, each memory die 130 is sequentially bonded on the base die 120 by a thermocompression bonding (TC) process. An insulating member 149 is attached to the lower surface of each memory die 130, and the second bump structure 146 on the lower surface of the memory die 130 is surrounded by the insulating member 149.

[0099] Through a thermocompression (TC) process, each of the second bump structures 146 is bonded to the corresponding bonding pad 145 within the bonding pad 145. The insulating member 149 is in a gel state before the thermocompression (TC) process, and during the thermocompression (TC) process, heat is applied to change it from a gel state to a liquid state, and finally to a hardened state.

[0100] Figure 17 is a cross-sectional view showing the step of aligning the dummy die 160 on the memory stack S.

[0101] Referring to Figure 17, the dummy die 160 is aligned on the memory stack S. The insulating member 150 is attached to the lower surface of the dummy die 160, and the second pad 161 is surrounded by the insulating member 150.

[0102] Figure 18 is a cross-sectional view showing the step of attaching a dummy die 160 onto the memory stack S.

[0103] Referring to Figure 18, the dummy die 160 is bonded to the memory stack S. The dummy die 160 is bonded to the memory stack S by a thermal compression (TC) process. The process of bonding the dummy die 160 to the memory stack S can be described using the methods explained in Figures 11(A) to 11(C) and Figure 12. The insulating member 150 is attached between the memory stack S and the dummy die 160 and surrounds the first pad 134 and the second pad 161.

[0104] Figure 19 is a cross-sectional view showing the steps of molding the memory stack S, insulating member 150, and dummy die 160 on the base die 120.

[0105] Referring to Figure 19, the memory stack S, insulating member 150, and dummy die 160 are molded on the base die 120 with molding material 170. In one embodiment, the molding process with molding material 170 includes compression molding or transfer molding. In one embodiment, the molding material 170 includes epoxy molding compound (EMC).

[0106] Figure 20 is a cross-sectional view showing the step of performing a chemical mechanical polishing (CMP) process on the molding material 170.

[0107] Referring to Figure 20, a chemical mechanical polishing (CMP) process is performed to level the upper surface of the molding material 170. After the chemical mechanical polishing (CMP) process, the upper surface of the dummy die 160 is exposed, and the fillet of the insulating member 150 is not exposed to the outside.

[0108] Although embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the embodiments described above, and can be modified and implemented in various ways without departing from the technical spirit of the present invention. [Explanation of Symbols]

[0109] 100, 100A, 100B, 100C, 100D High-bandwidth memory (HBM) 110 (1st) Bump structure 111, 147 Bump Filler 112, 148 Soldaball 120 base dies (logic dies, buffer dies) 121 Die Base Rear and front of the 121B and 121F die base. 122, 132 Front structure 123, 133 First and second through-silicon vias (TSVs) 130 Memory dies (semiconductor dies, core dies) Side view of the 130S memory die (memory stack) 130T Memory die located at the top 131 Memory die base Rear and front views of the 131B and 131F memory die bases. 134, 161 First pad 140, 140A Second and First Interconnection Structures 141, 142 1st (back), 2nd (front) silicon layer 143, 144 First (rear) and second (front) bonding pads 145 Bonding Pad 146 Second Bump Structure 149, 150 Insulating material 160 Dummy Dies (Dummy Structures) 160A, 160B 1st, 2nd part 160A1 Lower surface of the first part 160A2 Interface between the first and second parts Side views of parts 1 and 2 of 160AS and 160BS. 160BL, Part 2, Second Surface (Bottom Surface) 160BU Part 2, Side 1 160W Dummy Wafer (Dummy Panel) 170 Molding material 220, 221 First and second singulation processes CMP chemical mechanical polishing OP opening OS, OS1, OS2 offset Recessed section of RC dummy wafer S Semiconductor stack (memory stack)

Claims

1. Base die and A semiconductor stack comprising a plurality of core dies stacked on the base die and having a first width in the horizontal direction, A dummy die on the aforementioned semiconductor stack, An insulating member between the semiconductor stack and the dummy die, The base die comprises the semiconductor stack, the dummy die, and a molding material covering the insulating member, The dummy die is characterized by including a first portion having a second width smaller than the first width in the horizontal direction, and a second portion located on the first portion having a third width greater than or equal to the first width in the horizontal direction.

2. The high-bandwidth memory according to claim 1, characterized in that the first portion of the dummy die completely overlaps the semiconductor stack in the vertical direction.

3. The high-bandwidth memory according to claim 1, characterized in that the semiconductor stack completely overlaps the second portion of the dummy die in the vertical direction.

4. The high-bandwidth memory according to claim 1, characterized in that the insulating member includes a non-conductive film.

5. The insulating member includes an inorganic filler, The high-bandwidth memory according to claim 4, characterized in that the inorganic filler contains alumina.

6. The high-bandwidth memory according to claim 1, characterized in that the second width increases as the distance from the semiconductor stack increases.

7. Buffer die and A memory stack including a plurality of memory dies stacked on the buffer die, The dummy structure on the memory stack, An insulating member between the memory stack and the dummy structure, The buffer die includes the memory stack, the dummy structure, and a molding material covering the insulating member, The dummy structure is characterized in that each side of the first portion is recessed horizontally with respect to a corresponding side among the multiple memory dies, and each side of the second portion on the first portion protrudes horizontally with respect to a corresponding side among the multiple memory dies.

8. The high-bandwidth memory according to claim 7, characterized in that the insulating member is in contact with at least a portion of each side surface of the first portion.

9. The second portion of the dummy structure includes a first surface exposed to the outside from the molding material and a second surface which is the opposite surface of the first surface. The second surface extends between the side surface of the first part and the side surface of the second part, The high-bandwidth memory according to claim 7, characterized in that at least a portion of the second surface is in contact with the insulating member.

10. Base die and A semiconductor stack comprising a plurality of core dies and a plurality of interconnection structures, wherein the plurality of core dies and the plurality of interconnection structures are alternately stacked on the base die, The insulating member on the semiconductor stack, The dummy structure on the insulating member, The base die comprises the semiconductor stack, the dummy structure, and a molding material covering the insulating member, The dummy structure is characterized in that each side of the first structure is offset horizontally by a first length inward from the corresponding side of the plurality of core dies, and each side of the second structure on the first structure is offset by a second length outward from the corresponding side of the plurality of core dies.

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