Method for reducing power consumption of complementary metal-oxide-semiconductor and complementary metal-oxide-semiconductor

Abstract

A method for reducing the power consumption of a complementary metal-oxide-semiconductor and a complementary metal-oxide-semiconductor are provided, which can reduce the power consumption of CMOS with a simple structure and lower the chip temperature. [Solution] The method includes the steps of: electrically connecting the gate of an N-type metal oxide semiconductor and the gate of a P-type metal oxide semiconductor to the input voltage, and electrically connecting the source of the P-type metal oxide semiconductor to the highest voltage; electrically connecting the drain of an N-type metal oxide semiconductor and the drain of a P-type metal oxide semiconductor to each other, and electrically connecting the source of an N-type metal oxide semiconductor to the lowest voltage; and setting |VTN| + |VTP| ≥ (|VSP - VSN|) * 90%, where VTN is the cutoff voltage of the N-type metal oxide semiconductor, VTP is the cutoff voltage of the P-type metal oxide semiconductor, VSN is the source voltage of the N-type metal oxide semiconductor, and VSP is the source voltage of the P-type metal oxide semiconductor.

Description

[Technical Field]

[0001] The present invention relates to semiconductor integrated circuit elements and circuit manufacturing processes, and more particularly to a method for reducing the power consumption of complementary metal-oxide-semiconductors, which effectively suppresses the power consumed by the complementary metal-oxide-semiconductors during switching operations and lowers the chip temperature, as well as to complementary metal-oxide-semiconductors themselves. [Background technology]

[0002] To reduce the power consumption of chips, complementary metal oxide semiconductors (CMOS), particularly chips made by combining high-density transistors, have already become the mainstream for integrated circuits.

[0003] As the operating frequency of the chip increases, the power consumed by the CMOS increases with increasing frequency, based on the theory of dynamic power consumption during CMOS signal switching (changes in digital signals). Currently, CMOS power consumption is reduced by lowering the operating voltage of the chip.

[0004] A specific example is the fully rising complementary metal oxide semiconductor large capacitor load driving circuit disclosed in Patent Document 1, which utilizes two boost capacitors to improve the conversion speed of a low-voltage deep submicron CMOS ultra-large integrated circuit.

[0005] The invention described in Patent Document 1 above includes a basic part and a boost part, the basic part includes two P-type metal oxide semiconductors (PMOS) and two N-type metal oxide semiconductors (NMOS), the boost part includes two NMOS and two PMOS, the outputs of the PMOS in the boost part are connected to the NMOS and the NMOS and PMOS of the basic part respectively, and each includes a capacitor that controls and drives the NMOS of the basic part, the boost part further includes an inverter, and only one of the PMOS and NMOS conducts during each transient state. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Taiwan Patent Publication No. TW287278B Specification [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] However, the device described in Patent Document 1 above cannot control rising or falling transient states unless multiple sets of NMOS and multiple sets of PMOS are combined with each other, resulting in complex operation and an excessive number of devices, making it unsuitable for application in chips where miniaturization is a primary requirement today.

[0008] In view of this, the object of the present invention is to provide a method for reducing the power consumption of a complementary metal-oxide-semiconductor and a complementary metal-oxide-semiconductor that can effectively reduce the power consumption of a CMOS with a simple structure and lower the chip temperature. [Means for solving the problem]

[0009] To achieve the above objective, the present invention provides a method for reducing the power consumption of complementary metal oxide semiconductors, comprising the steps of: electrically connecting the gate of an N-type metal oxide semiconductor and the gate of a P-type metal oxide semiconductor to an input voltage, and electrically connecting the source of the P-type metal oxide semiconductor to the highest voltage; electrically connecting the drain of the N-type metal oxide semiconductor and the drain of the P-type metal oxide semiconductor to each other, and electrically connecting the source of the N-type metal oxide semiconductor to the lowest voltage; and setting |VTN| + |VTP| ≥ (|VSP - VSN|)* 90%, where VTN is the cutoff voltage of the N-type metal oxide semiconductor, VTP is the cutoff voltage of the P-type metal oxide semiconductor, VSN is the source voltage of the N-type metal oxide semiconductor, and VSP is the source voltage of the P-type metal oxide semiconductor.

[0010] Furthermore, the electrical connection to the highest voltage is an electrical connection to the power supply voltage, and the electrical connection to the lowest voltage is ground.

[0011] Furthermore, the process includes setting |VTN| + |VTP| = (|VSP - VSN|) * 90%.

[0012] Furthermore, the process includes changing the cutoff voltage of the N-type metal oxide semiconductor and / or changing the cutoff voltage of the P-type metal oxide semiconductor so that |VTN| + |VTP| ≥ (|VSP - VSN|) * 90%.

[0013] Furthermore, the process includes changing the gate oxide thickness of the N-type metal oxide semiconductor and / or changing the gate oxide thickness of the P-type metal oxide semiconductor, and correspondingly changing the cutoff voltage of the N-type metal oxide semiconductor and / or the P-type metal oxide semiconductor.

[0014] Furthermore, the process includes changing the channel impurity concentration of the N-type metal oxide semiconductor and / or changing the channel impurity concentration of the P-type metal oxide semiconductor, and correspondingly changing the cutoff voltage of the N-type metal oxide semiconductor and / or the P-type metal oxide semiconductor.

[0015] Furthermore, the process includes changing the substrate impurity concentration of the N-type metal oxide semiconductor and / or changing the substrate impurity concentration of the P-type metal oxide semiconductor, and correspondingly changing the cutoff voltage of the N-type metal oxide semiconductor and / or the P-type metal oxide semiconductor.

[0016] Furthermore, the process includes changing the energy level difference between the work function of the gate material of the N-type metal oxide semiconductor and the work function of the semiconductor, and / or changing the energy level difference between the work function of the gate material of the P-type metal oxide semiconductor and the work function of the semiconductor, and correspondingly changing the cutoff voltage of the N-type metal oxide semiconductor and / or the cutoff voltage of the P-type metal oxide semiconductor.

[0017] Furthermore, the process includes changing the voltage drop between the substrate voltage and source voltage of the N-type metal oxide semiconductor, and / or changing the voltage drop between the substrate voltage and source voltage of the P-type metal oxide semiconductor, thereby changing the cutoff voltage of the N-type metal oxide semiconductor and / or the P-type metal oxide semiconductor.

[0018] The complementary metal oxide semiconductor of the present invention is used in a method for reducing the power consumption of a complementary metal oxide semiconductor as described in any of the above, wherein the complementary metal oxide semiconductor comprises an N-type metal oxide semiconductor and a P-type metal oxide semiconductor, wherein the gate of the N-type metal oxide semiconductor is electrically connected to an input voltage, the source of the N-type metal oxide semiconductor is electrically connected to the lowest voltage, the gate of the P-type metal oxide semiconductor is electrically connected to the input voltage, the source of the P-type metal oxide semiconductor is electrically connected to the highest voltage, and the drain of the N-type metal oxide semiconductor and the drain of the P-type metal oxide semiconductor are electrically connected to each other. A. Changing the gate oxide thickness of the N-type metal oxide semiconductor, and / or changing the gate oxide thickness of the P-type metal oxide semiconductor. B. Changing the channel impurity concentration of the N-type metal oxide semiconductor and / or changing the channel impurity concentration of the P-type metal oxide semiconductor, C. Changing the substrate impurity concentration of the N-type metal oxide semiconductor and / or changing the substrate impurity concentration of the P-type metal oxide semiconductor, D. Changing the energy level difference between the work function of the gate material of the N-type metal oxide semiconductor and the work function of the semiconductor and / or changing the energy level difference between the work function of the gate material of the P-type metal oxide semiconductor and the work function of the semiconductor, E. Changing the voltage difference between the substrate voltage and the source voltage of the N-type metal oxide semiconductor and / or changing the voltage difference between the substrate voltage and the source voltage of the P-type metal oxide semiconductor, By at least one of the above means, change the cut-off voltage of the N-type metal oxide semiconductor and / or the cut-off voltage of the P-type metal oxide semiconductor, and further set |VTN| + |VTP| ≧ (|VSP - VSN|)*90%, where VTN is the cut-off voltage of the N-type metal oxide semiconductor, VTP is the cut-off voltage of the P-type metal oxide semiconductor, VSN is the source voltage of the N-type metal oxide semiconductor, and VSP is the source voltage of the P-type metal oxide semiconductor.

Advantages of the Invention

[0019] According to the present invention, the power consumption of the complementary metal oxide semiconductor can be significantly reduced, and the increase in chip temperature can be suppressed.

Brief Description of the Drawings

[0020] [Figure 1] It is a flowchart of a method for reducing the power consumption of a complementary metal oxide semiconductor according to an embodiment of the present invention. [Figure 2] It is Circuit Diagram 1 according to an embodiment of the present invention, showing the overall configuration of a complementary metal oxide semiconductor. [Figure 3] It is Circuit Diagram 2 according to an embodiment of the present invention, showing the static power consumption diagram of a complementary metal oxide semiconductor. [Figure 4]This is circuit diagram 3 according to an embodiment of the present invention, showing a dynamic power consumption diagram of the charge state of a complementary metal oxide semiconductor. [Figure 5] This is circuit diagram 4 according to an embodiment of the present invention, showing a dynamic power consumption diagram of the discharge state of a complementary metal oxide semiconductor. [Figure 6] Figure 1 shows the relationship between output voltage, main current, and input voltage according to an embodiment of the present invention, illustrating the situation when the cutoff voltage is 0.4 volts. [Figure 7] Figure 2 shows the relationship between output voltage, main current, and input voltage according to an embodiment of the present invention, illustrating the situation when the cutoff voltage is 0.5 volts. [Figure 8] Figure 3 shows the relationship between output voltage, main current, and input voltage according to an embodiment of the present invention, illustrating the situation when the cutoff voltage is 0.6 volts. [Modes for carrying out the invention]

[0021] Embodiments of the present invention will be described in detail below with reference to the drawings.

[0022] Figures 1 and 2 show a method for reducing the power consumption of a complementary metal-oxide-semiconductor, and the complementary metal-oxide-semiconductor itself.

[0023] In this embodiment, the complementary metal oxide semiconductor includes an N-type metal oxide semiconductor M1 and a P-type metal oxide semiconductor M2.

[0024] The gate of the N-type metal oxide semiconductor M1 is electrically connected to the input voltage VG, and the source of the N-type metal oxide semiconductor M1 is grounded.

[0025] The gate of the P-type metal oxide semiconductor M2 is electrically connected to the input voltage VG, and the source of the P-type metal oxide semiconductor M2 is electrically connected to the power supply voltage VDD.

[0026] In actual implementation, based on the overall circuit arrangement of the complementary metal-oxide-semiconductor, the source of the N-type metal-oxide-semiconductor M1 can be changed so that it is electrically connected to the lowest voltage of the entire complementary metal-oxide-semiconductor, and the source of the P-type metal-oxide-semiconductor M2 can be changed so that it is electrically connected to the highest voltage of the entire complementary metal-oxide-semiconductor.

[0027] The drains of the N-type metal oxide semiconductor M1 and the P-type metal oxide semiconductor M2 are electrically connected to each other and output an output voltage Vout, which is electrically connected to the sum of the load capacitance and parasitic capacitance, i.e., the load capacitance and parasitic capacitance C1.

[0028] In actual implementation, multiple sets of N-type metal-oxide-semiconductor elements M1, P-type metal-oxide-semiconductor elements M2, etc., can be connected in parallel to jointly form a single, more complex complementary metal-oxide-semiconductor; however, the best embodiment of the present invention involves using only one set.

[0029] Figures 3 to 5 show the power consumption of the complementary metal-oxide-semiconductor. This can be mainly divided into static power consumption (Figure 3) and dynamic power consumption (Figures 4 and 5).

[0030] Static power consumption is due to leakage current, while dynamic power consumption is related to the output of the changing charge / discharge state and the frequency switching of the circuit, forming a short-circuit current i. In the charge / discharge state, power consumption increases with increasing frequency.

[0031] Refer to Figure 2 and Table 1. Table 1 shows that, in different regions, the operation of N-type metal oxide semiconductor M1 and P-type metal oxide semiconductor M2 can be linear, saturated, or cutoff depending on the input conditions, respectively.

[0032] In Table 1, nMOS is an N-type metal oxide semiconductor M1, and pMOS is a P-type metal oxide semiconductor M2, V in The input voltages are VG and V DD The power supply voltage is VDD, V THn V is the cutoff voltage of the N-type metal oxide semiconductor M1. THpThis is the cutoff voltage of the P-type metal oxide semiconductor M2.

[0033] [Table 1]

[0034] Since the complementary metal-oxide-semiconductor has a NOT gate structure, in regions I and V, either or both of the N-type metal-oxide-semiconductor M1 and the P-type metal-oxide-semiconductor M2 are kept in a cutoff state. As a result, the current at the power supply voltage VDD consists only of the reverse saturation current between the drain and the substrate, so virtually no power is consumed in the entire circuit.

[0035] Furthermore, in areas II, III, and IV, the main current is always conducting, and in area III, the main current reaches its maximum value. The main current mentioned above is I D This refers to the current flowing from the power supply voltage VDD through the N-type metal oxide semiconductor M1 and the P-type metal oxide semiconductor M2, and is not necessarily limited to the drain current of one of them.

[0036] Therefore, in order to reduce the power consumption of complementary metal-oxide-semiconductors, it is necessary to expand regions I and V as much as possible, and to reduce regions II, III, and IV, where the main current conducts.

[0037] Since complementary metal-oxide-semiconductors generate the main current only in regions II, III, and IV, assuming a power supply voltage VDD of 1 volt, a cutoff voltage of N-type metal-oxide-semiconductor M1 of 0.5 volts, and a cutoff voltage of P-type metal-oxide-semiconductor M2 of -0.5 volts, regions II, III, and IV do not exist, and the problem of the main current causing power consumption in the complementary metal-oxide-semiconductor can be solved.

[0038] Circuit simulations were performed using LTSpice XVII under the condition that the power supply voltage VDD was 1 volt.

[0039] When the cut-off voltage of the N-type metal oxide semiconductor M1 is set to 0.4 volts and the cut-off voltage of the P-type metal oxide semiconductor M2 is set to -0.4 volts, the simulation results are as shown in Fig. 6.

[0040] When the cut-off voltage of the N-type metal oxide semiconductor M1 is set to 0.5 volts and the cut-off voltage of the P-type metal oxide semiconductor M2 is set to -0.5 volts, the simulation results are as shown in Fig. 7.

[0041] When the cut-off voltage of the N-type metal oxide semiconductor M1 is set to 0.6 volts and the cut-off voltage of the P-type metal oxide semiconductor M2 is set to -0.6 volts, the simulation results are as shown in Fig. 8.

[0042] As can be seen from Fig. 6, when the input voltage VG is between 0.4 and 0.6 volts, the generation of the main current starts, and when the input voltage VG is 0.5 volts, the main current reaches a maximum of 5μ(10 -6 )A.

[0043] As can be seen from Fig. 7, when the input voltage VG is 0.5 volts, the generation of the main current with a magnitude of 2p(10 -12 )A starts, and this 2p(10 -12 )A current is the reverse saturation current between the drain and the substrate, and the complementary metal oxide semiconductor does not generate the main current by signal switching. That is, the power consumption is almost 0.

[0044] As can be seen from Fig. 8, when the input voltage VG is between 0.4 and 0.6 volts, the magnitude of the main current is 0.5~1p(10 -12 )A, and in fact, it is also the reverse saturation current between the drain and the substrate, and the complementary metal oxide semiconductor does not generate the main current by signal switching. That is, the power consumption is almost 0.

[0045] As can be seen from the simulation results above, the power consumption of complementary metal-oxide-semiconductors can be reduced to the minimum by ensuring that 90% of the absolute value of the voltage drop between the highest voltage of the P-type metal-oxide-semiconductor M2 source and the lowest voltage of the N-type metal-oxide-semiconductor M1 source does not exceed the sum of the absolute values ​​of the cutoff voltages of the N-type metal-oxide-semiconductor M1 and the P-type metal-oxide-semiconductor M2, respectively.

[0046] Refer to Figures 1 and 2. Based on the above simulation results, a method for reducing the power consumption of the complementary metal oxide semiconductor is to prepare the complementary metal oxide semiconductor in advance, and then ensure that the sum of the absolute values ​​of the cutoff voltages of the N-type metal oxide semiconductor M1 and the P-type metal oxide semiconductor M2 is not less than 90% of the absolute value of the voltage difference between the source voltage of the N-type metal oxide semiconductor M1 and the source voltage of the P-type metal oxide semiconductor M2, preferably within the range of 90% to 110% of the absolute value of the voltage difference.

[0047] For example, assuming that the cutoff voltage of N-type metal oxide semiconductor M1 is 0.5 volts and the cutoff voltage of P-type metal oxide semiconductor M2 is -0.5 volts, the sum of the two after taking their absolute values ​​is 1 volt. In this case, the source voltages of N-type metal oxide semiconductor M1 and P-type metal oxide semiconductor M2 can be selected to be, for example, 0.3 volts, -0.7 volts, or -0.3 volts, -1.3 volts, respectively. Since both |-0.7-0.3| and |-1.3-(-0.3)| are equal to 1, the conditions for using the complementary metal oxide semiconductor in a method to reduce power consumption are met. However, these values ​​are merely examples.

[0048] This significantly reduces the power consumption of the complementary metal-oxide-semiconductor, and in particular, the situation where the equality holds, i.e., |VTN| + |VTP| = (|VSP - VSN|) * 90%, can reduce power consumption even more.

[0049] Even in the best embodiment of the present invention, the number of μm (10) in Figure 6 is small. -6 )A to the number p in Figure 8 (10 -12 Even just reducing it to A represents a difference of approximately 1 million times, and in today's society where the energy crisis is becoming increasingly serious, finding a way to reduce the power consumption of this low-power complementary metal-oxide-semiconductor is a crucial milestone.

[0050] Based on the formula for calculating the cutoff voltage of a metal oxide semiconductor, specifically by employing at least one of the following methods to change the cutoff voltage of the N-type metal oxide semiconductor M1 and / or the cutoff voltage of the P-type metal oxide semiconductor M2, it is possible to ensure that the sum of the absolute values ​​of the cutoff voltages of the N-type metal oxide semiconductor M1 and the P-type metal oxide semiconductor M2 does not fall below 90% of the absolute value of the voltage difference between the source voltage of the N-type metal oxide semiconductor M1 and the source voltage of the P-type metal oxide semiconductor M2.

[0051] The thickness of the gate oxide film of the AN-type metal oxide semiconductor M1 is changed, and / or the thickness of the gate oxide film of the P-type metal oxide semiconductor M2 is changed, and the cutoff voltage of the N-type metal oxide semiconductor M1 and / or the cutoff voltage of the P-type metal oxide semiconductor M2 are changed accordingly.

[0052] The channel impurity concentration of the BN-type metal oxide semiconductor M1 is changed, and / or the channel impurity concentration of the P-type metal oxide semiconductor M2 is changed, and the cutoff voltage of the N-type metal oxide semiconductor M1 and / or the cutoff voltage of the P-type metal oxide semiconductor M2 are changed accordingly.

[0053] The substrate impurity concentration of the CN-type metal oxide semiconductor M1 is changed, and / or the substrate impurity concentration of the P-type metal oxide semiconductor M2 is changed, and the cutoff voltage of the N-type metal oxide semiconductor M1 and / or the cutoff voltage of the P-type metal oxide semiconductor M2 are changed accordingly.

[0054] Work function (qψ) of gate material for DN-type metal oxide semiconductor M1 m) and the work function of the semiconductor (qψ s ) Energy level difference (qψ ms By changing the work function of the gate material of the P-type metal oxide semiconductor M2 and / or the work function of the semiconductor, i.e., the flatband voltage, the cutoff voltage of the N-type metal oxide semiconductor M1 and / or the cutoff voltage of the P-type metal oxide semiconductor M2 are changed accordingly.

[0055] The voltage difference between the substrate voltage and source voltage of the EN-type metal oxide semiconductor M1 is changed, and / or the voltage difference between the substrate voltage and source voltage of the P-type metal oxide semiconductor M2 is changed, thereby changing the cutoff voltage of the N-type metal oxide semiconductor M1 and / or the cutoff voltage of the P-type metal oxide semiconductor M2.

[0056] Although several embodiments of the present invention have been described above to make it easier to understand, those skilled in the art will understand that the same objectives and advantages as those of the above embodiments can be easily achieved using this description as a basis. Furthermore, those skilled in the art will understand that various changes, substitutions, and modifications can be made without departing from the spirit of the present invention. [Explanation of Symbols]

[0057] C1 Load capacity and parasitic capacity i Short-circuit current M1 N-type metal-oxide-semiconductor M2 P-type metal oxide semiconductor VDD power supply voltage VG Input Voltage Vout output voltage

Claims

1. A method for reducing the power consumption of a complementary metal-oxide-semiconductor, A step of electrically connecting the gate of an N-type metal oxide semiconductor and the gate of a P-type metal oxide semiconductor to the input voltage, and electrically connecting the source of the P-type metal oxide semiconductor to the highest voltage, The steps include electrically connecting the drain of the N-type metal oxide semiconductor and the drain of the P-type metal oxide semiconductor to each other, and electrically connecting the source of the N-type metal oxide semiconductor to the lowest voltage, The process is as follows: |VTN| + |VTP| ≥ (|VSP - VSN|) * 90%, where VTN is the cutoff voltage of the N-type metal oxide semiconductor, VTP is the cutoff voltage of the P-type metal oxide semiconductor, VSN is the source voltage of the N-type metal oxide semiconductor, and VSP is the source voltage of the P-type metal oxide semiconductor. A method for reducing the power consumption of a complementary metal-oxide-semiconductor, characterized by including [a specific element].

2. A method for reducing the power consumption of a complementary metal oxide semiconductor according to claim 1, characterized in that the electrical connection to the highest voltage is an electrical connection to the power supply voltage, and the electrical connection to the lowest voltage is to ground.

3. A method for reducing the power consumption of a complementary metal oxide film semiconductor according to claim 1, characterized by including a step of setting |VTN| + |VTP| = (|VSP - VSN|) * 90%.

4. A method for reducing the power consumption of a complementary metal oxide semiconductor according to claim 1, characterized by including a step of changing the cutoff voltage of the N-type metal oxide semiconductor and / or changing the cutoff voltage of the P-type metal oxide semiconductor so that |VTN| + |VTP| ≥ (|VSP - VSN|) * 90%.

5. A method for reducing the power consumption of a complementary metal oxide semiconductor according to claim 4, characterized by including the step of changing the gate oxide thickness of the N-type metal oxide semiconductor and / or changing the gate oxide thickness of the P-type metal oxide semiconductor, and correspondingly changing the cutoff voltage of the N-type metal oxide semiconductor and / or the cutoff voltage of the P-type metal oxide semiconductor.

6. A method for reducing the power consumption of a complementary metal oxide semiconductor according to claim 4, characterized by including the step of changing the channel impurity concentration of the N-type metal oxide semiconductor and / or changing the channel impurity concentration of the P-type metal oxide semiconductor, and / or correspondingly changing the cutoff voltage of the N-type metal oxide semiconductor and / or the cutoff voltage of the P-type metal oxide semiconductor.

7. A method for reducing the power consumption of a complementary metal oxide semiconductor according to claim 4, characterized by including the step of changing the substrate impurity concentration of the N-type metal oxide semiconductor and / or changing the substrate impurity concentration of the P-type metal oxide semiconductor, and / or correspondingly changing the cutoff voltage of the N-type metal oxide semiconductor and / or the P-type metal oxide semiconductor.

8. A method for reducing the power consumption of a complementary metal oxide semiconductor according to claim 4, characterized by including the step of changing the energy level difference between the work function of the gate material of the N-type metal oxide semiconductor and the work function of the semiconductor, and / or changing the energy level difference between the work function of the gate material of the P-type metal oxide semiconductor and the work function of the semiconductor, and correspondingly changing the cutoff voltage of the N-type metal oxide semiconductor and / or the cutoff voltage of the P-type metal oxide semiconductor.

9. A method for reducing the power consumption of a complementary metal oxide semiconductor according to claim 4, characterized by including the step of changing the voltage drop between the substrate voltage and the source voltage of the N-type metal oxide semiconductor, and / or changing the voltage drop between the substrate voltage and the source voltage of the P-type metal oxide semiconductor, and correspondingly changing the cutoff voltage of the N-type metal oxide semiconductor and / or the cutoff voltage of the P-type metal oxide semiconductor.

10. A complementary metal oxide semiconductor, used in a method for reducing the power consumption of a complementary metal oxide semiconductor according to any one of claims 1 to 9, wherein the complementary metal oxide semiconductor comprises an N-type metal oxide semiconductor and a P-type metal oxide semiconductor. The gate of the N-type metal oxide semiconductor is electrically connected to the input voltage, and the source of the N-type metal oxide semiconductor is electrically connected to the lowest voltage. The gate of the P-type metal oxide semiconductor is electrically connected to the input voltage, the source of the P-type metal oxide semiconductor is electrically connected to the highest voltage, and the drain of the N-type metal oxide semiconductor and the drain of the P-type metal oxide semiconductor are electrically connected to each other. A. Changing the gate oxide thickness of the N-type metal oxide semiconductor, and / or changing the gate oxide thickness of the P-type metal oxide semiconductor. B. Changing the channel impurity concentration of the N-type metal oxide semiconductor and / or changing the channel impurity concentration of the P-type metal oxide semiconductor. C. Changing the substrate impurity concentration of the N-type metal oxide semiconductor, and / or changing the substrate impurity concentration of the P-type metal oxide semiconductor. D. Changing the energy level difference between the work function of the gate material of the N-type metal oxide semiconductor and the work function of the semiconductor, and / or changing the energy level difference between the work function of the gate material of the P-type metal oxide semiconductor and the work function of the semiconductor. E. Changing the voltage difference between the substrate voltage and the source voltage of the N-type metal oxide semiconductor, and / or changing the voltage difference between the substrate voltage and the source voltage of the P-type metal oxide semiconductor. A complementary metal oxide semiconductor characterized in that at least one of the following means changes the cutoff voltage of the N-type metal oxide semiconductor and / or the cutoff voltage of the P-type metal oxide semiconductor, and further, |VTN| + |VTP| ≥ (|VSP - VSN|) * 90%, where VTN is the cutoff voltage of the N-type metal oxide semiconductor, VTP is the cutoff voltage of the P-type metal oxide semiconductor, VSN is the source voltage of the N-type metal oxide semiconductor, and VSP is the source voltage of the P-type metal oxide semiconductor.

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