Intermittent charging and discharging method, intermittent discharging method, and electronic circuit by intermittent charging and discharging.

Abstract

This invention provides an intermittent charging and discharging method, an electronic circuit using intermittent charging and discharging, and an intermittent discharge method. [Solution] The intermittent charging and discharging method of the present invention includes the steps of: generating multiple charging stages in the rising wavelength range of the voltage signal of the power stage circuit by charging the power stage circuit multiple times within multiple operating periods of multiple consecutive pulse waves of the charging control signal; and stopping charging to the power stage circuit within multiple non-operating periods of multiple consecutive pulse waves of the charging control signal, thereby generating a charging stop horizontal line segment or a discharge stage between two of the multiple charging stages in the voltage signal.

Description

Technical Field

[0001] The present invention relates to charging and discharging, and particularly to an intermittent charging and discharging method, an intermittent discharging method, and an electronic circuit by intermittent charging and discharging.

Background Art

[0002] In recent years, due to the evolution of science and technology and the improvement of environmental protection awareness, people's requirements for efficiency and electromagnetic interference have become increasingly high. Whether it is communication applications or energy conversion, switch control plays a very important role. Also, due to the increase in materials and labor costs, reducing the design area of products and improving technical quality have always been the goals that researchers are trying to break through.

Summary of the Invention

[0003] In response to the deficiencies of the prior art, the present invention provides an intermittent charging and discharging method including: in a first period, charging the power stage circuit multiple times within multiple operating periods of a plurality of continuous pulse waves of a charging control signal to respectively generate a plurality of first charging stages in the rising wavelength range of the voltage signal of the power stage circuit; and in the first period, stopping charging the power stage circuit within multiple non-operating periods of the plurality of continuous pulse waves of the charging control signal to generate a first charging stop horizontal line segment or a first discharging stage between two of the plurality of charging stages in the voltage signal.

Brief Description of the Drawings

[0004] [Figure 1] It is a block diagram of an electronic circuit by intermittent charging according to the first embodiment of the present invention. [Figure 2] It is a process flowchart of an intermittent charging method according to the first embodiment of the present invention. [Figure 3] It is a block diagram when adopting intermittent charging and discharging according to the second embodiment of the present invention. [Figure 4] It is a process flowchart of an intermittent discharging method according to the second embodiment of the present invention. [Figure 5]This is a circuit diagram of an electronic circuit using intermittent charging and discharging as a third embodiment of the present invention. [Figure 6] These are waveform diagrams of the main signals in the electronic circuits of the 4th to 9th embodiments of the present invention. [Figure 7] These are waveform diagrams of the main signals in the electronic circuits of the 4th to 9th embodiments of the present invention. [Figure 8] These are waveform diagrams of the main signals in the electronic circuits of the 4th to 9th embodiments of the present invention. [Figure 9] These are waveform diagrams of the main signals in the electronic circuits of the 4th to 9th embodiments of the present invention. [Figure 10] These are waveform diagrams of the main signals in the electronic circuits of the 4th to 9th embodiments of the present invention. [Figure 11] These are waveform diagrams of the main signals in the electronic circuits of the 4th to 9th embodiments of the present invention. [Figure 12] This is a circuit diagram of the control circuit for an electronic circuit using intermittent charging and discharging in the tenth embodiment of the present invention. [Figure 13] This is a waveform diagram of the charging control signal and other main signals of the electronic circuit according to the 10th embodiment of the present invention. [Figure 14] This is a waveform diagram of the discharge control signal and other main signals of the electronic circuit according to the 10th embodiment of the present invention. [Figure 15] This is a circuit diagram of an electronic circuit using intermittent charging and discharging in the 11th embodiment of the present invention. [Figure 16] This is a waveform diagram of the main signals of the electronic circuit according to the 12th embodiment of the present invention. [Modes for carrying out the invention]

[0005] The embodiments of the present invention will be described below by specific examples, and those skilled in the art will be able to understand the advantages and effects of the present invention from the disclosure herein. The present invention may be carried out or applied by other different specific embodiments, and each detail herein can be modified and changed in various ways without departing from the concept of the present invention, based on different viewpoints and applications.

[0006] Figure 1 is a block diagram of an electronic circuit for intermittent charging according to the first embodiment of the present invention, and Figure 2 is a process flowchart of the intermittent charging method according to the first embodiment of the present invention. Please refer to Figures 1 and 2. The intermittent charging method of the present invention includes intermittent charging steps S11 to S15 shown in Figure 2 and may be executed by an electronic circuit for intermittent charging according to the present invention (for example, electronic circuit 1 in Figure 1). As shown in Figure 1, electronic circuit 1 includes a control circuit 10, a charging circuit 11, and a power stage circuit 12. The control circuit 10 generates a charging control signal SCH. The charging circuit 11 is coupled to the control circuit 10 to receive the charging control signal SCH. The charging circuit 11 is further coupled to the power stage circuit 12. The control circuit 10 controls the power stage circuit 12 by the charging control signal SCH by operating during multiple switching periods. The operation of electronic circuit 1 in each switching period of the present invention will be described below with reference to Figures 1 and 2.

[0007] In step S11, the electronic circuit 1 enters the first period of the switching period (for example, the charging period P10 in Figure 6), and executes steps S12 to S15 during the first period. During the first period, the charging control signal SCH has a series of pulse waves (i.e., at least two pulse waves, for example, pulse waves P11 to P12 in Figure 6), each pulse wave including an operating period (duty-on period) (for example, operating periods DN11 to DN12 in Figure 6) and a non-operating period (duty-off period) (for example, non-operating periods DF11 to DF12 in Figure 6). In step S12, the control circuit 10 controls the charging circuit 11 to perform the first charge on the power stage circuit 12 using the charging control signal SCH. In detail, in step S12, within the first operating period of the charging control signal SCH (for example, the operating period DN11 of the pulse wave P11 in Figure 6), the control circuit 10 controls the charging circuit 11 to perform the first charge on the power stage circuit 12, thereby generating the first charging stage (for example, charging stage SU11 in Figure 6) in the rising wavelength range of the voltage signal (for example, the gate capacitor voltage signal VCg in Figure 5). In this embodiment, the power stage circuit 12 receives the above voltage signal. In step S13, the control circuit 10 controls the charging circuit 11 to stop the first charge on the power stage circuit 12 using the charging control signal SCH. In detail, in step S13, during the first non-operating period following the first operating period of the charging control signal SCH (for example, the non-operating period DF11 of the pulse wave P11 in Figure 6), the control circuit 10 controls the charging circuit 11 to stop the first charging of the power stage circuit 12, thereby generating the first charging stop horizontal line segment (for example, the charging stop horizontal line segment SH11 in Figure 6) in the voltage signal after the first charging stage.

[0008] Then, in step S14, during the second operating period following the first non-operating period of the charging control signal SCH (for example, the operating period DN12 of the pulse wave P12 in Figure 6), the control circuit 10 controls the charging circuit 11 to perform a second charge on the power stage circuit 12, thereby generating a second charging stage in the rising wavelength range of the voltage signal (for example, charging stage SU12 in Figure 6). Subsequently, in step S15, during the second non-operating period following the second operating period of the charging control signal SCH (for example, the non-operating period DF12 of the pulse wave P12 in Figure 6), the control circuit 10 controls the charging circuit 11 to stop the second charge on the power stage circuit 12, thereby generating a second charging stop horizontal line segment (for example, charging stop horizontal line segment SH12 in Figure 6) in the voltage signal after the second charging stage.

[0009] In the above embodiment, the intermittent charging method of the present invention will be explained using the first and second operating periods and the first and second non-operating periods of the charging control signal SCH in the first period as an example (i.e., the charging control signal SCH has two consecutive pulse waves as an example). If the charging control signal SCH in the first period includes three (for example, pulse waves P11 to P13 in Figure 6) or three or more consecutive pulse waves, the electronic circuit 1 can continue operations to the power stage circuit 12, performing operations similar to steps S12 and S13 (and / or steps S14 and S15) after step S15, thereby performing at least one charging operation and at least one charging stop operation. In other words, the intermittent charging method of the present invention realizes intermittent / multistage charging of the power stage circuit 12 by charging the power stage circuit 12 for a while and then stopping charging to the power stage circuit 12 during a rest period.

[0010] Conventional charging methods employ a single continuous charge, directly charging the voltage of the power stage circuit from the bottom level or initial low level to the peak level or a preset high level. However, in the present invention, the charging method for the power stage circuit 12 employs intermittent / multi-stage charging, charging the voltage signal of the power stage circuit 12 to different voltage levels during multiple charging cycles, and gradually increasing the voltage signal of the power stage circuit 12 until it reaches the peak level or a preset high level. Compared to conventional charging methods, the present invention employs an intermittent charging method, which allows the charging time length and charging rest time length (i.e., charging stop time length) of each stage to be set according to application needs, significantly improving the accuracy of charging control and allowing for more flexible control of the charging state of the power stage circuit 12.

[0011] Figure 3 is a block diagram of an electronic circuit for intermittent charging and discharging in a second embodiment of the present invention, and Figure 4 is a process flowchart of the intermittent discharging method in a second embodiment of the present invention. As shown in Figure 4, the intermittent discharging method of the present invention includes steps S21 to S25. As shown in Figure 3, in the second embodiment, the electronic circuit 3 for intermittent charging and discharging further includes a discharge circuit 13 in addition to the control circuit 10, charging circuit 11, and power stage circuit 12. Steps S21 to S25 may be performed by the control circuit 10, power stage circuit 12, and discharge circuit 13 of the electronic circuit 3. Please refer to Figure 3. The control circuit 10 further generates a discharge control signal SDG in addition to a charging control signal SCH. The discharge circuit 13 is coupled to the control circuit 10 to receive the discharge control signal SDG. The discharge circuit 13 is further coupled to the power stage circuit 12. The control circuit 10 controls the power stage circuit 12 with the charging control signal SCH and the discharge control signal SDG during multiple switching periods. The operation of the electronic circuit 3 of the present invention during the switching period will be explained below with reference to Figures 3 and 4.

[0012] In some embodiments, steps S21 to S25 follow steps S11 to S15 of the intermittent charging in Figure 2 (shown as dotted line blocks in Figure 4), and steps S11 to S15 and S21 to S25 are steps of the intermittent charge-discharge method of the present invention. The intermittent charge-discharge method of the present invention is performed by an electronic circuit for intermittent charge-discharge of the present invention (for example, electronic circuit 3 in Figure 3, electronic circuit 5 in Figure 5, or electronic circuit 15 in Figure 15).

[0013] Please refer to Figures 3 and 4. In step S21, the electronic circuit 3 enters the second period of the switching period (e.g., the discharge period P30 in Figure 6), and performs steps S22 to S25 during the second period. During the second period, the discharge control signal SDG has a series of pulse waves (i.e., at least two pulse waves, e.g., pulse waves P21 to P22 in Figure 6), each pulse wave including an operating period (e.g., operating periods DN21 to DN22 in Figure 6) and a non-operating period (e.g., non-operating periods DF21 to DF22 in Figure 6). In embodiments where steps S21 to S25 are connected to steps S11 to S15, the second period occurs after the first period on the time axis.

[0014] In step S22, the control circuit 10 controls the discharge circuit 13 to perform the first discharge to the power stage circuit 12 using the discharge control signal SDG. Specifically, in step S22, within the first operating period of the discharge control signal SDG (for example, the operating period DN21 of the pulse wave P21 in Figure 6), the control circuit 10 controls the discharge circuit 13 to perform the first discharge to the power stage circuit 12, thereby generating the first discharge stage in the falling wavelength range of the voltage signal (for example, the discharge stage SD21 in Figure 6). In step S23, the control circuit 10 controls the discharge circuit 13 to stop the first discharge to the power stage circuit 12 using the discharge control signal SDG. In detail, in step S23, during the first non-operating period following the first operating period of the discharge control signal SDG (for example, the non-operating period DF21 of the pulse wave P21 in Figure 6), the control circuit 10 controls the discharge circuit 13 to stop the first discharge to the power stage circuit 12, thereby generating the first discharge stop horizontal line segment (for example, the discharge stop horizontal line segment SH21 in Figure 6) in the voltage signal after the first discharge stage.

[0015] Then, in step S24, during the second operating period following the first non-operating period of the discharge control signal SDG (for example, the operating period DN22 of pulse wave P22 in Figure 6), the control circuit 10 controls the discharge circuit 13 to perform a second discharge on the power stage circuit 12, thereby generating a second discharge stage in the falling wavelength range of the voltage signal (for example, discharge stage SD22 in Figure 6). Subsequently, in step S25, during the second non-operating period following the second operating period of the discharge control signal SDG (for example, the non-operating period DF22 of pulse wave P22 in Figure 6), the control circuit 10 controls the discharge circuit 13 to stop the second discharge on the power stage circuit 12, thereby generating a second discharge stop horizontal line segment (for example, discharge stop horizontal line segment SH22 in Figure 6) in the voltage signal after the second discharge stage.

[0016] In the above embodiment, the first and second operating periods and the first and second non-operating periods of the discharge control signal SDG in the second period are taken as examples (that is, it is taken as an example that the discharge control signal SDG has two consecutive pulse waves), and the intermittent discharge method of the present invention is described. When the discharge control signal SDG includes three (for example, pulse waves P21 to P23 in FIG. 6) or more than three consecutive pulse waves in the second period, after step S25, the electronic circuit 3 performs operations similar to steps S22 and S23 (and / or steps S24 and S25) to continue at least one discharge operation and at least one discharge stop operation on the power stage circuit 12. However, in the intermittent discharge method of the present invention, after discharging the power stage circuit 12 for a while, the discharge of the power stage circuit 12 is stopped during the rest period, thereby realizing the intermittent / multi-stage discharge of the power stage circuit 12.

[0017] The conventional discharge method directly discharges the voltage of the power stage circuit from the peak level or the initial high level to the bottom level or a preset low level by adopting a single continuous discharge. The difference is that in the present invention, the discharge method for the power stage circuit 12 adopts an intermittent / multi-stage discharge, so that the voltage signal of the power stage circuit is discharged to different voltage levels during each discharge, and finally the voltage of the power stage circuit is gradually decreased until it drops to the bottom level or a preset low level. Compared with the conventional discharge method, the intermittent discharge method of the present invention can set the discharge time length and the discharge rest time length (that is, the time length of discharge stop) of each stage according to the application requirements, greatly improving the accuracy of discharge control and enabling more flexible control of the discharge state of the power stage circuit 12.

[0018] Compared with the conventional charge and discharge method, in the intermittent charge and discharge method of the present invention, the control circuit 10 intermittently controls the enable time of the charging circuit 11 and / or the discharging circuit 13 to accurately control the level of the voltage signal. For example, the control circuit 10 accurately controls the speed at which the voltage signal rises from the bottom level or the initial low level to the peak level or a preset high level (hereinafter referred to as the rising speed of the voltage signal), and / or the speed at which the voltage signal drops from the peak level or the initial high level to the bottom level or a preset low level (hereinafter referred to as the dropping speed of the voltage signal), so as to further control the switching speed at which the power stage circuit 12 switches to different operating states. The control circuit 10 selects an appropriate intermittent switching policy based on the characteristics such as the conduction curve and parasitic parameters of the selected power stage circuit 12 to control the rising and / or dropping speed of the voltage signal.

[0019] By simply setting the rising and / or dropping speed of the voltage signal, a relatively low-frequency constant-frequency control can be selected. Under the operation of a fixed frequency, there is relatively small noise. The frequency conversion control is suitable when there are relatively accurate requirements for the voltage level change of the voltage signal, and responds effectively and in real time through the frequency conversion operation.

[0020] Figure 5 is a circuit diagram of an electronic circuit for intermittent charging and discharging according to a third embodiment of the present invention. As shown in Figure 5, the electronic circuit 5 for intermittent charging and discharging according to the present invention includes a control circuit 10, a charging circuit 11A, a discharging circuit 13A, and a power stage circuit 12A. The control circuit 10 generates a charging control signal SCH and a discharging control signal SDG. In Figure 5, the pulse wave patterns of the charging control signal SCH and the discharging control signal SDG are schematic and are not used to limit the present invention. Comparing Figure 5 with Figure 3, the charging circuit 11A, discharging circuit 13A, and power stage circuit 12A in Figure 5 are embodiments of the charging circuit 11, discharging circuit 13, and power stage circuit 12 in Figure 3, respectively. The charging circuit 11A includes a charging-side current source circuit 110 (hereinafter referred to as "current source circuit 110") and a charging switch SW11. In this embodiment, the current source circuit 110 includes a charging-side current source CU1 (hereinafter referred to as "current source CU1"). The input terminal of the current source CU1 is coupled to the power supply voltage VCC, and its output terminal is coupled to the first terminal of the charge switch SW11. The second terminal of the charge switch SW11 is coupled to the input terminal of the power stage circuit 12A at node N10. The control terminal of the charge switch SW11 is coupled to the control circuit 10 to receive the charge control signal SCH.

[0021] The discharge circuit 13A includes a discharge-side current source circuit 130 (hereinafter referred to as "current source circuit 130") and a discharge switch SW13. In this embodiment, the current source circuit 130 includes a discharge-side current source CU2 (hereinafter referred to as "current source CU2"). The input terminal of the current source CU2 is coupled to the input terminal of the power stage circuit 12A at node N10, and its output terminal is coupled to the first terminal of the discharge switch SW13. The second terminal of the discharge switch SW13 is coupled to the ground terminal GND. The control terminal of the discharge switch SW13 is coupled to the control circuit 10 to receive the discharge control signal SDG.

[0022] Please refer to Figure 5. Power stage circuit 12A includes capacitor Cg and Power transistorsIt mainly includes M1. Depending on the system architecture in which the electronic circuit 5 is applied, the power stage circuit 12A may further include other circuit elements. For example, when the electronic circuit 5 is applied to a local interconnect network (LIN) system architecture, the power stage circuit 12A may further include an upper diode D1, a lower diode D2, resistors R1 and R2, and a capacitor C1. The first terminal of the capacitor Cg and Power transistors The control terminal of M1 is connected to the input terminal of the power stage circuit 12A at node N10, and through this input terminal of the power stage circuit 12A, it is connected to the second terminal of the charge switch SW11 and the first terminal of the current source CU2. The second terminal of capacitor Cg is connected to the ground terminal GND. Power transistors The first terminal of M1 is coupled to the cathode of the lower diode D2, and its second terminal is coupled to the ground terminal GND. The cathode of the upper diode D1 is coupled to the anode of the lower diode D2. The first terminals of resistor R2 and resistor R1 are coupled to the power supply voltage VBAT. The second terminal of resistor R2 is coupled to the anode of the upper diode D1. The second terminal of resistor R1, the cathode of the upper diode D1, the anode of the lower diode D2, and the first terminal of capacitor C1 are coupled to the output terminal LIN of the power stage circuit 12A. The second terminal of capacitor C1 is coupled to the ground terminal GND. In this embodiment, Power transistors M1 is realized with an N-type field-effect transistor, Power transistors The control terminal, first terminal, and second terminal of M1 are the gate, drain, and source of an N-type transistor, respectively.

[0023] When the charging switch SW11 is turned on based on the charging control signal SCH, the current source CU1 provides a charging current that flows through the turned-on charging switch SW11 to the capacitor Cg, charging the capacitor Cg and gradually increasing the voltage level of the gate capacitor voltage signal VCg at the first end of the capacitor Cg (i.e., the input end of the power stage circuit 12A). When the charging switch SW11 is turned off based on the charging control signal SCH, the current source circuit 110 stops supplying the charging current to the capacitor Cg, thereby stopping the charging circuit 11A from charging the capacitor Cg and stopping the increase in the voltage level of the gate capacitor voltage signal VCg. For example, the charging switch SW11 is turned on during the operating period of the charging control signal SCH and turned off during the non-operating period of the charging control signal SCH. Multiple operating periods of multiple consecutive pulse waves of the charging control signal SCH are: Power transistors It may also be determined based on the voltage difference between the control terminal and the second terminal of M1, i.e. Power transistors It may be determined based on the actual gate-source voltage (VGS) of M1.

[0024] When the discharge switch SW13 is turned on based on the discharge control signal SDG, the current source CU2 provides discharge current, which flows through the turned-on discharge switch SW13 to the ground terminal GND, discharging the capacitor Cg of the power stage circuit 12A and gradually decreasing the voltage level of the gate capacitor voltage signal VCg. When the discharge switch SW13 is turned off based on the discharge control signal SDG, the current source circuit 130 stops supplying the discharge current to the ground terminal GND, thereby stopping the discharge circuit 13A from discharging to the capacitor Cg and decreasing the voltage level of the gate capacitor voltage signal VCg. For example, the discharge switch SW13 is turned on during the operating period of the discharge control signal SDG and turned off during the non-operating period of the discharge control signal SDG. Multiple operating periods of multiple consecutive pulse waves of the discharge control signal SDG are: Power transistors It may be determined based on the actual gate-source voltage (VGS) of M1.

[0025] As described above, in this invention, by intermittently controlling the charging switch SW11 to a conductive state, the charging current output by the current source CU1 is gradually released to the capacitor Cg during discontinuous periods. Power transistors The voltage at the control terminal of M1 (i.e., the voltage level of the gate capacitor voltage signal VCg) is increased, thereby, Power transistors The conduction speed of M1 is controlled. Similarly, in this invention, by intermittently controlling the discharge switch SW13 to a conductive state, the capacitor Cg is gradually discharged during discontinuous periods, reducing the voltage at the control terminal of the power transistor M1, thereby controlling the cutoff speed of the power transistor M1. Power transistors M1 operates based on the gate capacitor voltage signal VCg and further controls the rate of level change (rise or fall) of the output voltage LIN at the output terminal of the power stage circuit 12A.

[0026] Figure 6 is a waveform diagram of the main signals of the electronic circuit of the fourth embodiment of the present invention. The multiple pulse wave patterns of the charge control signal SCH in Figure 6 are examples of the charge control signal SCH in Figures 1, 3, 5 and 15, respectively, and the multiple pulse wave patterns of the discharge control signal SDG in Figure 6 are examples of the discharge control signal SDG in Figures 3, 5 and 15, respectively.

[0027] As shown in Figure 6, the frequencies, operating periods, non-operating periods, or combinations thereof of the multiple pulse waves of the charge control signal SCH may be different from each other, and the frequencies, operating periods, non-operating periods, or combinations thereof of the multiple pulse waves of the discharge control signal SDG may also be different from each other. However, this is merely an example, and the present invention is not limited thereto. The control circuit 10 controls the power stage circuit 12A by the charge control signal SCH and the discharge control signal SDG during multiple switching periods. Please refer to Figure 6. The electronic circuit 5 can be operated during the connected periods P10, P20, P30, and P40 in the switching periods. The charge and discharge operation of the power stage circuit during the switching periods of the present invention will be described below using the combination of the electronic circuit 5 in Figure 5 and the main signals in Figure 6. During the charge period P10 of the power stage circuit 12A, the charge control signal SCH has multiple consecutive pulse waves P11 to P13, each pulse wave including an operating period and a non-operating period. Therefore, pulse waves P11 to P13 each include operating periods DN11 to DN13 and non-operating periods DF11 to DF13, respectively. During the charging period P10 and the connected maintenance period P20, the discharge control signal SDG is maintained at a voltage level without any pulse waves.

[0028] Please refer to Figures 5 and 6. During the charging period P10, the discharge control signal SDG is maintained at a low voltage level, so the discharge switch SW13 remains closed to interrupt the discharge path between node N10 and the ground terminal GND. During the charging period P10, the control circuit 10 conducts the charge switch SW11 during the operating periods DN11 to DN13 of the charge control signal SCH, thereby supplying the power stage circuit 12A with a charging current having a charging current value i1 via the current source circuit 110. In this way, the charging current from the current source circuit 110 is supplied to the first terminal of the capacitor Cg during the operating periods DN11 to DN13, charging the capacitor Cg multiple times, thereby generating multiple charging stages SU11 to SU13 in the gradually rising rise wavelength range of the gate capacitor voltage signal VCg. Please refer to Figures 5 and 6. During the operating period DN11 to DN13, the gate current ICg of capacitor Cg has a charging current value i1, and the charging current value i1 is a positive value, indicating that the direction of the gate current ICg is that of a flow-direction capacitor Cg (i.e., charging capacitor Cg). During the charging period P10, the control circuit 10 stops charging the power stage circuit 12A by the charging current by interrupting the charging switch SW11 during multiple non-operating periods DF11 to DF13 of the charging control signal SCH. Therefore, during the non-operating periods DF11 to DF13, the rise of the gate capacitor voltage signal VCg is stopped, and multiple charging stop horizontal line segments SH11 to SH13 are generated in the rising wavelength range. After the charging period P10, the electronic circuit 5 enters the maintenance period P20 and begins operation.

[0029] During the maintenance period P20, the control circuit 10 causes the charge control signal SCH to have a pulse wave P14. In this embodiment, the duration of the operating period of the pulse wave P14 (i.e., the pulse width of the pulse wave P14) is equal to the duration of the maintenance period P20, and the pulse wave P14 has no non-operating period. See Figures 5 and 6. During the maintenance period P20, the charge switch SW11 is conducted based on the pulse wave P14, and the charge circuit 11A provides a charge current to the first end of the capacitor Cg by the current source circuit 110, thereby recharging the capacitor Cg and causing the gate capacitor voltage signal VCg to rise again. When the gate capacitor voltage signal VCg rises to the peak level or a preset high level, the gate current ICg becomes zero, and the charge switch SW11 remains conducted based on the pulse wave P14 in order to maintain the gate capacitor voltage signal VCg at the peak level or a preset high level. When the maintenance period P20 ends, the charge control signal SCH is switched to a low voltage level (i.e., the pulse wave P14 ends). After the maintenance period P20, the electronic circuit 5 enters and operates the discharge period P30 of the power stage circuit 12A.

[0030] As shown in Figure 6, during the discharge period P30, the discharge control signal SDG has multiple consecutive pulse waves P21 to P23, each pulse wave including an operating period and a non-operating period. Therefore, each pulse wave P21 to P23 includes an operating period DN21 to DN23 and a non-operating period DF21 to DF23.

[0031] Refer to Figures 5 and 6. During the discharge period P30 and the subsequent maintenance period P40, the charge control signal SCH is switched to a low voltage level and maintained at that low voltage level, so the charge switch SW11 remains closed to interrupt the charge path between the power supply voltage VCC and node N10. During the discharge period P30, the control circuit 10 conducts the discharge switch SW13 during the operating periods DN21 to DN23 of the discharge control signal SDG, thereby causing the capacitor Cg to discharge by providing discharge current through the current source CU2. As a result, the gate capacitor voltage signal VCg generates multiple discharge stages SD21 to SD23 in the gradually decreasing falling wavelength range. Refer to Figures 5 and 6. During the operating periods DN21 to DN23, the gate current ICg of the capacitor Cg has a discharge current value -i2, and the discharge current value -i2 is a negative value, indicating that the direction of the gate current ICg is outflow capacitor Cg (i.e., capacitor Cg is discharging). During the discharge period P30, the control circuit 10 stops the discharge of capacitor Cg by interrupting the discharge switch SW13 within multiple non-operating periods DF21 to DF23 of the discharge control signal SDG, thereby stopping the discharge of capacitor Cg by the discharge circuit 13A. As a result, the gate capacitor voltage signal VCg stops dropping within the non-operating periods DF2 to DF23, generating multiple discharge-stopping horizontal line segments SH21 to SH23 in the falling wavelength range. After the discharge period P30, the electronic circuit 5 enters the maintenance period P40 and begins operation.

[0032] During the maintenance period P40, the control circuit 10 causes the discharge control signal SDG to have a pulse wave P24. In this embodiment, the duration of the operating period of the pulse wave P24 (i.e., the pulse width of the pulse wave P24) is equal to the duration of the maintenance period P40. See Figures 5 and 6. During the maintenance period P40, the discharge switch SW13 conducts based on the pulse wave P24, and the discharge circuit 13A re-discharges the capacitor Cg with the discharge current provided by the current source CU2, causing the gate capacitor voltage signal VCg to drop again. When the gate capacitor voltage signal VCg drops to the bottom level or a preset low level, the gate current ICg becomes zero, and the discharge switch SW13 continues to conduct based on the pulse wave P24 to maintain the gate capacitor voltage signal VCg at the bottom level or a preset low level. When the maintenance period P40 ends, the discharge control signal SDG is switched to a low voltage level (i.e., the pulse wave P24 ends). After the maintenance period P40, the electronic circuit 5 enters the charging period P10 of the next switching period and begins operation.

[0033] Figure 7 is a waveform diagram of the main signals of the electronic circuit of the fifth embodiment of the present invention. The multiple pulse wave patterns of the charge control signal SCH in Figure 7 are alternative examples of the charge control signal SCH in Figures 1, 3, 5 and 15, respectively, and the multiple pulse wave patterns of the discharge control signal SDG in Figure 7 are alternative examples of the discharge control signal SDG in Figures 3, 5 and 15, respectively.

[0034] Comparing Figure 6 and Figure 7, Figure 7 differs from Figure 6 in that, during the charging period P10, the discharge control signal SDG has the same pulse wave pattern as the charging control signal SCH. Based on the control operations of the charging circuit 11A and the discharge circuit 13A in the above embodiment, the charging switch SW11 is conducted during the operation period of the charging control signal SCH, and the discharge switch SW13 is conducted during the operation period of the discharge control signal SDG. Assume that the charging current value i1 is greater than the discharge current value i2. During the charging period P10 in Figure 7, when the charging switch SW11 is conducted, the discharge switch SW13 is also conducted, thereby allowing the current source circuit 110 to provide charging current to the first end of the capacitor Cg, while the current source CU2 provides discharge current to discharge the capacitor Cg. As shown in Figure 7, during the charging stage in the rising wavelength range of the gate capacitor voltage signal VCg, the capacitor Cg is charged based on the current difference between the charging current value i1 and the discharge current value i2 (i.e., gate current ICg, ICg = i1 - i2 (positive value)). In comparison with Figure 6, the gate capacitor voltage signal VCg in Figure 7 rises relatively slowly from the bottom level or initial low level to the peak level or a preset high level in the rising wavelength range. By appropriately employing a gate current ICg having a charging current value i1 or a current difference (ICg = i1 - i2) in the rising wavelength range of the gate capacitor voltage signal VCg (i.e., the charging period P10) to charge the capacitor Cg, the control accuracy of the conduction speed of the power stage circuit 12A can be improved.

[0035] Assume that the discharge current value i2 is greater than the charge current value i1. In another embodiment, during the discharge period P30, the charge switch SW11 is turned on and the discharge switch SW13 is turned on simultaneously, thereby the current source circuit 110 provides a charge current to the first terminal of the capacitor Cg, and the current source CU2 provides a discharge current to discharge the capacitor Cg. During the charging phase in the falling wavelength range of the gate capacitor voltage signal VCg, the capacitor Cg is discharged based on the current difference between the charge current value i1 and the discharge current value i2 (ICg = i1 - i2 (negative value)). Compared with Figure 6, in this embodiment, the gate capacitor voltage signal VCg is discharged directly from the peak level or initial high level to the bottom level or a preset low level at a relatively slow rate in the falling wavelength range. By discharging the capacitor Cg in the falling wavelength range of the gate capacitor voltage signal VCg (i.e., the discharge period P30) by appropriately employing a gate current ICg having a discharge current value i2 or a current difference (ICg = i1 - i2), the control accuracy of the interruption speed of the power stage circuit 12A can be improved.

[0036] Figures 8 to 11 are waveform diagrams of signals from electronic circuits according to the 6th to 9th embodiments of the present invention, respectively. The pulse wave patterns of the charge control signal SCH generated by the control circuit 10 in Figures 1, 3, 5, and 15, and / or the pulse wave patterns of the discharge control signal SDG generated by the control circuit 10 in Figures 3, 5, and 15, may be the same as the pulse wave patterns of the control signal SWa shown in Figure 8, the control signal SWb shown in Figure 9, the control signal SWc shown in Figure 10, or the control signal SWd shown in Figure 11. See Figure 8. Multiple pulse waves of the control signal SWa have the same frequency, for example, all of which are equal to a fixed frequency Fsw. See Figure 9. Multiple pulse waves of the control signal SWb have the same operating period, for example, all of which are equal to a fixed conduction time Ton. See Figure 10. Multiple pulse waves of the control signal SWc have the same non-operating period, for example, all of which are equal to a fixed cutoff time Toff. See Figure 11. The multiple pulse waves of the control signal SWd each have the same duty cycle D. The above pulse wave patterns are merely examples; the present invention is not limited thereto.

[0037] Figure 12 is a circuit diagram of the control circuit of an electronic circuit with intermittent charging and discharging according to the 10th embodiment of the present invention. Figure 13 is a waveform diagram of the charging control signal and other main signals during the switching period of the electronic circuit according to the 10th embodiment of the present invention. Figure 14 is a waveform diagram of the discharge control signal and other main signals during the switching period of the electronic circuit according to the 10th embodiment of the present invention. The control circuit 10A in Figure 12 is one embodiment of the control circuit 10 in Figures 1, 3, 5 and 15, and is described only as an example, but the present invention is not limited thereto. As shown in Figure 12, the control circuit 10A includes a charging / discharging switching circuit 100, a comparator 101, a signal generation circuit 102, a decision circuit 103, a sensing comparison circuit 104 and a state switching detection circuit 105. The control circuit 10A controls the power stage circuit 12A with a charging control signal SCH and a discharge control signal SDG during multiple switching periods.

[0038] The sensing circuit 120 senses the actual voltage difference VGS between the control terminal and the second terminal and outputs a sensing voltage signal S30. Power transistors The control terminal (gate) and second terminal (source) of M1 are coupled. The voltage level of the sensing voltage signal S30 represents the actual voltage difference VGS. In one embodiment, the voltage level of the sensing voltage signal S30 is equal to the value of the actual voltage difference VGS. Multiple comparators 121 to 123 (described in detail below) of the sensing comparison circuit 104 receive the sensing voltage signal S30 from the sensing circuit 120, compare each of the sensing voltage signals S30 with multiple reference voltages V31 to V33, and output multiple comparison signals S31 to S33, respectively.

[0039] The decision circuit 103 is coupled to the sensing comparison circuit 104 to receive comparison signals S31 to S33, and based on the comparison signals S31 to S33, it determines the time difference between the time it takes for the sensing voltage signal S30 to reach each reference voltage V31 to V33 and a time threshold, and generates a trigger signal S34 based on the decision result. The signal generation circuit 102 is coupled to the first output terminal of the decision circuit 103 to receive the trigger signal S34, and generates a state signal Vstate based on the trigger signal S34. In this embodiment, the signal generation circuit 102 controls the voltage level of the state signal Vstate based on the trigger signal S34. As described above, the trigger signal S34 is the sensing voltage signal S30( Power transistors The signal generation circuit 102 generates a state signal Vstate based on the level change of the actual voltage difference VGS (M1), and is controlled by the trigger signal S34 to generate the state signal Vstate, which is determined by the change in the actual voltage difference VGS.

[0040] The first input terminal of comparator 101 (e.g., the inverting input terminal (-)) is coupled to the signal generation circuit 102 to receive a reference voltage signal Vsaw, and its second input terminal (e.g., the non-inverting input terminal (+)) is coupled to the signal generation circuit 102 to receive a state signal Vstate. Comparator 101 compares the state signal Vstate with the reference voltage signal Vsaw and generates a switching signal S37 at the output terminal of comparator 101. If the voltage level of the state signal Vstate is higher than the voltage level of the reference voltage signal Vsaw, the switching signal S37 is at a high voltage level (corresponding to the operating period), and if the voltage level of the state signal Vstate is lower than the voltage level of the reference voltage signal Vsaw, the switching signal S37 is at a low voltage level (corresponding to the non-operating period). The input terminal of charge / discharge switching circuit 100 is coupled to the output terminal of comparator 101 to receive the switching signal S37. The first output terminal of the charge / discharge switching circuit 100 is the first output terminal of the control circuit 10A, which is connected to the input terminal of the charging circuit 11 shown in Figure 1 or Figure 3, or to the charging circuit 11A shown in Figure 5, or to the control terminal of the charging switch SW11 included in the charging circuit 11B shown in Figure 15. The second output terminal of the charge / discharge switching circuit 100 is the second output terminal of the control circuit 10A, which is connected to the input terminal of the discharge circuit 13 shown in Figure 3, or to the discharge circuit 13A shown in Figure 5, or to the control terminal of the discharge switch SW13 included in the discharge circuit 13B shown in Figure 15.

[0041] Refer to Figure 12. The sensing comparator circuit 104 may include a sensing circuit 120, a plurality of comparators 121-123, and a plurality of reference resistors R31-R33. In other embodiments, the sensing circuit 120 may be located outside the sensing comparator circuit 104. The first input terminal (e.g., the non-inverting input terminal (+)) of each comparator 121-123 is coupled to the output terminal of the sensing circuit 120 to receive the sensing voltage signal S30. The reference resistors R31-R33 are sequentially coupled in series between the power supply voltage VDD and the ground terminal GND. Specifically, the first terminal of reference resistor R31 is coupled to the power supply voltage VDD, the second terminal of reference resistor R31 is coupled to the first terminal of reference resistor R32, the second terminal of reference resistor R32 is coupled to the first terminal of reference resistor R33, and the second terminal of reference resistor R33 is coupled to the ground terminal GND. Reference resistors R31 to R33 generate reference voltages V31, V32, and V33 by dividing the voltage difference between the power supply voltage VDD and the voltage at the ground terminal GND.

[0042] The second input terminal of comparator 121 (e.g., the inverting input terminal (-)) is coupled to the first terminal of reference resistor R31 to receive the power supply voltage VDD as the reference voltage V31. Comparator 121 compares the voltage of the sensing voltage signal S30 with the reference voltage V31 and generates a comparison signal S31 at the output terminal of comparator 121. The second input terminal of comparator 122 (e.g., the non-inverting input terminal) is coupled to a common node between reference resistors R31 and R32 and receives the reference voltage V32 from this common node. Comparator 122 compares the voltage of the sensing voltage signal S30 with the reference voltage V32 and generates a comparison signal S32 at the output terminal of comparator 122. The second input terminal of comparator 123 (e.g., the non-inverting input terminal) is coupled to a common node between reference resistors R32 and R33 and receives the reference voltage V33 from this common node. The comparator 123 compares the voltage of the sensing voltage signal S30 with the reference voltage V33 and generates a comparison signal S33 at the output terminal of the comparator 123. The comparison signals S31 to S33 are provided to the decision circuit 103.

[0043] Refer to Figure 12. The signal generation circuit 102 may include a switch SW1, a switch SW2, an input current source CUin, and an input capacitor Cin. The first terminal of switch SW1 is coupled to the second input terminal of comparator 101 at node N11. The first terminal of input current source CUin is coupled to the second terminal of switch SW1, which is then coupled to ground GND. The control terminal of switch SW1 is coupled to the first output terminal of decision circuit 103 to receive the trigger signal S34. The first terminal of input capacitor Cin and the first terminal of switch SW2 are coupled to node N11. The second terminal of input capacitor Cin and the second terminal of switch SW2 are coupled to ground GND. Decision circuit 103 further generates a reset signal S35. The control terminal of switch SW2 is coupled to the second output terminal of decision circuit 103 to receive the reset signal S35.

[0044] When switch SW1 is turned on based on the trigger signal S34, the input current provided by the input current source CUin flows through switch SW1 to node N11, charging the input capacitor Cin and increasing the voltage at the first terminal of the input capacitor Cin (i.e., the voltage at node N11). The voltage signal at the first terminal of the input capacitor Cin is defined as the state signal Vstate. The decision circuit 103 turns on switch SW2 by issuing an enable reset signal S35 (for example, a pulse in the reset signal S35) at intervals equal to the time threshold (e.g., the ideal interval t0 in Figure 13), discharging the input capacitor Cin and thereby resetting the voltage at the second input terminal of comparator 101 (to zero).

[0045] The charge / discharge switching circuit 100 receives the switching signal S37 received from the output terminal of the comparator 101 as a charge control signal SCH and / or a discharge control signal SDG. For example, the charge / discharge switching circuit 100 receives from the state switching detection circuit 105 State switching detection signal Based on S38, it may be decided to output the switching signal S37 as a charging control signal SCH and / or a discharging control signal SDG, which will be described in detail below.

[0046] The state switching detection circuit 105 receives an instruction signal S39 (from an external circuit). According to one embodiment of the present invention, the rising edge of the instruction signal S39 indicates that the gate capacitor voltage signal VCg enters the rising wavelength range, and the falling edge of the instruction signal S39 indicates that the gate capacitor voltage signal VCg enters the falling wavelength range. The state switching detection circuit 105 detects the rising and falling edges of this instruction signal S39, State switching detection signal Output S38. According to one embodiment of the present invention, during the switching period, each time the state switching detection circuit 105 detects the rising edge of the instruction signal S39 shown in Figure 13, the state switching detection circuit 105 has a charging instruction message. State switching detection signal By outputting S38 to the charge / discharge switching circuit 100, the charge / discharge switching circuit 100 is instructed to set the switching signal S37 as the charge control signal SCH, thereby charging the capacitor Cg of the power stage circuit 12A. Power transistors M1 enters a conductive state.

[0047] According to one embodiment of the present invention, during the switching period, each time the state switching detection circuit 105 detects the falling edge of the instruction signal S39 shown in Figure 14, the state switching detection circuit 105 has a discharge instruction message State switching detection signal By outputting S38 to the charge / discharge switching circuit 100, the charge / discharge switching circuit 100 is instructed to use the switching signal S37 as the discharge control signal SDG, thereby discharging the capacitor Cg of the power stage circuit 12A. Power transistors M1 enters the cutoff state. As can be seen from the above, the instruction signal S39 is during each switching period. Power transistors This may represent the conduction and disconnection states of M1. In some embodiments, a state switching detection circuit 105 is provided within the decision circuit 103, and the decision circuit 103 is State switching detection signal S38 may be generated and output. In some other embodiments, the state switching detection circuit 105 is omitted, and the decision circuit 103 detects the rising and falling edges of this instruction signal S39. State switching detection signal You may also generate and output S38.

[0048] As shown in Figures 13 and 14, during the transition period, Power transistors The curve of the actual voltage difference VGS of M1 over time may deviate from the curve of the ideal voltage difference VGSTG over time. See Figure 13. From the rising edge of the instruction signal S39, it takes an ideal time tideal for the ideal voltage difference VGSTG to rise from 0 volts to the power supply voltage VDD. See Figure 14. From the falling edge of the instruction signal S39, it takes an ideal time tideal for the ideal voltage difference VGSTG to fall from the power supply voltage VDD to 0 volts. According to this embodiment of the present invention, the power supply voltage VDD is divided on average into m voltage segments. For example, the power supply voltage VDD is divided on average into 3 (m=3) voltage segments. Ideally, Power transistors The actual voltage difference VGS of M1 increases from 0 volts to 1 / 3 of the preset power supply voltage VDD (first target voltage) after an ideal interval time t0, then increases from 1 / 3 to 2 / 3 of the power supply voltage VDD (second target voltage) after an ideal interval time t0, and then increases from 2 / 3 of the power supply voltage VDD to the power supply voltage VDD (third target voltage) after an ideal interval time t0. Therefore, the ideal time Tideal is divided evenly into three ideal interval times t0, i.e., t0 = Tideal / m, and m = 3. Similarly, ideally, the actual voltage difference VGS drops from the power supply voltage VDD to 2 / 3 of the power supply voltage VDD, from 2 / 3 to 1 / 3 of the power supply voltage VDD, and from 1 / 3 of the power supply voltage VDD to 0 volts over three ideal interval times t0.

[0049] As described above, each time the decision circuit 103 enables the reset signal S35, the switch SW2 conducts based on the enabled reset signal S35 (i.e., based on the pulse of the reset signal S35), thereby discharging the voltage of the input capacitor Cin and resetting it to zero. Ideally, each time the decision circuit 103 enables the reset signal S35, the decision circuit 103 causes the trigger signal S34 to have an initial pulse wave P31 with a preset operating period DN31. In this embodiment, the preset operating period DN31 is equal to the ideal interval time t0 divided by a constant k (DN31 = t0 / k). In one embodiment, the constant k is preset based on system demand. For each ideal time Tideal, the trigger signal S34 has three initial pulse waves P31, each corresponding to three ideal interval times t0. In Figures 13 and 14, the initial pulse waves P31 are shown as dotted lines. Some initial pulse waves P31 completely or partially overlap with the modulated pulse waves shown by solid lines (for example, modulated pulse waves P41-P43 and P81-P83, which will be described later). Therefore, in Figures 13 and 14, the dotted lines representing the overlapping portions of the initial pulse waves P31 with the modulated pulse waves are not shown.

[0050] However, in reality, during the transition period, Power transistors The actual voltage difference VGS of M1 may reach at least one target voltage on time, early, or with a delay. Therefore, the control circuit 10A of the embodiment of the present invention allows the actual voltage difference VGS to gradually approach the ideal voltage difference VGSTG. Power transistors Based on the actual voltage difference VGS of M1, the operating period of multiple pulse waves of at least one of the charging control signal SCH and the discharging control signal SDG is adjusted.

[0051] Please refer to Figure 12. The decision circuit 103 also receives the instruction signal S39. As shown in Figure 13, in response to the rising edge of the instruction signal S39, the electronic circuit enters the current switching period, and the charge / discharge switching circuit 100, State switching detection signalBased on S38, the switching signal S37 is set as the charging control signal SCH, and the gate capacitor voltage signal VCg enters the rising wavelength range (i.e., enters the charging period of the power stage circuit 12A), thereby, Power transistors The actual voltage difference VGS of M1 gradually increases in accordance with the gate capacitor voltage signal VCg. Specifically, at the rising edge of the instruction signal S39 (i.e., the start of the first ideal interval time t0 in the charging period) and at the start of the second and third ideal interval times t0, the decision circuit 103 provides a pulse to conduct switch SW2 to the reset signal S35, thereby resetting the voltage of the input capacitor Cin to zero. In this embodiment, assuming that at the start of each of the first to third ideal interval times t0, the decision circuit 103 causes the trigger signal S34 to have an initial pulse wave P31, in other words, during the current switching period, the initial pulse wave P31 becomes the modulated pulse waves P41-P43 of the trigger signal S34, and the actual operating period Tvty(t) of the modulated pulse waves P41-P43 is equal to DN31(=t0 / k)(y is 41, 42, or 43), the switch SW1 is conducted and the input capacitor Cin is charged, and the voltage level of the state signal Vstate, for example the state signal Vstate shown by the dotted line in Figure 13, begins to increase. Based on the state signal Vstate of the current switching period, the charge control signal SCH has three initial pulse waves P60 for each of the first to third ideal interval times t0, through the operation of the comparator 101 and the charge / discharge switching circuit 100. During the charging period of the current switching period, based on these three initial pulse waves P60, the curve of the actual voltage difference VGS over time deviates from the curve of the ideal voltage difference VGSTG over time, as shown in Figure 13. As can be seen from the above, these three initial pulse waves P60 correspond to the three initial pulse waves P31 of the trigger signal S34, respectively. The initial pulse waves P60 are shown by dotted lines, and the modulated pulse waves P61~P63 (described later) are shown by solid lines. In Figure 13, there should be three initial pulse waves P60, but the first initial pulse wave P60 and the modulated pulse wave P61 completely overlap, so the first initial pulse wave P60 is not shown in Figure 13.

[0052] Please refer to Figure 13. During this current transition period, from the start of the first ideal interval time t0, Power transistors The actual voltage difference VGS of M1 takes an actual interval time t11 equal to the ideal interval time t0 to reach 1 / 3 of the power supply voltage VDD from 0 volts, i.e., t11=t0. Therefore, the time difference Δt11 is obtained by subtracting the ideal interval time t0 from the actual interval time t11 (Δt11=t11-t0=0, i.e., there is no error between the actual interval time t11 and the ideal interval time t0). In this embodiment of the present invention, when the actual voltage difference VGS increases from 0 volts and reaches 1 / 3 of the power supply voltage VDD, the voltage level of the sensing voltage signal S30 is equal to the reference voltage V33. At this time, the comparison signal S33 output by the comparator 123 is switched to a high voltage level. The decision circuit 103 obtains the actual interval time t11 based on the rising edge of the instruction signal S39 and the time when the comparison signal S33 is switched to a high voltage level. The decision circuit 103 determines that the actual interval time t11 is equal to the ideal interval time t0 (t11=t0), and calculates that the time difference Δt11 is equal to zero (Δt11=0).

[0053] Based on Equation 1, the decision circuit 103 determines the actual operating period of one of the multiple modulated pulse waves of the trigger signal S34 during the next switching period. Tvty(t+1)=Tvty(t)+c*Δtx (Equation 1)

[0054] Tvty(t) represents the actual operating period of one modulated pulse wave of the trigger signal S34 during the current switching period, Tvty(t+1) represents the actual operating period of one modulated pulse wave of the trigger signal S34 during the next switching period, c is a predetermined error compensation coefficient, x is 11, 12, 13, 21, 22, or 23, and y is 41, 42, 43, 81, 82, or 83.

[0055] As described above, in the previous switching period, the actual operating period Tvt41(t) of the modulated pulse wave P41 of the trigger signal S34 is equal to DN31 (=t0 / k), and Δt11=0. Therefore, based on Equation 1, the decision circuit 103 determines that the actual operating period Tvt41(t+1) of the modulated pulse wave P41 of the trigger signal S34 in the next switching period is equal to t0 / k, that is, equal to the preset operating period DN31 (Tvt41(t+1)=t0 / k+c*0=t0 / k=DN31). In this embodiment, the multiple modulated pulse waves of the trigger signal S34 are shown by solid lines. Therefore, the solid modulated pulse wave P41 overlaps with the corresponding dotted initial pulse wave P31, and only the realized modulated pulse wave P41 is shown in Figure 13.

[0056] As described above, the actual operating period Tvt41 of the modulated pulse wave P41 is equal to the preset operating period DN31 of the initial pulse wave P31. In the next switching period, switch SW1 is conducted within the preset operating period DN31 based on the modulated pulse wave P41, and the input current provided by the input current source CUin charges the input capacitor Cin through switch SW1 for the duration of the preset operating period DN31. As shown in Figure 13, the duration during which the actual voltage level of the state signal Vstate, shown by the solid line, is higher than the voltage level of the reference voltage signal Vsaw is equal to the ideal operating period (i.e., the operating period of the initial pulse wave P60). In this way, the duration during which the switching signal S37 is at a high voltage level is equal to the above ideal operating period. In the next switching period, the charge / discharge switching circuit 100 State switching detection signal When S38 outputs a switching signal S37 as a charging control signal SCH in accordance with the rising edge of the instruction signal S39, the charge / discharge switching circuit 100 controls the operating period of the first pulse wave of the charging control signal SCH to be equal to the above-mentioned ideal operating period (i.e., the operating period of the modulated pulse wave P61 to be equal to the above-mentioned ideal operating period), Power transistors The conduction period of M1 is made equal to the ideal operating period described above.

[0057] Please refer to Figure 13. During this current transition period, from the start of the second ideal interval time t0, Power transistors The actual voltage difference VGS of M1 takes an actual interval time t12 to reach 2 / 3 of the power supply voltage VDD with a delay from 1 / 3 of the power supply voltage VDD. Since the actual interval time t12 is greater than the ideal interval time t0, i.e., t12 > t0, the ideal interval time t0 is subtracted from the actual interval time t12 to obtain the time difference Δt12 (Δt12 = t12 - t0 > 0, i.e., there is an error between the actual interval time t12 and the ideal interval time t0). In this embodiment of the present invention, when the actual voltage difference VGS increases from 1 / 3 of the power supply voltage VDD and reaches 2 / 3 of the power supply voltage VDD, the voltage level of the sensing voltage signal S30 is equal to the reference voltage V32. At this time, the comparison signal S32 output by the comparator 122 is switched to a high voltage level. The decision circuit 103 obtains the actual interval time t12 based on the start time of the second ideal interval time t0 and the time when the comparison signal S32 is switched to a high voltage level. The decision circuit 103 determines that the actual interval time t12 is greater than the ideal interval time t0 (t12>t0), and calculates that the time difference Δt12 is greater than zero (Δt12>0). As described above, in the current switching period, the actual operating period Tvt42(t) of the modulated pulse wave P42 of the trigger signal S34 is equal to DN31 (=t0 / k). Based on Equation 1, the decision circuit 103 determines that the actual operating period Tvt42(t+1) of the modulated pulse wave P42 of the trigger signal S34 in the next switching period is equal to t0 / k+c*Δt12, which is greater than the preset operating period DN31 (Tvt42(t+1)=t0 / k+c*Δt12>DN31).

[0058] As described above, the actual operating period Tvt42 of the modulated pulse wave P42 is longer than the preset operating period DN31 of the initial pulse wave P31. Therefore, in the next switching period, switch SW1 conducts for a relatively long actual operating period Tvt42 based on the modulated pulse wave P42, and the time for the input current provided by the input current source CUin to charge the input capacitor Cin through switch SW1 becomes longer (longer than the preset operating period DN31), and as shown in Figure 13, the duration for which the actual voltage level of the state signal Vstate, shown by the solid line, is higher than the voltage level of the reference voltage signal Vsaw becomes longer (longer than the ideal operating period described above). In this way, the duration for which the switching signal S37 is at a high voltage level becomes longer. During the next switching period, when the charge / discharge switching circuit 100 outputs a switching signal S37 as a charging control signal SCH in accordance with the rising edge of the instruction signal S39, the charge / discharge switching circuit 100 controls the operation period of the second pulse wave of the charging control signal SCH to be longer than the ideal operation period (i.e., the operation period of the modulated pulse wave P62 to be longer than the ideal operation period), Power transistors The conduction period of M1 is extended. The second initial pulse wave P60 partially overlaps with the modulated pulse wave P62, which is shown by the solid line. Therefore, in Figure 13, the dotted line indicating the overlap between the second initial pulse wave P60 and the modulated pulse wave P62 is not shown.

[0059] Please refer to Figure 13. During this current transition period, from the start of the third ideal interval time t0, Power transistorsThe actual voltage difference VGS of M1 takes an actual interval time t13 to reach the power supply voltage VDD earlier from 2 / 3 of the power supply voltage VDD. Since the actual interval time t13 is smaller than the ideal interval time t0, that is, t13 < t0, the ideal interval time t0 is subtracted from the actual interval time t13 to obtain a time difference Δt13 (Δt13 = t13 - t0 < 0). In an embodiment of the present invention, when the actual voltage difference VGS increases from 2 / 3 of the source voltage VDD and reaches the power supply voltage VDD, the voltage level of the sensing voltage signal S30 is equal to the reference voltage V33. At this time, the comparison signal S31 output by the comparator 121 is switched to a high voltage level. The determination circuit 103 obtains the actual interval time t13 based on the start point of the third ideal interval time t0 and the point when the comparison signal S31 is switched to the high voltage level. The determination circuit 103 determines that the actual interval time t13 is smaller than the ideal interval time t0 (t13 < t0), and calculates that the time difference Δt13 is smaller than zero (Δt13 < 0, that is, there is an error between the actual interval time t13 and the ideal interval time t0). As described above, in the current switching period, the actual operation period Tvt43(t) of the modulation pulse wave P43 of the trigger signal S34 is equal to DN31 (= t0 / k). Based on Equation 1, the determination circuit 103 determines that the actual operation period Tvt43(t + 1) of the modulation pulse wave P43 of the trigger signal S34 in the next switching period is equal to t0 / k + c*Δt13, that is, smaller than the preset operation period DN31 (Tvt43(t + 1) = t0 / k + c*Δt13 < DN31).

[0060] As described above, the actual operating period Tvt43 of the modulated pulse wave P43 is shorter than the preset operating period DN31 of the initial pulse wave P31. Therefore, in the next switching period, switch SW1 conducts for a relatively short actual operating period Tvt43 based on the modulated pulse wave P43, and the time for the input current provided by the input current source CUin to charge the input capacitor Cin through switch SW1 is shortened (shorter than the preset operating period DN31), and as shown in Figure 13, the duration for which the actual voltage level of the state signal Vstate, shown by the solid line, is higher than the voltage level of the reference voltage signal Vsaw is shortened (shorter than the ideal operating period described above). In this way, the duration for which the switching signal S37 is at a high voltage level is shortened. During the next switching period, when the charge / discharge switching circuit 100 outputs a switching signal S37 as a charging control signal SCH in accordance with the rising edge of the instruction signal S39, the charge / discharge switching circuit 100 controls the operating period of the third pulse wave of the charging control signal SCH to be shorter than the ideal operating period (i.e., the operating period of the modulated pulse wave P63 to be shorter than the ideal operating period), Power transistors The conduction time of M1 is shortened. The third initial pulse wave P60 partially overlaps with the modulated pulse wave P63, which is shown by the solid line. Therefore, the dotted line indicating the overlap between the modulated pulse wave P63 and the third initial pulse wave P60 is not shown in Figure 13.

[0061] During each switching period, at the end of the third ideal interval time t0 in the charging period, the decision circuit 103 causes the reset signal S35 to pulse in order to conduct switch SW2, thereby resetting the voltage of input capacitor Cin to zero. Simultaneously, at the end of the third ideal interval time t0, the charge / discharge switching circuit 100 causes the charge control signal SCH to pulse wave P64, and the pulse width period of pulse wave P64 ends at the falling edge of instruction signal S39. During the pulse width period of pulse wave P64 (i.e., the maintenance period of power stage circuit 12A), the charge switch SW11 remains conducted based on pulse wave P64, and the gate capacitor voltage signal VCg rises and is maintained at a peak level or a preset high level, thereby, Power transistors The actual voltage difference VGS of M1 rises and is maintained at a specific level (this specific level is higher than the power supply voltage VDD).

[0062] In one embodiment, during each switching period, the decision circuit 103 starts counting the number of pulses of the reset signal S35 in accordance with the rising edge of the instruction signal S39. When the cumulative number of pulses of the reset signal S35 from the rising edge of the instruction signal S39 reaches a pulse wave number threshold (for example, four as shown in Figure 13 (=m+1=3+1)), the decision circuit 103 outputs a control signal S40 to control the charge / discharge switching circuit 100, thereby causing the outputted charge control signal SCH to have a pulse wave P64.

[0063] As described above, in accordance with the rising edge of the instruction signal S39, the gate capacitor voltage signal VCg enters the rising wavelength range. During the period in the rising wavelength range of the gate capacitor voltage signal VCg, in the intermittent charge / discharge method of the present invention, Power transistors Based on the actual voltage difference VGS of M1, the operating period of multiple pulse waves of the charging control signal SCH (i.e., the conduction time of the charging switch SW11) is adjusted. In this way, Power transistors The actual voltage difference VGS of M1 gradually approaches the ideal voltage difference VGSTG.

[0064] During each switching period, in the charging and maintenance periods of the power stage circuit 12A, the charge / discharge switching circuit 100 controls the discharge control signal SDG to maintain a low voltage level, thereby shutting off the discharge switch SW13 and thereby blocking the discharge path between node N10 and the ground terminal GND until the falling edge of the instruction signal S39.

[0065] As shown in Figure 14, during the current switching period, the charge / discharge switching circuit 100 operates in accordance with the falling edge of the instruction signal S39. State switching detection signal Based on S38, the switching signal S37 is set as the discharge control signal SDG, and the gate capacitor voltage signal VCg enters the falling wavelength range (i.e., enters the discharge period of the power stage circuit 12A), thereby, Power transistors The actual voltage difference VGS of M1 gradually decreases in accordance with the gate capacitor voltage signal VCg. During the discharge period, the charge / discharge switching circuit 100 first controls the discharge control signal SDG to have a pulse wave P80, thereby conducting the discharge switch SW13 during the operating period of the pulse wave P80, and thereby, Power transistors The actual voltage difference VGS of M1 begins to drop from a specific level higher than the power supply voltage VDD. The operating period of the pulse wave P80 is predetermined and starts from the point when the actual voltage difference VGS begins to drop from a specific level and ends at the point of the first pulse in the discharge period of the reset signal S35.

[0066] Furthermore, in response to the falling edge of the instruction signal S39, the charge / discharge switching circuit 100 switches to a low voltage level and controls the charge control signal SCH to maintain the low voltage level until the rising edge of the instruction signal S39 in the next switching period.

[0067] Then, during the current switching period, at the start of each of the first to third ideal interval times t0 in the discharge period, the decision circuit 103 causes each of the reset signals S35 to pulse in order to conduct the switch SW2, thereby resetting the voltage of the input capacitor Cin to zero. In this embodiment, assuming that at the start of each of the first to third ideal interval times t0 in the discharge period, the decision circuit 103 causes the trigger signal S34 to have an initial pulse wave P31, in other words, if the initial pulse wave P31 in the current switching period is the modulated pulse waves P81 to P83 of the trigger signal S34, then the actual operating period Tvty(t) of the modulated pulse waves P81 to P83 is equal to DN31 (=t0 / k) (where y is 81, 82, or 83). Furthermore, at the start of each of the first to third ideal interval times t0 during the discharge period, the decision circuit 103 causes the trigger signal S34 to have an initial pulse wave P31 in order to conduct the switch SW1, thereby charging the input capacitor Cin, and the voltage level of the state signal Vstate, for example, shown by the dotted line in Figure 14, begins to increase. Based on the state signal Vstate of the current switching period, the charge control signal SCH has three initial pulse waves P60 for each of the first to third ideal interval times t0, through the operation of the comparator 101 and the charge / discharge switching circuit 100. During the discharge period of the current switching period, based on these three initial pulse waves P60, the curve of the actual voltage difference VGS over time deviates from the curve of the ideal voltage difference VGSTG over time, as shown in Figure 14. As can be seen from the above, the three initial pulse waves P60 during the discharge period correspond to the three initial pulse waves P31 of the trigger signal S34, respectively. The initial pulse wave P60 is shown by a dotted line, and the modulated pulse waves P91-P93 (described later) are shown by solid lines.

[0068] Please refer to FIG. 14. In this current switching period, starting from the start point of the first ideal interval time t0, the actual voltage difference VGS takes an actual interval time t23 shorter than the ideal interval time t0 to quickly reach from the power supply voltage VDD to 2 / 3 of the power supply voltage VDD, that is, t23 < t0. Based on the above description and the analog operation during the charging period, the determination circuit 103 calculates that the time difference Δt23 is smaller than zero (Δt23 = t23 - t0 < 0, that is, there is an error between the actual interval time t23 and the ideal interval time t0). As described above, in the previous switching period, the actual operation period Tvt81(t) of the modulation pulse wave P81 of the trigger signal S34 is equal to DN31 (= t0 / k). Based on Equation 1, the determination circuit 103 determines that the actual operation period Tvt81(t + 1) of the modulation pulse wave P81 of the trigger signal S34 in the next switching period is equal to t0 / k + c*Δt23, that is, smaller than the preset operation period DN31 (Tvt81(t + 1) = t0 / k + c*Δt23 < DN31). The switch SW1 is turned on for a relatively short actual operation period Tvt81, and the time for charging the input capacitor Cin becomes shorter (shorter than the time length of the preset operation period DN31). As shown in FIG. 14, the duration during which the actual voltage level of the state signal Vstate is higher than the voltage level of the reference voltage signal Vsaw becomes shorter (shorter than the above ideal operation period). In this way, the duration during which the switching signal S37 is at the high voltage level becomes shorter. In the next switching period, when the charge-discharge switching circuit 100 outputs the switching signal S37 as the discharge control signal SDG in response to the falling edge of the instruction signal S39, the charge-discharge switching circuit 100 controls the operation period of the first pulse wave of the discharge control signal SDG to be shorter than the above ideal operation period (that is, the operation period of the modulation pulse wave P91 is shorter than the above ideal operation period), Power transistors to shorten the conduction time of M1. Since the first initial pulse wave P60 partially overlaps with the modulation pulse wave P91, the dotted line at the overlapping part of the modulation pulse wave P91 in the first initial pulse wave P60 is not shown in FIG. 14.

[0069] Please refer to Figure 14. Since the start of the operating period of the modulated pulse wave P91 coincides with the end of the operating period of the pulse wave P80, the rising edge of the modulated pulse wave P91 is not shown in Figure 14.

[0070] Refer to Figure 14. During this current switching period, from the start of the second ideal interval time t0, the actual voltage difference VGS takes longer to reach 1 / 3 of the power supply voltage VDD than the ideal interval time t0, i.e., t22 > t0. Based on the above explanation and the analogous operation during the charging period, the decision circuit 103 calculates that the time difference Δt22 is greater than zero (Δt22 = t22 - t0 > 0, i.e., there is an error between the actual interval time t22 and the ideal interval time t0). As described above, during the current switching period, the actual operating period Tvt82(t) of the modulated pulse wave P82 of the trigger signal S34 is equal to DN31 (= t0 / k). Based on Equation 1, the decision circuit 103 determines that the actual operating period Tvt82(t+1) of the modulated pulse wave P82 of the trigger signal S34 during the next switching period is equal to t0 / k+c*Δt22, i.e., longer than the preset operating period DN31 (Tvt82(t+1)=t0 / k+c*Δt22>DN31). The switch SW1 conducts for a relatively long actual operating period Tvt82, and the time during which the input capacitor Cin is charged becomes longer (longer than the preset operating period DN31), and as shown in Figure 14, the duration for which the actual voltage level of the state signal Vstate is higher than the voltage level of the reference voltage signal Vsaw becomes longer (longer than the ideal operating period described above). In this way, the duration for which the switching signal S37 is at a high voltage level becomes longer. During the next switching period, when the charge / discharge switching circuit 100 outputs a switching signal S37 as a discharge control signal SDG in accordance with the falling edge of the instruction signal S39, the charge / discharge switching circuit 100 controls the operation period of the second pulse wave of the discharge control signal SDG to be longer than the ideal operation period (i.e., the operation period of the modulated pulse wave P92 to be longer than the ideal operation period), Power transistorsIncrease the conduction time of M1. Since the second initial pulse wave P60 partially overlaps with the modulation pulse wave P92, the dotted line at the overlapping part of the modulation pulse wave P92 in the second initial pulse wave P60 is not shown in FIG. 14.

[0071] Refer to FIG. 14. In this current switching period, from the start point of the third ideal interval time t0, the actual voltage difference VGS takes an actual interval time t21 shorter than the ideal interval time t0 to reach from 1 / 3 of the power supply voltage VDD to 0 volts earlier, that is, t21 < t0. Based on the above description and the analog operation during the charging period, the determination circuit 103 calculates that the time difference Δt21 is smaller than zero (Δt21 = t21 - t0 < 0, that is, there is an error between the actual interval time t21 and the ideal interval time t0). As described above, in the current switching period, the actual operation period Tvt83(t) of the modulation pulse wave P83 of the trigger signal S34 is equal to DN31 (= t0 / k). Based on Equation 1, the determination circuit 103 determines that the actual operation period Tvt83(t + 1) of the modulation pulse wave P83 of the trigger signal S34 in the next switching period is equal to t0 / k + c*Δt21, that is, smaller than the preset operation period DN31 (Tvt83 = t0 / k + c*Δt21 < DN31). The switch SW1 is turned on for a relatively short actual operation period Tvt83, and the time for charging the input capacitor Cin becomes shorter (shorter than the time length of the preset operation period DN31). As shown in FIG. 14, the duration during which the actual voltage level of the state signal Vstate is higher than the voltage level of the reference voltage signal Vsaw becomes shorter (shorter than the above ideal operation period). In this way, the duration during which the switching signal S37 is at the high voltage level becomes shorter. In the next switching period, when the charge-discharge switching circuit 100 outputs the switching signal S37 as the electric control signal SDG in response to the falling edge of the instruction signal S39, the charge-discharge switching circuit 100 controls the operation period of the third pulse wave of the discharge control signal SDG to be shorter than the above ideal operation period (that is, the operation period of the modulation pulse wave P93 is shorter than the above ideal operation period) so that Power transistorsThe conduction time of M1 is shortened. The third initial pulse wave P60 partially overlaps with the modulated pulse wave P93, so the dotted line indicating the overlap between the third initial pulse wave P60 and the modulated pulse wave P93 is not shown in Figure 14.

[0072] During each switching period, at the end of the third ideal interval time t0 in the discharge period, the decision circuit 103 causes the reset signal S35 to pulse again in order to conduct switch SW2, thereby resetting the voltage of input capacitor Cin to zero. Simultaneously, at the end of the third ideal interval time t0, the charge / discharge switching circuit 100 causes the discharge control signal SDG to have a pulse wave P94, and the pulse width period of pulse wave P94 ends at the rising edge of instruction signal S39. During the pulse width period of pulse wave P94 (i.e., the maintenance period of power stage circuit 12A), the discharge switch SW13 remains conducted based on pulse wave P94, and the gate capacitor voltage signal VCg is maintained at the bottom level or a preset low level, thereby, Power transistors The actual voltage difference VGS of M1 is maintained at 0 volts.

[0073] In one embodiment, during each switching period, the decision circuit 103 starts counting the number of pulses of the reset signal S35 in accordance with the falling edge of the instruction signal S39. When the cumulative number of pulses of the reset signal S35 from the falling edge of the instruction signal S39 reaches a pulse wave number threshold (for example, four as shown in Figure 14 (=m+1=3+1)), the decision circuit 103 outputs a control signal S40 to control the charge / discharge switching circuit 100, thereby causing the outputted discharge control signal SDG to have a pulse wave P94.

[0074] As described above, in accordance with the falling edge of the instruction signal S39, the gate capacitor voltage signal VCg enters the falling wavelength range. During the period in the falling wavelength range of the gate capacitor voltage signal VCg, in the intermittent charge / discharge method of the present invention, Power transistors Based on the actual voltage difference VGS of M1, the operating period of multiple pulse waves of the discharge control signal SDG (i.e., the conduction time of the discharge switch SW13) is adjusted, thereby, Power transistors The actual change in the voltage difference VGS of M1 can be made closer to the ideal voltage difference VGSTG.

[0075] As described above, during the current switching period, the control circuit 10A realizes the intermittent charge-discharge method of the present invention by determining the pulse wave pattern of the charge control signal SCH and the discharge control signal SDG for the next switching period based on the actual voltage difference VGS, thereby improving the accuracy of charge-discharge control and flexibly controlling the charge and discharge state of the power stage circuit 12A. With the charge-discharge control of the present invention, Power transistors The curve of the actual voltage difference VGS of M1 as it changes over time can gradually match the curve of the ideal voltage difference VGSTG as it changes over time, and furthermore, the rate of change of the output voltage level at the output terminal LIN of the power stage circuit 12A can be set to a desired value.

[0076] In the above embodiment, Power transistors The pulse wave patterns of the charge control signal SCH and / or the discharge control signal SDG are determined based on the actual gate-source voltage (VGS) of M1. In other embodiments, Power transistors The pulse wave patterns of the charge control signal SCH and / or the discharge control signal SDG may be determined based on the drain-source voltage (VDS) of M1. In detail, the control circuit 10A, Power transistors Based on the situation in which the drain-source voltage of M1 drops from the power supply voltage VDD to 0 volts over an ideal time tideal, the pulse wave patterns of the charge control signal SCH and / or the discharge control signal SDG may be determined by performing an operation similar to those shown in Figures 12 to 14. For related descriptions, please refer to the explanations of Figures 12 to 14. The explanation is omitted here.

[0077] Please refer to Figure 15, a circuit diagram of an electronic circuit 15 for intermittent charging and discharging in the 11th embodiment of the present invention. In Figure 5, the charging circuit 11A includes a current source CU1, and the discharging circuit 13A includes a current source CU2. In the embodiment of Figure 15, the charging circuit 11B includes a charging-side resistor R15 instead of the charging circuit 11A in Figure 5, and the discharging circuit 13B includes a discharging-side resistor R16 instead of the discharging circuit 13A in Figure 5.

[0078] When the charge switch SW11 is turned on based on the charge control signal SCH, the charge current flows sequentially from the power supply voltage VCC through the charge-side resistor R15 and the turned-on charge switch SW11 to the capacitor Cg, charging the capacitor Cg and gradually increasing the voltage level of the gate capacitor voltage signal VCg at the first end of the capacitor Cg. When the discharge switch SW13 is turned on based on the discharge control signal SDG, the discharge current flows sequentially from the first end of the capacitor Cg through the discharge-side resistor R16 and the turned-on discharge switch SW13 to the ground terminal GND, discharging the capacitor Cg and gradually decreasing the voltage level of the gate capacitor voltage signal VCg.

[0079] In the above embodiment, the charge / discharge switching circuit 100 is performed in accordance with the rising edge of the instruction signal S39. State switching detection signal Based on S38, the switching signal S37 is set to only the charging control signal SCH, and in accordance with the falling edge of the instruction signal S39, the charge / discharge switching circuit 100 is configured as follows: State switching detection signal Based on S38, the switching signal S37 is set to only the discharge control signal SDG. In some embodiments, depending on the rising edge and / or falling edge of the instruction signal S39, the charge / discharge switching circuit 100 State switching detection signal Based on S38, the switching signal S37 is set to both the charge control signal SCH and the discharge control signal SDG. For example, as shown in Figure 7, during the charging period, in response to the rising edge of the instruction signal S39, the charge / discharge switching circuit 100 sets the switching signal S37 to both the charge control signal SCH and the discharge control signal SDG, such that the charge control signal SCH and the discharge control signal SDG have the same pulse wave pattern.

[0080] According to the above, during the current switching period, the control circuit 10A controls the charging circuit 11A and the discharging circuit 13A based on the switching signal S37 determined in the previous switching period, thereby controlling the charging and discharging of the power stage circuit 12A, and further Power transistorsThe conduction and cutoff speed of M1 is controlled. According to another embodiment of the present invention, during the charging period of this current switching period, the power stage circuit 12A charges based on the switching signal S37 determined in the previous switching cycle, and at the same time, the control circuit 10A determines whether to add and enable the discharge control signal SDG (i.e., add and control the discharge control signal SDG to the high voltage level) based on the actual voltage difference VGS. See Figures 12 and 13 for details. During the charging period of the current switching period, the judgment circuit 103 indicates that overcharging has occurred in the power stage circuit 12A if it determines that any one of the comparison signals S31 to S33 will be switched to a high voltage level within the first ideal interval time t0, or if it determines that comparison signal S31 or S32 will be switched to a high voltage level within the second ideal interval time t0, or if it determines that comparison signal S31 will be switched to a high voltage level within the first half of the third ideal interval time t0. At this time, the decision circuit 103 reduces the voltage level of the gate capacitor voltage signal VCg by controlling the charge / discharge switching circuit 100 to add and enable the discharge control signal SDG based on the decision signal S36. See, for example, Figure 16. During the charging period P15, the discharge control signal SDG is not switched to a low voltage level as shown in Figure 7 to conduct the discharge switch SW13, but is maintained at a high voltage level (i.e., compared to the corresponding pulse wave in Figure 7, the discharge control signal SDG is added and enabled, thereby extending the operating period of this corresponding pulse wave of the discharge control signal SDG). Therefore, the gate capacitor voltage signal VCg drops during period P15, thereby introducing a discharge stage SD11 in the rising wavelength range of the gate capacitor voltage signal VCg, thereby compensating for the gate capacitor voltage signal VCg rising too quickly due to overcharging. As shown in Figure 16, the discharge stage SD11 is between the two charging stages.

[0081] Similarly, during the discharge period of this current switching period, the power stage circuit 12A discharges based on the switching signal S37 determined in the previous switching cycle, while the control circuit 10A decides whether to add and enable the charging control signal SCH (i.e., add and control the charging control signal SCH to the high voltage level) based on the actual voltage difference VGS. See Figures 12 and 14 for details. During the discharge period of the current switching period, the decision circuit 103 indicates that over-discharge has occurred in the power stage circuit 12A if it determines that the comparison signal S32 or S33 will be switched to a low voltage level within the first ideal interval time t0, or if it determines that the comparison signal S33 will be switched to a low voltage level within the second ideal interval time t0, or if it determines that the comparison signal S33 will be switched to a low voltage level within the first half of the third ideal interval time t0. At this time, the decision circuit 103 increases the voltage level of the gate capacitor voltage signal VCg by controlling the charge / discharge switching circuit 100 to add and enable the charge control signal SCH based on the decision signal S36. See, for example, Figure 16. During the charging period P16, the charge control signal SCH is not maintained at a low voltage level as in Figure 7 in order to conduct the charge switch SW11, but is switched to a high voltage level (i.e., the charge control signal SCH is added and enabled compared to Figure 7). As a result, the gate capacitor voltage signal VCg rises during period P16, thereby introducing a charging stage SU21 in the falling wavelength range of the gate capacitor voltage signal VCg, thereby compensating for the excessively rapid level drop due to over-discharge of the gate capacitor voltage signal VCg. As shown in Figure 16, the charging stage SU21 is between the two discharge stages. In this embodiment, the length of period P15 is equal to the length of P16.

[0082] In the embodiment shown in Figure 16, if the power stage circuit 12A generates overcharge or over-discharge during the current switching period based on the switching signal S37 determined in the previous switching period, the control circuit 10A can fine-tune the pulse wave patterns of the charge control signal SCH and / or the discharge control signal SDG in real time, thereby, Power transistors The level change of the gate capacitor voltage signal VCg is corrected so that the curve of the time evolution of the actual voltage difference VGS of M1 matches the curve of the time evolution of the ideal voltage difference VGSTG.

[0083] In other embodiments, the control circuit 10A or the charge / discharge switching circuit 100 may further include a compensation circuit that receives a decision signal S36 and generates a pulse corresponding to the discharge stage SD11 and / or a pulse corresponding to the charge stage SU21 based on the decision signal S36. When the charge / discharge switching circuit 100 receives this pulse during the charging period, the controlled discharge control signal SDG has this pulse (for example, in Figure 16, the pulse corresponding to period P15 on the discharge control signal SDG), and when the charge / discharge switching circuit 100 receives this pulse during the discharge period, the controlled discharge control signal SDG has this pulse (for example, in Figure 16, the pulse corresponding to period P16 on the charge control signal SCH). In the present invention, the specific configuration of the compensation circuit is not limited, and any circuit that can generate a fixed-width pulse based on the decision signal S36 can be the compensation circuit described above.

[0084] However, the intermittent charging and discharging method of the present invention can achieve more precise control than the conventional method which continuously charges during the charging period and continuously discharges during the discharging period. It should be noted that the charging circuit, discharging circuit, and multiple circuit elements included in the electronic circuit for the intermittent charging and discharging of the present invention are merely illustrative examples, and the present invention is not limited thereto.

[0085] As described above, the present invention provides an intermittent charging and discharging method, an intermittent discharging method, and an electronic circuit using intermittent charging and discharging. In the intermittent charging and discharging method and the electronic circuit using intermittent charging and discharging of the present invention, intermittent control is employed for both the conduction and interruption of the charging circuit (including the charging switch) and the discharging circuit (including the discharging switch), and in the intermittent discharging method of the present invention, intermittent control is employed for the conduction and interruption of the discharging circuit (including the discharging switch). Therefore, compared to the prior art, the intermittent charging and discharging method, the intermittent discharging method, and the electronic circuit using intermittent charging and discharging of the present invention significantly improve control accuracy. Furthermore, compared to the prior art, the electronic circuit using intermittent charging and discharging of the present invention reduces the required control hardware circuit, and further reduces the design area and power consumption, thereby saving costs.

[0086] The information disclosed above is merely a preferred and feasible embodiment of the present invention and does not limit the scope of the patent application for the present invention; therefore, all equivalent technical modifications made using the content of the specification and drawings of the present invention are included within the scope of the claims of the present invention. [Explanation of symbols]

[0087] 1, 3, 5, 15: Electronic circuit 10, 10A: Control circuit 11, 11A, 11B: Charging circuit 12, 12A: Power stage circuit 13, 13A, 13B: Discharge circuit 100: Charge / Discharge Switching Circuit 102: Signal generation circuit 103: Judgment circuit 104: Sensing comparison circuit 105: State switching detection circuit 101: Comparator 110: Charging side current source circuit 120: Sensing Circuit 121~123: Comparator 130: Discharge side current source circuit C1, Cg: Capacitors Cin: Input capacitor CU1: Charging side current source CU2: Discharge side current source CUin: Input current source D: Duty cycle D1: Upper diode D2: Lower diode DN11~DN13, DN21~DN23, DN31: Operating period DF11~DF13, DF21~DF23: Non-operating period Fsw: Fixed frequency GND: Grounding end i1: Charging current value i2: Discharge current value ICg: Gate current LIN: Output terminal M1: Power transistors N10, N11: Nodes P10: Charging period P11~P14: Pulse wave P15, P16: Period P20, P40: Maintenance period P21~P24: Pulse wave P30:Discharge period P31: Initial pulse wave P41~P43: Modulated pulse wave P60: Initial pulse wave P61~P63: Modulated pulse wave P64: Pulse wave P80: Pulse wave P81~P83: Modulated pulse wave P91~P93: Modulated pulse wave P94: Pulse wave R1, R2: Resistance R15: Charging side resistance R16: Discharge side resistance R31~R33: Reference resistors S11~S15, S21~S25: Process S30: Sensing voltage signal S31~S33: Comparison signal S34: Trigger signal S35: Reset signal S36: Judgment signal S37: Switching signal S38: State switching detection signal S39: Instruction signal S40: Control signal SCH: Charge control signal SD11, SD21~SD23: Discharge stage SDG: Discharge Control Signal SH11~SH13: Charging stop horizontal line segment SH21~SH23: Discharge stop horizontal line segment SU11~SU13, SU21: Charging stage SW1, SW2: Switches SW11: Charging switch SW13: Discharge switch SWa, SWb, SWc, SWd: Control signals t0: Ideal interval time t11, t12, t13, t21, t22, t23: Actual interval time Tideal: Ideal time Toff: Fixed cutoff time Ton: Fixed conduction time V31~V33: Reference voltage VCg: Gate capacitor voltage signal VCC, VBAT, VDD: Power supply voltage VGS: Actual Gate-Source Voltage / Actual Voltage Difference VGSTG: Ideal Voltage Difference Vsaw: Reference voltage signal Vstate: State signal Δt11~Δt13: Time difference Δt21~Δt23: Time difference

Claims

1. In the first period, the process involves generating multiple first charging stages in the rising wavelength range of the voltage signal of the power stage circuit by charging the power stage circuit multiple times within multiple operating periods of multiple consecutive pulse waves of the charging control signal, In the first period, the charging of the power stage circuit is stopped within a plurality of non-operating periods of a plurality of consecutive pulse waves of the charging control signal, thereby generating a charging stop horizontal line segment or a first discharge stage between two of the plurality of first charging stages in the voltage signal. An intermittent charging and discharging method including [a specific component].

2. The process involves discharging the power stage circuit multiple times within multiple operating periods of multiple consecutive pulse waves of the discharge control signal, thereby generating multiple discharge stages in the falling wavelength range for each voltage signal of the power stage circuit, The process of generating a discharge stop horizontal line segment or charging stage between two of the multiple discharge stages in the voltage signal by stopping the discharge to the power stage circuit within multiple non-operating periods of the multiple pulse waves of the discharge control signal, An intermittent discharge method including [a specific component].

3. A control circuit that generates a charging control signal, A power stage circuit that receives a voltage signal, A charging circuit coupled to the power stage circuit and the control circuit, and controlled by the control circuit based on the charging control signal, Equipped with, During the first period, the control circuit controls the charging circuit to charge the power stage circuit multiple times within multiple operating periods of multiple consecutive pulse waves of the charging control signal, thereby generating multiple first charging stages in the rising wavelength range of the voltage signal. In the first period, the control circuit controls the charging circuit to stop charging the power stage circuit within a plurality of non-operating periods of a plurality of consecutive pulse waves of the charging control signal, thereby generating a charging stop horizontal line segment or a first discharge stage between two of the plurality of first charging stages in the voltage signal, an electronic circuit for intermittent charging and discharging.

4. The control circuit further generates a discharge control signal, and the electronic circuit due to the intermittent charging and discharging, The power stage circuit and the control circuit are further coupled, and the control circuit is controlled by the control circuit based on the discharge control signal, Within a second period following the first period, the control circuit controls the charging circuit to discharge the power stage circuit multiple times within multiple operating periods of multiple consecutive pulse waves of the discharge control signal, thereby generating multiple second discharge stages in the falling wavelength range for each voltage signal. In the second period, the control circuit controls the discharge circuit to stop discharging to the power stage circuit within a plurality of non-operating periods of a plurality of consecutive pulse waves of the discharge control signal, thereby generating a discharge stop horizontal line segment or a second charge stage in the voltage signal between two of the plurality of second discharge stages, as described in claim 3.

5. The aforementioned power stage circuit is A first capacitor whose first end is connected to the input terminal of the power stage circuit of the charging circuit and the discharge circuit, and whose second end is connected to the ground terminal, A power transistor having a first terminal coupled to a first power supply voltage, a second terminal coupled to the ground terminal, and a control terminal coupled to the input terminal, Equipped with, The voltage signal is generated at the input terminal in the electronic circuit according to claim 4, which is formed by intermittent charging and discharging.

6. The aforementioned control circuit is A first comparator that receives a first reference voltage signal at its first input terminal and a status signal at its second input terminal, compares the first reference voltage signal with the status signal which represents the change in the voltage difference between the control terminal and the second terminal of the power transistor, and generates a switching signal at its output terminal. An output circuit that receives the switching signal and outputs the switching signal as the charging control signal or the discharging control signal, An electronic circuit for intermittent charging and discharging according to claim 5, comprising the above.

7. The aforementioned control circuit is A sensing comparison circuit is configured to receive a sensing voltage signal, compare the sensing voltage signal representing the voltage difference of the power transistor with a plurality of second reference voltages, and output a plurality of comparison signals. A determination circuit is configured to receive a plurality of comparison signals and, based on the plurality of comparison signals, determine the time difference between the time it takes for the sensing voltage signal to reach each of the second reference voltages and a time threshold, thereby generating a trigger signal. A signal generation circuit configured to receive the trigger signal and generate the status signal, and to control the level of the status signal based on the trigger signal, An electronic circuit for intermittent charging and discharging according to claim 6, further comprising the above.

8. The aforementioned sensing comparison circuit is A sensing circuit configured to sense the voltage difference of the power transistor and output the sensing voltage signal, To receive the sensing voltage signal, a plurality of second comparators are provided, each having a first input terminal coupled to the sensing circuit, each having a second input terminal coupled to a plurality of second reference voltages, and each having a plurality of output terminals that output a plurality of comparison signals. Multiple reference resistors are connected in series between the second power supply voltage and the ground terminal, Equipped with, The second power supply voltage is set as one of the second reference voltages, The electronic circuit for intermittent charging and discharging according to claim 7, wherein the plurality of reference resistors include a first reference resistor and a second reference resistor, and the voltage at a common node between the first reference resistor and the second reference resistor is another second reference voltage among the second reference voltages.

9. The aforementioned signal generation circuit is A first switch whose first end is connected to the second input terminal of the first comparator at the first node, and whose control end receives the trigger signal, The first end is connected to the second end of the first switch, the second end is connected to the ground terminal, and when the first switch is turned on based on the trigger signal, the input current source circuit provides an input current source that supplies current to the first node by the first switch, An input capacitor whose first end is connected to the first node where the status signal is generated, and whose second end is connected to the ground terminal, A second switch, the first end of which is connected to the first node and the second end of which is connected to the ground terminal, Equipped with, The judgment circuit generates a reset signal, and the control terminal of the second switch receives the reset signal. The electronic circuit for intermittent charging and discharging according to claim 7, wherein the determination circuit enables the reset signal to conduct to the second switch at time intervals equal to the time threshold.

10. The conduction and disconnection states of the power transistors in the power stage circuit are controlled by the voltage signal, the instruction signal represents the conduction and disconnection states of the power transistors, and the control circuit, The system further includes a state switching detection circuit configured to receive the instruction signal, detect the rising edge and falling edge of the instruction signal, and output a state switching detection signal. Each time the state switching detection circuit detects the rising edge of the instruction signal, the state switching detection circuit outputs the state switching detection count signal and controls the output circuit to output the switching signal as the charging control signal. The electronic circuit for intermittent charging and discharging according to claim 6, wherein each time the state switching detection circuit detects the falling edge of the instruction signal, the state switching detection circuit outputs the state switching detection count signal and controls the output circuit to output the switching signal as the discharge control signal.

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