Integrated circuits, methods, media, apparatus, and chips for data transmission.

Abstract

Embodiments of this disclosure disclose integrated circuits and methods, media, apparatus, and chips for data transmission. [Solution] The integrated circuit includes at least two processing elements, where one of the at least two processing elements is a first processing element, which includes a first buffer and a first memory, and the first processing element determines the data transmission priority between the first memory and a second processing element cascaded to the front of the first processing element based on the current cache state of the first buffer, acquires the data to be transmitted based on the data transmission priority, caches the data to be transmitted in the first buffer, and is configured so that the data to be transmitted can be read by a cascaded circuit downstream of the first processing element.

Description

Technical Field

[0001] The present disclosure relates to integrated circuit technology, and particularly to integrated circuits, methods, media, devices, and chips for data transmission.

Background Art

[0002] In an on-chip interconnection network, a ring-type interconnection network is a common topology structure. In the data transmission of a ring-type interconnection network, a data loop is formed. When all buffers (e.g., first-in-first-out queues) on the data loop are full, a ring-shaped data dependency is formed on the data loop, and all data (or called transmission load) cannot be transmitted forward. Therefore, deadlocks are likely to occur, and further, the data transmission efficiency is affected.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Embodiments of the present disclosure provide an integrated circuit, a method, a medium, a device, and a chip for data transmission to avoid the occurrence of deadlocks in a data loop and ensure data transmission efficiency.

Means for Solving the Problems

[0004] A first aspect of an embodiment of the present disclosure includes at least two processing elements. A first processing element among the at least two processing elements includes a first buffer and a first memory. The first processing element determines the data transmission priority between the first memory and a second processing element connected in cascade in front of the first processing element based on the current cache state of the first buffer, acquires transmission target data based on the data transmission priority, caches the transmission target data in the first buffer, and is configured such that the transmission target data can be read by a cascade circuit behind the first processing element, and provides an integrated circuit for data transmission.

[0005] A second embodiment of the present disclosure provides a data transmission method comprising: determining a data transmission priority between a first memory in the first processing element and a cascaded second processing element preceding the first processing element based on the current cache state of a first buffer in the first processing element; acquiring data to be transmitted based on the data transmission priority; and caching the data to be transmitted in the first buffer so that the data to be transmitted can be read by a cascaded circuit following the first processing element.

[0006] A third embodiment of the embodiments of the present disclosure provides a computer-readable storage medium which, when executed by a processor, stores a computer program for performing the data transmission method described in any of the above embodiments of the present disclosure.

[0007] A fourth embodiment of the embodiments of the present disclosure provides an electronic device comprising a processor and a second memory for storing instructions that the processor can execute, the processor reading and executing the instructions from the second memory, and used to implement a data transmission method described in any of the above embodiments of the present disclosure.

[0008] A fifth embodiment of the embodiments of the present disclosure provides a computer program product, wherein when instructions in the computer program product are executed by a processor, a data transmission method provided in any of the above embodiments of the present disclosure is performed.

[0009] A sixth embodiment of the embodiments of the present disclosure provides a chip that includes an integrated circuit for data transmission provided in any of the embodiments of the present disclosure. [Effects of the Invention]

[0010] Based on the integrated circuits and methods, media, apparatus and chips for data transmission provided by the above embodiments of this disclosure, any processing element (referred to as the first processing element) on the data transmission path can determine the data transmission priority of two data sources (i.e., the first memory and the second processing element) based on the current cache state of the first buffer for caching the data to be transmitted within the first processing element, and further acquire the data to be transmitted based on the data transmission priority and cache the data to be transmitted in the first buffer. This allows the data to be preferentially acquired from data sources with higher data transmission priority when the remaining memory space of the first buffer is small. For example, by preferentially acquiring the data to be transmitted from the second processing element, the buffer of the second processing element can free up some of its cache space, ensuring that at least one buffer is not full on the data transmission path at any given time, thereby avoiding a situation where all buffers on the data transmission path become full, and further effectively solving the deadlock problem in a ring interconnect network. [Brief explanation of the drawing]

[0011] [Figure 1] This is one exemplary application scenario of the data transmission integrated circuit provided in this disclosure. [Figure 2] This is a schematic diagram of an integrated circuit for data transmission provided by one exemplary embodiment of the present disclosure. [Figure 3] This is a schematic diagram of an integrated circuit for data transmission provided in another exemplary embodiment of the present disclosure. [Figure 4] This is a schematic diagram of a processing element provided by one exemplary embodiment of the present disclosure. [Figure 5] This is a schematic diagram of an integrated circuit for data transmission provided by yet another exemplary embodiment of the present disclosure. [Figure 6] This is a flowchart of a data transmission method provided by one exemplary embodiment of the present disclosure. [Figure 7]This is a flowchart of a data transmission method provided by another exemplary embodiment of the present disclosure. [Figure 8] This is a flowchart of a data transmission method provided by yet another exemplary embodiment of the present disclosure. [Figure 9] This is a flowchart of a data transmission method provided by another exemplary embodiment of the present disclosure. [Figure 10] This is a flowchart of a data transmission method provided by yet another exemplary embodiment of the present disclosure. [Figure 11] This is a flowchart of a data transmission method provided by another exemplary embodiment of the present disclosure. [Figure 12] This is a structural diagram of an electronic device provided by an embodiment of the present disclosure. [Modes for carrying out the invention]

[0012] To illustrate this disclosure, exemplary embodiments of this disclosure will be described in detail below with reference to the drawings. Clearly, the embodiments described are only a selection of embodiments of this disclosure, not all embodiments, and it should be understood that this disclosure is not limited to exemplary embodiments.

[0013] It should be noted that the relative arrangements of parts and steps, formulas, and numerical values ​​described in these embodiments do not limit the scope of this disclosure unless specifically stated otherwise.

[0014] Summary of this disclosure In the process of realizing this disclosure, the inventors discovered that in an on-chip ring interconnect network topology structure of a chip, data transmission in a ring interconnect network forms a data loop, and when all buffers on the data loop (e.g., first-in, first-out queues) are full, a ring-shaped data dependency is formed on the data loop, preventing all data (or transmission load) from being transmitted forward. This makes it easy to cause a deadlock in the ring interconnect network and further affects data transmission efficiency.

[0015] Example Overview Figure 1 shows one exemplary application scene of an integrated circuit for data transmission provided by this disclosure. As shown in Figure 1, the application scene takes an on-chip ring interconnect network as an example, and the ring interconnect network may include at least two processing elements, and at least two processing elements are interconnected to form a ring interconnect network. For example, the ring interconnect network in the figure includes a total of n processing elements, processing element 11, processing element 12, ..., processing element 1n, where n is an integer greater than 1, and each processing element 1i (i=1, 2, ..., n) may include a buffer 1i1, and in the data transmission process, each processing element 1i may cache the data to be transmitted via buffer 1i1, and for any processing element 1i, a cascaded processing element 1j (j=i+1 if i is less than n, j=1 if i=n) downstream of that processing element 1i reads the data to be transmitted from the buffer 1i1 of processing element 1i to realize data transmission. The data source for the data to be transmitted in processing element 1i includes two sources: a cascaded processing element 1k preceding processing element 1i (k=i-1 if i is greater than 1, and k=n if i=1) and the internal memory of processing element 1i. In other words, processing element 1i can cache data from the preceding cascaded processing element 1k in buffer 1i1, and can also cache data from its internal memory in buffer 1i1, thereby allowing the subsequent cascaded processing element 1j to read the data to be transmitted from buffer 1i1. The data from the preceding cascaded processing element 1k comes from buffer 1k1 within processing element 1k. The data transmission integrated circuit of this disclosure includes, for any processing element (referred to as the first processing element, and may also be referred to as the first processing unit) 1i in each processing element, a buffer (referred to as the first buffer) 1i1 and memory (referred to as the first memory).When the first processing element 1i determines the data transmission priority between the first memory and the second processing element 1k connected in cascade in front of the first processing element 1i based on the current cache state of the buffer 1i1, acquires the data to be transmitted based on the data transmission priority, caches the data to be transmitted in the first buffer 1i1, and the data to be transmitted is read by a cascade circuit (for example, a processing element 1j connected in cascade at the subsequent stage) at the subsequent stage of the first processing element 1i, and is configured to realize data transmission. Thereby, when the remaining storage space of the first buffer 1i1 is small, the data to be transmitted can be preferentially acquired from a data source with a high data transmission priority. For example, by preferentially acquiring the data to be transmitted from the second processing element 1k, the buffer 1k1 of the second processing element 1k releases a part of the cache space, and it can be ensured that there is at least one buffer on the data transmission path that is not full of data at any time. Thereby, it is possible to avoid a situation where all buffers on the data transmission path are full of data, and effectively solve the deadlock problem in the ring-type interconnected network.

[0016] In actual applications, the integrated circuit for data transmission in the embodiments of the present disclosure is not limited to a ring-type interconnected network, and can also be applied to other non-ring-type topological structures, and is not specifically limited.

[0017] Exemplary device FIG. 2 is a schematic structural diagram of an integrated circuit for data transmission provided by one exemplary embodiment of the present disclosure. This embodiment can be applied to a chip, specifically, for example, can be applied to a chip in a terminal device such as an in-vehicle computing platform, a mobile phone, a tablet, etc. As shown in FIG. 2, an integrated circuit for data transmission (abbreviated as an integrated circuit) of an embodiment of the present disclosure can include at least two processing elements. In the figure, n processing elements are taken as an example, that is, processing element 11, processing element 12,..., processing element 1n, where n is an integer greater than 1. Any first processing element 1i (i = 1, 2,..., n) among at least two processing elements includes a buffer (referred to as the first buffer) 1i1 and a memory (referred to as the first memory) 1i2.

[0018] The first processing element 1i determines the data transmission priority (or abbreviated as priority) between the first memory 1i2 and the second processing element 1k (when i is greater than 1, k = i - 1) connected in cascade in front of the first processing element 1i based on the current cache state of the first buffer 1i1, acquires the transmission target data based on the data transmission priority, caches the transmission target data in the first buffer 1i1, and is configured such that the transmission target data is read by the cascade circuit behind the first processing element 1i.

[0019] Here, the number of processing elements included in the integrated circuit can be determined based on the needs of the actual application scenario, and the embodiments of the present disclosure do not limit this. For example, the number n of processing elements may be 2, 3, 4,....

[0020] In some selective embodiments, processing element 1i may be any device with which data exchange needs exist with other devices, for example, in computer vision fields such as intelligent drives and security monitoring, where data transmission needs exist between processing devices such as CPUs (Central Processing Units), GPUs (Graphics Processing Units), NPUs (Neural Network Processing Units), DPUs (Data Processing Units), TPUs (Tensor Processing Units), and ISPs (Image Signal Processing) units, and these processing devices may each be processing elements in embodiments of this disclosure.

[0021] In some selective embodiments, at least two processing elements are interconnected to form a ring interconnect topology. Referring to Figure 2, for processing element 11, if processing element 11 is interconnected with processing element 1n, a ring interconnect topology is formed, where the cascade circuit preceding processing element 11 is processing element 1n, and the cascade circuit following processing element 1n is processing element 11. For example, in an intelligent drive scene, there are data exchange needs between processing elements for sensing, positioning, and planning control, each of which can be a processing element in the embodiments of this disclosure. Sensing processing is a process of sensing the surrounding environment of the vehicle based on sensor data and obtaining sensing results. Sensing results may include obstacles, road elements, etc., around the vehicle that have been sensed. Positioning processing is a process of positioning the vehicle in real time based on the sensing results. Planning control is a process of planning a route based on the sensing results and positioning results, and controlling the driving state of the vehicle based on the planned route. The vehicle's driving status is further provided to the sensing processing element for continued sensing processing, thereby interconnecting each processing element to form a ring-type interconnection topology structure. It should be understood that the processing elements for sensing, positioning, and planning control described above are merely illustrative examples and do not limit the embodiments of this application. In actual applications, processing such as sensing, positioning, and planning control is not limited to each corresponding to a single processing element; for example, at least one processing element can cooperate to realize intelligent drive functions such as sensing, positioning, and planning control, and each of the processing elements in that at least one processing element can be a processing element in the embodiments of this disclosure. Furthermore, the processing elements in the embodiments of this disclosure are not limited to processing elements in an intelligent drive scene; as long as there is a data transmission need between multiple processing elements, data transmission can be realized via the data transmission integrated circuit of the embodiments of this disclosure.

[0022] In some selective embodiments, buffer 1i1 may be any memory with caching capabilities. For example, buffer 1i1 may be a FIFO (First Input First Output) buffer or another type of buffer.

[0023] In some selective embodiments, memory 1i2 may be any memory having data storage capabilities. For example, memory 1i2 may include DRAM (Dynamic Random Access Memory), and may specifically be, but is not limited to, DDR (Double Data Rate Synchronous Dynamic Random Access Memory) or LPDDR (Low Power Double Data Rate Synchronous Dynamic Random-Access Memory).

[0024] In some selective embodiments, the current cache state of the first buffer 1i1 is a state representing the degree of occupancy of the first buffer 1i1. The current cache state can include multiple preset states, for example, multiple preset states of different degrees based on the degree of occupancy of the first buffer 1i1, and each preset state can include multiple preset states, for example, empty, almost empty, intermediate, almost full, and full. Here, the empty state can be described as the ratio of occupied cache space to total cache space (abbreviated as the occupancy ratio) being less than the first threshold; the almost empty state (also called the near-empty state) can be described as the ratio of occupied cache space to total cache space being greater than or equal to the first threshold and less than the second threshold; the intermediate state can be described as the ratio of occupied cache space to total cache space being greater than or equal to the second threshold and less than the third threshold; the almost full state (also called the near-full state) can be described as the ratio of occupied cache space to total cache space being greater than or equal to the third threshold and less than the fourth threshold; and the full state (also called the full state) can be described as the ratio of occupied cache space to total cache space being greater than or equal to the fourth threshold. The first, second, third, and fourth thresholds can be set based on actual needs. For example, the third and fourth thresholds can be determined based on the bandwidth of each data transmission. If the occupancy ratio is greater than the fourth threshold, the remaining free cache space cannot support caching the data for one transmission, i.e., the remaining free cache space is smaller than the size of the data to be transmitted. If the occupancy ratio is greater than the third threshold and less than the fourth threshold, the remaining free cache space can support caching the data for at least one transmission. The specific values ​​of each threshold are not limited to the embodiments of this disclosure.For example, each preset state may include a first preset state (i.e., a full state where the occupancy ratio is greater than or equal to the fourth threshold), a second preset state (i.e., a near-full state where the occupancy ratio is less than the fourth threshold and greater than or equal to the third threshold), and other preset states (where the occupancy ratio is less than the third threshold). These other preset states cover the empty state, almost empty state, and intermediate state described above. The specific distinctions between cache states are not limited.

[0025] In some selective embodiments, the cascaded second processing element 1k preceding the first processing element 1i refers to the preceding processing element on which the input data of the first processing element 1i depends. For example, in Figure 2, the cascaded second processing element preceding processing element 12 is processing element 11, and the cascaded second processing element preceding processing element 13 is processing element 12. The data transmission priority between the first memory 1i2 and the second processing element 1k can take two forms: one where the data transmission priority of the second processing element 1k is higher than that of the first memory 1i2, and another where the data transmission priority of the second processing element 1k is the same as that of the first memory 1i2.

[0026] In some selective embodiments, the correspondence between multiple cache states of the first buffer 1i1 and data transmission priorities can be pre-configured, and the data transmission priority between the first memory 1i2 and the second processing element 1k can be determined based on the current cache state of the first buffer 1i1 and the pre-configured correspondence between multiple cache states and data transmission priorities. For example, the data transmission priorities corresponding to the empty state, almost empty state, and intermediate state are all the same for the first memory 1i2 and the second processing element 1k, while the data transmission priority corresponding to the almost full state is higher for the second processing element 1k than for the first memory 1i2. The specific correspondence between multiple cache states and data transmission priorities can be configured based on actual needs and are not limited to the exemplary relationships described above.

[0027] In some selective embodiments, the data transmission priority between the first memory 1i2 and the second processing element 1k may further include priority types that indicate that the acquisition of data to be transmitted from the first memory 1i2 and the second processing element 1k should be paused. For example, the data transmission priority may include three types: priority, same, and pause, where priority indicates that the data transmission priority of the second processing element 1k is higher than that of the first memory 1i2, same indicates that the data transmission priority of the second processing element 1k is the same as that of the first memory 1i2, and pause indicates that the acquisition of data to be transmitted should be paused. For example, if the current cache state of the first buffer 1i1 is full, the data transmission priority between the second processing element 1k and the first memory 1i2 is determined to be paused.

[0028] In some selective embodiments, the data transmission priorities of the first memory 1i2 and the second processing element 1k can be represented using priority numbers. For example, a priority of 1 for the second processing element 1k and a priority of 2 for the first memory 1i2 indicates that the priority of the second processing element 1k is first class and the priority of the first memory 1i2 is second class, with first class being higher than second class. In practical applications, data transmission priorities can be represented in other ways, as long as the data transmission priorities of the first memory 1i2 and the second processing element 1k can be determined.

[0029] In some selective embodiments, the data to be transmitted is data that the first processing element 1i needs to transmit to a subsequent cascade circuit. Possible data sources for the data to be transmitted include the second processing element 1k and the first memory 1i2. The data transmission priority of the first memory 1i2 and the second processing element 1k determines the data source of the current data to be transmitted, and the data to be transmitted is preferentially acquired from the data source with the higher priority. If the data transmission priority of the first memory 1i2 and the second processing element 1k is the same, both the first memory 1i2 and the second processing element 1k can be used as data sources, and the data in both the first memory 1i2 and the second processing element 1k can be used as the data to be transmitted. If the data transmission priority of the second processing element 1k is higher than the priority of the first memory 1i2, the data to be transmitted is preferentially acquired from the second processing element 1k, that is, the data from the second processing element 1k (which can be called the first data) is preferentially designated as the data to be transmitted, and the data to be transmitted is cached in the first buffer 1i1. As for the data in the first memory 1i2 (which can be called the second data), if the first buffer 1i1 can store the second data further, the second data can be cached in the first buffer 1i1. If the first buffer 1i1 cannot cache the second data, the acquisition of the second data from the first memory 1i2 can be temporarily suspended, and after waiting for the cache space of the first buffer 1i1 to be released, the second data can be acquired from the first memory 1i2 again, the second data can be designated as the data to be transmitted, and the data to be transmitted can be cached in the first buffer 1i1. The data cached in the first buffer 1i1 is data that needs to be transmitted to the subsequent cascade circuit. The subsequent cascade circuit can read the data from the first buffer 1i1 and transmit the data from the first processing element 1i to the subsequent cascade circuit. Each processing element can transmit the data according to the above process, thereby realizing data transmission between the preceding and succeeding cascade-connected processing elements.

[0030] In some selective embodiments, the cascade circuit after the first processing element 1i can be determined based on the position of the first processing element 1i within each processing element. For example, for processing element 1n, if buffer 1n1 is connected to processing element 11, the cascade circuit after processing element 1n is processing element 11. If buffer 1n1 of processing element 1n is connected to an output interface or pin of an integrated circuit, the cascade circuit after buffer 1n1 is an external circuit of the integrated circuit. For other processing elements 1i (where i is not equal to n), the cascade circuit after processing element 1i is 1j (j=i+1).

[0031] In some selective embodiments, the number of cascaded processing elements 1j following the first processing element 1i may be one or more, and is not specifically limited. For example, the cascaded processing elements following the sensing processing element may include a positioning processing element and a planning control element, i.e., the sensing result of the sensing processing element can be transmitted to the positioning processing element and the planning control element, respectively, the positioning processing element performs positioning relative to the vehicle based on the sensing result, the positioning result is transmitted to the planning control element, and the planning control element performs planning control based on the sensing result and the positioning result.

[0032] The data transmission integrated circuit provided by this embodiment can determine the data transmission priority of two data sources (i.e., the first memory and the second processing element) based on the current cache state of the first buffer for caching the data to be transmitted within the first processing element, for any processing element on the data transmission path (referred to as the first processing element). Furthermore, it can acquire the data to be transmitted based on the data transmission priority and cache the data to be transmitted in the first buffer. In this way, if the remaining memory space of the first buffer is small, the data to be transmitted can be preferentially acquired from the data source with the higher data transmission priority. For example, by preferentially acquiring the data to be transmitted from the second processing element, the buffer of the second processing element can free up some of its cache space. This ensures that at least one buffer is not full on the data transmission path at any given time, thereby avoiding a situation where all buffers on the data transmission path become full, and effectively solving the deadlock problem in a ring interconnect network.

[0033] Figure 3 is a schematic diagram of an integrated circuit for data transmission provided in another exemplary embodiment of the present disclosure.

[0034] In some selective embodiments, based on any of the embodiments described above, the first processing element 1i further includes an interface (referred to as the first interface) 1i3 and an arbiter (referred to as the first arbiter) 1i4, as shown in Figure 3.

[0035] The first interface 1i3 is for receiving the first data from the second processing element 1k.

[0036] The first arbiter 1i4 determines the data transmission priority between the first memory 1i2 and the second processing element 1k based on the current cache state of the first buffer 1i1, and based on the data transmission priority, determines at least one of the first data received by the first interface 1i3 and the second data in the first memory 1i2 as the data to be transmitted, and is configured to cache the data to be transmitted in the first buffer 1i1.

[0037] Here, the first interface 1i4 may be an interface that satisfies the corresponding communication protocol between processing elements. The first processing element 1i can read data from the buffer 1k1 of the second processing element 1k via the first interface 1i4 and use the read data as the first data.

[0038] In some selective embodiments, the first interface 1i4 is connected to the second processing element 1k and the first arbiter 1i4, respectively. The first arbiter 1i4 is connected to the first memory 1i2 and the first buffer 1i1, respectively.

[0039] In some selective embodiments, the first arbiter 1i4 may be any logic device, controller, processor, etc., that has a corresponding arbitration function. The first arbiter 1i4 can be implemented based on hardware, software, or a combination of hardware and software, and is not specifically limited. The first arbiter 1i4 is configured to determine the data transmission priority of the first memory 1i2 and the second processing element 1k based on the current cache state of the first buffer 1i1, and if the priority of the second processing element 1k is higher than the priority of the first memory 1i2, it determines the first data received by the first interface 1i3 as data to be transmitted and caches the data to be transmitted in the first buffer 1i1, and if the priority of the second processing element 1k is the same as the priority of the first memory 1i2, it determines the first data and the second data in the first memory 1i2 as data to be transmitted, respectively, and caches the first data and the second data in the first buffer 1i1.

[0040] In the embodiments of this disclosure, the first processing element communicates with the second processing element via a first interface, receives first data from the second processing element, and further performs arbitration on the first data and the second data in the first memory based on the current cache state of the first buffer via a first arbiter to determine the data to be transmitted, caches the data to be transmitted in the first buffer, and achieves effective control of data transmission. As a result, when the first buffer is nearly full, the first processing element preferentially obtains the data to be transmitted from the second processing element, allowing the second processing element's buffer to free up some cache space. This ensures that there is always at least one buffer that is not full on the data transmission path, thereby avoiding the occurrence of deadlock problems.

[0041] In some selective embodiments, the first arbiter 1i4 is further configured to determine the current cache state of the first buffer 1i1 based on a state signal output by the first buffer 1i1.

[0042] Here, the status signal output by the first buffer 1i1 is a signal that characterizes the current occupancy level of the first buffer 1i1.

[0043] In some selective embodiments, the status signal output by the first buffer 1i1 can be obtained by monitoring the cache space occupancy status of the first buffer. For example, the current amount of memory in the first buffer 1i1 can be determined by counting the difference between the number of writes and reads, and the status signal that the first buffer 1i1 should output can be determined based on the current amount of memory and the total amount of memory in the first buffer. Alternatively, for example, by having a read pointer and a write pointer point to the read address and write address of the cache space, respectively, the status signal that the first buffer 1i1 should output can be determined based on the relationship between the read address and write address and the address range of the cache space of the first buffer 1i1. The specific method for determining the status signal output by the first buffer 1i1 is determined by the specific function of the first buffer 1i1, and the embodiments of this disclosure are not limited thereto.

[0044] In some selective embodiments, the integrated circuit of the embodiments of the present disclosure may further include a control unit configured to determine the current cache state of the first buffer 1i1 based on a status signal output by the first buffer 1i1. The control unit is connected to the first buffer 1i1 and the first arbiter 1i4, respectively, and transmits the current cache state to the first arbiter 1i4, which then determines the data transmission priority of the first memory 1i2 and the second processing element 1k based on the current cache state, acquires the data to be transmitted based on the data transmission priority, and caches the data to be transmitted in the first buffer 1i1.

[0045] In some selective embodiments, the state signal can characterize different cache states of the first buffer 1i1 by different signal values. For example, if the state signal is a first signal value, it indicates that the first buffer 1i1 is in a first preset state (e.g., full state); if the state signal value is a second signal value, it indicates that the first buffer 1i1 is in a second preset state (e.g., near-full state); and if the state signal value is a third signal value, it indicates that the first buffer 1i1 is in a third preset state (e.g., not nearly full state).

[0046] In some selective embodiments, the status signal may include multiple status signals, for example, a status signal may include a first status signal (e.g., a full signal indicating whether it is full or not), a second status signal (e.g., an almost full signal indicating whether it is nearly full or not), a third status signal (e.g., an almost empty signal indicating whether it is nearly empty or not), and a fourth status signal (e.g., an empty signal indicating whether it is empty or not). This allows the current cache state of the first buffer 1i1 to be determined comprehensively based on the current signal values ​​of the multiple status signals. The specific status signals can be determined by the output function of the first buffer 1i1. For example, a FIFO buffer may output a full signal, an almost full signal, an almost empty signal, and an empty signal, each of which may include two preset values, for example, 1 and 0, where for the full signal, 1 indicates full and 0 indicates not full; for the almost full signal, 1 indicates nearly full and 0 indicates not nearly full. For the almost empty signal, 1 indicates that it is almost empty, and 0 indicates that it is not almost empty. For the empty signal, 1 indicates that it is empty, and 0 indicates that it is not empty. Not being full includes multiple situations such as almost full and not almost full, and not almost full includes multiple situations such as not almost empty, almost empty and empty. Therefore, the current cache state of the first buffer 1i1 can be determined by combining the specific signal values ​​of multiple state signals. For example, if the first state signal is the first preset value (e.g., 1), it can be determined that the current cache state of the first buffer 1i1 is full (i.e., the first preset state). If the first state signal is the second preset value (e.g., 0), the value of the second state signal can be determined further, and if the second state signal is the first preset value, it can be determined that the current cache state of the first buffer 1i1 is near full (i.e., the second preset state).

[0047] In the embodiments of this disclosure, the current cache state of the first buffer is determined based on the status signal output by the first buffer, and since the status signal output by the first buffer characterizes the current occupancy level of the first buffer, real-time and accurate current cache state can be ensured.

[0048] In some selective embodiments, the status signal includes a first status signal, a second status signal, and a third status signal.

[0049] Here, the first state signal can be represented as a full signal, indicating whether the first buffer 1i1 is currently full or not. The second state signal can be represented as an almost full signal, indicating whether the first buffer 1i1 is currently almost full or not. The third state signal can be represented as an almost empty signal, indicating whether the first buffer 1i1 is currently almost empty or not. Optionally, the state signals may further include a fourth state signal, which can be represented as an empty signal, indicating whether the first buffer 1i1 is currently empty or not.

[0050] The first arbiter 1i4 is configured to determine the current cache state as the first preset state in response to the first state signal being a first preset value, or to determine the current cache state as the second preset state in response to the first state signal being a second preset value and the second state signal being a first preset value, or to determine the current cache state as the third preset state in response to the second state signal being a second preset value, or to determine the current cache state as the fourth preset state in response to the third state signal being a first preset value.

[0051] Here, the first preset value and the second preset value may be any two different preset values ​​used to represent different semantics. For example, the first preset value may be 1 and the second preset value may be 0, or the first preset value may be 0 and the second preset value may be 1, and the specific values ​​of the first and second preset values ​​are not limited. Embodiments of this disclosure will be explained using the example of the first preset value being 1 and the second preset value being 0.

[0052] In some selective embodiments, a first state signal of a first preset value (e.g., 1) indicates that the current cache state is full (i.e., the first preset state), meaning that the first buffer 1i1 is currently full. A first state signal of a second preset value (e.g., 0) indicates that the first buffer 1i1 is not currently full. Further determining the current cache state of the first buffer 1i1 based on the second state signal, where the second state signal is a first preset value (e.g., 1), indicates that the first buffer 1i1 is currently nearly full but not yet full (abbreviated as near-full) (i.e., the second preset state), meaning that the first buffer 1i1 is already approaching full and there is little remaining usable cache space. If the second state signal is a second preset value (e.g., 0), it indicates that the first buffer 1i1 is not currently nearly full (i.e., in the third preset state), meaning that the current amount of memory in the first buffer 1i1 does not meet the nearly full condition (e.g., the occupancy ratio is less than the third threshold). If the third state signal is a first preset value (e.g., 1), it indicates that the first buffer 1i1 is currently nearly empty (i.e., in the fourth preset state), meaning that the current amount of memory in the first buffer 1i1 is very small and close to empty.

[0053] In the embodiments of this disclosure, three state signals determine the current cache state of the first buffer and provide an accurate and effective criterion for determining the data transmission priority between the first memory and the second processing element.

[0054] In some selective embodiments, the first arbiter 1i4 is configured to determine the data transmission priority so as to preferentially acquire the data to be transmitted from the second processing element 1k in response to the current cache state being the second preset state, or to determine the data transmission priority so as to be the same for the second processing element 1k and the first memory 1i2 in response to the current cache state being the third or fourth preset state.

[0055] Here, if the current cache state is the second preset state, it means that the first buffer 1i1 is currently in a near-full state and there is little remaining free cache space. To avoid all buffers on the data transmission path becoming full, the priority of the second processing element 1k is determined to be higher than that of the first memory 1i2. The data to be transmitted is then preferentially retrieved from the buffer 1k1 of the second processing element 1k, freeing up some cache space from the buffer of the second processing element 1k. This ensures that at least one buffer on the data transmission path is not full, thus avoiding a deadlock problem. If the current cache state is the third or fourth preset state, it means that the first buffer 1i1 is not currently nearly full, has sufficient free cache space, and can support obtaining data to be transmitted from both the second processing element 1k and the first memory 1i2. Therefore, the data transmission priority is determined so that the priority of the second processing element 1k and the first memory 1i2 are the same. If both the first data from the second processing element 1k and the second data from the first memory 1i2 currently exist, the first data and the second data can be cached in the first buffer 1i1 as data to be transmitted, respectively. What should be understood is that if the data transmission priority is the same for the second processing element 1k and the first memory 1i2, if only the first data from the second processing element 1k currently exists, the first data will be used as the data to be transmitted. If only the second data from the first memory 1i2 currently exists, the second data will be used as the data to be transmitted.

[0056] In the embodiments of this disclosure, if the current cache state of the first buffer is near full, the remaining free cache space is small. Therefore, by preferentially obtaining the data to be transmitted from the second processing element, the buffer of the second processing element can free up some of the cache space. This ensures that there is always at least one buffer that is not full on the data transmission path, effectively avoiding deadlock problems.

[0057] In some selective embodiments, the first arbiter 1i4 is configured to determine the data transmission priority so that, in response to the current cache state being a second preset state, it retrieves the first data only from the second processing element 1k as data to be transmitted and temporarily suspends data acquisition from the first memory 1i2.

[0058] Here, if the current cache state is the second preset state, it indicates that the first buffer 1i1 is currently in a near-full state and that there is little remaining free cache space. In this case, the data transmission priority is determined so that only the data to be transmitted is retrieved from the second processing element 1k, and data retrieval from the first memory 1i2 is temporarily suspended. That is, only the first data from the second processing element is cached in the first buffer 1i1 as the data to be transmitted, and the second data from the first memory 1i2 is not retrieved temporarily.

[0059] In the embodiments of this disclosure, when the first buffer is near full, it is supported to obtain the data to be transmitted only from the second processing element, temporarily suspending data acquisition from the first memory, ensuring that there is always at least one buffer that is not full on the data transmission path, thereby effectively avoiding deadlock problems.

[0060] In some selective embodiments, the first arbiter is further configured to pause data acquisition from the first memory 1i2, and then, in response to a change in the current cache state to a third or fourth preset state, resume acquisition of the data to be transmitted from the first memory 1i2 and cache the data to be transmitted in the first buffer 1i1.

[0061] Here, after temporarily suspending data acquisition from the first memory 1i2, as data continues to flow and each processing element continues to operate, the cache state of the first buffer 1i1 can change in real time. When the current cache state changes from the second preset state to the third or fourth preset state, it indicates that the current cache state of the first buffer 1i1 has changed to a state that is not nearly full or nearly empty, and there is sufficient cache space to support simultaneously caching data from the second processing element 1k and data from the first memory 1i2. Therefore, the acquisition of data to be transmitted from the first memory 1i2 can be resumed and the data to be transmitted can be cached in the first buffer 1i1.

[0062] In the embodiments of this disclosure, when the first buffer is in a near-full state, the acquisition of data to be transmitted from the first memory is temporarily suspended to avoid a deadlock problem. The acquisition of data to be transmitted from the first memory is then resumed until the current cache state of the first buffer can support simultaneously caching the data to be transmitted from the first memory and the second processing element. The data to be transmitted is then cached in the first buffer, maintaining data transmission efficiency while ensuring that a deadlock problem does not occur.

[0063] In some selective embodiments, based on any of the above embodiments, the first processing element 1i is configured to acquire data to be transmitted from the second processing element 1k in response to the data transmission priority of the second processing element 1k being higher than the data transmission priority of the first memory 1i2, or to acquire data to be transmitted from both the second processing element 1k and the first memory 1i2 in response to the data transmission priorities of the second processing element 1k and the first memory 1i2 being the same.

[0064] Here, if the data transmission priority of the second processing element 1k is higher than the data transmission priority of the first memory 1i2, the data to be transmitted is preferentially retrieved from the second processing element 1k, allowing the buffer of the second processing element 1k to free up some of its cache space, thus avoiding a situation where all buffers on the data transmission path become full. After preferentially retrieving the data to be transmitted from the second processing element 1k and caching the data to be transmitted in the first buffer 1i1, if the first buffer 1i1 can store more data from the first memory 1i2, the data to be transmitted can then be retrieved from the first memory 1i2 and cached in the first buffer 1i1.

[0065] It should be explained that, in the embodiments of this disclosure, for any processing element 1i, the data to be transmitted is a general term for data that needs to be transmitted at the present time as it changes in real time, and does not refer to specific data; that is, any data to be transmitted acquired at any point in time is called the data to be transmitted, and data acquired from the second processing element 1k can be called the data to be transmitted, and data acquired from the first memory 1i2 can also be called the data to be transmitted. If the first data from the second processing element 1k and the second data from the first memory 1i2 exist simultaneously at the same time, the first data or the second data is determined to be the data to be transmitted, or both the first data and the second data are determined to be the data to be transmitted, based on the data transmission priority of the second processing element 1k and the first memory 1i2.

[0066] In the embodiments of this disclosure, if the data transmission priority of the second processing element 1k is higher than the data transmission priority of the first memory 1i2, the data to be transmitted can be obtained from the second processing element 1k, freeing up some cache space from the buffer of the second processing element 1k, ensuring that there is always at least one buffer that is not full on the data transmission path, and effectively avoiding deadlock problems. If the data transmission priorities of the second processing element 1k and the first memory 1i2 are the same, the data to be transmitted can be obtained from both the second processing element 1k and the first memory 1i2, respectively, ensuring data transmission efficiency.

[0067] In some selective embodiments, the first arbiter 1i4 is further configured to pause the acquisition of data to be transmitted in response to the current cache state being a first preset state.

[0068] Here, if the current cache state of the first buffer 1i1 is the first preset state, it indicates that the first buffer 1i1 is currently full and cannot store new data. Therefore, the acquisition of data to be transmitted is temporarily suspended, and a situation where data loss occurs due to the inability to cache acquired data can be effectively avoided.

[0069] In some selective embodiments, after temporarily suspending the acquisition of data to be transmitted, the acquisition of data to be transmitted from the second processing element 1k may be resumed in response to a change in the current cache state to a second preset state, and the acquisition of data to be transmitted from the second processing element 1k and the first memory 1i2 may be resumed in response to a change in the current cache state to a third or fourth preset state. This allows for the dynamic adjustment of the data source for the data to be transmitted or the temporary suspension of the acquisition of data to be transmitted based on real-time changes in the cache state of the first buffer 1i1, thereby ensuring smooth data transmission on the data transmission path and avoiding deadlock problems.

[0070] In some selective embodiments, the current cache state of the first buffer 1i1 can be represented as a combination of different preset values ​​for the first, second, third, and fourth state signals. That is, the data transmission priority between the second processing element 1k and the first memory 1i2 can be directly determined based on the specific status of the state signals output by the first buffer 1i1. The operation of determining the current cache state based on the state signals, and then determining the data transmission priority based on the current cache state, is simplified to an operation of determining the data transmission priority based on the state signals. For example, the first arbiter 1i4 is configured to determine the data transmission priority so as to preferentially acquire the data to be transmitted from the second processing element 1k in response to the first state signal being a second preset value and the second state signal being a first preset value, that is, to determine that the priority of the second processing element 1k is higher than the priority of the first memory 1i2, and to determine the data transmission priority so as to be the same as that of the second processing element 1k and the first memory 1i2 in response to the second state signal being a second preset value and / or the third state signal being a first preset value.

[0071] In some selective embodiments, the first arbiter 1i4 is further configured to determine data transmission priority so as to acquire only the first data from the second processing element 1k as data to be transmitted, and to temporarily suspend data acquisition from the first memory 1i2, in response to the first state signal being a second preset value and / or the third state signal being a first preset value, and to resume acquiring the data to be transmitted from the first memory 1i2 and cache the data to be transmitted in the first buffer 1i1, in response to the second state signal changing to a second preset value and / or the third state signal being a first preset value.

[0072] In some selective embodiments, the first arbiter 1i4 is further configured to pause the acquisition of data to be transmitted in response to the first state signal being a first preset value.

[0073] In some selective embodiments, the functionality of the first arbiter 1i4 in any of the above embodiments can be realized by one or more hardware logic devices such as comparators, data selectors, AND gates, OR gates, and NOT gates. For example, AND gates, OR gates, NOT gates, etc., can be used to configure a logic component that determines the current cache state based on a state signal and is used as a logic component that triggers data transmission priority in different preset states. The data transmission priority logic component can selectively connect the second processing element 1k and the first memory 1i2 by a data selector, and the acquisition of data to be transmitted can be paused or resumed by enable control of the data selector. The specific structure of the first arbiter is not described in detail. By realizing the first arbiter in hardware, processing efficiency is effectively improved, thereby improving the real-time nature of data transmission.

[0074] In some selective embodiments, when the current cache state of the first buffer 1i1 is the second preset state, there are two different data transmission priority types: one that preferentially acquires the data to be transmitted from the second processing element (referred to as the first type), and another that acquires the data to be transmitted only from the second processing element and temporarily suspends data acquisition from the first memory (referred to as the second type). Therefore, for any two processing elements in an integrated circuit, both processing elements may adopt the first type, both may adopt the second type, or the two processing elements may each adopt the first type and the second type, and are not specifically limited.

[0075] Figure 4 is a schematic diagram of a processing element provided by one exemplary embodiment of the present disclosure.

[0076] In some selective embodiments, as shown in Figure 4, the first interface 1i3 may include a second arbiter 1i31.

[0077] The second arbiter 1i31 is configured to receive third data from the second processing element 1k, transmit the third data to the first arbiter 1i4 based on the configured transmission control information, and / or store the third data in the first memory 1i2.

[0078] Here, the transmission control information is pre-configured setting information for controlling the flow method of data (called third data) from the second processing element 1k, and the transmission control information may include control information that instructs whether or not to transmit the third data from the second processing element 1k to the first arbiter 1i4, and control information that instructs whether or not to store the third data in the local first memory 1i2.

[0079] In some selective embodiments, if it is determined based on transmission control information that the third data needs to be transmitted only to the first arbiter 1i4, the third data is transmitted to the first arbiter 1i4 and does not need to be stored in the local first memory 1i2. If it is determined based on transmission control information that the third data needs to be stored only in the local first memory 1i2, the third data is stored in the local first memory 1i2. If it is determined based on transmission control information that the third data needs to be transmitted to the first arbiter 1i4 and stored in the local first memory 1i2, the third data is transmitted to the first arbiter 1i4 and stored in the local first memory 1i2. The specific data flow path is set based on the needs of the actual application scene and is not limited to the embodiments of this disclosure. For example, in an intelligent drive scene, the sensing result of a sensing processing element can be stored in a local memory in a positioning processing element, and the sensing result can be cached in a buffer by the first arbiter of the positioning processing element and further transmitted to a planning control element via the buffer. The sensing results stored in the local memory of the positioning processing element are used in the positioning process to obtain a positioning result, which is stored in the local memory. Furthermore, the first arbiter caches the positioning result stored in the local memory in a buffer and transmits it to the planning control element via the buffer. That is, the planning control element can read the sensing results and positioning results from the buffer of the positioning processing element, and further performs planning and control based on the sensing results and positioning results to control the driving state of the vehicle.

[0080] In some selective embodiments, the second arbiter 1i31 is connected to the first arbiter 1i4 and the first memory 1i2, respectively.

[0081] In some selective embodiments, when third data from the second processing element 1k is transmitted to the first arbiter 1i4, the third data becomes the first data from the second processing element in the above embodiment.

[0082] In the embodiments of this disclosure, the data flow from the second processing element is controlled by the second arbiter in the first interface, enabling each processing element to acquire the necessary data or transmit data to the next processing element, thereby achieving an effective data flow and ensuring the normal operation of each processing element.

[0083] In some selective embodiments, the second arbiter 1i31 can be implemented by any means, such as hardware, software, or a combination of hardware and software. For example, the second arbiter 1i31 can ensure real-time data transmission by implementing the corresponding arbitration function using combinational logic circuitry.

[0084] In some selective embodiments, the first processing element 1i may include a second interface, the second interface including a first arbiter 1i4 and a first buffer 1i1. The first interface 1i3 may be called a Slave Interface, and the second interface may be called a Master Interface. Figure 5 is a schematic diagram of an integrated circuit for data transmission provided by yet another exemplary embodiment of the present disclosure. As shown in Figure 5, each processing element 1i includes a Slave Interface (i.e., a first interface 1i3), a Master Interface (i.e., a second interface), and Memory (i.e., a first memory), the Master Interface including a first arbiter (i.e., ARB1) and a first buffer (a FIFO is used as an example in the figure). The Slave Interface includes an ARB2 (i.e., a second arbiter).The data loop is as shown by the flow of arrows in the diagram. Processing element 11 receives data A from processing element 1n via the Slave Interface, that is, reads data A from processing element 1n's FIFO via the Slave Interface, allowing processing element 1n's FIFO to release some cache space so that new data can be transmitted continuously. ARB2 transmits data A to ARB1 and / or stores data A in Memory based on the set transmission control information. When data A has been transmitted to ARB1 and data B to be transmitted also exists in Memory in processing element 11, ARB1 in processing element 11 processes data B with processing element 1n based on the FIFO status signal. The data transmission priority of Memory in element 11 is determined, and based on the data transmission priority, data A and / or data B are designated as data to be transmitted. For example, if the data transmission priority of processing element 1n is higher than that of Memory in processing element 11, data A is given priority as data to be transmitted. If the data transmission priority of processing element 1n is the same as that of Memory in processing element 11, both data A and data B are designated as data to be transmitted. The data to be transmitted is cached in a FIFO. A cascade circuit downstream of processing element 11 (e.g., processing element 12) reads data C (which may be data A and / or data B, and may be data that was cached before data A and / or B were cached) from the FIFO of processing element 11 via the Slave Interface, causing the FIFO of processing element 11 to free up some of its cache space. This process is repeated so that at least one FIFO always has free cache space during the data loop, ensuring data transmission efficiency and avoiding situations where all FIFOs become full.For example, if priority is not considered, processing element 11 continuously acquires data to be transmitted from processing element 1n and Memory, meaning that each time data A and data B are acquired, they are both cached in the FIFO. However, since the cache space of the FIFO is finite, and data is constantly being added from Memory while data from other FIFOs also exists, each FIFO may become full. For example, after one loop data transmission, only processing element 11's FIFO still has a small amount of free cache space, while the FIFOs of the other processing elements are all already full. At this point, if processing element 11 acquires data B from Memory again and caches it in the FIFO, processing element 11's FIFO will also become full, and all FIFOs in the loop will become full, leaving no remaining free cache space to support the data flow in the loop, thus causing a loop deadlock problem. In any embodiment of the present disclosure, the first processing element can determine the data source for data to be cached in the FIFO based on the real-time cache state of its internal FIFO. If the free cache space of the FIFO is small, it preferentially caches data from the FIFO of the preceding cascaded second processing element in the first processing element's internal FIFO. Even if the first processing element's internal FIFO becomes full at this time, the second processing element's FIFO will release some cache space because the data cached this time is from the second processing element's FIFO, thus allowing the loop data flow to continue to be supported. This ensures that there is always at least one FIFO that is not full in the loop, effectively avoiding deadlock problems in loop data transmission.

[0085] In some selective embodiments, the Master Interface in the first processing element 1i may include a control unit connected to a local FIFO and a subsequent cascade circuit, respectively. When valid data exists in the FIFO, the control unit raises the Valid (data valid) signal connected to the subsequent cascade circuit to a high level (indicating validity), allowing the subsequent cascade circuit to read the data from the FIFO buffer. The principles of reading and writing to the FIFO are not described in detail.

[0086] Each of the embodiments described herein may be implemented individually or combined in any non-conflicting manner, specifically based on actual needs, and this disclosure is not limited thereto.

[0087] Exemplary Method Figure 6 is a flowchart of a data transmission method provided by one exemplary embodiment of the present disclosure. The method of this embodiment can be implemented by corresponding integrated circuit embodiments of the present disclosure, and the method shown in Figure 6 may include steps 210 to 230.

[0088] In step 210, the data transmission priority between the first memory in the first processing element and the cascaded second processing element preceding the first processing element is determined based on the current cache state of the first buffer in the first processing element.

[0089] In step 220, the data to be transmitted is acquired based on the data transmission priority.

[0090] In step 230, the data to be transmitted is cached in the first buffer, and the data to be transmitted can be read by the cascade circuit following the first processing element.

[0091] Here, the specific structure and interconnection relationships of the first and second processing elements, as well as the specific operations of each step, can be found in the previously described embodiments and will not be explained here.

[0092] Figure 7 is a flowchart of a data transmission method provided by another exemplary embodiment of the present disclosure.

[0093] In some selective embodiments, based on the embodiment shown in Figure 6, step 220, which acquires the data to be transmitted based on the data transmission priority, may include steps 2210 and 2220.

[0094] In step 2210, in response to the data transmission priority of the second processing element being higher than the data transmission priority of the first memory, the data to be transmitted is obtained from the second processing element.

[0095] In step 2220, in response to the fact that the data transmission priority of the second processing element and the first memory is the same, the data to be transmitted is obtained from the second processing element and the first memory.

[0096] Figure 8 is a flowchart of a data transmission method provided by another exemplary embodiment of the present disclosure.

[0097] In some selective embodiments, the method of the embodiment of the present disclosure may further include step 310 on the basis of any of the embodiments described above.

[0098] In step 310, the first data from the second processing element is received based on the first interface in the first processing element.

[0099] Step 210, which determines the data transmission priority between the first memory in the first processing element and the cascaded second processing element preceding the first processing element based on the current cache state of the first buffer in the first processing element, may include step 2110.

[0100] In step 2110, the first arbiter in the first processing element determines the data transmission priority between the first memory and the second processing element based on the current cache state of the first buffer.

[0101] Step 220, which acquires the data to be transmitted based on the data transmission priority, may include step 22a0.

[0102] In step 22a0, based on the data transmission priority, at least one of the first data and the second data in the first memory is determined to be the data to be transmitted.

[0103] Figure 9 is a flowchart of a data transmission method provided by another exemplary embodiment of the present disclosure.

[0104] In some selective embodiments, the method of the embodiment of the present disclosure may further include step 410 on the basis of any of the embodiments described above.

[0105] In step 410, the current cache state of the first buffer is determined based on the status signal output by the first buffer.

[0106] Figure 10 is a flowchart of a data transmission method provided by another exemplary embodiment of the present disclosure.

[0107] In some selective embodiments, the status signal includes a first status signal, a second status signal, and a third status signal. As shown in Figure 10, step 410, which determines the current cache state of the first buffer based on the status signal output by the first buffer, may include steps 4110 to 4140.

[0108] In step 4110, in response to the first state signal of the first buffer being the first preset value, the current cache state is determined to be the first preset state.

[0109] In step 4120, the current cache state is determined to be the second preset state in response to the first state signal of the first buffer being the second preset value, and the second state signal being the first preset value.

[0110] In step 4130, in response to the second state signal of the first buffer being the second preset value, the current cache state is determined to be the third preset state.

[0111] In step 4140, in response to the third state signal of the first buffer being the first preset value, the current cache state is determined to be the fourth preset state.

[0112] In some selective embodiments, as shown in Figure 10, step 210, which determines the data transmission priority between the first memory in the first processing element and the cascaded second processing element preceding the first processing element based on the current cache state of the first buffer in the first processing element, may include steps 21a0 and 21b0.

[0113] In step 21a0, in response to the current cache state being the second preset state, the data transmission priority is determined so that the data to be transmitted is preferentially retrieved from the second processing element.

[0114] In step 21b0, in response to the current cache state being either the third or fourth preset state, the data transmission priority is determined such that the priority of the second processing element and the first memory are the same.

[0115] It should be explained that there is no distinction in priority between the execution of step 21a0 and step 21b0.

[0116] In some selective embodiments, step 210, which determines the data transmission priority between a first memory in a first processing element and a cascaded second processing element preceding the first processing element, based on the current cache state of a first buffer in the first processing element, may include a step of determining the data transmission priority such that, in response to the current cache state being a second preset state, the first data is acquired only from the second processing element as data to be transmitted, and data acquisition from the first memory is temporarily suspended.

[0117] In some selective embodiments, the method of the embodiments of the present disclosure may further include the step of pausing data retrieval from a first memory, then resuming retrieval of data to be transmitted from the first memory in response to a change in the current cache state to a third preset state or a fourth preset state, and caching the data to be transmitted in a first buffer.

[0118] In some selective embodiments, the methods of the embodiments of the present disclosure may further include the step of pausing the acquisition of data to be transmitted in response that the current cache state is a first preset state.

[0119] Figure 11 is a flowchart of a data transmission method provided by another exemplary embodiment of the present disclosure.

[0120] In some selective embodiments, the method of the embodiment of the present disclosure may further include steps 510 to 520, as shown in Figure 11, on the basis of any of the embodiments described above.

[0121] In step 510, the third data is received from the second processing element.

[0122] In step 520, based on the configured transmission control information, the third data is transmitted to the first arbiter in the first processing element, and / or stored in the first memory in the first processing element.

[0123] Each step of the above embodiments of the disclosure can be performed by the corresponding component in the embodiment of the integrated circuit, and a detailed description is omitted.

[0124] Each of the embodiments described herein may be implemented independently or combined in any non-conflicting manner, specifically based on actual needs, and this disclosure is not limited thereto.

[0125] The beneficial technical effects corresponding to exemplary embodiments of this method can be found by referring to the corresponding beneficial technical effects of the exemplary integrated circuit portion described above, and are therefore omitted from this explanation.

[0126] Any one of the data transmission methods provided by the embodiments of this disclosure can be performed by any suitable electronic device having data processing capabilities, including, but not limited to, electronic devices such as terminal devices and servers. Alternatively, any one of the data transmission methods provided by the embodiments of this disclosure can be performed by a processor, for example, by calling a corresponding command stored in memory to perform any one of the data transmission methods described in the embodiments of this disclosure. Further explanation is omitted below.

[0127] Exemplary electronic device Figure 12 is a structural diagram of an electronic device provided by an embodiment of the present disclosure, the electronic device 90 including at least one processor 91 and a second memory 92.

[0128] The processor 91 may be a central processing unit (CPU) or another form of processing unit having data processing capability and / or instruction execution capability, and can control other components in the electronic device 90 to perform desired functions.

[0129] The second memory 92 may include one or more computer program products, including various forms of computer-readable storage media such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or high-speed cache memory (cache). Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions can be stored in the computer-readable storage media, and the processor 91 can execute one or more computer program instructions to realize the methods of each embodiment of the present disclosure described above and / or other desired functions.

[0130] In one example, the electronic device 90 may further include an input device 93 and an output device 94, and these components are connected to each other via a bus system and / or other forms of connection mechanisms (not shown).

[0131] The input device 93 may further include, for example, a touchscreen, a microphone, and various sensors. Sensors may include, for example, image sensors (e.g., cameras, video cameras), laser radar, millimeter-wave radar, ultrasonic radar, positioning sensors, pressure sensors, air mass sensors, and temperature sensors. Image sensors, laser radar, millimeter-wave radar, and ultrasonic radar can be used to sense the surrounding environment, that is, to detect dynamic and static objects in the surrounding environment. Dynamic and static objects may include, for example, static objects such as lane markings, road curbs, arrows, signs, trees, and buildings, and dynamic objects such as surrounding vehicles, pedestrians, and cyclists. Positioning sensors are used to position the mobile device on which the electronic device is located (e.g., a vehicle, a robot, etc.). Positioning sensors may include, for example, an inertial measurement unit (IMU) and a global positioning system (GPS). Pressure sensors can be used to detect seat pressure. A temperature sensor can be used to detect the temperature inside the vehicle's cabin. An air mass sensor can be used to detect the air mass inside the vehicle's cabin.

[0132] The output device 94 can output various types of information to the outside, and may include, for example, a display, speaker, printer, communication network, and remote output devices connected thereto.

[0133] Naturally, for the sake of simplification, only the components of the electronic device 90 relevant to this disclosure are shown in Figure 12, and components such as buses and input / output interfaces are omitted. Beyond this, the electronic device 90 may include any other appropriate components depending on the specific application.

[0134] Embodiments of the present disclosure further provide a chip which includes an integrated circuit for data transmission provided in any of the embodiments described above.

[0135] Exemplary computer program products and computer-readable storage media In addition to the methods and apparatus described above, embodiments of the present disclosure may also provide a computer program product that, when executed by a processor, includes computer program instructions that cause the processor to perform steps of the various embodiments of the present disclosure described in the “Exemplary Methods” section above.

[0136] Computer program products can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and common procedural programming languages ​​such as the C language or similar programming languages, to create program code for performing the operations of the embodiments of this disclosure. The program code may run entirely on a user computing device, partially on a user computing device, as a standalone software package, partially on a user computing device, partially on a remote computing device, or entirely on a remote computing device or server.

[0137] In addition, embodiments of the present disclosure may further be a computer-readable storage medium storing computer program instructions that, when executed by a processor, cause the processor to perform the steps of the various embodiments of the present disclosure described in the “Exemplary Methods” section above.

[0138] Computer-readable storage media may employ any combination of one or more readable media. The readable media may be readable signal media or readable storage media. Readable storage media may include, but are not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any combination thereof. More specific examples (non-exclusive list) of readable storage media include electrical connections with one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above.

[0139] While the basic principles of this disclosure have been explained above with reference to specific examples, the advantages, advantages, and effects mentioned in this disclosure are merely illustrative and not limiting, and it is not assumed that these advantages, advantages, and effects must be present in each example of this disclosure. Furthermore, the specific details disclosed above are merely illustrative and intended to facilitate understanding, and are not limiting, nor do they imply that this disclosure must be implemented in the specific details described above.

[0140] Those skilled in the art can make various modifications and variations to this disclosure without departing from the spirit and scope of the application. Thus, if such modifications and variations of the application fall within the scope of the claims of this disclosure and the equivalent art, this disclosure is intended to include such modifications and variations.

Claims

1. It includes at least two processing elements, The first processing element of any of the at least two processing elements includes a first buffer and a first memory, The first processing element is, Based on the current cache state of the first buffer, the data transmission priority between the first memory and the cascaded second processing element preceding the first processing element is determined. Based on the aforementioned data transmission priority, acquire the data to be transmitted, An integrated circuit for data transmission, configured to cache the data to be transmitted in the first buffer so that the data to be transmitted can be read by a cascade circuit downstream of the first processing element.

2. The first processing element is, In response to the data transmission priority of the second processing element being higher than the data transmission priority of the first memory, the data to be transmitted is acquired from the second processing element, or The data transmission integrated circuit according to claim 1, configured to acquire the data to be transmitted from the second processing element and the first memory in response to the fact that the data transmission priority of the second processing element and the first memory is the same.

3. The first processing element is, A first interface for receiving first data from the second processing element, The first arbitrage, and further, The aforementioned first arbiter is, The data transmission integrated circuit according to claim 1, configured to determine the data transmission priority between the first memory and the second processing element based on the current cache state of the first buffer, determine at least one of the first data received by the first interface and the second data in the first memory as the data to be transmitted based on the data transmission priority, and cache the data to be transmitted in the first buffer.

4. The aforementioned first arbiter further, The data transmission integrated circuit according to claim 3, configured to determine the current cache state of the first buffer based on a state signal output by the first buffer.

5. The status signal includes a first status signal, a second status signal, and a third status signal. The aforementioned first arbiter is, In response to the above first state signal being a first preset value, the current cache state is determined to be the first preset state, or In response to the first state signal being a second preset value and the second state signal being a first preset value, the current cache state is determined to be the second preset state, or In response to the second state signal being the second preset value, the current cache state is determined to be the third preset state, or The data transmission integrated circuit according to claim 4, configured to determine the current cache state as a fourth preset state in response to the third state signal being a first preset value.

6. The aforementioned first arbiter is, In response to the current cache state being the second preset state, the data transmission priority is determined so as to preferentially acquire the data to be transmitted from the second processing element, or The data transmission integrated circuit according to claim 3, configured to determine the data transmission priority such that the priority of the second processing element and the first memory are the same, in response to the current cache state being a third preset state or a fourth preset state.

7. The aforementioned first arbiter is, The data transmission integrated circuit according to claim 3, configured to determine the data transmission priority so as to acquire the first data as the data to be transmitted only from the second processing element and to temporarily suspend data acquisition from the first memory, in response to the current cache state being a second preset state.

8. The aforementioned first arbiter is, The data transmission integrated circuit according to claim 7, configured to temporarily suspend data acquisition from the first memory, and then, in response to a change in the current cache state to a third preset state or a fourth preset state, resume acquisition of data to be transmitted from the first memory and cache the data to be transmitted in the first buffer.

9. The aforementioned first arbiter is, The data transmission integrated circuit according to claim 3, configured to temporarily suspend the acquisition of the data to be transmitted in response to the current cache state being a first preset state.

10. The first interface includes a second arbiter, The previous second arbiter was, The third data is received from the second processing element. The data transmission integrated circuit according to claim 3, configured to transmit the third data to the first arbiter and / or store the third data in the first memory based on the set transmission control information.

11. A step of determining the data transmission priority between a first memory in the first processing element and a cascaded second processing element preceding the first processing element, based on the current cache state of a first buffer in the first processing element. Based on the aforementioned data transmission priority, the steps include acquiring the data to be transmitted, A data transmission method performed by an integrated circuit for data transmission, comprising the step of caching the data to be transmitted in a first buffer so that the data to be transmitted can be read by a cascade circuit downstream of the first processing element.

12. A computer-readable storage medium that stores a computer program for performing the data transmission method described in claim 11 when executed by a processor.

13. Processor and The processor includes a second memory for storing executable instructions, The processor is an electronic device used to read and execute the executable instructions from the second memory to realize the data transmission method described in claim 11.

14. A chip comprising an integrated circuit for data transmission according to any one of claims 1 to 10.

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