Indication device

Abstract

To provide a display device that offers improved design flexibility when arranging multiple transistors in a multi-layered subpixel circuit. [Solution] A display device according to one embodiment of this specification includes a substrate containing a plurality of subpixels, a plurality of first signal lines arranged on the substrate, a first buffer layer arranged on the plurality of first signal lines, a first transistor arranged on the first buffer layer and electrically connected to one of the plurality of first signal lines, a second buffer layer arranged on the first transistor, and a second transistor arranged on the second buffer layer.

Description

Technical Field

[0001] This specification relates to a display device.

Background Art

[0002] The field of display devices for visually displaying electrical information signals has been rapidly developing, and research continues to improve the performance of various display devices, such as thinning, weight reduction, and low power consumption.

[0003] Typical display devices include liquid crystal displays (LCDs), field emission displays (FEDs), electro-wetting displays (EWDs), and organic light-emitting displays (OLEDs). Among them, field emission displays represented by organic light-emitting displays are self-emitting display devices. Different from liquid crystal displays, they do not require a separate light source and can realize a lighter and thinner display device.

[0004] In order to provide a high-resolution video while minimizing the design area in a display device, transistors constituting a sub-pixel circuit can be arranged in multiple layers. However, when the signal wiring of the sub-pixel circuit is arranged relatively in the upper layer on the substrate in the display device, the design of contact holes for connecting the signal wiring from the upper part to the lower part is inevitable, and there is a problem that other components cannot be designed to overlap in the lower region of the signal wiring.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem to be solved by this specification is to provide a display device with improved design freedom when arranging a plurality of transistors in multiple layers in a sub-pixel circuit.

[0006] The problems that this specification seeks to solve are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] A display device according to one embodiment of this specification includes a substrate containing a plurality of subpixels, a plurality of first signal lines disposed on the substrate, a first buffer layer disposed on the plurality of first signal lines, a first transistor disposed on the first buffer layer and electrically connected to one of the plurality of first signal lines, a second buffer layer disposed on the first transistor, and a second transistor disposed on the second buffer layer.

[0008] Other embodiments of this specification include a substrate containing a plurality of subpixels, a light-emitting element contained in each of the plurality of subpixels, a plurality of first signal lines arranged on the substrate and including data lines that supply a data voltage and high-potential power supply lines that supply a high-potential power supply voltage, and a plurality of subpixel circuits arranged on the substrate for each of the plurality of subpixels and electrically connected to the plurality of first signal lines. In this case, the plurality of subpixel circuits include a first transistor including a first electrode connected to the high-potential power supply line, a gate electrode to which a second light-emitting signal is input, and a second electrode connected to a first node connected to the first electrode of a drive transistor that drives the light-emitting element, and a second transistor including a first electrode connected to a second node connected to the second electrode of the drive transistor, a gate electrode to which a second scan signal is input, and a second electrode connected to the data line. In this case, a plurality of first signal lines are arranged below the first transistor and the second transistor.

[0009] Another embodiment of this specification includes a substrate containing a plurality of subpixels, a plurality of first signal lines disposed on the substrate, a first buffer layer disposed on the plurality of first signal lines, and a first transistor disposed on the first buffer layer and electrically connected to one of the plurality of first signal lines, and comprising a first electrode, a gate electrode, a second electrode, and a semiconductor layer. In this case, the first electrode of the first transistor is superimposed on one of the first signal lines and electrically connected to either one of the first signal lines or the semiconductor layer of the first transistor through one contact hole formed continuously through the first buffer layer.

[0010] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0011] According to this specification, signal wiring can be placed on the bottom layer of the substrate, and multilayer transistors can be placed on top of the signal wiring, which has the effect of increasing design flexibility.

[0012] Furthermore, according to this specification, it is possible to reduce the design area without requiring significant changes to the arrangement of the subpixel circuit components, while still enabling high-resolution video.

[0013] The effects relating to this specification are not limited to those exemplified above, and a wider variety of effects are described herein. [Brief explanation of the drawing]

[0014] [Figure 1] This is a block diagram of a display device according to one embodiment of this specification. [Figure 2] This is a pixel circuit diagram of a display device according to one embodiment of this specification. [Figure 3a] This is a schematic enlarged plan view of the display area of ​​a display device according to one embodiment of this specification. [Figure 3b] This is a schematic enlarged plan view of the display area of ​​a display device according to one embodiment of this specification. [Figure 3c] This is a schematic enlarged plan view of the display area of ​​a display device according to one embodiment of this specification. [Figure 3d] This is a schematic enlarged plan view of the display area of ​​a display device according to one embodiment of this specification. [Figure 3e] This is a schematic enlarged plan view of the display area of ​​a display device according to one embodiment of this specification. [Figure 3f] This is a schematic enlarged plan view of the display area of ​​a display device according to one embodiment of this specification. [Figure 3g] This is a schematic enlarged plan view of the display area of ​​a display device according to one embodiment of this specification. [Figure 3h] This is an enlarged plan view of the display area of ​​a display device according to one embodiment of this specification. [Figure 4] This is a cross-sectional view of a subpixel of a display device according to one embodiment of this specification. [Figure 5] This is a cross-sectional view illustrating an example of a structure in which a metal pattern of a display device according to one embodiment of this specification is in contact with an active layer. [Figure 6] This is a cross-sectional view illustrating another example of a structure in which a metal pattern of a display device according to one embodiment of this specification is in contact with an active layer. [Modes for carrying out the invention]

[0015] The advantages and features of this specification, and the methods for achieving them, will become clearer with reference to the examples described below in detail with the accompanying drawings. However, this specification is not limited to the examples disclosed below, which can be embodied in a variety of different shapes, and these examples are provided simply to make the disclosure of this specification complete and to fully inform a person with ordinary skill in the art to which this specification belongs of the scope of one example of this specification.

[0016] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary, so the embodiments of this specification are not limited to the matters illustrated. Throughout the specification, the same reference numerals refer to the same components. Also, when explaining an embodiment of this specification, if it is determined that a detailed description of related known technologies may obscure the gist of an embodiment of this specification, that detailed description will be omitted. When terms such as "including", "having", "being made" mentioned in this specification are used, other parts can be added as long as "only" is not used. When a component is expressed in the singular, it includes the case of including a plurality unless there are specific descriptions to the contrary.

[0017] When interpreting a component, it is interpreted as including an error range even without separate explicit descriptions.

[0018] When it is an explanation of a positional relationship, for example, when a two-part positional relationship such as "on", "above", "below", "next to", etc. is described, one or more other parts may be located between the two parts as long as "immediately" or "directly" is not used.

[0019] An element or layer referred to as "on" another element or layer includes both the case where there is no other layer or other element intervening immediately above the other element and the case where there is another layer or other element intervening in the middle.

[0020] Also, first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical idea of this specification.

[0021] Throughout the specification, the same reference numerals refer to the same components.

[0022] The area and thickness of each component shown in the drawings are provided for illustrative purposes only, and the embodiments described herein are not necessarily limited to the area and thickness of the components shown.

[0023] The features of each of the various embodiments described herein can be combined or combined with one another, either partially or as a whole, enabling a variety of technically diverse interoperability and drive, and each embodiment may be implemented independently of the others or together in relation to one another.

[0024] Examples of this specification will be described below with reference to the drawings.

[0025] Figure 1 is a block diagram of a display device according to one embodiment of this specification.

[0026] Figure 2 is a pixel circuit diagram of a display device according to one embodiment of this specification.

[0027] Referring to Figure 1, the display device 100 according to the embodiment of this specification may include a display panel 110, an image processing unit 10 that transmits signals to the display panel 110, a degradation compensation unit 50, a memory 60, a timing control unit 20, a gate drive unit 30, a data drive unit 40, and a power supply unit 80. The display device 100 according to one embodiment of this specification is not limited thereto. For example, the display device 100 may omit one or more of the components mentioned above by design, and may further include one or more other components.

[0028] The video processing unit 10 outputs drive signals to drive various devices along with the video data supplied from an external source. For example, the drive signals may include data enable signals, vertical synchronization signals, horizontal synchronization signals, and clock signals.

[0029] The timing control unit 20 can receive a drive signal output from the video processing unit 10 and video data modulated by the degradation compensation unit 50. Based on the drive signal input from the video processing unit 10, the timing control unit 20 can generate and output a gate timing control signal GDC for controlling the operation timing of the gate drive unit 30 and a data timing control signal DDC for controlling the operation timing of the data drive unit 40. The timing control unit 20 can control the operation timing of the gate drive unit 30 and the data drive unit 40 to obtain at least one sensing voltage from each subpixel SP and supply it to the degradation compensation unit 50.

[0030] The gate drive unit 30 can output a scan signal to the display panel 110 in response to the gate timing control signal GDC supplied from the timing control unit 20. The gate drive unit 30 can output scan signals and light emission signals through a plurality of gate wirings GL1 to GLm.

[0031] The gate drive unit 30 may, but is not limited to, be formed in the form of an integrated circuit (IC). The gate drive unit 30 may be formed in a GIP (Gate In Panel) structure by directly stacking thin-film transistors on the substrate of the display device 100. The GIP structure may include a number of circuits such as a shift register and a level shifter. The gate drive unit 30 according to one embodiment of this specification is not limited thereto. For example, the gate drive unit 30 may be individually arranged on a separate panel or film. For example, the gate drive unit 30 may be connected to the display panel 110 through a tape automated bonding (TAB) method, a chip on glass (COG) method, a chip on panel (COP) method, or a chip on film (COF) method.

[0032] The data drive unit 40 can output a data voltage to the display panel 110 in response to a data timing control signal DDC input from the timing control unit 20. The data drive unit 40 can sample and latch the digital data signal DATA supplied from the timing control unit 20 and convert it into an analog data voltage based on a gamma voltage. The data drive unit 40 can output the data voltage through a plurality of data lines DL1 to DLn. The data drive unit 40 can supply the sensing voltage input from the display panel 110 to the degradation compensation unit 50. The data drive unit 40 can be mounted on the display panel 110 in the form of an IC (Integrated Circuit), or it can be formed by stacking various patterns directly on the display panel 110, but is not limited to this. For example, the data drive unit 40 can be individually arranged on a separate panel or film. For example, the data drive unit 40 can be connected to the display panel 110 via a tape automated bonding (TAB) method, a chip-on-glass (COG) method, a chip-on-panel (COP) method, or a chip-on-film (COF) method, etc.

[0033] The degradation compensation unit 50 calculates a degradation compensation gain value for each subpixel SP of the display panel 110 based on the sensing voltage supplied from the data drive unit 40, calculates a dimming weight based on the calculated degradation compensation gain value, modulates the input video data of each subpixel SP of the current frame using the calculated degradation compensation gain value and dimming weight, and then supplies the modulated video data to the timing control unit 20. For example, the degradation compensation unit 50 may be omitted depending on the design of the display device 100.

[0034] Memory 60 may store a look-up table for degradation compensation gain and the degradation compensation point for the light-emitting layer of the subpixel SP. The degradation compensation point for the light-emitting layer may be the number of times the light-emitting device has been driven or the driving time.

[0035] The power supply unit 80 can supply a high-potential power supply voltage ELVDD and a low-potential power supply voltage ELVSS to the display panel 110. The high-potential power supply voltage ELVDD and the low-potential power supply voltage ELVSS can be supplied to the display panel 110 through high-potential power supply wiring and low-potential power supply wiring, respectively.

[0036] The voltage output from the power supply unit 80 may be output to the gate drive unit 30 or the data drive unit 40 and used to drive them. The power supply unit 80 can output gate high voltage VGH, gate low voltage VGL, initialization voltage Vini, etc. The gate high voltage VGH and gate low voltage VGL are supplied to the gate drive unit 30, and constant voltages such as high potential power supply voltage ELVDD, low potential power supply voltage ELVSS, and initialization voltage Vini are supplied to the subpixel SP through power supply wiring commonly connected to the subpixel SP. The power supply unit 80 can also supply a gamma reference voltage VGMA to the data drive unit 40. The dynamic range of the data voltage output from the data drive unit 40 is the voltage range between the highest gradation voltage and the lowest gradation voltage, and is determined by the voltage range of the gamma reference voltage VGMA.

[0037] Referring to Figure 2, the subpixel SP of the display device 100 according to one embodiment of this specification includes a light-emitting element 130 and a subpixel circuit that drives the light-emitting element 130.

[0038] The subpixel circuit may include a drive transistor DT, a plurality of switching transistors T1 to T5, and a storage capacitor C. The subpixel circuit is also connected to signal wiring, which includes data wiring DL to which the data voltage Vdata is applied, gate wiring GL to which scan signals SC1(n) and SC2(n) and light emission signals EM(n) and EM(n-2) are applied, respectively, high-potential power wiring to which the high-potential power supply voltage ELVDD is applied, low-potential power supply wiring to which the low-potential power supply voltage ELVSS is applied, and initialization signal wiring to which the initialization voltage Vini is applied. The signal wiring that supplies voltage on the display panel 110 may be connected in common to all subpixels SP. For example, among the gate wiring GL, the wiring to which the scan signals SC1(n) and SC2(n) are applied may be called scan wiring, and the wiring to which the light emission signals EM(n) and EM(n-2) are applied may be called light emission signal wiring.

[0039] Scan signals and light emission signals can swing between the gate-on voltage and the gate-off voltage. For example, a transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be the gate-high voltage and the gate-off voltage may be the gate-low voltage VGL. In the case of a p-channel transistor, the gate-on voltage may be the gate-low voltage VGL and the gate-off voltage may be the gate-high voltage VGH.

[0040] The fundamental voltage level of the high-potential supply voltage ELVDD is set to a voltage higher than the maximum voltage of the data voltage Vdata, and at a voltage that allows the drive transistor DT to operate in the saturation region. The initialization voltage Vini may be set to a voltage lower than the high-potential supply voltage ELVDD and higher than the low-potential supply voltage ELVSS. The gate high voltage VGH may be set to a voltage higher than the high-potential supply voltage ELVDD, and the gate low voltage VGL may be set to a voltage lower than the low-potential supply voltage ELVSS. For example, the constant voltages applied to the pixel circuit may be set to ELVDD=+8[V], Vini=+1.3[V], VSSEL=0[V], VGH=12.5[V], VGL=-5[V], etc., but are not limited to these.

[0041] At least one of the transistors in the subpixel circuit is an oxide semiconductor thin-film transistor containing a semiconductor layer that is an oxide semiconductor, and the remaining transistors may contain semiconductor layers that are polycrystalline semiconductors. For example, the transistors containing semiconductor layers that are polycrystalline semiconductors may be low-temperature polycrystalline silicon (LTPS) thin-film transistors. In Figure 3, the first transistor T1, the second transistor T2, and the fourth transistor T4 are LTPS thin-film transistors, and the driving transistor DT, the third transistor T3, and the fifth transistor T5 are oxide semiconductor thin-film transistors as an example. The subpixel circuit according to one embodiment of this specification is not limited thereto. For example, each of the transistors in the subpixel circuit may be a thin-film transistor containing any semiconductor layer such as an oxide semiconductor, polycrystalline semiconductor, compound semiconductor, organic semiconductor, amorphous semiconductor, etc.

[0042] In each transistor described below, the first electrode may be referred to as the source electrode or drain electrode, and the second electrode may be referred to as the drain electrode or source electrode.

[0043] The first transistor T1 is switched by the second light emission signal EM(n). The gate electrode of the first transistor T1 is connected to the light emission signal wiring to which the second light emission signal EM(n) is applied, and the first electrode of the first transistor T1 is connected to the high-potential power supply wiring to which the high-potential power supply voltage ELVDD is applied, and the second electrode of the drive transistor DT and the first electrode of the third transistor T3 may be connected.

[0044] The second transistor T2 is switched by the second scan signal SC2(n). The gate electrode of the second transistor T2 is connected to the scan line to which the second scan signal SC2(n) is input, the first electrode of the second transistor T2 is connected to the second electrode of the drive transistor DT and the first electrode of the fourth transistor T4, and the second electrode of the second transistor T2 may be connected to the data line to which the data voltage Vdata is applied.

[0045] The drive transistor DT is switched by the voltage of the first capacitor electrode of the storage capacitor C, the gate electrode of the drive transistor DT is connected to the first capacitor electrode of the storage capacitor C and the first electrode of the third transistor T3, the first electrode of the drive transistor DT is connected to the second electrode of the first transistor T1 and the second electrode of the third transistor T3, and the second electrode of the drive transistor DT may be connected to the first electrode of the second transistor T2 and the first electrode of the fourth transistor T4.

[0046] The third transistor T3 is switched by the first scan signal SC1(n). The gate electrode of the third transistor T3 is connected to the scan wiring to which the first scan signal SC1(n) is input, the first electrode of the third transistor T3 is connected to the gate electrode of the drive transistor DT and the first electrode of the storage capacitor C, and the second electrode of the third transistor T3 is connected to the second electrode of the first transistor T1 and the first electrode of the drive transistor DT.

[0047] The fourth transistor T4 is switched by the first light emission signal EM(n-2). The gate electrode of the fourth transistor T4 is connected to the light emission signal wiring to which the first light emission signal EM(n-2) is applied, the first electrode of the fourth transistor T4 is connected to the second electrode of the drive transistor DT and the first electrode of the second transistor T2, and the second electrode of the fourth transistor T4 may be connected to the first electrode of the fifth transistor T5, the second capacitor electrode of the storage capacitor C, and the first electrode of the light-emitting element 130.

[0048] The fifth transistor T5 is switched by the first light emission signal EM(n-2). The gate electrode of the fifth transistor T5 is connected to the light emission signal wiring to which the first light emission signal EM(n-2) is applied, the first electrode of the fifth transistor T5 is connected to the second electrode of the fourth transistor T4, the second capacitor electrode of the storage capacitor C, and the first electrode of the light-emitting element 130, and the second electrode of the fifth transistor T5 may be connected to the initialization signal wiring to which the initialization voltage Vini is applied.

[0049] The storage capacitor C stores the data voltage Vdata and the threshold voltage Vth. The first capacitor electrode of the storage capacitor C is connected to the gate electrode of the drive transistor DT and the first electrode of the third transistor T3, and the second capacitor electrode of the storage capacitor C may be connected to the second electrode of the fourth transistor T4, the first electrode of the fifth transistor T5, and the first electrode of the light-emitting element.

[0050] On the other hand, the light-emitting element 130 is connected between the fourth and fifth transistors T4 and T5 and the low-potential power supply voltage ELVSS, and emits light with a brightness proportional to the current of the drive transistor DT. The first electrode of the light-emitting element 130 is connected to the second electrode of the fourth transistor T4, the first electrode of the fifth transistor, and the second capacitor electrode of the storage capacitor C, and the second electrode of the light-emitting element 130 may be connected to the low-potential power supply wiring to which the low-potential power supply voltage ELVSS is applied. The first electrode of the light-emitting element 130 may be the anode electrode, and the second electrode may be the cathode electrode, but is not limited to these.

[0051] As shown in Figure 2, the second electrode of the first transistor T1, the second electrode of the third transistor T3, and the first electrode of the drive transistor DT constitute the first node N1. The second electrode of the drive transistor DT, the first electrode of the second transistor T2, and the first electrode of the fourth transistor T4 constitute the second node N2. The first electrode of the third transistor T3, the gate electrode of the drive transistor DT, and the first capacitor electrode of the storage capacitor C constitute the third node N3. The second electrode of the fourth transistor T4, the first electrode of the fifth transistor T5, the second capacitor electrode of the capacitor C, and the first electrode of the light-emitting element 130 constitute the fourth node N4. The subpixel circuit according to one embodiment of this specification is not limited thereto. For example, the configuration of the subpixel circuit can be changed in various ways. For example, the subpixel circuit may include one or more transistors and one or more capacitors, and can be configured not only with the 6T1C structure shown in Figure 2, but also with 2T1C, 3T1C, 4T1C, 5T2C, 7T2C structures, etc.

[0052] In the following, the structure of the display device 100 according to one embodiment of this specification will be described in more detail with reference to Figures 3a to 6.

[0053] Figures 3a to 3g are schematic enlarged plan views of the display area of ​​a display device according to one embodiment of this specification. Figure 3h is an enlarged plan view of the display area of ​​a display device according to one embodiment of this specification. Figure 4 is a cross-sectional view of a subpixel of a display device according to one embodiment of this specification.

[0054] In Figures 3a to 3g, the multiple layers of the display device 100 according to one embodiment of this specification, shown in Figure 3h, are shown separated into some of the layers. Figures 3a to 3g may include at least one overlapping layer, but this is shown as an overlap for the sake of explanation, and the layers can be stacked sequentially without overlapping, as shown in Figure 3h.

[0055] As previously explained with reference to Figures 1 and 2, various signals such as scan signals, light emission signals, data voltages, initialization voltages, high-potential power supply voltages, and low-potential power supply voltages are used to drive the light-emitting element 130. These signals are applied to the subpixels through multiple signal lines, including gate lines (e.g., scan signal lines and light emission signal lines), data lines, initialization signal lines, high-potential power supply lines, and low-potential power supply lines.

[0056] Some of these multiple signal lines must be applied to the transistors located relatively lower among the multiple transistors (i.e., DT and T1-T5) described earlier in Figure 2. Therefore, if the relevant signal line is located at the top of the stacked structure at the bottom of the light-emitting element 130, the design of contact holes from top to bottom becomes unavoidable, and there is a problem that other components cannot be superimposed on the lower region of the relevant signal line.

[0057] In one embodiment of the present invention, the display device 100 has a first signal wiring SM arranged on the bottommost layer of the substrate on the stacked structure below the light-emitting element 130. Through this, other components, in particular, multilayer transistors, can be arranged above the first signal wiring SM. Therefore, it is possible to greatly improve the degree of design freedom and provide high-resolution images, while at the same time reducing the design area without requiring significant changes in the arrangement of the components of the subpixel circuit.

[0058] Referring to Figures 4, 3a, and 3b, in one embodiment of this specification, the display device 100 may have a first signal wiring SM arranged on a substrate, and a blocking layer BSM may be arranged on the first signal wiring SM.

[0059] For example, referring to Figure 4, a first buffer layer 112a is arranged on substrates 111a, 111b, and 111c, a first signal wiring SM is arranged on the first buffer layer 112a, a second buffer layer 112b is arranged on the first signal wiring SM, and a blocking layer BSM is arranged on the second buffer layer 112b. The substrate according to one embodiment of this specification is not limited thereto. In the above description, the substrate was explained as three substrates 111a, 111b, and 111c as an example, but the substrate can be a single substrate or two or more substrates. Also, depending on the design of the display device 100 according to one embodiment of this specification, at least one of the first buffer layer 112a and the second buffer layer 112b may be omitted.

[0060] The substrates 111a, 111b, and 111c serve to support and protect the components of the display device 100, which is positioned on top of them.

[0061] For example, if the substrate is made of polyimide (PI), moisture can penetrate the polyimide (PI) substrate and permeate to the thin-film transistor or light-emitting element, degrading the performance of the display device 100. To prevent such degradation of the display device 100's performance due to moisture permeation, the display device 100 according to one embodiment of this specification can be made by applying a double polyimide (PI) structure as the substrate.

[0062] For example, the substrate may include a first substrate 111a and a second substrate 111c, both made of polyimide (PI), and an inorganic insulating layer 111b formed between the first substrate 111a and the second substrate 111c.

[0063] The inorganic insulating layer 111b may consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). For example, silicon dioxide (SiO2) can be used as the inorganic insulating layer 111b, but is not limited to this, and the inorganic insulating layer 111b may be formed as a bilayer of silicon dioxide (SiO2) and silicon nitride (SiNx). The inorganic insulating layer 111b blocks moisture from penetrating to the upper part of the second substrate 111c. Furthermore, if a charge is charged on the first substrate 111a, the inorganic insulating layer 111b can block the influence of the charged charge through the second substrate 111c on the upper thin-film transistor. In this way, by blocking the charge charged on the lower polyimide (PI) through the inorganic insulating layer 111b, the reliability of the product can be improved. In addition, since the process of placing a separate metal layer for charge blocking can be omitted, the process can be simplified and the unit cost of production can be reduced.

[0064] A first buffer layer 112a, a second buffer layer 112b, and a third buffer layer 112c are arranged on substrates 111a, 111b, and 111c. For example, the first buffer layer 112a may be a multi-buffer layer or a single buffer layer, and the third buffer layer 112c may be an active buffer layer, but is not limited to these.

[0065] A light shield layer (BSM) is positioned below the third buffer layer 112c. The light shield layer (BSM) may act as a light shield to prevent the semiconductor layer from degrading due to light incident from outside the display device. For example, the light shield layer (BSM) may be a metal layer, but is not limited to that. For example, the light shield layer (BSM) may have a larger area than the active layer of the thin-film transistor, but is not limited to that. The light shield layer (BSM) can also prevent the inflow of charge from the substrate. For example, if a voltage is applied to the gate electrode of a thin-film transistor for a long time, the electric field generated by the transistor may cause charge from the substrate to flow into the channel region of the active layer of the thin-film transistor, causing a variation in the amount of charge in that channel region. The charge may be a hole or an electric charge depending on the polarity of the electric field. In this way, the substrate can change the current of the thin-film transistor and induce a change in the threshold voltage of the thin-film transistor. This can lead to changes in pixel brightness and afterimages. According to the present invention, by arranging a blocking layer BSM between the substrate and the active layer, the inflow of unwanted charge from the substrate into the thin-film transistor is blocked, and fluctuations in the threshold voltage of the thin-film transistor can be prevented. Therefore, according to the present invention, the generation of afterimages can be suppressed, and display quality can be improved.

[0066] Thus, the BSM (Blocking Layer) is a metal layer positioned relatively lower on the subpixel stacked structure. However, if the transistor positioned above the BSM is a transistor with a semiconductor layer made of polycrystalline semiconductor material, planarization is necessary for the crystallization of the transistor's semiconductor layer. Therefore, the BSM must be formed very thinly. For example, the BSM may have a thickness of about 650 Å. In such a case, the resistance of the BSM becomes high, which is unfavorable for use as a signal trace.

[0067] Therefore, a second buffer layer 112b is further arranged between the multi-buffer layer and the active buffer layer, a first signal wiring SM is arranged on the first buffer layer 112a, the second buffer layer 112b is arranged on the first signal wiring SM, and a blocking layer BSM is arranged on the second buffer layer 112b. As shown in Figure 3a, the first signal wiring SM may be a high-potential power wiring that applies a high-potential power supply voltage ELVDD and a data wiring that applies a data voltage. For example, the blocking layer BSM may be configured to overlap at least a portion of the first signal wiring SM, or it may be configured not to overlap. Also, one blocking layer BSM may, but is not limited to, overlapping with at least one first signal wiring SM.

[0068] Referring to both Figure 4 and Figure 3c, multiple transistors are arranged on multiple first signal lines SM and barrier layers BSM.

[0069] For example, referring to Figures 3c and 4, the first transistor T1, second transistor T2, and fourth transistor T4 described in Figure 2 may be arranged on the third buffer layer 112c. Figure 4 shows a portion of a cross-section obtained by cutting in one direction a display area AA, on which a plurality of subpixels SP are arranged, in a display device 100 according to one embodiment of this specification. Thus, although only the cross-sections of the first transistor T1 and fourth transistor T4 on the third buffer layer 112c are shown in Figure 4, the second transistor T2 may also be arranged on the same layer as in Figure 3c.

[0070] Referring to Figure 3c, the active layers L-ACT of the first transistor T1 and the fourth transistor T4 are arranged on the high-potential power supply wiring BSM to which the high-potential power supply voltage ELVDD is applied, and the active layer L-ACT of the second transistor T2 is arranged on the data wiring BSM to which the data voltage Vdata is applied, and the gate electrodes L-GAT of the first transistor T1, the second transistor T2, and the fourth transistor T4 are arranged on the respective active layers L-ACT. For example, the active layer may be called a semiconductor layer. Referring to both Figures 3a and 3c, for example, a portion of the first transistor T1 and a portion of the fourth transistor T4 can be superimposed on the first signal wiring SM, which is a high-potential power supply wiring. Also, a portion of the second transistor T2 can be superimposed on the first signal wiring SM1, which is a data wiring.

[0071] For example, as shown in Figure 4, the first active layer L-ACT1 of the first transistor T1 and the second active layer L-ACT2 of the fourth transistor T4 are arranged on the third buffer layer 112c. In this case, the first blocking layer BSM1 is placed below the first active layer L-ACT1 of the first transistor T1, and the second blocking layer BSM2 is placed below the second active layer L-ACT2 of the fourth transistor T4.

[0072] The first active layer L-ACT1 and the second active layer L-ACT2 may be amorphous silicon or polycrystalline silicon. For example, the first active layer L-ACT1 and the second active layer L-ACT2 may be low-temperature polysilicon (LTPS). Polysilicon materials have high mobility (100 cm² / Vs or more), low energy consumption, and excellent reliability.

[0073] The first active layer L-ACT1 and the second active layer L-ACT2 may each include a channel region where a channel is formed when the transistor is driven, a source region on both sides of the channel region, and a drain region. For example, the source region and drain region may be formed by ion doping (impurity doping) of the active layer. The source region and drain region may be generated by ion doping of polysilicon material. The channel region may represent the portion of polysilicon material that is not ion-doped or is doped with a small amount of ions.

[0074] A first gate insulating layer 113a is placed on top of the first active layer L-ACT1 and the second active layer L-ACT2.

[0075] The first gate insulating layer 113a may be disposed over the entire substrate including the first active layer L-ACT1 and the second active layer L-ACT2. For example, the first gate insulating layer 113a may consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). Contact holes may be formed in the first gate insulating layer 113a for electrical connection to the source region and drain region of the first active layer L-ACT1 of the first transistor T1 and the second active layer L-ACT2 of the fourth transistor T4, respectively.

[0076] The first gate electrode L-GAT1 of the first transistor T1 and the second gate electrode L-GAT2 of the fourth transistor T4 are placed on the first gate insulating layer 113a. An electrode layer L-GAT3, which serves as a light-shielding layer, may also be placed on the first gate insulating layer 113a, but is not limited to this. For example, the electrode layer L-GAT3 may be omitted depending on the design of the display device 100.

[0077] The first gate electrode L-GAT1, the second gate electrode L-GAT2, and the electrode layer L-GAT3 can be formed as a single or multiple layer of one of the following materials or alloys thereof: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd).

[0078] The first gate electrode L-GAT1 and the second gate electrode L-GAT2 may be formed on the first gate insulating layer 113a so as to overlap with the channel regions of the first active layer L-ACT1 of the first transistor T1 and the second active layer L-ACT2 of the fourth transistor T4, respectively.

[0079] On the other hand, the first capacitor electrode of the storage capacitor C described in Figure 2 may be formed from the same material as the first gate electrode L-GAT1 and the second gate electrode L-GAT2, and may be formed on the same layer. That is, the first capacitor electrode may be formed by the same process as the first gate electrode L-GAT1 and the second gate electrode L-GAT2, but is not limited to this. For example, the first capacitor electrode of the storage capacitor C may be omitted based on the driving characteristics of the display device 100, the structure and type of the transistor, etc.

[0080] Referring to both Figure 4 and Figure 3d, a first metal pattern TM1 and a second metal pattern TM2 are arranged on the gate electrodes L-GAT of multiple transistors, and a first contact hole CNT1 and a second contact hole CNT2 are formed to electrically connect the first metal pattern TM1 and the second metal pattern TM2 to the active layer L-ACT of the transistor below, respectively.

[0081] For example, referring to Figure 4, the first interlayer insulating layer 114a and the second interlayer insulating layer 114b are placed on top of the first gate insulating layer 113a, the first gate electrode L-GAT1, the second gate electrode L-GAT2, and the electrode layer L-GAT3, and the first metal pattern TM1 is placed on top of the second interlayer insulating layer 114b. Then, the fourth buffer layer 112d is placed on top of the second interlayer insulating layer 114b and the first metal pattern TM1, and the second metal pattern TM2 is placed on top of the fourth buffer layer 112d. For example, at least one of the first interlayer insulating layer 114a, the second interlayer insulating layer 114b, and the fourth buffer layer 112d may be omitted depending on the design. For example, the first metal pattern TM1 may be placed on the same layer as the second metal pattern TM2.

[0082] The fourth buffer layer 112d may consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

[0083] On the other hand, the second capacitor electrode of the storage capacitor C described in Figure 2 may be placed on the first interlayer insulating layer 114a or the second interlayer insulating layer 114b. The second capacitor electrode may be formed as a single or multilayer structure made of one of the following materials or an alloy thereof: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd). The second capacitor electrode may be formed to overlap with the first capacitor electrode. The second capacitor electrode may also be made of the same material as the first capacitor electrode. The second capacitor electrode may be omitted based on the driving characteristics of the display device 100, the structure and type of the transistor, etc.

[0084] The first interlayer insulating layer 114a and the second interlayer insulating layer 114b may consist of a single layer or multiple layers thereof of silicon nitride (SiNx) or silicon oxide (SiOx). The first interlayer insulating layer 114a and the second interlayer insulating layer 114b may have a first contact hole CNT1 and a second contact hole CNT2-1 formed therein to expose the source region and drain region of the first active layer L-ACT1 of the first transistor T1.

[0085] For example, the source region of the first active layer L-ACT1 may be connected to the first metal pattern TM1, and the drain region may be connected to the second metal pattern TM2. However, depending on the design of the subpixel circuit, the first metal pattern TM1 may be connected to the drain region and the second metal pattern TM2 may be connected to the source region.

[0086] In this case, the first contact hole CNT1 is formed by penetrating the second interlayer insulating layer 114b, the first interlayer insulating layer 114a, the first gate insulating layer 113a, the third buffer layer 112c, and the second buffer layer 112b. Through the first contact hole CNT1, the first metal pattern TM1 is connected to the source region of the first active layer L-ACT1 of the first transistor T1, and the first metal pattern TM1 is also connected to the first signal wiring SM through the first contact hole CNT1. In this way, the first signal wiring SM is electrically connected to the first active layer L-ACT1 of the first transistor T1 through the first metal pattern TM1.

[0087] Figure 5 is a cross-sectional view illustrating an example of a structure in which a metal pattern of a display device according to one embodiment of this specification is in contact with an active layer.

[0088] Figure 5 shows a cross-sectional view of a portion of the subpixel circuit, viewed from a different direction than in Figure 4.

[0089] As shown in Figure 5, the first metal pattern TM1 is positioned along the side of the contact hole penetrating the second interlayer insulating layer 114b, the first interlayer insulating layer 114a, the first gate insulating layer 113a, the third buffer layer 112c, and the second buffer layer 112b, extending down to the bottom, with its lower surface in contact with the first signal wiring SM on the first buffer layer 112a. At this time, a portion of the first active layer L-ACT1 of the first transistor T1 protrudes from the side of the contact hole penetrating the first interlayer insulating layer 114a, the first gate insulating layer 113a, the third buffer layer 112c, and the second buffer layer 112b, and the side of the first metal pattern TM1 is positioned to cover the protruding portion of the first active layer L-ACT1, thus making side contact with the first active layer L-ACT1 of the first transistor T1. In this manner, the first signal wiring SM and the first active layer L-ACT1 of the first transistor T1 can be electrically connected through the first metal pattern TM1. For example, the first metal pattern TM1 may be positioned to contact the upper, side, and lower surfaces of a portion of the first active layer L-ACT1 of the first transistor T1 that protrudes from the side of the contact hole, but is not limited thereto. For example, the first metal pattern TM1 may be continuous with the portion of the first active layer L-ACT1 of the first transistor T1 that protrudes from the side of the contact hole, but is not limited thereto.

[0090] Referring to Figure 4, the second-first contact hole CNT2-1, the second-second contact hole CNT2-2, and the second-third contact hole CNT2-3 are formed by penetrating the fourth buffer layer 112d, the second interlayer insulating layer 114b, the first interlayer insulating layer 114a, and the first gate insulating layer 113a, respectively. Through the second-first contact hole CNT2-1, the second-first metal pattern TM2-1 is connected to the drain region of the first active layer L-ACT1 of the first transistor T1. Through the second-second contact hole CNT2-2, the second-second metal pattern TM2-2 is connected to the source region of the second active layer L-ACT2 of the fourth transistor T4, and through the second-third contact hole CNT2-3, the second-third metal pattern TM2-3 may be connected to the drain region of the second active layer L-ACT2 of the fourth transistor T4.

[0091] Referring to both Figure 4 and Figure 3e, multiple transistors are arranged on top of the second metal pattern TM2.

[0092] For example, referring to Figure 4, the fifth buffer layer 112e is arranged on the second-first metal pattern TM2-1, the second-second metal pattern TM2-2, the second-third metal pattern TM2-3, and the fourth buffer layer 112d, and the third transistor T3, the drive transistor DT, and the fifth transistor T5, as described in Figure 2, can be arranged on the fifth buffer layer 112e. In Figure 4, only the cross-sections of the drive transistor DT and the fifth transistor T5 on the fifth buffer layer 112e are shown, but the third transistor T3 can also be arranged on the same layer as in Figure 3e. For example, referring to Figures 3a, 3c, and 3e together, a portion of the drive transistor DT can be superimposed on the first signal wiring SM, which is a high-potential power supply wiring. Also, a portion of the third transistor T3 and a portion of the fifth transistor T5 can be superimposed on the first signal wiring SM, which is a data wiring.

[0093] The fifth buffer layer 112e may consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). Contact holes may be formed in the fifth buffer layer 112e to expose the second-first metal pattern TM2-1, the second-second metal pattern TM2-2, and the second-third metal pattern TM2-3, respectively.

[0094] Referring to Figure 3e, the active layers O-ACT of the third transistor T3, the driving transistor DT, and the fifth transistor T5 are arranged on the second metal pattern TM2, and the gate electrodes O-GAT1 of the third transistor T3, the driving transistor DT, and the fifth transistor T5 are arranged on each of the active layers O-ACT.

[0095] For example, as shown in Figure 4, the third active layer O-ACT1 of the drive transistor DT and the fourth active layer O-ACT2 of the fifth transistor T5 are arranged on the fifth buffer layer 112e.

[0096] The third active layer O-ACT1 and the fourth active layer O-ACT2 may be made of an oxide semiconductor. Thin-film transistors including active layers made of oxide semiconductors are suitable for high-resolution display elements because the off-current is small, which can reduce the size of the auxiliary capacitance. For example, the third active layer O-ACT1 and the fourth active layer O-ACT2 may be made of a metal oxide, and may be made of a variety of metal oxides such as IGZO (indium-gallium-zinc-oxide), but are not limited to these. For example, the third active layer O-ACT1 and the fourth active layer O-ACT2 may be formed of other metal oxides such as IZO (indium-zinc-oxide), IGTO (indium-gallium-tin-oxide), or IGO (indium-gallium-oxide). Such third active layer O-ACT1 and fourth active layer O-ACT2 may be formed by depositing a metal oxide onto a fifth buffer layer 112e, performing a heat treatment process for stabilization, and then patterning the metal oxide. The third active layer O-ACT1 and the fourth active layer O-ACT2 may each include a channel region where a channel is formed when the transistor is driven, source regions on both sides of the channel region, and drain regions, respectively.

[0097] The second gate insulating layer 113b is placed on top of the third active layer O-ACT1 and the fourth active layer O-ACT2.

[0098] The second gate insulating layer 113b may be disposed over the entire substrate including the third active layer O-ACT1 and the fourth active layer O-ACT2. For example, the second gate insulating layer 113b may consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). Contact holes may be formed in the second gate insulating layer 113b for electrical connection to the source and drain regions of the third active layer O-ACT1 of the drive transistor DT and the fourth active layer O-ACT2 of the fifth transistor T5, respectively.

[0099] The third gate electrode O-GAT1-1 of the drive transistor DT and the fourth gate electrode O-GAT1-2 of the fifth transistor T5 are placed on the second gate insulating layer 113b.

[0100] The third gate electrode O-GAT1-1 and the fourth gate electrode O-GAT1-2 may be formed as a single or multilayer structure consisting of one of the following materials or an alloy thereof: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd).

[0101] On the other hand, an electrode layer L-GAT3, which serves as a light-shielding layer as described earlier, may be placed beneath the fifth thin-film transistor T5. For example, as shown in Figure 4, the electrode layer L-GAT3 may be placed on the first gate insulating layer 113a so as to overlap with the fourth active layer O-ACT2 of the fifth transistor T5.

[0102] The third gate electrode O-GAT1-1 and the fourth gate electrode O-GAT1-2 may be formed on the second gate insulating layer 113b so as to overlap with the channel regions of the third active layer O-ACT1 of the driving transistor DT and the fourth active layer O-ACT2 of the fifth transistor T5, respectively.

[0103] Referring to both Figure 4 and Figure 3f, a third metal pattern O-GAT2 is placed on the gate electrode O-GAT1 of multiple transistors, and a third contact hole CNT3 is formed to electrically connect the third metal pattern O-GAT2 to the active layer O-ACT and the second metal pattern TM2 of the lower transistor.

[0104] For example, referring to Figure 4, a third interlayer insulating layer 114c is placed on top of the third gate electrode O-GAT1-1 and the fourth gate electrode O-GAT1-2, and the third-first metal pattern O-GAT2-1, the third-second metal pattern O-GAT2-2, and the third-third metal pattern O-GAT2-3 are placed on top of the third interlayer insulating layer 114c.

[0105] The third interlayer insulating layer 114c may consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). The third interlayer insulating layer 114c may have third-first contact holes CNT3-1 and third-second contact holes CNT3-2 formed therein to expose the source and drain regions of the third active layer O-ACT1 of the drive transistor DT. Furthermore, the third interlayer insulating layer 114c may have third-third contact holes CNT3-3 formed therein to expose the source region of the fourth active layer O-ACT2 of the fifth transistor T5. For example, the source region of the third active layer O-ACT1 may be connected to the third-first metal pattern O-GAT2-1, and the drain region may be connected to the third-second metal pattern O-GAT2-2. Also, the source region of the fourth active layer O-ACT2 may be connected to the third-third metal pattern O-GAT2-3. However, depending on the design of the subpixel circuit, the third-first metal pattern O-GAT2-1 and the third-third metal pattern O-GAT2-3 may be connected to the drain region, and the third-second metal pattern O-GAT2-2 may be connected to the source region.

[0106] At this time, the 3-1 contact hole CNT3-1, the 3-2 contact hole CNT3-2, and the 3-3 contact hole CNT3-3 are formed by penetrating the 3rd interlayer insulating layer 114c, the 2nd gate insulating layer 113b, and the 5th buffer layer 112e.

[0107] Through the third-first contact hole CNT3-1, the third-first metal pattern O-GAT2-1 is connected to the source region of the third active layer O-ACT1 of the driving transistor TD, and also through the third-first contact hole CNT3-1, the third-first metal pattern O-GAT2-1 is connected to the second-first metal pattern TM2-1. Through the third-second contact hole CNT3-2, the third-second metal pattern O-GAT2-2 is connected to the drain region of the third active layer O-ACT1 of the driving transistor TD, and also through the third-second contact hole CNT3-2, the third-second metal pattern O-GAT2-2 is connected to the second-second metal pattern TM2-2. In this way, the driving transistor DT is electrically connected to the lower first transistor T1.

[0108] Through the third-third contact hole CNT3-3, the third-third metal pattern O-GAT2-3 is connected to the source region of the fourth active layer O-ACT2 of the fifth transistor T5, and also through the third-third contact hole CNT3-3, the third-third metal pattern O-GAT2-3 is connected to the second-third metal pattern TM2-3. In this way, the fifth transistor T5 is electrically connected to the lower fourth transistor T4.

[0109] Figure 6 is a cross-sectional view illustrating another example of a structure in which a metal pattern of a display device according to one embodiment of this specification contacts an active layer.

[0110] Figure 6 shows a cross-sectional view of a portion of the subpixel circuit, viewed from a different direction than in Figure 4.

[0111] As shown in Figure 6, the third-first metal pattern O-GAT2-1 is positioned along the side of the contact hole that penetrates the third interlayer insulating layer 114c, the second gate insulating layer 113b, and the fifth buffer layer 112e, extending down to the bottom, with its lower surface in contact with the second-first metal pattern TM2-1 on the fourth buffer layer 112d. At this time, a portion of the third active layer O-ACT1 of the drive transistor DT protrudes from the side of the contact hole that penetrates the third interlayer insulating layer 114c, the second gate insulating layer 113b, and the fifth buffer layer 112e, and the side of the third-first metal pattern O-GAT2-1 is positioned to cover the protruding portion of the third active layer O-ACT1, thus making side contact with the third active layer O-ACT1 of the drive transistor DT. In this manner, the third active layer O-ACT1 of the drive transistor TD and the first active layer L-ACT1 of the first transistor T1 can be electrically connected through the third-first contact hole CNT3-1 and the second-first contact hole CNT2-1.

[0112] In this manner, the third active layer O-ACT1 of the drive transistor TD and the second active layer L-ACT2 of the fourth transistor T4 can be electrically connected through the third-second contact hole CNT3-2 and the second-second contact hole CNT2-2. Furthermore, the fourth active layer O-ACT2 of the fifth transistor T5 and the second active layer L-ACT2 of the fourth transistor T4 can be electrically connected through the third-third contact hole CNT3-3 and the second-third contact hole CNT2-3.

[0113] Referring to both Figure 4 and Figure 3g, a plurality of second signal wirings SD1 are arranged on top of the third metal pattern O-GAT2, and a fourth contact hole O-CNT is formed to electrically connect the second signal wirings SD1 to the gate electrode O-GAT1 of the transistor, the third metal pattern O-GAT2, and the active layer O-ACT of the transistor. The second signal wirings SD1 may be scan wiring for applying a scan signal, light emission signal wiring for applying a light emission signal, initialization signal wiring for applying an initialization voltage, or low-potential power supply wiring for applying a low-potential power supply voltage.

[0114] For example, referring to Figure 4, the fourth interlayer insulating layer 114d is placed on the third-first metal pattern O-GAT2-1, the third-second metal pattern O-GAT2-2, and the third-third metal pattern O-GAT2-3, and the second-first signal wiring SD1-1, the second-second signal wiring SD1-2, and the second-third signal wiring SD1-3 are placed on the fourth interlayer insulating layer 114d.

[0115] The fourth interlayer insulating layer 114d may consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). The fourth interlayer insulating layer 114d may have a fourth-first contact hole O-CNT1 for exposing the third gate electrode O-GAT1-1 of the drive transistor DT, a fourth-second contact hole O-CNT2 for exposing the third-third metal pattern O-GAT2-3, and a fourth-third contact hole O-CNT3 for exposing the drain region of the fourth active layer O-ACT2 of the fifth transistor T5.

[0116] For example, the third gate electrode O-GAT1-1 of the drive transistor DT may be connected to the second-first signal wiring SD1-1 to which the scan signal is applied, the third-third metal pattern O-GAT2-3 may be connected to the second-second signal wiring SD1-2, and the drain region of the fourth active layer O-ACT2 of the fifth transistor T5 may be connected to the second-third signal wiring SD1-3 to which the initialization voltage is applied. However, depending on the design of the subpixel circuit, the source region of the fourth active layer O-ACT2 may also be connected to the second-third signal wiring SD1-3.

[0117] At this time, the 4-1 contact hole O-CNT1 is formed through the 4th interlayer insulating layer 114d and the 3rd interlayer insulating layer 114c, and the 2-1 signal wiring SD1-1 is electrically connected to the 3rd gate electrode O-GAT1-1 through the 4-1 contact hole O-CNT1. The 4-2 contact hole O-CNT2 is formed through the 4th interlayer insulating layer 114d, and the 2-2 signal wiring SD1-2 is electrically connected to the 3-3 metal pattern O-GAT2-3 through the 4-2 contact hole O-CNT2. Furthermore, the 4-3 contact hole O-CNT3 is formed by penetrating the 4th interlayer insulating layer 114d, the 3rd interlayer insulating layer 114c, and the 2nd gate insulating layer 113b, and the 2-3 signal wiring SD1-3, which is an initialization signal wiring, is electrically connected to the 4th active layer O-ACT2 of the 5th transistor T5 through the 4-3 contact hole O-CNT3.

[0118] For example, for each of the multiple transistors described with reference to Figures 3a to 3g and Figure 4, at least some of the metal patterns TM1, TM2, O-GAT2, and SD1 that are in direct contact with the source region and drain region of the active layer can be referred to as source electrodes and drain electrodes.

[0119] As described above, the multiple layers of the display device 100 according to one embodiment of this specification can be stacked sequentially as shown in Figure 3h.

[0120] Referring to Figure 4, an inorganic layer 115 may be placed above the fourth interlayer insulating layer 114d and the second-first signal wiring SD1-1, the second-second signal wiring SD1-2, and the second-third signal wiring SD1-3.

[0121] The inorganic layer 115 is a passivation layer for protecting multiple transistors (e.g., drive transistor DT, fifth transistor T5, etc.), and may consist of, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a composite layer thereof.

[0122] A first planarization layer 116a and a second planarization layer 116b are placed on top of the inorganic layer 115.

[0123] The first planarization layer 116a may be an organic layer for planarizing and protecting the tops of multiple transistors (e.g., drive transistor DT, fifth transistor T5, etc.). For example, the first planarization layer 116a may be formed from an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0124] An auxiliary electrode SD2 may be placed on the first planarization layer 116a.

[0125] The auxiliary electrode SD2 can be connected to the second-second signal wiring SD1-2 through contact holes formed in the first planarization layer 116a and the inorganic layer 115. That is, the auxiliary electrode SD2 can be connected to the second-second signal wiring SD1-2 and electrically connected to the third-third metal pattern O-GAT2-3, the fourth active layer O-ACT2 of the fifth thin-film transistor T5, the second-third metal pattern TM2-3, and the second active layer L-ACT2 of the fourth transistor T4, respectively.

[0126] Furthermore, the auxiliary electrode SD2 can serve to electrically connect the transistor and the first electrode 131 of the light-emitting element 130. For example, the auxiliary electrode SD2 may be formed as a single or multilayer of one of the following materials or an alloy thereof: molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd). The auxiliary electrode SD2 may, but is not limited to, the same material as the metal pattern connected to the source and drain regions included in the active layer of the thin-film transistor. For example, the auxiliary electrode SD2 may be formed from a different material than the metal pattern connected to the source and drain regions included in the active layer of the transistor. Also, the auxiliary electrode SD2 may be omitted depending on the design of the display device 100.

[0127] A second planarization layer 116b is placed on the auxiliary electrode SD2 and the first planarization layer 116a. For example, the second planarization layer 116b can be formed from an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. The light-emitting element 130 is placed on the second planarization layer 116b.

[0128] The light-emitting element 130 includes a first electrode 131, a light-emitting layer 132, and a second electrode 133. For example, the first electrode 131 may be an anode electrode, and the second electrode 133 may be a cathode electrode, but is not limited to these.

[0129] Furthermore, a bank 120 is placed on the second planarization layer 116b. The bank 120 may include open regions that expose the portion corresponding to the light-emitting area of ​​each subpixel.

[0130] The first electrode 131 of the light-emitting element 130 is placed on the second planarization layer 116b. The first electrode 131 may be made of a metallic material and may be electrically connected to the auxiliary electrode SD2 through a contact hole provided in the second planarization layer 116b.

[0131] For example, if the display device 100 according to one embodiment of this specification is a top emission type, the light emitted by the light-emitting element 130 is emitted onto the top of the substrate, and in this case, the first electrode 131 may further include a transparent conductive layer and a reflective layer on the transparent conductive layer. For example, the transparent conductive layer may be made of a transparent conductive oxide such as ITO or IZO, and the reflective layer may be made of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or alloys thereof.

[0132] The bank 120 is positioned to cover both ends of the first electrode 131, and a portion of the first electrode 131 may be exposed through the open region of the bank 120. For example, the bank 120 may, but is not limited to, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material such as a benzocyclobutene resin, an acrylic resin, or an imide resin.

[0133] The light-emitting layer 132 of the light-emitting element 130 is positioned in and around the open region of bank 120. This allows the light-emitting layer 132 to be positioned on the first electrode 131 exposed through the open region of bank 120. For example, the light-emitting layer 132 can contain multiple organic films. A second electrode 133 is positioned on the light-emitting layer 132 of the light-emitting element 130.

[0134] On the other hand, the display device 100 according to one embodiment of this specification may further include a sealing layer disposed on the light-emitting element 130.

[0135] The sealing layer may have a single-layer structure or a multilayer structure. For example, the sealing layer may include a first sealing layer, a second sealing layer, and a third sealing layer. In this case, the first and third sealing layers may be composed of inorganic films, and the second sealing layer may be composed of an organic film. Of the first, second, and third sealing layers, the second sealing layer is the thickest and can serve as a planarization layer.

[0136] The sealing layer can be arranged such that the first sealing layer is as close as possible to the light-emitting element 130. That is, the first sealing layer can be placed on the second electrode 133 of the light-emitting element 130.

[0137] The first sealing layer can be formed from an inorganic insulating material that can be deposited at low temperatures. For example, the first sealing layer may be composed of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Since the first sealing layer is deposited in a low-temperature atmosphere, damage to the light-emitting layer 132, which contains organic materials that are vulnerable to high-temperature atmospheres, can be prevented during the deposition process.

[0138] The second sealing layer may be formed over a smaller area than the first sealing layer. In this case, the second sealing layer may be formed so as to expose both ends of the first sealing layer. The second sealing layer can serve as a buffer to alleviate stress between layers due to warping of the flexible display device 100 and to enhance planarization performance. For example, the second sealing layer may be composed of an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, or silicon oxycarbon (SiOC). For example, the second sealing layer may be formed by an inkjet method, but is not limited thereto.

[0139] The third sealing layer may be formed on top of the substrate on which the second sealing layer is formed, so as to cover the upper and side surfaces of the second and first sealing layers, respectively. In this case, the third sealing layer can minimize or block the penetration of external moisture and oxygen into the first and second sealing layers. For example, the third sealing layer may be made of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0140] Furthermore, the display device 100 according to one embodiment of this specification may further include, but is not limited to, a color filter portion and a touch sensing portion disposed on the sealing layer.

[0141] For example, a touch buffer film for arranging a touch sensing unit may be placed on the third sealing layer, and multiple touch electrodes of the touch sensing unit may be placed on the touch buffer film. The touch electrodes may include a touch sensor metal and a bridge metal located in different layers from each other, and an interlayer insulating film may be placed between the touch sensor metal and the bridge metal.

[0142] Furthermore, the display device 100 according to one embodiment of this specification may further include an organic layer covering the color filter portion and the touch sensing portion on the sealing layer. For example, an organic layer covering the touch electrode of the touch sensing portion may be provided, and such an organic layer may be composed of an organic insulating film.

[0143] Furthermore, the display device 100 according to one embodiment of this specification may further include a polarizing layer and a cover member disposed on the sealing layer.

[0144] The polarizing layer can suppress the reflection of external light on the display area AA of the substrate. For example, when the display device 100 is used outdoors, external natural light may flow in and be reflected by the reflective layer contained in the first electrode 131 of the light-emitting element 130, or by an electrode made of metal located below the light-emitting element 130. The image on the display device 100 may not be visible due to the light reflected in this way. The polarizing layer can polarize the light flowing in from the outside in a specific direction and prevent the reflected light from being emitted outside the display device 100.

[0145] Furthermore, the cover member, such as the cover glass, can protect the components of the display device 100 from external impacts and prevent damage such as scratches. The cover glass may be bonded to the polarizing layer by an adhesive layer. For example, the adhesive layer may be formed using, but is not limited to, an optically transparent display adhesive such as a pressure-sensitive adhesive, an optically clear adhesive (OCR), or an optically clear resin (OCR).

[0146] The various embodiments of the display devices described herein can be described as follows:

[0147] A display device according to one embodiment of this specification includes a substrate containing a plurality of subpixels, a plurality of first signal lines disposed on the substrate, a first buffer layer disposed on the plurality of first signal lines, a first transistor disposed on the first buffer layer and electrically connected to one of the plurality of first signal lines, a second buffer layer disposed on the first transistor, and a second transistor disposed on the second buffer layer.

[0148] According to other features of this specification, the first transistor may include a semiconductor layer made of a polycrystalline semiconductor, and the second transistor may include a semiconductor layer made of an oxide semiconductor.

[0149] According to other features of this specification, the plurality of first signal lines may include high-potential power lines and data lines.

[0150] According to other features of this specification, the first and second transistors may be superimposed on high-potential power supply wiring.

[0151] According to other features of this specification, the first and second transistors may be superimposed on data wiring.

[0152] According to other features of this specification, the configuration may further include a third buffer layer located below the first buffer layer and positioned on a substrate and a plurality of first signal lines, and a blocking layer located on the third buffer layer and positioned to overlap with the semiconductor layer of the first transistor.

[0153] According to other features of this specification, the invention further includes an insulating layer disposed on the gate electrode of a first transistor, and a metal pattern disposed on the insulating layer, the metal pattern being able to electrically connect the first transistor and the first signal wiring.

[0154] According to other features of this specification, the invention further includes a plurality of second signal wires positioned above the source and drain electrodes of the second transistor, one of which may be electrically connected to the second transistor.

[0155] According to other features of this specification, the multiple second signal lines may include scan lines, light emission signal lines, and initialization signal lines.

[0156] According to other features of this specification, a plurality of second signal lines may be arranged between the light-emitting elements contained in a plurality of subpixels and the source and drain electrodes of a second transistor. In this case, the light-emitting elements may be electrically connected to the source or drain electrode of the second transistor through the second signal lines.

[0157] According to other features of this specification, the source electrode of the first transistor may be superimposed on the first signal wiring.

[0158] According to other features of this specification, the display device may further include a first insulating layer disposed on the gate electrode of a first transistor, and a second insulating layer disposed between the gate electrode and a first semiconductor layer of the first transistor. In this case, the source electrode of the first transistor may be connected to either a first signal wiring or the first semiconductor layer of the first transistor through a first contact hole formed continuously through the first buffer layer, the first insulating layer, and the second insulating layer.

[0159] According to other features of this specification, the source electrode of the first transistor extends along the side of the first contact hole to the bottom of the first contact hole, and the bottom surface of the source electrode of the first transistor may contact the first signal wiring. In this case, a portion of the first semiconductor layer of the first transistor protrudes from the side of the first contact hole, is covered by the source electrode of the first transistor, and may be in lateral contact with the source electrode of the first transistor.

[0160] According to other features of this specification, the source electrode of the first transistor may be in contact with the upper, side, and lower surfaces of a portion of the first semiconductor layer of the first transistor that protrudes from the side of the first contact hole.

[0161] According to other features of this specification, one of the source and drain electrodes of the second transistor may be superimposed on one of the source and drain electrodes of the first transistor.

[0162] According to other features of this specification, the display device may further include a third insulating layer disposed on the gate electrode of a second transistor, and a fourth insulating layer disposed between the gate electrode and the second semiconductor layer of the second transistor. In this case, one of the source electrode and drain electrode of the second transistor may be connected to either one of the source electrode and drain electrode of the first transistor or to the second semiconductor layer of the second transistor through a second contact hole formed continuously through the second buffer layer, the third insulating layer, and the fourth insulating layer.

[0163] According to other features of this specification, one of the source and drain electrodes of the second transistor extends along the side surface of the second contact hole to the bottom of the second contact hole, and the bottom surface of one of the source and drain electrodes of the second transistor can contact one of the source and drain electrodes of the first transistor. In this case, a portion of the second semiconductor layer of the second transistor protrudes from the side surface of the second contact hole, is covered by one of the source and drain electrodes of the second transistor, and can make lateral contact with one of the source and drain electrodes of the second transistor.

[0164] Other embodiments of this specification include a substrate containing a plurality of subpixels, a light-emitting element contained in each of the plurality of subpixels, a plurality of first signal lines arranged on the substrate and including data lines that supply a data voltage and high-potential power supply lines that supply a high-potential power supply voltage, and a plurality of subpixel circuits arranged on the substrate for each of the plurality of subpixels and electrically connected to the plurality of first signal lines, wherein the plurality of subpixel circuits include a first transistor including a first electrode connected to the high-potential power supply line, a gate electrode to which a second light-emitting signal is input, and a second electrode connected to a first node connected to a first electrode of a drive transistor that drives a light-emitting element, and a second transistor including a first electrode connected to the second node, a gate electrode to which a scan signal is input, and a second electrode connected to the data line, wherein a plurality of first signal lines are arranged below the first transistor and the second transistor.

[0165] According to other features of this specification, a plurality of second signal lines may be further included, including a first scan line for supplying a first scan signal, a second scan line for supplying a second scan signal, a first light-emitting signal line for supplying a first light-emitting signal, a second light-emitting signal line for supplying a second light-emitting signal, and an initialization signal line for supplying an initialization voltage.

[0166] According to other features of this specification, a plurality of subpixel circuits may include a drive transistor comprising a first electrode connected to a first node, a gate electrode connected to a third node, and a second electrode connected to a second node; a third transistor comprising a first electrode connected to a third node, a gate electrode connected to a first scan trace, and a second electrode connected to a first node; a fourth transistor comprising a first electrode connected to a second node, a gate electrode connected to a first light-emitting signal trace, and a second electrode connected to a fourth node; a capacitor connected between the third and fourth nodes; and a fifth transistor comprising a first electrode connected to the fourth node, a gate electrode connected to a first light-emitting signal trace, and a second electrode connected to an initialization signal trace.

[0167] According to other features of this specification, the first, second, and fourth transistors may each include a semiconductor layer made of low-temperature polysilicon (LTPS), and the third, driver, and fifth transistors may each include a semiconductor layer made of oxide semiconductor.

[0168] According to other features of this specification, a third transistor, a drive transistor, and a fifth transistor may be arranged on top of the first transistor, the second transistor, and the fourth transistor. In this case, a plurality of second signal lines may be arranged on top of the first and second electrodes of the third transistor, the drive transistor, and the fifth transistor, respectively.

[0169] A display device according to yet another embodiment of this specification includes a substrate containing a plurality of subpixels, a plurality of first signal lines disposed on the substrate, a first buffer layer disposed on the plurality of first signal lines, and a first transistor disposed on the first buffer layer and electrically connected to one of the plurality of first signal lines, and including a first electrode, a gate electrode, a second electrode, and a semiconductor layer. In this case, the first electrode of the first transistor may be superimposed on one first signal line and electrically connected to either one first signal line or the semiconductor layer of the first transistor through one contact hole formed continuously through the first buffer layer.

[0170] According to other features of this specification, a portion of the semiconductor layer of the first transistor protrudes from the side of the contact hole, is covered by the first electrode of the first transistor, and can make lateral contact with the first electrode of the first transistor.

[0171] Although embodiments of this specification have been described in more detail above with reference to the attached drawings, this specification is not necessarily limited to these embodiments and can be modified and implemented in various ways within the scope of the technical concept of this specification. Accordingly, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited by such embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. All technical concepts within the same scope as this specification should be interpreted as being included in the technical scope described herein.

Claims

1. A substrate containing multiple subpixels, A plurality of first signal wirings arranged on the substrate, A first buffer layer arranged on the plurality of first signal lines, A first transistor is disposed on the first buffer layer and electrically connected to one of the plurality of first signal lines. A second buffer layer is placed on the first transistor, and The second transistor is located on the second buffer layer. A display device, including a display device.

2. The first transistor includes a semiconductor layer made of a polycrystalline semiconductor, The second transistor includes a semiconductor layer made of an oxide semiconductor, The display device according to claim 1.

3. The display device according to claim 1, wherein the plurality of first signal lines include high-potential power supply lines and data lines.

4. The display device according to claim 3, wherein the first transistor and the second transistor are superimposed on the high-potential power supply wiring.

5. The display device according to claim 3, wherein the first transistor and the second transistor are superimposed on the data wiring.

6. A third buffer layer is located below the first buffer layer and is arranged on the substrate and the plurality of first signal lines, and A blocking layer is placed on the third buffer layer and is arranged to overlap with the semiconductor layer of the first transistor. The display device according to claim 1, further comprising:

7. An insulating layer disposed on the gate electrode of the first transistor, and Metal pattern disposed on the insulating layer It further includes, The metal pattern electrically connects the first transistor and the first signal wiring. The display device according to claim 1.

8. The system further includes a plurality of second signal wirings positioned above the source and drain electrodes of the second transistor. One of the plurality of second signal lines is electrically connected to the second transistor. The display device according to claim 1.

9. The display device according to claim 8, wherein the plurality of second signal lines include scan lines, light emission signal lines and initialization signal lines.

10. The plurality of second signal lines are arranged between the light-emitting element included in the plurality of subpixels and the source electrode and the drain electrode of the second transistor. The light-emitting element is electrically connected to the source electrode or the drain electrode of the second transistor through the second signal wiring. The display device according to claim 8.

11. The display device according to claim 1, wherein the source electrode of the first transistor is superimposed on the first signal wiring.

12. A first insulating layer disposed on the gate electrode of the first transistor, and A second insulating layer disposed between the gate electrode and the first semiconductor layer of the first transistor. It further includes, The source electrode of the first transistor is connected to either the first signal wiring or the first semiconductor layer of the first transistor through a first contact hole that is continuously formed penetrating the first buffer layer, the first insulating layer, and the second insulating layer. The display device according to claim 11.

13. The source electrode of the first transistor extends along the side surface of the first contact hole to the bottom of the first contact hole, and the bottom surface of the source electrode of the first transistor is in contact with the first signal wiring. A portion of the first semiconductor layer of the first transistor protrudes from the side surface of the first contact hole, is covered by the source electrode of the first transistor, and is in lateral contact with the source electrode of the first transistor. The display device according to claim 12.

14. The display device according to claim 13, wherein the source electrode of the first transistor is in contact with the upper, side, and lower surfaces of a portion of the first semiconductor layer of the first transistor that protrudes from the side surface of the first contact hole.

15. The display device according to claim 1, wherein one of the source electrode and drain electrode of the second transistor is superimposed on one of the source electrode and drain electrode of the first transistor.

16. A third insulating layer disposed on the gate electrode of the second transistor, and A fourth insulating layer disposed between the gate electrode and the second semiconductor layer of the second transistor. It further includes, One of the source electrode and drain electrode of the second transistor is connected to either the source electrode and drain electrode of the first transistor or to the second semiconductor layer of the second transistor through a second contact hole that is continuously formed through the second buffer layer, the third insulating layer and the fourth insulating layer. The display device according to claim 15.

17. One of the source electrode and drain electrode of the second transistor extends along the side surface of the second contact hole to the bottom of the second contact hole, and the bottom surface of one of the source electrode and drain electrode of the second transistor contacts one of the source electrode and drain electrode of the first transistor. A portion of the second semiconductor layer of the second transistor protrudes from the side surface of the second contact hole, is covered by one of the source electrode and the drain electrode of the second transistor, and is in lateral contact with one of the source electrode and the drain electrode of the second transistor. The display device according to claim 16.

18. A substrate containing multiple subpixels, Each of the aforementioned subpixels contains a light-emitting element, A plurality of first signal lines are arranged on the substrate, including data lines that supply data voltage and high-potential power lines that supply high-potential power supply voltage, and Multiple subpixel circuits arranged on the substrate for each of the multiple subpixels and electrically connected to the multiple first signal lines. Includes, The aforementioned multiple subpixel circuits are, A first transistor including a first electrode connected to the high-potential power supply wiring, a gate electrode to which a second light-emitting signal is input, and a second electrode connected to a first node connected to the first electrode of a drive transistor that drives the light-emitting element, and A second transistor including a first electrode connected to a second node connected to the second electrode of the drive transistor, a gate electrode to which a second scan signal is input, and a second electrode connected to the data wiring. Includes, The plurality of first signal wirings are arranged below the first transistor and the second transistor. Display device.

19. First scan wiring that supplies the first scan signal, The second scan wiring that supplies the second scan signal, First light-emitting signal wiring that supplies the first light-emitting signal, The second light-emitting signal wiring that supplies the second light-emitting signal, and Initialization signal wiring that supplies the initialization voltage The display device according to claim 18, further comprising a plurality of second signal wirings including the

20. The aforementioned multiple subpixel circuits are, The drive transistor includes the first electrode connected to the first node, the gate electrode connected to the third node, and the second electrode connected to the second node. A third transistor including a first electrode connected to the third node, a gate electrode connected to the first scan wiring, and a second electrode connected to the first node. A fourth transistor including a first electrode connected to the second node, a gate electrode connected to the first light-emitting signal wiring, and a second electrode connected to the fourth node, A capacitor connected between the third node and the fourth node, and A fifth transistor including a first electrode connected to the fourth node, a gate electrode connected to the first light-emitting signal wiring, and a second electrode connected to the initialization signal wiring. The display device according to claim 19, including the following:

21. The first transistor, the second transistor, and the fourth transistor each include a semiconductor layer made of low-temperature polysilicon (LTPS). The third transistor, the drive transistor, and the fifth transistor each include a semiconductor layer made of an oxide semiconductor. The display device according to claim 20.

22. The third transistor, the drive transistor, and the fifth transistor are arranged above the first transistor, the second transistor, and the fourth transistor. The plurality of second signal wires are arranged above the first and second electrodes of the third transistor, the drive transistor, and the fifth transistor, respectively. The display device according to claim 21.

23. A substrate containing multiple subpixels, Multiple first signal wirings arranged on the aforementioned substrate, A first buffer layer arranged on the plurality of first signal lines, and Displaced on the first buffer layer and electrically connected to one of the plurality of first signal lines, the first transistor includes a first electrode, a gate electrode, a second electrode, and a semiconductor layer. The first electrode of the first transistor is Superimposed on the aforementioned first signal wiring, Through a single contact hole continuously formed through the first buffer layer, it is electrically connected to both the first signal wiring and the semiconductor layer of the first transistor. Display device.

24. The display device according to claim 23, wherein a portion of the semiconductor layer of the first transistor protrudes from the side surface of the contact hole, is covered by the first electrode of the first transistor, and is in lateral contact with the first electrode of the first transistor.

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