Comparator and imaging device

Abstract

This aims to reduce the power supply voltage of the comparator while suppressing the degradation of image quality. [Solution] The comparator comprises a preamplifier that generates a preamplifier output based on the preamplifier input, a postamplifier that generates a postamplifier output based on the preamplifier output, a clamp transistor that limits the amplitude of the preamplifier output based on the postamplifier output, a clamp capacitor that generates a clamp voltage to clamp the gate potential of the clamp transistor, and a reset switch that resets the clamp capacitor.

Description

[Technical Field]

[0001] The present technology relates to a comparator and an image pickup apparatus. More specifically, the present technology relates to a comparator capable of differential input and an image pickup apparatus. [Background Art]

[0002] Comparators are sometimes used for comparing input signals. For example, a comparator that compares a pixel signal with a ramp wave to perform AD (Analog to Digital) conversion on the pixel signal has been disclosed (see, for example, Patent Document 1). [Prior Art Literature] [Patent Literature]

[0003] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2013-168880 [Summary of Invention] [Problem to be Solved by Invention]

[0004] However, in the above-described conventional technology, there has been a risk that image quality degradation is caused along with the reduction of the power supply voltage of the comparator.

[0005] The present technology has been made in view of such circumstances, and an object thereof is to achieve a reduction in the power supply voltage of a comparator while suppressing degradation of the image quality of a captured image. [Means for Solving the Problem]

[0006] This technology was developed to solve the aforementioned problems, and its first aspect is a comparator comprising a pre-amplifier that generates a pre-output based on the pre-input, a post-amplifier that generates a post-output based on the pre-output, a clamp transistor that limits the amplitude of the pre-output based on the post-output, a clamp capacitor that generates a clamp voltage to clamp the gate potential of the clamp transistor, and a reset switch that resets the clamp capacitor. This results in the effect of limiting the amplitude of the pre-output of the pre-amplifier while eliminating the potential difference between the pre-output and the post-output based on the clamp voltage.

[0007] Furthermore, in the first aspect, the preamplifier may include a differential amplifier that generates a preamplifier output based on a differential input, the clamp transistor may be connected between the output of the differential amplifier and the power supply potential, the clamp capacitance may be connected between the gate of the clamp transistor and the output of the subsequent amplifier, and the reset switch may be connected between the gate of the clamp transistor and the output of the differential amplifier. This results in the effect of limiting the amplitude of the output of the differential amplifier while eliminating the potential difference between the output of the differential amplifier and the output of the subsequent amplifier based on the clamp voltage.

[0008] Furthermore, in the first aspect, the preamplifier comprises a differential amplifier that generates a preamplifier output based on a differential input, the postamplifier comprises a first postamplifier that generates a first postamplifier output based on the preamplifier output, and a second postamplifier that generates a second postamplifier output based on the first postamplifier output, the clamp transistor is connected between the output of the first postamplifier and ground potential, the clamp capacitance is connected between the gate of the clamp transistor and the second postamplifier output of the second postamplifier, and the reset switch may be connected between the gate of the clamp transistor and the output of the first postamplifier. This results in the potential difference between the first postamplifier output and the second postamplifier output being eliminated based on the clamp voltage while limiting the amplitude of the output of the differential amplifier.

[0009] Furthermore, in the first aspect, an AZ switch is provided to perform AZ (Auto Zero) of the preceding amplifier and the succeeding amplifier, and the reset switch may be turned on when the preceding amplifier and the succeeding amplifier are performing AZ operation. This results in the potential difference between the output of the differential amplifier and the output of the succeeding amplifier being eliminated at the AZ operating point.

[0010] The second aspect is a comparator comprising: a first transistor to which a first input is applied to the gate; a second transistor to which a second input is applied to the gate; a third transistor connected in series with the first transistor; a fourth transistor connected in series with the second transistor and having its gate connected to the gate of the third transistor; a fifth transistor connected to the first and second transistors; a subsequent amplifier that generates a subsequent output based on the preceding output from the connection point of the first and third transistors; a bias capacitor connected to the gate of the fifth transistor; a first switching unit that switches the connection of the gates of the third and fourth transistors between a first bias voltage and the drain of the third transistor; and a clamp transistor that limits the amplitude of the preceding output based on the subsequent output. This results in the voltage drop across the third and fourth transistors being reduced by the threshold voltage of the third and fourth transistors based on the switching operation of the first switching unit, and the amplitude of the preceding output from the connection point of the first and third transistors being limited.

[0011] Furthermore, in the second aspect, the system may include a clamp capacitance that generates a clamp voltage to clamp the gate potential of the clamp transistor, and a reset switch that resets the clamp capacitance. This allows for the elimination of the potential difference between the preceding and succeeding stage outputs based on the clamp voltage, while also accommodating low power supply voltages.

[0012] Furthermore, in a second aspect, the clamp transistor may be connected between the connection point of the first and third transistors and the power supply potential, the clamp capacitance may be connected between the gate of the clamp transistor and the output of the subsequent amplifier, and the reset switch may be connected between the connection point of the first and third transistors and the gate of the clamp transistor. This results in the effect of limiting the amplitude of the preceding output from the connection point of the first and third transistors while eliminating the potential difference between the preceding output and the subsequent output based on the clamp voltage.

[0013] Furthermore, in a second aspect, the system may include a second switching unit that switches the connection between the gate of the fifth transistor and the drain of the first or second transistor. This results in the gate voltage of the fifth transistor being set based on the bias voltage generated by the bias capacitance when the gate of the fifth transistor is disconnected from the drain of the first or second transistor.

[0014] Furthermore, in a second aspect, the first switching unit may include a first switch for switching the input of a first bias voltage to the gate of the third transistor and a second switch for switching the connection between the gate and drain of the third transistor, and the second switching unit may include a third switch for switching the connection between the gate of the fifth transistor and the drain of the third transistor. This results in the comparator's power supply voltage being set to the same value during the reset phase and the comparison phase, while simultaneously realizing the comparator's reset and comparison operations.

[0015] Furthermore, the third aspect comprises a pixel array section in which pixels are arranged in a matrix in the row direction and column direction, and a column ADC section that performs analog-to-digital (AD) conversion of the pixel signals output from the pixels for each column, wherein the column ADC section includes a comparator that compares the pixel signals with a reference signal, and the comparator may include a preamplifier that generates a preamplifier output based on the preamplifier input, a postamplifier that generates a postamplifier output based on the preamplifier output, a clamp transistor that limits the amplitude of the preamplifier output based on the postamplifier output, a clamp capacitor that generates a clamp voltage to clamp the gate potential of the clamp transistor, and a reset switch that resets the clamp capacitor. As a result, based on the switching operation of the first switching section, the voltage drop of the third and fourth transistors is reduced by the threshold voltage of the third and fourth transistors, the pixel signals are AD converted, and the amplitude of the preamplifier output from the connection point of the first and third transistors is limited.

[0016] Furthermore, in a third aspect, the preamplifier may include a differential amplifier that generates a preamplifier output based on a differential input, the clamp transistor may be connected between the output of the differential amplifier and the power supply potential, the clamp capacitance may be connected between the gate of the clamp transistor and the output of the postamplifier, and the reset switch may be connected between the gate of the clamp transistor and the output of the differential amplifier. This results in the AD conversion of the pixel signal having the amplitude of the differential amplifier output limited while eliminating the potential difference between the output of the differential amplifier and the output of the postamplifier based on the clamp voltage.

[0017] Furthermore, in a third aspect, the preamplifier comprises a differential amplifier that generates a preamplifier output based on a differential input, the postamplifier comprises a first postamplifier that generates a first postamplifier output based on the preamplifier output, and a second postamplifier that generates a second postamplifier output based on the first postamplifier output, the clamp transistor is connected between the output of the first postamplifier and ground potential, the clamp capacitance is connected between the gate of the clamp transistor and the second postamplifier output of the second postamplifier, and the reset switch may be connected between the gate of the clamp transistor and the output of the first postamplifier. This results in the AD conversion of the pixel signal having the potential difference between the first postamplifier output and the second postamplifier output being eliminated based on the clamp voltage while limiting the amplitude of the differential amplifier output.

[0018] Furthermore, in a third aspect, the comparator may include a first transistor to which a first input is applied to the gate, a second transistor to which a second input is applied to the gate, a third transistor connected in series with the first transistor, a fourth transistor connected in series with the second transistor and having its gate connected to the gate of the third transistor, a fifth transistor connected with the first and second transistors, a subsequent amplifier that generates a subsequent output based on the preceding output from the connection point of the first and third transistors, a bias capacitor connected to the gate of the fifth transistor, a first switching unit that switches the connection of the gates of the third and fourth transistors between a first bias voltage and the drain of the third transistor, and a clamp transistor that limits the amplitude of the preceding output based on the subsequent output. This results in the AD conversion of the pixel signal being reduced by the threshold voltage of the third and fourth transistors based on the switching operation of the first switching unit, and the amplitude of the preceding output from the connection point of the first and third transistors being limited.

[0019] Furthermore, in a third aspect, the comparator may include a clamp capacitor that generates a clamp voltage for clamping the gate potential of the clamp transistor, and a reset switch that resets the clamp capacitor. This achieves the effect of eliminating the potential difference between the preceding-stage output and the subsequent-stage output based on the clamp voltage while achieving lower power supply voltage in AD conversion of pixel signals.

[0020] Furthermore, in the third aspect, the comparator may further include a second switching unit that switches connection between the gate of the fifth transistor and the drain of the first transistor or the second transistor. This achieves the effect of performing AD conversion on a pixel signal while setting the gate voltage of the fifth transistor based on a bias voltage generated by a bias capacitor when the gate of the fifth transistor is disconnected from the drain of the first transistor or the second transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] [Figure 1] It is a circuit diagram showing a configuration example of the comparator according to the first embodiment. [Figure 2] It is a diagram showing an example of voltages applied to each transistor during and after inversion of the comparator according to the first embodiment. [Figure 3] It is a timing chart showing waveforms of each part during operation of the comparator according to the first embodiment. [Figure 4] It is a circuit diagram showing a configuration example of the comparator according to the second embodiment. [Figure 5] It is a diagram showing an example of voltages applied to each transistor during and after inversion of the comparator according to the second embodiment. [Figure 6] It is a circuit diagram showing a configuration example of the comparator according to the third embodiment. [Figure 7] It is a diagram showing an example of voltages applied to each transistor during and after inversion of the comparator according to the third embodiment. [Figure 8]FIG. 1 is a circuit diagram showing a configuration example of a comparator according to a fourth embodiment. [Figure 9] FIG. 2 is a diagram showing an example of voltages applied to each transistor during and after inversion of the comparator according to the fourth embodiment. [Figure 10] FIG. 3 is a circuit diagram showing a configuration example of a comparator according to a fifth embodiment. [Figure 11] FIG. 4 is a circuit diagram showing a configuration example of a comparator according to a sixth embodiment. [Figure 12] FIG. 5 is a timing chart showing waveforms at each part during operation of the comparator according to the sixth embodiment. [Figure 13] FIG. 6 is a circuit diagram showing a configuration example of a comparator according to a seventh embodiment. [Figure 14] FIG. 7 is a timing chart showing waveforms at each part during operation of the comparator according to the seventh embodiment. [Figure 15] FIG. 8 is a circuit diagram showing a configuration example of a comparator according to an eighth embodiment. [Figure 16] FIG. 9 is a circuit diagram showing a configuration example of a comparator according to a ninth embodiment. [Figure 17] FIG. 10 is a circuit diagram showing a configuration example of a comparator according to a tenth embodiment. [Figure 18] FIG. 11 is a block diagram showing a configuration example of an imaging device according to an eleventh embodiment. [Figure 19] FIG. 12 is a block diagram showing a configuration example of a solid-state imaging device according to an eleventh embodiment. [Figure 20] FIG. 13 is a diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the eleventh embodiment. [Figure 21] FIG. 14 is a block diagram showing a configuration example for each column of the solid-state imaging device according to the eleventh embodiment. [Figure 22] FIG. 15 is a timing chart showing an example of waveforms at each part during signal readout of the solid-state imaging device according to the eleventh embodiment. [Figure 23] FIG. 16 is a block diagram showing a schematic configuration example of a vehicle control system. [Figure 24]This is an explanatory diagram showing an example of the installation location of the imaging unit. [Modes for carrying out the invention]

[0022] The following describes the embodiments for implementing this technology. The description will proceed in the following order. 1. First Embodiment (An example in which an N-channel clamp transistor is provided between the differential amplifier and the subsequent amplifier to limit the amplitude of the differential amplifier's output based on the output of the subsequent amplifier) 2. Second Embodiment (An example in which a P-channel clamp transistor is provided between the differential amplifier and the subsequent amplifier to limit the amplitude of the differential amplifier's output based on the output of the subsequent amplifier) 3. Third Embodiment (An example in which a P-channel clamp transistor is provided between the downstream amplifier and the inverter to limit the amplitude of the output of the downstream amplifier based on the output of the inverter downstream of the downstream amplifier) 4. Fourth Embodiment (An example in which a P-channel clamp transistor is provided between the first and second stages of the subsequent amplifier to limit the amplitude of the output of the first stage of the subsequent amplifier based on the output of the second stage of the subsequent amplifier) 5. Fifth Embodiment (An example in which a P-channel clamp transistor is provided between the differential amplifier and the first stage of the subsequent amplifier to limit the amplitude of the output of the differential amplifier based on the output of the first stage of the subsequent amplifier, and a P-channel clamp transistor is provided between the first and second stages of the subsequent amplifier to limit the amplitude of the output of the first stage of the subsequent amplifier based on the output of the second stage of the subsequent amplifier) 6. Sixth Embodiment (An example in which an N-channel clamp transistor is provided between the differential amplifier and the subsequent amplifier to limit the amplitude of the differential amplifier's output based on the output of the subsequent amplifier, and the power supply voltage for the comparator's reset phase is reduced.) 7. Seventh Embodiment (An example in which a P-channel clamp transistor is provided between the differential amplifier and the subsequent amplifier to limit the amplitude of the differential amplifier's output based on the output of the subsequent amplifier, and the power supply voltage for the comparator's reset phase is reduced.) 8. Eighth Embodiment (An example in which a P-channel clamp transistor is provided between the downstream amplifier and the inverter to limit the amplitude of the output of the downstream amplifier based on the output of the inverter downstream of the downstream amplifier, and the power supply voltage of the comparator reset phase is reduced.) 9. Ninth Embodiment (An example in which a P-channel clamp transistor is provided between the first and second stages of the subsequent amplifier to limit the amplitude of the output of the first stage of the subsequent amplifier based on the output of the second stage of the subsequent amplifier, and the power supply voltage of the comparator's reset phase is reduced.) 10. Tenth Embodiment (An example in which a P-channel clamp transistor is provided between the differential amplifier and the first stage of the subsequent amplifier to limit the amplitude of the output of the differential amplifier based on the output of the first stage of the subsequent amplifier, and a P-channel clamp transistor is provided between the first and second stages of the subsequent amplifier to limit the amplitude of the output of the first stage of the subsequent amplifier based on the output of the second stage of the subsequent amplifier, and the power supply voltage of the comparator reset phase is reduced.) 11. Eleventh Embodiment (An example in which a comparator with a reduced power supply voltage during the reset phase is applied to an imaging device) 12. Examples of applications to mobile devices

[0023] <1. First Embodiment> Figure 1 is a circuit diagram showing an example of the configuration of a comparator according to the first embodiment.

[0024] In the figure, comparator CM1 balances comparator inputs DV1 and DV2 based on auto-zero operation and outputs a voltage VO corresponding to the difference between comparator inputs DV1 and DV2. Comparator CM1 includes a differential amplifier AN1, a subsequent amplifier AN2, and an inverter AN3. Subsequent amplifier AN2 is connected after differential amplifier AN1, and inverter AN3 is connected after subsequent amplifier AN2. Comparator CM1 also includes a clamp transistor TK, a clamp capacitor CK, and a reset switch WR.

[0025] The differential amplifier AN1 generates an output to the subsequent amplifier AN2 based on the differential input. The differential amplifier AN1 comprises PMOS transistors T3 and T4, NMOS transistors T1, T2, and T5, and AZ (Auto Zero) switches Z1 and Z2. The PMOS transistors T3 and T4 can operate as load transistors, the NMOS transistors T1 and T2 can operate as differential transistors, and the NMOS transistor T5 can operate as a current source transistor.

[0026] PMOS transistor T3 and NMOS transistor T1 are connected in series with each other. PMOS transistor T4 and NMOS transistor T2 are also connected in series with each other. The sources of each PMOS transistor T3 and T4 are connected to the power supply voltage VDD1, and the gates of each PMOS transistor T3 and T4 are connected to the drain of PMOS transistor T3. Capacitor C3 is also connected in parallel with PMOS transistor T4.

[0027] The gate of NMOS transistor T1 receives the input signal VIN via input capacitor C1. The gate of NMOS transistor T2 receives the input signal VIP via input capacitor C2. The input signals VIN and VIP can generate a differential input.

[0028] An AZ switch Z1 is connected between the gate and drain of NMOS transistor T1, and an AZ switch Z2 is connected between the gate and drain of NMOS transistor T2. The sources of each NMOS transistor T1 and T2 are connected to ground potential GND via NMOS transistor T5. Each AZ switch Z1 and Z2 is opened and closed based on the auto-zero signal AZ.

[0029] A bias voltage VB is applied to the gate of the NMOS transistor T5. Based on the bias voltage VB, the NMOS transistor T5 can operate as a constant current source.

[0030] The subsequent amplifier AN2 amplifies the output of the differential amplifier AN1. The subsequent amplifier AN2 includes a PMOS transistor T10 and an NMOS transistor T11.

[0031] PMOS transistor T10 and NMOS transistor T11 are connected in series. The source of PMOS transistor T10 is connected to the power supply voltage VDD1. The gate of PMOS transistor T10 is connected to the drain of PMOS transistor T4. A switch W14 is connected between the gate and drain of NMOS transistor T11. Capacitor C4 is also connected to the gate of NMOS transistor T11. The source of NMOS transistor T11 is connected to ground potential GND. Switch W14 is opened and closed based on the auto-zero signal AZ.

[0032] A clamp transistor TK is connected between the differential amplifier AN1 and the subsequent amplifier AN2. The clamp transistor TK limits the amplitude of the output of the differential amplifier AN1 based on the output of the subsequent amplifier AN2. In this case, the clamp transistor TK can be connected in parallel with the PMOS transistor T4. An NMOS transistor can be used for the clamp transistor TK.

[0033] A clamp capacitor CK is connected between the gate of clamp transistor TK and the drain of PMOS transistor T10. The clamp capacitor CK generates a clamp voltage that clamps the gate potential of clamp transistor TK.

[0034] A reset switch WR is connected between the gate of clamp transistor TK and the drain of PMOS transistor T4. The reset switch WR resets the clamp capacitance CK. The reset switch WR can be turned on when differential amplifier AN1 and subsequent amplifier AN2 are operating in AZ mode. The reset switch WR is opened and closed based on the reset signal RSK.

[0035] When the output of differential amplifier AN1 is inverted, the output of differential amplifier AN1 decreases, and NMOS transistors T1 and T2 move into the linear operating region. At this time, a trap-detrap phenomenon occurs in the channel region of NMOS transistors T1 and T2, and vertical lines appear in the captured image due to variations in the trap-detrap phenomenon between columns. If the output of differential amplifier AN1 decreases too much, PMOS transistor T10 turns on, and the drain potential of PMOS transistor T10 increases. As a result, clamp transistor TK turns on, and the source potential of clamp transistor TK increases. As a result, the decrease in the output of differential amplifier AN1 is suppressed, the occurrence of the trap-detrap phenomenon in the channel region of NMOS transistors T1 and T2 is prevented, and vertical lines in the captured image can be prevented.

[0036] On the other hand, if the clamp transistor TK of comparator CM1 is provided and the voltage of comparator CM1 is reduced, the clamp transistor TK may turn on at the inversion point of the output of differential amplifier AN1. When the clamp transistor TK turns on at the inversion point of the output of differential amplifier AN1, the current flowing to the subsequent amplifier AN2 decreases, and the characteristics of comparator CM1 deteriorate.

[0037] Here, the clamp capacitance CK generates a clamp voltage that clamps the gate potential of the clamp transistor TK. This clamp voltage can be set so that the clamp transistor TK turns off at the inversion point of the output of the differential amplifier AN1. Therefore, by connecting the clamp capacitance CK to the gate of the clamp transistor TK, it is possible to prevent the clamp transistor TK from turning on at the inversion point of the output of the differential amplifier AN1, thereby preventing a degradation in the characteristics of the comparator CM1 while lowering the voltage of the comparator CM1.

[0038] Inverter AN3 inverts the output of the subsequent amplifier AN2. Inverter AN3 includes a PMOS transistor T12 and an NMOS transistor T13.

[0039] PMOS transistor T12 and NMOS transistor T13 are connected in series. The gates of PMOS transistor T12 and NMOS transistor T13 are connected to the drain of PMOS transistor T10. The source of PMOS transistor T12 is connected to the power supply voltage VDD2. The output voltage VO is output from the drain of NMOS transistor T13. The power supply voltage VDD2 can be less than the power supply voltage VDD1.

[0040] Figure 2 shows an example of the voltages across each transistor during and after the inversion of the comparator according to the first embodiment. In the figure, a represents the voltage across each transistor during the inversion of the comparator CM1, and b represents the voltage across each transistor after the inversion of the comparator CM1.

[0041] In figure a, when comparator CM1 is inverted, the differential amplifier AN1 has the power supply voltage VDD1 allocated to the gate / source voltages Vgs11 of PMOS transistors T3 and T4, the source / drain voltages Vds12 of NMOS transistors T1 and T2, and the source / drain voltage Vds13 of NMOS transistor T5.

[0042] Furthermore, in the subsequent amplifier AN2 when comparator CM1 is inverted, the power supply voltage VDD1 is allocated to the source / drain voltage Vds21 of PMOS transistor T10, the gate / source voltage Vgs21 of PMOS transistor T10, and the source / drain voltage Vds22 of NMOS transistor T11.

[0043] In this case, the gate / source voltage Vgs11 of the PMOS transistors T3 and T4 of differential amplifier AN1 is determined by the power supply voltage VDD1. Also, the source / drain voltage Vds22 of the NMOS transistor T11 of the subsequent amplifier AN2 is determined by the ground potential GND. Here, if the power supply voltage VDD1 is reduced, the source / drain voltage Vds22 of the NMOS transistor T11 becomes greater than the voltage obtained by subtracting the gate / source voltage Vgs11 of the PMOS transistors T3 and T4 from the power supply voltage VDD1. For this reason, without a clamp capacitor CK, the clamp transistor TK may turn on at the operating point when the comparator CM1 is inverted.

[0044] On the other hand, by providing a clamp capacitor CK, a charge corresponding to the potential difference between the gate / source voltages Vgs11 of PMOS transistors T3 and T4 and the source / drain voltage Vds22 of NMOS transistor T11 at the AZ operating point can be accumulated in the clamp capacitor CK. At this time, the clamp voltage VK generated by the clamp capacitor CK can cancel out the potential difference between the gate / source voltages Vgs11 of PMOS transistors T3 and T4 and the source / drain voltage Vds22 of NMOS transistor T11 at the AZ operating point. As a result, the gate / source voltage Vgsk of clamp transistor TK at the AZ operating point can be set to 0, preventing clamp transistor TK from turning on at the operating point when comparator CM1 is inverted.

[0045] In figure b, after the inversion of comparator CM1, the output of differential amplifier AN1 decreases. If the output of differential amplifier AN1 decreases too much, PMOS transistor T10 turns on, and the drain potential of PMOS transistor T10 increases. As a result, the gate / source voltage Vgsk of clamp transistor TK increases, and clamp transistor TK turns on. This increases the source potential of clamp transistor TK, which can suppress the decrease in the output of differential amplifier AN1. At this time, the output of differential amplifier AN1 can be stopped from decreasing based on the sum of the clamp voltage VK generated by clamp capacitor CK and the gate / source voltage Vgsk of clamp transistor TK. Therefore, it is possible to prevent the source / drain voltage Vds12 of NMOS transistors T1 and T2 from collapsing, and to prevent deterioration of the characteristics of differential amplifier AN1.

[0046] Figure 3 is a timing chart showing the waveforms of each part during the operation of the comparator according to the first embodiment.

[0047] In the figure, the reference signal VRF is used as the input signal VIN of comparator CM1, and the potential of the vertical signal line VSL that transmits the pixel signal is used as the input signal VIP of comparator CM1. The reference signal VRF can include ramp waves RAP and RAD. The ramp wave RAP is compared with the P-phase level of the pixel signal, and the ramp wave RAD is compared with the D-phase level of the pixel signal.

[0048] Then, when the auto-zero signal AZ rises (time t11), the AZ switches Z1 and Z2 and switch W14 are turned on. At this time, charge is accumulated in the input capacitors C1 and C2 so that the comparator inputs DV1 and DV2 are balanced based on the current flowing through the PMOS transistors T3 and T4. Also, charge is accumulated in capacitor C4 so that the operating point of the subsequent amplifier AN2 is optimized based on the current flowing through the NMOS transistor T11.

[0049] Furthermore, the reset signal RSK rises simultaneously with the rising edge of the auto-zero signal AZ (at time t11). At this time, the reset switch WR is turned on, and the clamp capacitance CK is reset.

[0050] Next, after the auto-zero signal AZ and reset signal RSK fall, the ramp wave RAP is input as the reference signal VRF (time t12). Then, in comparator CM1, the potential of the vertical signal line VSL is compared with the ramp wave RAP, and when the level of the potential of the vertical signal line VSL matches the level of the ramp wave RAP, the output of comparator CM1 inverts. At this time, the P-phase level of the pixel signal can be converted using AD conversion based on the inversion timing of the output of comparator CM1.

[0051] Next, a ramp wave RAD is input as the reference signal VRF (time t13). Then, the potential of the vertical signal line VSL is compared with the ramp wave RAD in comparator CM1. When the level of the potential of the vertical signal line VSL matches the level of the ramp wave RAD, the output of comparator CM1 inverts. At this time, the D-phase level of the pixel signal can be converted using AD conversion based on the inversion timing of the output of comparator CM1.

[0052] As described above, in the first embodiment, a clamp transistor TK is connected between the differential amplifier AN1 and the subsequent amplifier AN2, and a clamp capacitor CK is connected to the gate of the clamp transistor TK. This allows the potential difference between the output of the differential amplifier AN1 and the output of the subsequent amplifier AN2 to be eliminated based on the clamp voltage generated by the clamp capacitor CK, while limiting the amplitude of the output of the differential amplifier AN1. As a result, it is possible to prevent vertical lines in the captured image caused by variations in the trap-detrap phenomenon between columns in the channel region of the NMOS transistors T1 and T2, and to lower the voltage of the comparator CM1 while preventing a decrease in the characteristics of the comparator CM1.

[0053] <2. Second Embodiment> In the first embodiment described above, a clamp transistor TK is connected between the differential amplifier AN1 and the subsequent amplifier AN2, a clamp capacitor CK is connected to the gate of the clamp transistor TK, and an N-channel transistor is used for the clamp transistor TK. In this second embodiment, a clamp transistor is connected between the differential amplifier and the subsequent amplifier, a clamp capacitor CK is connected to the gate of the clamp transistor, and a P-channel transistor is used for the clamp transistor.

[0054] Figure 4 is a circuit diagram showing an example of the configuration of a comparator according to the second embodiment.

[0055] In the figure, comparator CM2 balances comparator inputs DV1 and DV2 based on auto-zero operation and outputs a voltage VO corresponding to the difference between comparator inputs DV1 and DV2. Comparator CM2 includes a differential amplifier AP1, a subsequent amplifier AP2, and an inverter AP3. Subsequent amplifier AP2 is connected after differential amplifier AP1, and inverter AP3 is connected after subsequent amplifier AP2. Comparator CM2 also includes a clamp transistor TK', a clamp capacitor CK, and a reset switch WR.

[0056] The differential amplifier AP1 generates an output to the subsequent amplifier AP2 based on the differential input. The differential amplifier AP1 comprises PMOS transistors T3', T4', NMOS transistors T1', T2', T5', and AZ switches Z1, Z2. The PMOS transistors T3' and T4' can operate as load transistors, the NMOS transistors T1' and T2' can operate as differential transistors, and the NMOS transistor T5' can operate as a current source transistor.

[0057] PMOS transistor T3' and NMOS transistor T1' are connected in series with each other. PMOS transistor T4' and NMOS transistor T2' are also connected in series with each other. The sources of each PMOS transistor T3' and T4' are connected to ground potential (GND), and the gates of each PMOS transistor T3' and T4' are connected to the drain of PMOS transistor T3'. Capacitor C3 is connected in parallel with PMOS transistor T4'.

[0058] The input signal VIN is input to the gate of NMOS transistor T1' via input capacitor C1. The input signal VIP is input to the gate of NMOS transistor T2' via input capacitor C2.

[0059] An AZ switch Z1 is connected between the gate and drain of NMOS transistor T1', and an AZ switch Z2 is connected between the gate and drain of NMOS transistor T2'. The sources of each NMOS transistor T1' and T2' are connected to the power supply voltage VDD1 via NMOS transistor T5'.

[0060] A bias voltage VB is applied to the gate of the NMOS transistor T5'. Based on the bias voltage VB, the NMOS transistor T5' can operate as a constant current source.

[0061] The subsequent amplifier AP2 amplifies the output of the differential amplifier AP1. The subsequent amplifier AP2 includes an NMOS transistor T10' and a PMOS transistor T11'.

[0062] The NMOS transistor T10' and the PMOS transistor T11' are connected in series. The source of the NMOS transistor T10' is connected to ground potential GND. The gate of the NMOS transistor T10' is connected to the drain of the PMOS transistor T4'. A switch W14 is connected between the gate and drain of the PMOS transistor T11'. Capacitor C4 is also connected to the gate of the PMOS transistor T11'. The source of the PMOS transistor T11' is connected to the power supply voltage VDD1.

[0063] A clamp transistor TK' is connected between the differential amplifier AP1 and the subsequent amplifier AP2. The clamp transistor TK' limits the amplitude of the output of the differential amplifier AP1 based on the output of the subsequent amplifier AP2. In this case, the clamp transistor TK' can be connected in parallel with a PMOS transistor T4'. A PMOS transistor can be used for the clamp transistor TK'.

[0064] A clamping capacitor CK is connected between the gate of clamping transistor TK' and the drain of NMOS transistor T10'. A reset switch WR is connected between the gate of clamping transistor TK' and the drain of PMOS transistor T4'.

[0065] Inverter AP3 inverts the output of the subsequent amplifier AP2. Inverter AP3 can be configured similarly to inverter AN3 in the first embodiment described above.

[0066] Figure 5 shows an example of the voltages across each transistor during and after the inversion of the comparator according to the second embodiment. In the figure, a represents the voltage across each transistor during the inversion of the comparator CM2, and b represents the voltage across each transistor after the inversion of the comparator CM2.

[0067] In figure a, when comparator CM2 is inverted, the differential amplifier AP1 has the power supply voltage VDD1 allocated to the gate / source voltages Vgs11 of PMOS transistors T3' and T4', the source / drain voltages Vds12 of NMOS transistors T1' and T2', and the source / drain voltage Vds13 of NMOS transistor T5'.

[0068] Furthermore, in the subsequent amplifier AP2 when the comparator CM2 is inverted, the power supply voltage VDD1 is allocated to the source / drain voltage Vds21 of the NMOS transistor T10', the gate / source voltage Vgs21 of the PMOS transistor T10', and the source / drain voltage Vds22 of the PMOS transistor T11'.

[0069] In this case, the gate / source voltage Vgs11 of the PMOS transistors T3' and T4' of the differential amplifier AP1 is determined from the ground potential GND. Also, the source / drain voltage Vds22 of the PMOS transistor T11' of the subsequent amplifier AP2 is determined from the power supply voltage VDD1.

[0070] In figure b, after the inversion of comparator CM2, the output of differential amplifier AP1 stops rising based on the sum of the clamp voltage VK generated by clamp capacitor CK and the gate / source voltage Vgsk of clamp transistor TK'. This prevents the source / drain voltage Vds12 of NMOS transistors T1' and T2' from being crushed, thus preventing deterioration of the characteristics of differential amplifier AP1.

[0071] Thus, in the second embodiment described above, a clamp transistor TK' is connected between the differential amplifier AP1 and the subsequent amplifier AP2, and a clamp capacitor CK is connected to the gate of the clamp transistor TK'. This makes it possible to limit the amplitude of the output of the differential amplifier AP1 while eliminating the potential difference between the output of the differential amplifier AP1 and the output of the subsequent amplifier AP2 based on the clamp voltage generated by the clamp capacitor CK.

[0072] <3. Third Embodiment> In the second embodiment described above, a clamp transistor TK' is connected between the differential amplifier AP1 and the subsequent amplifier AP2, and a clamp capacitor CK is connected to the gate of the clamp transistor TK'. In this third embodiment, the clamp transistor TK' is connected between the subsequent amplifier AP2 and the inverter AP3, and a clamp capacitor CK is connected to the gate of the clamp transistor TK'.

[0073] Figure 6 is a circuit diagram showing an example of the configuration of a comparator according to the third embodiment.

[0074] In the figure, the comparator CM3 includes a differential amplifier AP1, a subsequent amplifier AP2, and an inverter AP3. Here, the clamp transistor TK' is connected between the subsequent amplifier AP2 and the inverter AP3. In this case, the clamp transistor TK' can be connected in parallel with the NMOS transistor T10'.

[0075] The clamp capacitance CK is connected between the gate of clamp transistor TK' and the drain of PMOS transistor T12. The reset switch WR is connected between the gate of clamp transistor TK' and the drain of NMOS transistor T10'.

[0076] Additionally, a reset switch WR' is connected between the drain and gate of PMOS transistor T12. The reset switch WR' is opened and closed based on the reset signal RSK. The reset switch WR' can short the input and output to expose the inversion threshold of inverter AP3 to the clamp capacitance CK when crossing a logic gate.

[0077] Figure 7 shows an example of the voltages across each transistor during and after the inversion of the comparator according to the third embodiment. In the figure, a represents the voltage across each transistor during the inversion of the comparator CM3, and b represents the voltage across each transistor after the inversion of the comparator CM3.

[0078] In point a of the same figure, when the comparator CM3 is inverted, the power supply voltage VDD1 in the subsequent amplifier AP2 is allocated to the source / drain voltage Vds21 of the NMOS transistor T10' and the gate / source voltage Vgs22 of the PMOS transistor T11'.

[0079] Furthermore, in inverter AP3 when comparator CM3 is inverted, the power supply voltage VDD1 is allocated to the gate / source voltage Vgs32 of PMOS transistor T12 and the gate / source voltage Vgs31 of NMOS transistor T13.

[0080] In point b of the figure, after the inversion of the comparator CM3, the output of the subsequent amplifier AP2 stops rising based on the sum of the clamp voltage VK generated by the clamp capacitor CK and the gate / source voltage Vgsk of the clamp transistor TK'. This prevents the gate / source voltage Vgs22 of the PMOS transistor T11' from being crushed, thus preventing deterioration of the characteristics of the subsequent amplifier AP2.

[0081] Thus, in the third embodiment described above, the clamp transistor TK' is connected between the downstream amplifier AP2 and the inverter AP3, and the clamp capacitor CK is connected to the gate of the clamp transistor TK'. This makes it possible to limit the amplitude of the output of the downstream amplifier AP2 while eliminating the potential difference between the output of the downstream amplifier AP2 and the output of the inverter AP3 based on the clamp voltage generated by the clamp capacitor CK.

[0082] <4. Fourth Embodiment> In the third embodiment described above, the clamp transistor TK' is connected between the subsequent amplifier AP2 and the inverter AP3, and the clamp capacitor CK is connected to the gate of the clamp transistor TK'. In this fourth embodiment, the clamp transistor TK' is connected between the first and second stages of the subsequent amplifier, and the clamp capacitor CK is connected to the gate of the clamp transistor TK'.

[0083] Figure 8 is a circuit diagram showing an example of the configuration of a comparator according to the fourth embodiment.

[0084] In the figure, this comparator CM4 is the same as the comparator CM3 of the third embodiment described above, with the addition of a subsequent amplifier AP5. A subsequent amplifier AP2 is connected after the differential amplifier AP1, a subsequent amplifier AP5 is connected after the subsequent amplifier AP2, and an inverter AP3 is connected after the subsequent amplifier AP5.

[0085] The subsequent amplifier AP5 amplifies the output of the subsequent amplifier AP2. The subsequent amplifier AP5 includes a PMOS transistor T14 and an NMOS transistor T15.

[0086] PMOS transistor T14 and NMOS transistor T14 are connected in series with each other. The source of PMOS transistor T14 is connected to the power supply voltage VDD1. The gate of PMOS transistor T14 is connected to the drain of PMOS transistor T11'. A switch W15 is connected between the gate and drain of NMOS transistor T15. Capacitor C5 is also connected to the gate of NMOS transistor T15. The source of NMOS transistor T15 is connected to ground potential GND. Switch W15 is opened and closed based on the auto-zero signal AZ.

[0087] The clamp transistor TK' is connected between the subsequent amplifiers AP2 and AP5. In this case, the clamp transistor TK' can be connected in parallel with the NMOS transistor T10'.

[0088] The clamp capacitance CK is connected between the gate of the clamp transistor TK' and the drain of the PMOS transistor T14. The reset switch WR is connected between the gate of the clamp transistor TK' and the drain of the NMOS transistor T10'. The rest of the configuration of the comparator CM4 in the fourth embodiment is the same as that of the comparator CM3 in the third embodiment described above.

[0089] Figure 9 shows an example of the voltages across each transistor during and after the inversion of the comparator according to the fourth embodiment. In the figure, a represents the voltage across each transistor during the inversion of the comparator CM4, and b represents the voltage across each transistor after the inversion of the comparator CM4.

[0090] In point a of the same figure, when the comparator CM4 is inverted, the power supply voltage VDD1 in the subsequent amplifier AP2 is allocated to the source / drain voltage Vds21 of the NMOS transistor T10' and the gate / source voltage Vgs22 of the PMOS transistor T11'.

[0091] Furthermore, in the subsequent amplifier AP5 when the comparator CM3 is inverted, the power supply voltage VDD1 is allocated to the source / drain voltage Vds51 of the PMOS transistor T14 and the gate / source voltage Vgs52 of the NMOS transistor T15.

[0092] In point b of the figure, after the inversion of the comparator CM4, the output of the subsequent amplifier AP2 stops rising based on the sum of the clamp voltage VK generated by the clamp capacitor CK and the gate / source voltage Vgsk of the clamp transistor TK'. This prevents the gate / source voltage Vgs22 of the PMOS transistor T11' from being crushed, thus preventing deterioration of the characteristics of the subsequent amplifier AP2.

[0093] Thus, in the fourth embodiment described above, the clamp transistor TK' is connected between the subsequent amplifiers AP2 and AP5, and the clamp capacitor CK is connected to the gate of the clamp transistor TK'. This makes it possible to limit the amplitude of the output of the subsequent amplifier AP2 while eliminating the potential difference between the output of the subsequent amplifier AP2 and the output of the subsequent amplifier AP5 based on the clamp voltage generated by the clamp capacitor CK.

[0094] <5. Fifth Embodiment> In the fourth embodiment described above, a clamp transistor TK' is connected between the subsequent amplifiers AP2 and AP5, and a clamp capacitor CK is connected to the gate of the clamp transistor TK'. In this fifth embodiment, clamp transistors are connected between the differential amplifier AP1 and the subsequent amplifier AP2, and between the subsequent amplifiers AP2 and AP5, respectively, and clamp capacitors are connected to the gate of each clamp transistor.

[0095] Figure 10 is a circuit diagram showing an example of the configuration of a comparator according to the fifth embodiment.

[0096] In the figure, this comparator CM5 is the same as the comparator CM4 of the fourth embodiment described above, with the addition of a clamp transistor TK'', a clamp capacitor CK'', and a reset switch WR''. The other configurations of the comparator CM5 of the fifth embodiment are the same as those of the comparator CM4 of the fourth embodiment described above.

[0097] The clamp transistor TK'' is connected between the differential amplifier AP1 and the subsequent amplifier AP2. The clamp transistor TK'' limits the amplitude of the output of the differential amplifier AP1 based on the output of the subsequent amplifier AP2. In this case, the clamp transistor TK'' can be connected in parallel with the PMOS transistor T4''. A PMOS transistor can be used for the clamp transistor TK''.

[0098] A clamping capacitor CK is connected between the gate of clamping transistor TK'' and the drain of NMOS transistor T10''. A reset switch WR is connected between the gate of clamping transistor TK'' and the drain of PMOS transistor T4''.

[0099] Thus, in the fifth embodiment described above, a clamp transistor TK' is connected between the differential amplifier AP1 and the subsequent amplifier AP2, and a clamp capacitor CK is connected to the gate of the clamp transistor TK'. Additionally, the clamp transistor TK' is connected between the subsequent amplifiers AP2 and AP5, and a clamp capacitor CK is connected to the gate of the clamp transistor TK'. This allows the amplitude of the outputs of the differential amplifier AP1 and the subsequent amplifier AP2 to be limited, while eliminating the potential difference between the outputs of the differential amplifier AP1 and the subsequent amplifier AP2, and the potential difference between the outputs of the subsequent amplifiers AP2 and AP5, based on the clamp voltages generated by the clamp capacitors CK and CK'.

[0100] <6. Sixth Embodiment> In the first embodiment described above, a clamp transistor TK is connected between the differential amplifier AN1 and the subsequent amplifier AN2, and a clamp capacitor CK is connected to the gate of the clamp transistor TK. In this sixth embodiment, a clamp transistor TK is connected between the differential amplifier AN1 and the subsequent amplifier AN2, a clamp capacitor CK is connected to the gate of the clamp transistor TK, and the power supply voltage for the comparator's reset phase is reduced.

[0101] Figure 11 is a circuit diagram showing an example of the configuration of a comparator according to the sixth embodiment.

[0102] In the figure, this comparator CM6 has switching units K1, K4, and K12 added to the comparator CM1 of the first embodiment described above. The other configurations of the comparator CM6 of the sixth embodiment are the same as those of the comparator CM1 of the first embodiment described above.

[0103] The switching unit K1 switches the connection between the gates of PMOS transistors T3 and T4 between the bias voltage VB1 and the drain of PMOS transistor T3. The switching unit K1 includes switches W1 and W2. Switch W1 switches the input of the bias voltage VB1 to the gates of PMOS transistors T3 and T4. Switch W2 switches the connection between the gate and drain of PMOS transistor T3.

[0104] The switching section K12 switches the connection between the gate of NMOS transistor T5 and the drain of NMOS transistor T1. The switching section K12 includes a switch W3. The switch W3 switches the connection between the gate of NMOS transistor T5 and the drain of NMOS transistor T1.

[0105] The switching unit K4 switches the connection of the gate of PMOS transistor T10 between the bias voltage VB3 and the drain of PMOS transistor T4. The switching unit K4 includes switches W12 and W13. Switch W12 switches the input of the bias voltage VB3 to the gate of PMOS transistor T10. Switch W13 switches the connection between the gate of PMOS transistor T10 and the drain of PMOS transistor T4.

[0106] Switches W1, W3, and W12 receive the auto-zero signal AZ, while switches W2 and W13 receive the auto-zero inversion signal XAZ. The auto-zero inversion signal XAZ is the inverted version of the auto-zero signal AZ.

[0107] During the reset phase, the AZ switches Z1 and Z2 are turned on based on the auto-zero signal AZ. At this time, charge is accumulated in the input capacitors C1 and C2 so that the comparator inputs DV1 and DV2 are balanced based on the current flowing through the PMOS transistors T3 and T4.

[0108] Furthermore, switches W1 and W3 are turned on based on the auto-zero signal AZ, and switch W2 is turned off based on the auto-zero inversion signal XAZ. Then, a bias voltage VB1 is applied to the gates of PMOS transistors T3 and T4, and current flows through PMOS transistors T3 and T4. At this time, the voltage drop across PMOS transistors T3 and T4 is equivalent to the source / drain voltage Vds11 of PMOS transistors T3 and T4. On the other hand, if the gates of PMOS transistors T3 and T4 are connected to the drain of PMOS transistor T3, the voltage drop across PMOS transistors T3 and T4 is equivalent to the gate / source voltage Vgs11 of PMOS transistors T3 and T4. For this reason, when a bias voltage VB1 is applied to the gates of PMOS transistors T3 and T4, the voltage drop across PMOS transistors T3 and T4 is reduced by the threshold voltage Vth1 of PMOS transistors T3 and T4 compared to when the gates of PMOS transistors T3 and T4 are connected to the drain of PMOS transistor T3. Therefore, the power supply voltage VDD can be reduced by the threshold voltage Vth1 of the PMOS transistors T3 and T4.

[0109] Furthermore, the gate potential of NMOS transistor T5 is equal to the drain potential of NMOS transistor T1. Therefore, the sum of the voltage drop across NMOS transistor T1 and the voltage drop across NMOS transistor T5 is equivalent to the gate / source voltage Vgs13 of NMOS transistor T5. Here, the voltage drop across NMOS transistor T1 is equivalent to the gate / source voltage Vgs12 of NMOS transistor T1. The voltage drop across NMOS transistor T5 is equivalent to the source / drain voltage Vds13 of NMOS transistor T5. At this time, a charge corresponding to the drain potential of NMOS transistor T1 is accumulated in the bias capacitance CB.

[0110] Furthermore, during the reset phase, switches W12 and W14 are turned on based on the auto-zero signal AZ, and switch W13 is turned off based on the auto-zero inversion signal XAZ. Then, a bias voltage VB3 is applied to the gate of PMOS transistor T10, and current flows through PMOS transistor T10. At this time, the voltage drop across PMOS transistor T10 is equivalent to the source / drain voltage Vds21 of PMOS transistor T10. Also, the gate potential of NMOS transistor T11 becomes equal to the drain potential of NMOS transistor T11. At this time, a charge corresponding to the drain potential of NMOS transistor T11 is accumulated in capacitor C4.

[0111] In the comparison phase, comparator CM6 compares comparator inputs DV1 and DV2, and outputs a voltage VO corresponding to the comparison result. At this time, the AZ switches Z1 and Z2 are turned off based on the auto-zero signal AZ.

[0112] Furthermore, switches W1 and W3 are turned off based on the auto-zero signal AZ, and switch W2 is turned on based on the auto-zero inversion signal XAZ. Then, the gates of PMOS transistors T3 and T4 are connected to the drain of PMOS transistor T3, and current flows through PMOS transistors T3 and T4. At this time, the voltage drop across PMOS transistors T3 and T4 is equivalent to the gate / source voltage Vgs11 of PMOS transistors T3 and T4.

[0113] Furthermore, the gate potential of NMOS transistor T5 is equal to the bias potential generated by the bias capacitance CB. Here, NMOS transistor T5 can operate in the saturation region based on the bias potential generated by the bias capacitance CB. At this time, the voltage drop across NMOS transistor T5 is equivalent to the source / drain voltage Vds13 of NMOS transistor T5. Also, the voltage drop across NMOS transistor T1 is equivalent to the source / drain voltage Vds12 of NMOS transistor T1.

[0114] Therefore, in the comparison phase, the voltage drop across NMOS transistor T1 is lower by the threshold voltage Vth2 of NMOS transistor T1 compared to the reset phase. On the other hand, in the reset phase, the voltage drop across PMOS transistors T3 and T4 is lower by the threshold voltage Vth1 of PMOS transistors T3 and T4 compared to the comparison phase. Therefore, the threshold voltage Vth2 of NMOS transistor T1 in the comparison phase can be compensated for by the threshold voltage Vth1 of PMOS transistors T3 and T4 in the reset phase, and the power supply voltage VDD in the reset phase and the comparison phase can be made equal.

[0115] Furthermore, during the comparison phase, comparator inputs DV1 and DV2 are compared by comparator CM6, and a voltage VO corresponding to the comparison result is amplified and output from comparator CM6. At this time, switches W12 and W14 are turned off based on the auto-zero signal AZ, and switch W13 is turned on based on the auto-zero inversion signal XAZ. Then, the gate of PMOS transistor T10 is connected to the drain of PMOS transistor T4, and a voltage corresponding to the drain potential of PMOS transistor T4 is output from the drain of PMOS transistor T10.

[0116] Furthermore, the gate potential of the NMOS transistor T11 is equal to the bias potential generated by capacitor C4. Thus, the NMOS transistor T11 can operate in the saturation region based on the bias potential generated by capacitor C4.

[0117] Figure 12 is a timing chart showing the waveforms of each part during the operation of the comparator according to the sixth embodiment.

[0118] In the figure, the operation of the comparator CM6 includes a reset phase RFZ and a comparison phase CFZ.

[0119] During the reset phase RFZ, when the auto-zero signal AZ rises (time t11), switches Z1 and Z2 and switches W1, W3, W12, and W14 are turned on. When the auto-zero inversion signal XAZ falls, switches W2 and W13 are turned off. At this time, charge is accumulated in input capacitors C1 and C2 so that the comparator inputs DV1 and DV2 are balanced based on the current flowing through PMOS transistors T3 and T4. Charge is also accumulated in capacitor C4 so that the operating point of the subsequent amplifier AN2 is optimized based on the current flowing through NMOS transistor T11. Furthermore, a bias voltage VB1 is applied to the gates of PMOS transistors T3 and T4, and the gate potential of NMOS transistor T5 becomes equal to the drain potential of NMOS transistor T1. In addition, a bias voltage VB3 is applied to the gate of PMOS transistor T10.

[0120] Furthermore, the reset signal RSK rises simultaneously with the rising edge of the auto-zero signal AZ (at time t11). At this time, the reset switch WR is turned on, and the clamp capacitance CK is reset.

[0121] In the comparison phase CFZ, when the auto-zero signal AZ falls, AZ switches Z1 and Z2 and switches W1, W3, W12, and W14 are turned off. Conversely, when the auto-zero inversion signal XAZ rises, switches W2 and W13 are turned on. At this time, the gates of PMOS transistors T3 and T4 are connected to the drain of PMOS transistor T3. Furthermore, the gate potential of NMOS transistor T5 becomes equal to the bias potential generated by the bias capacitance CB.

[0122] After the auto-zero signal AZ and reset signal RSK fall, the ramp wave RAP is input as the reference signal VRF (time t12). Then, in comparator CM6, the potential of the vertical signal line VSL is compared with the ramp wave RAP, and when the level of the potential of the vertical signal line VSL matches the level of the ramp wave RAP, the output of comparator CM6 inverts. At this time, the P-phase level of the pixel signal can be converted using AD conversion based on the inversion timing of the output of comparator CM6.

[0123] Next, a ramp wave RAD is input as the reference signal VRF (time t13). Then, in comparator CM6, the potential of the vertical signal line VSL is compared with the ramp wave RAD, and when the level of the potential of the vertical signal line VSL matches the level of the ramp wave RAD, the output of comparator CM6 is inverted. At this time, the D-phase level of the pixel signal can be converted using AD conversion based on the inversion timing of the output of comparator CM6.

[0124] Thus, in the sixth embodiment described above, a clamp transistor TK is connected between the differential amplifier AN1 and the subsequent amplifier AN2, a clamp capacitor CK is connected to the gate of the clamp transistor TK, and the power supply voltage for the reset phase of the comparator CM6 is reduced. This makes it possible to limit the amplitude of the output of the differential amplifier AN1, eliminate the potential difference between the output of the differential amplifier AN1 and the output of the subsequent amplifier AN2 based on the clamp voltage generated by the clamp capacitor CK, and reduce the power supply voltage of the comparator CM6.

[0125] <7. Seventh Embodiment> In the sixth embodiment described above, a clamp transistor TK is connected between the differential amplifier AN1 and the subsequent amplifier AN2, a clamp capacitor CK is connected to the gate of the clamp transistor TK, and the power supply voltage for the reset phase of the comparator CM6 is reduced. In this seventh embodiment, a clamp transistor TK' is connected between the differential amplifier AP1 and the subsequent amplifier AP2, a clamp capacitor CK is connected to the gate of the clamp transistor TK', and the power supply voltage for the reset phase of the comparator is reduced.

[0126] Figure 13 is a circuit diagram showing an example of the configuration of a comparator according to the seventh embodiment.

[0127] In the figure, this comparator CM7 has switching units K1, K4, and K12 added to the comparator CM1 of the second embodiment described above. The other configurations of the comparator CM6 of the seventh embodiment are the same as those of the comparator CM2 of the second embodiment described above.

[0128] The switching unit K1 switches the connection between the gates of PMOS transistors T3' and T4' between the bias voltage VB1 and the drain of PMOS transistor T3'. The switching unit K1 includes switches W1 and W2. Switch W1 switches the input of the bias voltage VB1 to the gates of PMOS transistors T3' and T4'. Switch W2 switches the connection between the gate and drain of PMOS transistor T3'.

[0129] The switching section K12 switches the connection between the gate of NMOS transistor T5' and the drain of NMOS transistor T1'. The switching section K12 includes a switch W3. Switch W3 switches the connection between the gate of NMOS transistor T5' and the drain of NMOS transistor T1'.

[0130] The switching section K4 switches the connection of the gate of PMOS transistor T10' between the bias voltage VB3 and the drain of PMOS transistor T4'. The switching section K4 includes switches W12 and W13. Switch W12 switches the input of the bias voltage VB3 to the gate of PMOS transistor T10'. Switch W13 switches the connection between the gate of PMOS transistor T10' and the drain of PMOS transistor T4.

[0131] Figure 14 is a timing chart showing the waveforms of each part during the operation of the comparator according to the seventh embodiment.

[0132] In the figure, the operation of the comparator CM7 includes a reset phase RFZ and a comparison phase CFZ.

[0133] During the reset phase RFZ, when the auto-zero signal AZ rises (time t11), switches Z1 and Z2 and switches W1, W3, W12, and W14 are turned on. When the auto-zero inversion signal XAZ falls, switches W2 and W13 are turned off. At this time, charge is accumulated in input capacitors C1 and C2 so that the comparator inputs DV1 and DV2 are balanced based on the current flowing through each PMOS transistor T3' and T4'. Charge is also accumulated in capacitor C4 so that the operating point of the subsequent amplifier AP2 is optimized based on the current flowing through the NMOS transistor T11'. Furthermore, a bias voltage VB1 is applied to the gates of PMOS transistors T3' and T4', and the gate potential of NMOS transistor T5' becomes equal to the drain potential of NMOS transistor T1'. In addition, a bias voltage VB3 is applied to the gate of PMOS transistor T10.

[0134] Furthermore, the reset signal RSK rises simultaneously with the rising edge of the auto-zero signal AZ (at time t11). At this time, the reset switch WR is turned on, and the clamp capacitance CK is reset.

[0135] In the comparison phase CFZ, when the auto-zero signal AZ falls, AZ switches Z1 and Z2 and switches W1, W3, W12, and W14 are turned off. Conversely, when the auto-zero inversion signal XAZ rises, switches W2 and W13 are turned on. At this time, the gates of PMOS transistors T3' and T4' are connected to the drain of PMOS transistor T3. Furthermore, the gate potential of NMOS transistor T5' becomes equal to the bias potential generated by the bias capacitance CB.

[0136] After the auto-zero signal AZ and reset signal RSK fall, the ramp wave RAP is input as the reference signal VRF (time t12). Then, in comparator CM7, the potential of the vertical signal line VSL is compared with the ramp wave RAP, and when the level of the potential of the vertical signal line VSL matches the level of the ramp wave RAP, the output of comparator CM7 inverts. At this time, the P-phase level of the pixel signal can be converted using AD conversion based on the inversion timing of the output of comparator CM7.

[0137] Next, a ramp wave RAD is input as the reference signal VRF (time t13). Then, in comparator CM7, the potential of the vertical signal line VSL is compared with the ramp wave RAD, and when the level of the potential of the vertical signal line VSL matches the level of the ramp wave RAD, the output of comparator CM7 inverts. At this time, the D-phase level of the pixel signal can be converted using AD conversion based on the inversion timing of the output of comparator CM7.

[0138] Thus, in the seventh embodiment described above, a clamp transistor TK' is connected between the differential amplifier AP1 and the subsequent amplifier AP2, a clamp capacitor CK is connected to the gate of the clamp transistor TK', and the power supply voltage for the reset phase of the comparator CM7 is reduced. This makes it possible to limit the amplitude of the output of the differential amplifier AP1, eliminate the potential difference between the output of the differential amplifier AP1 and the output of the subsequent amplifier AP2 based on the clamp voltage generated by the clamp capacitor CK, and reduce the power supply voltage of the comparator CM7.

[0139] <8. Eighth Embodiment> In the seventh embodiment described above, a clamp transistor TK' is connected between the differential amplifier AP1 and the subsequent amplifier AP2, a clamp capacitor CK is connected to the gate of the clamp transistor TK', and the power supply voltage for the reset phase of the comparator CM7 is reduced. In this eighth embodiment, the clamp transistor TK' is connected between the subsequent amplifier AP2 and the inverter AP3, a clamp capacitor CK is connected to the gate of the clamp transistor TK', and the power supply voltage for the reset phase of the comparator is reduced.

[0140] Figure 15 is a circuit diagram showing an example of the configuration of a comparator according to the eighth embodiment.

[0141] In the figure, this comparator CM8 has switching units K1, K4, and K12 added to the comparator CM3 of the third embodiment described above. In this case, the switching units K1, K4, and K12 of comparator CM8 can be connected in the same way as the switching units K1, K4, and K12 of comparator CM7 of the seventh embodiment described above. The other configurations of comparator CM8 of the eighth embodiment are the same as the configurations of comparator CM3 of the third embodiment described above.

[0142] The timing chart for the operation of comparator CM8 is the same as the timing chart for the operation of comparator CM7 in the seventh embodiment described above. In this case, comparator CM8 can operate according to the timing chart in Figure 14.

[0143] Thus, in the eighth embodiment described above, the clamp transistor TK' is connected between the downstream amplifier AP2 and the inverter AP3, the clamp capacitor CK is connected to the gate of the clamp transistor TK', and the power supply voltage for the reset phase of the comparator CM8 is reduced. This makes it possible to limit the amplitude of the output of the downstream amplifier AP2, eliminate the potential difference between the output of the downstream amplifier AP2 and the output of the inverter AP3 based on the clamp voltage generated by the clamp capacitor CK, and reduce the power supply voltage of the comparator CM8.

[0144] <9. The ninth embodiment> In the eighth embodiment described above, the clamp transistor TK' is connected between the downstream amplifier AP2 and the inverter AP3, the clamp capacitor CK is connected to the gate of the clamp transistor TK', and the power supply voltage for the reset phase of the comparator CM8 is reduced. In this ninth embodiment, the clamp transistor TK' is connected between the downstream amplifiers AP2 and AP5, the clamp capacitor CK is connected to the gate of the clamp transistor TK', and the power supply voltage for the reset phase of the comparator is reduced.

[0145] Figure 16 is a circuit diagram showing an example of the configuration of a comparator according to the ninth embodiment.

[0146] In the figure, this comparator CM9 has switching units K1, K4, and K12 added to the comparator CM4 of the fourth embodiment described above. In this case, the switching units K1, K4, and K12 of comparator CM9 can be connected in the same way as the switching units K1, K4, and K12 of comparator CM7 of the seventh embodiment described above. The other configurations of comparator CM9 of the ninth embodiment are the same as the configurations of comparator CM4 of the fourth embodiment described above.

[0147] The timing chart for the operation of comparator CM9 is the same as the timing chart for the operation of comparator CM7 in the seventh embodiment described above. In this case, comparator CM9 can operate according to the timing chart in Figure 14.

[0148] Thus, in the ninth embodiment described above, the clamp transistor TK' is connected between the subsequent amplifiers AP2 and AP5, the clamp capacitor CK is connected to the gate of the clamp transistor TK', and the power supply voltage for the reset phase of the comparator CM9 is reduced. This makes it possible to limit the amplitude of the output of the subsequent amplifier AP2, eliminate the potential difference between the output of the subsequent amplifier AP2 and the output of the subsequent amplifier AP5 based on the clamp voltage generated by the clamp capacitor CK, and reduce the power supply voltage of the comparator CM9.

[0149] <10. Tenth Embodiment> In the ninth embodiment described above, a clamp transistor TK' is connected between the subsequent amplifiers AP2 and AP5, a clamp capacitor CK is connected to the gate of the clamp transistor TK', and the power supply voltage for the comparator's reset phase is reduced. In this tenth embodiment, a clamp transistor TK' is connected between the differential amplifier AP1 and the subsequent amplifier AP2, a clamp capacitor CK is connected to the gate of the clamp transistor TK', and the power supply voltage for the comparator's reset phase is reduced.

[0150] Figure 17 is a circuit diagram showing an example of the configuration of a comparator according to the tenth embodiment.

[0151] In the figure, this comparator CM10 has switching units K1, K4, and K12 added to the comparator CM5 of the fifth embodiment described above. In this case, the switching units K1, K4, and K12 of comparator CM10 can be connected in the same way as the switching units K1, K4, and K12 of comparator CM7 of the seventh embodiment described above. The other configurations of comparator CM10 of the tenth embodiment are the same as the configurations of comparator CM5 of the fifth embodiment described above.

[0152] The timing chart for the operation of comparator CM10 is the same as the timing chart for the operation of comparator CM7 in the seventh embodiment described above. In this case, comparator CM10 can operate according to the timing chart in Figure 14.

[0153] As described above, in the tenth embodiment, a clamp transistor TK' is connected between the differential amplifier AP1 and the subsequent amplifier AP2, and a clamp capacitor CK is connected to the gate of the clamp transistor TK'. The clamp transistor TK' is connected between the subsequent amplifiers AP2 and AP5, and a clamp capacitor CK is connected to the gate of the clamp transistor TK', thereby lowering the power supply voltage of the reset phase of the comparator CM10. This makes it possible to limit the amplitude of the outputs of the differential amplifier AP1 and the subsequent amplifier AP2, and to eliminate the potential difference between the outputs of the differential amplifier AP1 and the subsequent amplifier AP2, and the potential difference between the outputs of the subsequent amplifiers AP2 and AP5, based on the clamp voltages generated by the clamp capacitors CK and CK', while also lowering the power supply voltage of the comparator CM10.

[0154] In the sixth to tenth embodiments described above, an example was shown in which a clamp capacitor was connected to the gate of the clamp transistor and a reset transistor was provided to reset the clamp capacitor. In the comparators of the sixth to tenth embodiments described above, the switching units K1, K4, K12 and the clamp transistor may be provided, but the clamp capacitor and the reset transistor may be omitted.

[0155] <11. Eleventh Embodiment> In the first embodiment described above, a clamp transistor TK was connected between the differential amplifier AN1 and the subsequent amplifier AN2, and a clamp capacitor CK was connected to the gate of the clamp transistor TK. In this eleventh embodiment, a comparator is applied to the imaging device, in which a clamp transistor is connected between the differential amplifier and the subsequent amplifier, and a clamp capacitor is connected to the gate of the clamp transistor.

[0156] Figure 18 is a block diagram showing an example configuration of an imaging device according to the 11th embodiment.

[0157] In the figure, the imaging device 100 comprises an optical system 101, a solid-state imager 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, image processing unit 104, storage unit 105, display unit 106, and operation unit 107 are connected to each other via a bus 108. The imaging device 100 may be used as a standalone unit, incorporated into a mobile terminal such as a smartphone, incorporated into an authentication device or monitoring device, or incorporated into a vehicle or drone.

[0158] The optical system 101 directs light from the subject onto the solid-state imager 102 and forms an optical image on the light-receiving surface of the solid-state imager 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0159] The solid-state imaging device 102 converts the optical image formed on the light-receiving surface into an electrical signal for each pixel, and outputs the electrical signal digitized. Single-slope AD conversion can be used for the digitization of the electrical signal. In this case, the solid-state imaging device 102 may support CDS (Correlated Double Sampling) readout or DDS (Double Data Sampling) readout. Each pixel may have a single photodiode or multiple photodiodes with different sensitivities. The solid-state imaging device 102 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor. The solid-state imaging device 102 may also be a LOFIC (Lateral Overflow Integration Capacitor) type image sensor.

[0160] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, and imaging timing of the solid-state imaging device 102.

[0161] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. Image processing includes, for example, gamma correction, white balance processing, sharpness processing, and gradation conversion processing. The image processing unit 104 may also include a processor that performs processing based on software.

[0162] The storage unit 105 stores images captured by the solid-state imaging device 102, as well as imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store programs that operate the imaging device 100 based on software. The storage unit 105 may include ROM (Read Only Memory), RAM (Random Access Memory), and a memory card.

[0163] The display unit 106 displays captured images and various information to support the imaging operation. The display unit 106 may be a liquid crystal display or an organic EL (Electro-Luminescence) display.

[0164] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0165] Depending on the configuration of the imaging device 100, some of the above-mentioned functions may be omitted, or conversely, it may have additional functions that are not disclosed.

[0166] Figure 19 is a block diagram showing an example configuration of a solid-state imaging device according to the 11th embodiment.

[0167] In the figure, the solid-state imaging device 102 includes a pixel array unit 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing unit 114, a horizontal scanning circuit 115, and a control circuit 116.

[0168] The pixel array section 111 comprises multiple pixels PX. The pixels PX are arranged in a matrix along the row direction (also called the horizontal direction) and the column direction (also called the vertical direction). Each pixel PX can form a source follower with the column readout circuit 113 when a signal is read out. Each pixel PX is connected to a horizontal drive line HSL for each row and to a vertical signal line VSL for each column. The horizontal drive line HSL drives each pixel PX row by row when a signal is read from each pixel PX. The vertical signal line VSL transmits the pixel signals read from the pixels PX to the column signal processing unit 114 column by column.

[0169] Each pixel PX may be a single pixel, a shared pixel of four pixels, or a shared pixel of eight pixels. Furthermore, the pixel PX may form a Bayer array or a quad-Bayer array. The light received by each pixel PX may be visible light, near-infrared (NIR), short-wavelength infrared (SWIR), ultraviolet light, or X-rays, etc.

[0170] The vertical scanning circuit 112 scans the pixels PX to be read out in the column direction. The vertical scanning circuit 112 may include a vertical register. Here, the vertical scanning circuit 112 can drive each pixel PX row by row via the horizontal drive line HSL when reading a signal from each pixel PX.

[0171] The column readout circuit 113 can configure a source follower with each pixel PX when reading a signal from each pixel PX. In this case, the column readout circuit 113 can change the potential of the vertical signal line VSL for each column based on the charge held in each pixel PX.

[0172] The column signal processing unit 114 processes the signals transmitted from each pixel PX in the column direction. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted from each pixel PX in the column direction. Furthermore, the column signal processing unit 114 can perform analog-to-digital (AD) conversion processing based on the signals transmitted from each pixel PX in the column direction and output an imaging signal Gout. The column signal processing unit 114 includes a column ADC unit 114A.

[0173] The column ADC unit 114A can perform AD conversion processing in parallel for each column. In this case, the column ADC unit 114A can perform AD conversion for each column based on the comparison result between the pixel signal read from the pixel PX and the reference signal REF.

[0174] The horizontal scanning circuit 115 scans the pixels PX to be read out in the row direction. The horizontal scanning circuit 115 may also include a horizontal register.

[0175] The control circuit 116 controls the vertical scanning circuit 112, the column reading circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column reading circuit 113, and the processing timing of the column signal processing unit 114. In this case, the control circuit 116 can coordinate the vertical scanning circuit 112, the column reading circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115 so that the accumulation operation, shutter operation, and read operation are performed for each row in each frame.

[0176] Figure 20 is a block diagram showing an example of a pixel circuit configuration provided in a solid-state imaging device according to the 11th embodiment.

[0177] In the figure, pixel PX comprises a photodiode PD, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion FD. MOS transistors can be used as the transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125.

[0178] The amplification transistor 124 and the selection transistor 125 are connected in series. The cathode of the photodiode PD is connected to the floating diffusion FD via the transfer transistor 122. The floating diffusion FD is connected to the power supply voltage VDD via the reset transistor 123. The power supply voltage VDD is connected to the vertical signal line VSL via the series circuit of the amplification transistor 124 and the selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion FD.

[0179] The transfer signal TGL is applied to the gate of the transfer transistor 122. The reset signal RST is applied to the gate of the reset transistor 123. The selection signal SEL is applied to the gate of the selection transistor 125. The transfer signal TGL, the reset signal RST, and the selection signal SEL can be transmitted to each pixel PX via the horizontal drive line HSL shown in Figure 19.

[0180] When the transfer transistor 122 is turned on, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD. Then, when the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes according to the potential of the floating diffusion FD. The source potential of the amplification transistor 124 is then applied to the vertical signal line VSL via the selection transistor 125 and transmitted through the vertical signal line VSL. Furthermore, when the reset transistor 123 is turned on, the charge accumulated in the floating diffusion FD is discharged.

[0181] Figure 21 is a block diagram showing an example configuration of the signal readout unit according to the 11th embodiment. Although the figure shows vertical signal lines VSL1 and VSL2 for two columns, the same method can be applied to cases where there are more vertical signal lines.

[0182] In the figure, pixels PX1 and PX2 are connected to vertical signal lines VSL1 and VSL2, respectively. At this time, the amplification transistors 124 of each pixel PX1 and PX2 are connected to vertical signal lines VSL1 and VSL2, respectively, via selection transistors 125.

[0183] The column readout circuit 113 includes current sources LM1 and LM2. Each column is provided with a current source LM1 and LM2. Each current source LM1 and LM2 is connected to the vertical signal lines VSL1 and VSL2, respectively. During signal readout, each current source LM1 and LM2 can form a source follower with each pixel PX1 and PX2 via the vertical signal lines VSL1 and VSL2, respectively. Each current source LM1 and LM2 may be a MOS transistor.

[0184] The column ADC section 114A is equipped with comparators CP1 and CP2 and counters CN1 and CN2 for each column. Comparator CP1 compares the pixel signal transmitted via the vertical signal line VSL1 with the reference signal REF. Comparator CP2 compares the pixel signal transmitted via the vertical signal line VSL2 with the reference signal REF.

[0185] Furthermore, an auto-zero signal AZ is input to each of the comparators CP1 and CP2. The auto-zero signal AZ activates the auto-zero operation during the auto-zero period. At this time, for comparator CP1, a DC-blocking capacitor CA1 is connected to the non-inverting input terminal, and a DC-blocking capacitor CB1 is connected to the inverting input terminal. Similarly, for comparator CP2, a DC-blocking capacitor CA2 is connected to the non-inverting input terminal, and a DC-blocking capacitor CB2 is connected to the inverting input terminal.

[0186] Each of the comparators CP1 and CP2 may be any of the comparators CM1 to CM10 from the first to tenth embodiments described above.

[0187] In auto-zero operation, the charge stored in DC-blocking capacitors CA1 and CB1 is controlled so that the non-inverting and inverting inputs of comparator CP1 are balanced. Similarly, in auto-zero operation, the charge stored in DC-blocking capacitors CA2 and CB2 is controlled so that the non-inverting and inverting inputs of comparator CP2 are balanced.

[0188] Each counter CN1 and CN2 performs a counting operation column by column until the level of the pixel signal read from each pixel PX1 and PX2 matches the level of the ramp wave of the reference signal REF, and holds the digital values ​​D1 and D2 of the pixel signal read from each pixel PX1 and PX2 for each column. At this time, the digitization of the pixel signal read from each pixel PX1 and PX2 can be performed row by row in each comparator CP1 and CP2. The digital values ​​D1 and D2 held in each counter CN1 and CN2 can then be updated row by row.

[0189] During this time, in each comparator CP1 and CP2, the pixel signals read from each pixel PX1 and PX2 are compared column by column with the ramp wave included in the reference signal REF during the AD conversion period provided for each horizontal scanning period. Based on the comparison results in each comparator CP1 and CP2 during that AD conversion period, the digital values ​​D1 and D2 of the pixel signals read from each pixel PX1 and PX2 are stored in counters CN1 and CN2.

[0190] Figure 22 is a timing chart showing an example of the waveforms of each part during signal readout of a solid-state imaging device according to the 11th embodiment. Note that the figure shows an example of the waveform within a 1H period (1 horizontal synchronization period).

[0191] In the figure, the reset signal RST rises (t1), the reset transistor 123 turns on, and the floating diffusion 126 is reset. Also, the selection signal SEL rises, and the selection transistor 125 turns on. At this time, the potentials of the respective vertical signal lines VSL1 and VSL2 are set based on the source follower operation when the power supply voltage VDD is applied to the gate of the amplification transistor 124.

[0192] Next, the reset signal RST falls (t2), and the reset transistor 123 turns off. At this time, the potentials of the vertical signal lines VSL1 and VSL2 are set based on the source follower operation when the P-phase level of the floating diffusion 126 is applied to the gate of the amplification transistor 124.

[0193] Next, in each comparator CP1 and CP2, the potentials of each vertical signal line VSL1 and VSL2 corresponding to the P-phase level are compared with the reference signal REF, and the timing when the level of the reference signal REF matches the potential of each vertical signal line VSL1 and VSL2 is output as the comparison result. At this time, the P-phase level read from the pixel PX is AD converted column by column based on the count operation until the level of the reference signal REF matches the potential of each vertical signal line VSL1 and VSL2.

[0194] Next, when the transfer signal TGL rises (t3), the transfer transistor 122 turns on and the charge accumulated in the photodiode 121 is transferred to the floating diffusion 126. At this time, the potentials of the vertical signal lines VSL1 and VSL2 are set based on the source follower operation when the cathode potential of the photodiode 121 is applied to the gate of the amplification transistor 124.

[0195] Next, when the transfer signal TGL falls (t4), the transfer transistor 122 turns off. At this time, the potentials of the vertical signal lines VSL1 and VSL2 are set based on the source follower operation when the D-phase level of the floating diffusion 126 is applied to the gate of the amplification transistor 124.

[0196] Next, in each comparator CP1 and CP2, the potentials of each vertical signal line VSL1 and VSL2 corresponding to the D-phase level are compared with the reference signal REF, and the timing when the level of the reference signal REF matches the potentials of each vertical signal line VSL1 and VSL2 is output as the comparison result. At this time, the D-phase level read from the pixel PX is AD converted column by column based on the count operation until the level of the reference signal REF matches the potentials of each vertical signal line VSL1 and VSL2.

[0197] Thus, in the 11th embodiment described above, a clamp transistor is connected between the differential amplifier and the subsequent amplifier, and one of the comparators CM1 to CM10, each with a clamp capacitor connected to the gate of the clamp transistor, is applied to the solid-state imaging device 102. This makes it possible to prevent vertical lines in the captured image, and to lower the voltage of each comparator CM1 to CM10 while preventing a decrease in the characteristics of each comparator CM1 to CM10.

[0198] <12. Examples of applications to mobile devices> The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein may be implemented as a device mounted on any type of mobile vehicle, such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, or robot.

[0199] Figure 23 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0200] The vehicle control system 12000 comprises multiple electronic control units connected via a communication network 12001. In the example shown in Figure 23, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0201] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0202] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0203] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0204] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0205] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0206] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking system based on information from inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0207] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0208] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0209] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 23, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0210] Figure 24 shows an example of the installation position of the imaging unit 12031.

[0211] In Figure 24, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0212] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0213] Figure 24 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0214] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0215] For example, the microcomputer 12051, based on distance information obtained from imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to vehicle 12100). In particular, it can extract the nearest object on the vehicle 12100's path that is traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0216] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, heavy vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0217] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0218] The above describes an example of a vehicle control system to which the technology of this disclosure may be applied. The technology of this disclosure can be applied to the imaging unit 12031 of the configuration described above. Specifically, for example, each comparator of the above embodiment can be applied to the imaging unit 12031. By applying the technology of this disclosure to the vehicle control system 12000, it becomes possible to prevent vertical lines in the captured image, and to reduce the comparator voltage while preventing a deterioration in the comparator's characteristics.

[0219] The embodiments described above are merely examples for realizing the present technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of the present technology bearing the same name. However, the present technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology. Furthermore, the effects described herein are merely examples and are not limiting, and other effects may also exist.

[0220] Furthermore, this technology can also be configured as follows. (1) A first transistor to which the first input is applied to the gate, A preamplifier that generates a preamplifier output based on the second preamplifier input, A subsequent amplifier that generates a subsequent output based on the aforementioned preceding output, A clamp transistor that limits the amplitude of the preceding output based on the subsequent output, A clamping capacitance that generates a clamping voltage to clamp the gate potential of the clamping transistor, A reset switch for resetting the clamp capacity and A comparator equipped with the following features. (2) The preceding amplifier includes a differential amplifier that generates a preceding output based on the differential input, The clamp transistor is connected between the output of the differential amplifier and the power supply potential. The clamp capacitance is connected between the gate of the clamp transistor and the output of the subsequent amplifier. The reset switch is connected between the gate of the clamp transistor and the output of the differential amplifier. The comparator described in (1) above. (3) The preceding amplifier includes a differential amplifier that generates a preceding output based on the differential input, The aforementioned downstream amplifier is A first downstream amplifier that generates a first downstream output based on the preceding downstream output, The system comprises a second downstream amplifier that generates a second downstream output based on the first downstream output, The clamp transistor is connected between the output of the first subsequent amplifier and the ground potential. The clamp capacitance is connected between the gate of the clamp transistor and the second output of the second amplifier. The reset switch is connected between the gate of the clamp transistor and the output of the first subsequent amplifier. The comparator described in (1) above. (4) The preceding amplifier and the succeeding amplifier are equipped with an AZ switch for performing AZ (Auto Zero), The reset switch is turned on when the preceding amplifier and the succeeding amplifier are in AZ operation. A comparator as described in any of (1) to (3) above. (5) A first transistor to which the first input is applied to the gate, A second transistor to which the second input is applied to the gate, A third transistor connected in series with the first transistor, A fourth transistor is connected in series with the second transistor, and its gate is connected to the gate of the third transistor, A fifth transistor connected to the first transistor and the second transistor, A subsequent amplifier that generates a subsequent output based on the preceding output from the connection point of the first transistor and the third transistor, The bias capacitance connected to the gate of the fifth transistor, A first switching unit that switches the gate connection of the third transistor and the fourth transistor between the first bias voltage and the drain of the third transistor, A clamp transistor that limits the amplitude of the preceding output based on the subsequent output, A comparator equipped with the following features. (6) A clamp capacitance that generates a clamp voltage to clamp the gate potential of the clamp transistor, A reset switch for resetting the clamp capacity and The comparator according to (5) above, comprising: (7) The clamp transistor is connected between the connection point of the first transistor and the third transistor and the power supply potential, The clamp capacitance is connected between the gate of the clamp transistor and the output of the subsequent amplifier. The reset switch is connected between the connection point of the first transistor and the third transistor and the gate of the clamp transistor. The comparator described in (6) above. (8) A second switching unit that switches the connection between the gate of the fifth transistor and the drain of the first or second transistor. A comparator according to any one of (5) to (7) above, further comprising the above. (9) The first switching unit is A first switch that switches the input of the first bias voltage to the gate of the third transistor, The system includes a second switch for switching the connection between the gate and drain of the third transistor, The second switching unit is a third switch that switches the connection between the gate of the fifth transistor and the drain of the third transistor. The comparator described in (8) above, comprising: (10) A pixel array section in which pixels are arranged in a matrix in the row direction and column direction, The system includes a column ADC unit that performs analog-to-digital (AD) conversion on each column of the pixel signals output from the aforementioned pixels. The column ADC unit includes a comparator that compares the pixel signal with a reference signal. The aforementioned comparator, A preamplifier that generates a preamplifier output based on the preamplifier input, A subsequent amplifier that generates a subsequent output based on the aforementioned preceding output, A clamp transistor that limits the amplitude of the preceding output based on the subsequent output, A clamping capacitance that generates a clamping voltage to clamp the gate potential of the clamping transistor, A reset switch for resetting the clamp capacity and An imaging device equipped with the following features. (11) The preceding amplifier includes a differential amplifier that generates a preceding output based on the differential input, The clamp transistor is connected between the output of the differential amplifier and the power supply potential. The clamp capacitance is connected between the gate of the clamp transistor and the output of the subsequent amplifier. The reset switch is connected between the gate of the clamp transistor and the output of the differential amplifier. The imaging device described in (10) above. (12) The preceding amplifier includes a differential amplifier that generates a preceding output based on the differential input, The aforementioned downstream amplifier is A first downstream amplifier that generates a first downstream output based on the preceding downstream output, The system comprises a second downstream amplifier that generates a second downstream output based on the first downstream output, The clamp transistor is connected between the output of the first subsequent amplifier and the ground potential. The clamp capacitance is connected between the gate of the clamp transistor and the second output of the second amplifier. The reset switch is connected between the gate of the clamp transistor and the output of the first subsequent amplifier. The imaging device described in (10) above. (13) The comparator is A first transistor to which the first input is applied to the gate, A second transistor to which the second input is applied to the gate, A third transistor connected in series with the first transistor, A fourth transistor is connected in series with the second transistor, and its gate is connected to the gate of the third transistor, A fifth transistor connected to the first transistor and the second transistor, A subsequent amplifier that generates a subsequent output based on the preceding output from the connection point of the first transistor and the third transistor, The bias capacitance connected to the gate of the fifth transistor, A first switching unit that switches the gate connection of the third transistor and the fourth transistor between the first bias voltage and the drain of the third transistor, A clamp transistor that limits the amplitude of the preceding output based on the subsequent output, An imaging device according to any one of (10) to (12) above, comprising: (14) The comparator is A clamping capacitance that generates a clamping voltage to clamp the gate potential of the clamping transistor, A reset switch for resetting the clamp capacity and The imaging apparatus according to (13) above, comprising: (15) The comparator is a second switching unit that switches the connection between the gate of the fifth transistor and the drain of the first transistor or the second transistor. The imaging apparatus according to (14) further comprising the above. [Explanation of symbols]

[0221] TK Clamp Transistor CK clamp capacity WR Reset Switch CM1 Comparator K1, K2 switching section T1, T2, T5 NMOS transistors T3, T4 PMOS transistors W1 to W4 switches CB bias capacity Z1, Z2 AZ switch C1, C2 Input Capacitance

Claims

1. A preamplifier that generates a preamplifier output based on the preamplifier input, A subsequent amplifier that generates a subsequent output based on the aforementioned preceding output, A clamp transistor that limits the amplitude of the preceding output based on the subsequent output, A clamping capacitance that generates a clamping voltage to clamp the gate potential of the clamping transistor, A reset switch for resetting the clamp capacity and A comparator equipped with the following features.

2. The preceding amplifier includes a differential amplifier that generates a preceding output based on the differential input, The clamp transistor is connected between the output of the differential amplifier and the power supply potential. The clamp capacitance is connected between the gate of the clamp transistor and the output of the subsequent amplifier. The reset switch is connected between the gate of the clamp transistor and the output of the differential amplifier. The comparator according to claim 1.

3. The preceding amplifier includes a differential amplifier that generates a preceding output based on the differential input, The aforementioned downstream amplifier is A first downstream amplifier that generates a first downstream output based on the preceding downstream output, The system includes a second downstream amplifier that generates a second downstream output based on the first downstream output, The clamp transistor is connected between the output of the first subsequent amplifier and the ground potential. The clamp capacitance is connected between the gate of the clamp transistor and the second output of the second amplifier. The reset switch is connected between the gate of the clamp transistor and the output of the first subsequent amplifier. The comparator according to claim 1.

4. The preceding amplifier and the succeeding amplifier are equipped with an AZ switch for performing AZ (Auto Zero), The reset switch is turned on when the preceding amplifier and the succeeding amplifier are in AZ operation. The comparator according to claim 1.

5. A first transistor to which the first input is applied to the gate, A second transistor to which the second input is applied to the gate, A third transistor connected in series with the first transistor, A fourth transistor is connected in series with the second transistor, and its gate is connected to the gate of the third transistor, A fifth transistor connected to the first transistor and the second transistor, A subsequent amplifier that generates a subsequent output based on the preceding output from the connection point of the first transistor and the third transistor, The bias capacitance connected to the gate of the fifth transistor, A first switching unit that switches the gate connection of the third transistor and the fourth transistor between the first bias voltage and the drain of the third transistor, A clamp transistor that limits the amplitude of the preceding output based on the subsequent output, A comparator equipped with the following features.

6. A clamping capacitance that generates a clamping voltage to clamp the gate potential of the clamping transistor, A reset switch for resetting the clamp capacity and The comparator according to claim 5, comprising:

7. The clamp transistor is connected between the connection point of the first transistor and the third transistor and the power supply potential. The clamp capacitance is connected between the gate of the clamp transistor and the output of the subsequent amplifier. The reset switch is connected between the connection point of the first transistor and the third transistor and the gate of the clamp transistor. The comparator according to claim 6.

8. A second switching unit that switches the connection between the gate of the fifth transistor and the drain of the first or second transistor. The comparator according to claim 5, further comprising:

9. The first switching unit is, A first switch that switches the input of the first bias voltage to the gate of the third transistor, The system includes a second switch for switching the connection between the gate and drain of the third transistor, The second switching unit is a third switch that switches the connection between the gate of the fifth transistor and the drain of the third transistor. The comparator according to claim 8, comprising:

10. A pixel array section in which pixels are arranged in a matrix in the row direction and column direction, The system includes a column ADC unit that performs analog-to-digital (AD) conversion on each column of the pixel signals output from the aforementioned pixels. The column ADC unit includes a comparator that compares the pixel signal with a reference signal. The aforementioned comparator, A preamplifier that generates a preamplifier output based on the preamplifier input, A subsequent amplifier that generates a subsequent output based on the aforementioned preceding output, A clamp transistor that limits the amplitude of the preceding output based on the subsequent output, A clamping capacitance that generates a clamping voltage to clamp the gate potential of the clamping transistor, A reset switch for resetting the clamp capacity and An imaging device equipped with the following features.

11. The preceding amplifier includes a differential amplifier that generates a preceding output based on the differential input, The clamp transistor is connected between the output of the differential amplifier and the power supply potential. The clamp capacitance is connected between the gate of the clamp transistor and the output of the subsequent amplifier. The reset switch is connected between the gate of the clamp transistor and the output of the differential amplifier. The imaging apparatus according to claim 10.

12. The preceding amplifier includes a differential amplifier that generates a preceding output based on the differential input, The aforementioned downstream amplifier is A first downstream amplifier that generates a first downstream output based on the preceding downstream output, The system includes a second downstream amplifier that generates a second downstream output based on the first downstream output, The clamp transistor is connected between the output of the first subsequent amplifier and the ground potential. The clamp capacitance is connected between the gate of the clamp transistor and the second output of the second amplifier. The reset switch is connected between the gate of the clamp transistor and the output of the first subsequent amplifier. The imaging apparatus according to claim 10.

13. The aforementioned comparator, A first transistor to which the first input is applied to the gate, A second transistor to which the second input is applied to the gate, A third transistor connected in series with the first transistor, A fourth transistor is connected in series with the second transistor, and its gate is connected to the gate of the third transistor, A fifth transistor connected to the first transistor and the second transistor, A subsequent amplifier that generates a subsequent output based on the preceding output from the connection point of the first transistor and the third transistor, The bias capacitance connected to the gate of the fifth transistor, A first switching unit that switches the gate connection of the third transistor and the fourth transistor between the first bias voltage and the drain of the third transistor, A clamp transistor that limits the amplitude of the preceding output based on the subsequent output, The imaging apparatus according to claim 10, comprising:

14. The aforementioned comparator, A clamping capacitance that generates a clamping voltage to clamp the gate potential of the clamping transistor, A reset switch for resetting the clamp capacity and The imaging device according to claim 13, comprising:

15. The comparator is a second switching unit that switches the connection between the gate of the fifth transistor and the drain of the first transistor or the second transistor. The imaging device according to claim 14, further comprising:

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