Nitride semiconductor devices

Abstract

Reduce on-resistance. [Solution] The nitride semiconductor device 1 comprises a substrate 10, an n-type drift layer 12, a p-type block layer 14, an electron transport layer 22 and an electron supply layer 24 provided to cover the inner surface of a first opening 20 that penetrates the block layer 14 and reaches the drift layer 12, and the area above the block layer 14, a p-type shielding layer 27, an intermediate layer 26 provided between the electron supply layer 24 and the shielding layer 27 at a position that overlaps the first opening 20 in a plan view, a gate electrode 32 provided above the electron supply layer 24 at a position that overlaps the block layer 14 but does not overlap the first opening 20 in a plan view, a source electrode 34 provided away from the gate electrode 32, a shielding electrode 38 provided above the shielding layer 27 and electrically connected to the source electrode 34, and a drain electrode 36 provided below the substrate 10. The side surface 26b of the intermediate layer 26 is covered by the shielding layer 27.

Description

[Technical Field]

[0001] The present disclosure relates to a nitride semiconductor device. [Background Art]

[0002] Patent Document 1 discloses a nitride semiconductor device including a two-dimensional electron gas (2DEG: 2 Dimensional Electron Gas) as a channel. In the nitride semiconductor device disclosed in Patent Document 1, a p-type semiconductor layer is provided directly below a gate electrode. The p-type semiconductor layer raises the potential at the conduction band edge of the channel portion to increase the threshold voltage, thereby realizing a normally-off transistor. [Prior Art Literature] [Patent Literature]

[0003] [Patent Document 1] Japanese Patent No. 6511645 [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] However, the above conventional nitride semiconductor device has a problem that the concentration of 2DEG decreases due to the influence of a depletion layer extending from the p-type semiconductor layer, resulting in an increase in on-resistance.

[0005] Accordingly, the present disclosure provides a nitride semiconductor device capable of reducing on-resistance. [Means for Solving the Problem]

[0006] A nitride semiconductor device according to one aspect of the present disclosure includes: a substrate; an n-type first nitride semiconductor layer provided above the substrate; a p-type second nitride semiconductor layer provided above the first nitride semiconductor layer; an electron transit layer and an electron supply layer that are provided in order from the substrate side so as to cover an inner surface of a first opening that penetrates the second nitride semiconductor layer and reaches the first nitride semiconductor layer, and a region above the second nitride semiconductor layer; a p-type third nitride semiconductor layer provided above the electron supply layer; an intermediate layer provided between the electron supply layer and the third nitride semiconductor layer at a position overlapping the first opening in a plan view of the substrate; a gate electrode provided above the electron supply layer at a position that does not overlap the first opening but overlaps the second nitride semiconductor layer in a plan view of the substrate; a source electrode provided above the second nitride semiconductor layer at a position spaced apart from the gate electrode; a shielding electrode provided above the third nitride semiconductor layer at a position overlapping the first opening in a plan view of the substrate and electrically connected to the source electrode; and a drain electrode provided below the substrate, wherein a side surface of the intermediate layer is covered by the third nitride semiconductor layer. Effects of the Invention

[0007] According to the present disclosure, on-resistance can be reduced. Brief Description of the Drawings

[0008] [Figure 1] FIG. 1 is a cross-sectional view of the nitride semiconductor device according to Embodiment 1. [Figure 2] FIG. 2 is a cross-sectional view of the nitride semiconductor device according to Embodiment 2. [Figure 3] FIG. 3 is a cross-sectional view of the nitride semiconductor device according to Embodiment 3. [Figure 4] FIG. 4 is a cross-sectional view of the nitride semiconductor device according to Embodiment 4. [Figure 5] FIG. 5 is a cross-sectional view of the nitride semiconductor device according to Embodiment 5. [Figure 6] FIG. 6 is a cross-sectional view of the nitride semiconductor device according to Embodiment 6. [Modes for carrying out the invention]

[0009] (Summary of this disclosure) A nitride semiconductor device according to a first aspect of the present disclosure includes a substrate, an n-type first nitride semiconductor layer provided above the substrate, a p-type second nitride semiconductor layer provided above the first nitride semiconductor layer, an electron transport layer and an electron supply layer provided in order from the substrate side so as to cover the inner surface of a first opening that penetrates the second nitride semiconductor layer and reaches the first nitride semiconductor layer and the area above the second nitride semiconductor layer, a p-type third nitride semiconductor layer provided above the electron supply layer, and the first opening between the electron supply layer and the third nitride semiconductor layer in a plan view of the substrate. The device comprises an intermediate layer provided in a position overlapping the portion; a gate electrode provided above the electron supply layer in a position that overlaps the second nitride semiconductor layer but does not overlap the first opening in a plan view of the substrate; a source electrode provided above the second nitride semiconductor layer, away from the gate electrode; a shielding electrode provided above the third nitride semiconductor layer in a position that overlaps the first opening in a plan view of the substrate and is electrically connected to the source electrode; and a drain electrode provided below the substrate, wherein the side surface of the intermediate layer is covered by the third nitride semiconductor layer.

[0010] As a result, 2DEG is generated near the interface between the electron transport layer and the electron supply layer, which can be used as a channel. In the region that overlaps with the p-type third nitride semiconductor layer in a plan view, the potential at the conduction band edge of the channel can be increased. Therefore, the nitride semiconductor device can be operated as a normally-off transistor. At this time, in the region that overlaps with the intermediate layer in a plan view, the influence of the third nitride semiconductor layer on the channel can be suppressed. The decrease in the concentration of 2DEG can be suppressed, and the on-resistance can be reduced. In addition, since the side surface of the intermediate layer is covered by the third nitride semiconductor layer, the leakage current through the side surface of the intermediate layer can be reduced.

[0011] A nitride semiconductor device according to a second aspect of the present disclosure is a nitride semiconductor device according to a first aspect, wherein the third nitride semiconductor layer includes a shielding portion that overlaps the first opening in a plan view of the substrate and is electrically connected to the shielding electrode, and a gate portion that overlaps the upper surface of the second nitride semiconductor layer in a plan view of the substrate and is electrically connected to the gate electrode.

[0012] This design provides a shielding electrode and shielding section electrically connected to the source electrode, allowing the electric field lines extending from the drain electrode to be terminated by the shielding electrode and shielding section. This reduces parasitic capacitance between the gate and drain, enabling faster switching. Furthermore, since the on / off state of the transistor is controlled at the gate, it is less susceptible to the influence of the channel's slope. Therefore, the controllability of the transistor's on / off state can be improved.

[0013] A nitride semiconductor device according to a third aspect of this disclosure is a nitride semiconductor device according to a second aspect, wherein the side surface of the intermediate layer is covered with the shielding portion.

[0014] This reduces leakage current through the sides of the intermediate layer.

[0015] A nitride semiconductor device according to a fourth aspect of this disclosure is a nitride semiconductor device according to a third aspect, wherein the end of the shielding portion on the source electrode side overlaps the upper surface of the second nitride semiconductor layer in a plan view of the substrate.

[0016] This increases the overlapping area between the p-type shielding layer and the p-type second nitride semiconductor layer, thereby enhancing the shielding effect and further reducing the parasitic capacitance between the gate and drain.

[0017] A nitride semiconductor device according to a fifth aspect of this disclosure is a nitride semiconductor device according to a third aspect, wherein the end of the shielding portion on the source electrode side overlaps the inclined surface of the first opening in a plan view of the substrate.

[0018] As a result, the area in which the p-type shielding portion contacts the electron supply layer without an intermediate layer is reduced, which suppresses the decrease in 2DEG concentration and reduces on-resistance.

[0019] A nitride semiconductor device according to a sixth aspect of this disclosure is a nitride semiconductor device according to a second aspect, wherein the side surface of the intermediate layer is covered with the gate portion.

[0020] This reduces leakage current through the sides of the intermediate layer. Furthermore, the increased area of ​​the intermediate layer further suppresses the decrease in 2DEG concentration, thereby further reducing on-resistance.

[0021] A nitride semiconductor device according to the seventh aspect of this disclosure is a nitride semiconductor device according to any one of the first to sixth aspects, wherein the intermediate layer includes a GaN layer mainly composed of GaN and an AlGaN layer mainly composed of AlGaN provided above the GaN layer.

[0022] This prevents the interfaces between the GaN layer and the p-type shielding layer and p-type threshold adjustment layer from being exposed, thereby reducing leakage current. Furthermore, the difference in etching rates between the AlGaN layer and the GaN layer can be utilized, simplifying the etching process.

[0023] The nitride semiconductor device according to the eighth aspect of this disclosure is the nitride semiconductor device according to the seventh aspect, wherein the Al composition ratio of the AlGaN layer is 10% or more.

[0024] This enhances the effect of reducing leakage current. Furthermore, it allows for a larger difference in etching rate relative to the GaN layer, making the etching process easier.

[0025] A nitride semiconductor device according to the ninth aspect of this disclosure is a nitride semiconductor device according to any one of the first to eighth aspects, wherein the electron supply layer contains Al, and the Al composition ratio of the electron supply layer is 10% or more.

[0026] This allows for an increase in polarization and thus an increase in the concentration of 2DEG.

[0027] A nitride semiconductor device according to a tenth aspect of the present disclosure is a nitride semiconductor device according to any one of the second to ninth aspects, wherein the electron supply layer is provided with a recess portion at a position that overlaps the upper surface of the second nitride semiconductor layer in a plan view of the substrate, and the gate portion is provided in contact with at least a part of the bottom surface of the recess portion.

[0028] This allows the transistor threshold to be adjusted by the depth of the recess. For example, it makes it easy to implement normally-off transistor operation. Furthermore, it becomes possible to increase the thickness of the electron supply layer in areas other than the recess, allowing for a higher concentration of 2DEG in the thickened areas. Therefore, it is possible to achieve both normally-off operation and reduced on-resistance.

[0029] A nitride semiconductor device according to the eleventh aspect of this disclosure is a nitride semiconductor device according to any one of the second to tenth aspects, wherein the upper surface of the electron supply layer is a flat surface between the source electrode and the shielding portion and overlaps with the upper surface of the second nitride semiconductor layer in a plan view of the substrate.

[0030] This eliminates the need to form recesses, thereby improving process stability.

[0031] A nitride semiconductor device according to a twelfth aspect of the present disclosure is a nitride semiconductor device according to any one of the first to eleventh aspects, wherein the source electrode is electrically connected to the second nitride semiconductor layer via a second opening that penetrates the electron supply layer and the electron transport layer and reaches the second nitride semiconductor layer.

[0032] This allows a reverse bias to be applied to the pn junction between the p-type second nitride semiconductor layer and the n-type first nitride semiconductor layer via the source and drain electrodes. Therefore, the breakdown voltage of the vertical transistor can be increased.

[0033] A nitride semiconductor device according to a thirteenth aspect of the present disclosure is a nitride semiconductor device according to a twelfth aspect, comprising a p-type fourth nitride semiconductor layer provided in contact with the second nitride semiconductor layer within the second opening, and the source electrode being in contact with the fourth nitride semiconductor layer.

[0034] Since etching damage can occur in the second nitride semiconductor layer when forming the second aperture, good contact may not be obtained and contact resistance may increase when the second nitride semiconductor layer and the source electrode are brought into contact. In contrast, according to this embodiment, the source electrode and the second nitride semiconductor layer are electrically connected via the fourth nitride semiconductor layer, so contact resistance can be reduced.

[0035] A nitride semiconductor device according to a 14th aspect of this disclosure is a nitride semiconductor device according to any one of the 1st to 13th aspects, wherein the intermediate layer mainly comprises a nitride semiconductor.

[0036] This allows the electron supply layer and the intermediate layer to be formed continuously by epitaxial growth. Since defect levels are less likely to form at the interface, the operation of the transistor can be stabilized.

[0037] A nitride semiconductor device according to the 15th aspect of this disclosure is a nitride semiconductor device according to any one of the 1st to 14th aspects, wherein the conductivity type of the intermediate layer is n-type.

[0038] This allows the n-type intermediate layer to push down the potential at the conduction band edge of the channel, which is lifted by the p-type third nitride semiconductor layer. Therefore, the decrease in the concentration of 2DEG can be suppressed, and the on-resistance can be reduced. In addition, the n-type intermediate layer can suppress the diffusion of p-type impurities from the p-type third nitride semiconductor layer. The n-type intermediate layer can counteract the p-type conversion caused by p-type impurities, and the expansion of the depletion region is suppressed. Therefore, the decrease in the concentration of 2DEG can be suppressed, and the on-resistance can be reduced.

[0039] A nitride semiconductor device according to the sixteenth aspect of this disclosure is a nitride semiconductor device according to the fifteenth aspect, wherein the carrier concentration of the intermediate layer is 2 × 10 17 cm -3 That's all.

[0040] This allows the potential at the conduction band edge of the channel to be sufficiently lowered. Therefore, the decrease in the concentration of 2DEG can be suppressed, and the on-resistance can be reduced.

[0041] A nitride semiconductor device according to the 17th aspect of this disclosure is a nitride semiconductor device according to any one of the 1st to 14th aspects, wherein the conductivity type of the intermediate layer is i-type.

[0042] This allows the i-type intermediate layer to suppress the diffusion of p-type impurities from the p-type third nitride semiconductor layer. Since the expansion of the depletion region associated with the expansion of the p-type region is suppressed, the decrease in the concentration of 2DEG can be suppressed, and the on-resistance can be reduced.

[0043] A nitride semiconductor device according to the 18th aspect of this disclosure is a nitride semiconductor device according to the 17th aspect, wherein the intermediate layer contains a p-type impurity.

[0044] This allows the i-type intermediate layer to suppress the diffusion of p-type impurities.

[0045] A nitride semiconductor device according to the 19th aspect of this disclosure is a nitride semiconductor device according to any one of the 1st to 18th aspects, wherein the thickness of the intermediate layer is 20 nm or more and 500 nm or less.

[0046] This effectively suppresses the diffusion of p-type impurities.

[0047] The embodiments will be described in detail below with reference to the drawings.

[0048] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. Furthermore, any components in the following embodiments that are not described in an independent claim will be described as optional components.

[0049] Furthermore, each figure is a schematic diagram and not necessarily a strictly accurate representation. Therefore, for example, the scale may not necessarily match in each figure. Also, in each figure, substantially identical components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0050] Furthermore, in this specification, terms indicating relationships between elements such as parallel and orthogonal, terms indicating the shape of elements such as rectangles, and numerical ranges do not represent only strict meanings, but also include substantially equivalent ranges, such as differences of a few percent.

[0051] Furthermore, in this specification, the "thickness direction" of a substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layer and is also referred to as the "vertical direction." In addition, the direction parallel to the main surface of the substrate may be referred to as the "horizontal direction." A "vertical" semiconductor device means a device in which the main path of current, such as drain current or forward current, is in the vertical direction, that is, a device in which the main current passes through the substrate in the vertical direction. A "horizontal" semiconductor device means a device in which the main path of current, such as drain current or forward current, is in the horizontal direction, that is, a device in which the main current does not pass through the substrate.

[0052] Furthermore, the side of the substrate on which the heterostructure generating 2DEG is provided is considered the "upper" or "upper side," and the opposite side is considered the "lower" or "lower side." In this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather are used as terms defined by the relative positional relationship based on the stacking order in the stacked configuration. Moreover, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close contact with each other and are in touch.

[0053] Furthermore, in this specification, unless otherwise specified, "plan view" refers to a view of the semiconductor device substrate from a direction perpendicular to the main surface, that is, a view of the main surface of the substrate from the front.

[0054] Furthermore, in this specification, "A and B overlap in a plan view" means that at least a part of A and at least a part of B overlap. That is, this includes cases where only a part of A and only a part of B overlap, where all of A overlaps with B, where all of B overlaps with A, where A and B completely overlap each other, and so on.

[0055] Furthermore, n-type and p-type represent the conductivity types of semiconductors, and they are conductivity types with opposite polarities. +The n+ type represents a state where an n-type dopant is added at a high concentration to a semiconductor, that is, so-called heavy doping. Also, n - - type represents a state where an n-type dopant is added at a low concentration to a semiconductor, that is, so-called light doping. n + + type and n - - type are both examples of n-type, and they may be collectively described as n-type without distinguishing between them. Also, for p-type, p + + type and p - - type, the same applies.

[0056] Also, in the present specification, the "main component" means the component with the highest content ratio among all components constituting a member. For example, a component with a content ratio of 50% or more is a main component. Components include materials, elements, compounds, and the like.

[0057] Also, in the present specification, AlGaN refers to the ternary mixed crystal Al x Ga 1-x N (0<x<1). Hereinafter, multicomponent mixed crystals are abbreviated by the arrangement of respective constituent element symbols, such as AlInN, GaInN, etc. For example, Al x Ga 1-x-y In y N (0<x<1, 0<y<1, and 0<x+y<1), which is an example of a nitride semiconductor, is abbreviated as AlGaInN. x, 1-x-y, and y respectively represent the composition ratios of Al, Ga, and In.

[0058] Also, in the present specification, ordinal numbers such as "first" and "second" do not mean the number or order of constituent elements unless otherwise specified, and are used for the purpose of avoiding confusion and distinguishing between constituent elements of the same type.

[0059] (Embodiment 1) First, the configuration of the nitride semiconductor device according to Embodiment 1 will be described with reference to FIG. 1.

[0060] Figure 1 is a cross-sectional view of the nitride semiconductor device 1 according to this embodiment. In Figure 1, each component of the nitride semiconductor device 1, such as the semiconductor layer, insulating layer, and electrodes, is shaded with diagonal lines to represent its cross-section. However, the diagonal shading representing the cross-section of the electron transport layer 22 is omitted. The same applies to the other cross-sectional views from Figure 2 onward.

[0061] The nitride semiconductor device 1 shown in Figure 1 is a normally-off vertical FET (Field Effect Transistor). In the nitride semiconductor device 1, for example, the source electrode 34 is grounded and a positive potential is applied to the drain electrode 36. The potential applied to the drain electrode 36 is, for example, between 100V and 1200V, but is not limited to this. The nitride semiconductor device 1 performs modulation operation according to the potential applied to the gate electrode 32. For example, when 0V or a negative potential (for example, -5V) is applied to the gate electrode 32, no current flows between the drain electrode 36 and the source electrode 34. That is, the nitride semiconductor device 1 becomes non-conductive (off). When a positive potential (for example, +5V) is applied to the gate electrode 32, current flows from the drain electrode 36 to the source electrode 34. That is, the nitride semiconductor device 1 becomes conductive (on). The current that flows from the drain electrode 36 to the source electrode 34 when it is ON is called the drain current. The drain current flows through the substrate 10 in the direction of its thickness (i.e., the longitudinal direction).

[0062] As shown in Figure 1, the nitride semiconductor device 1 comprises a substrate 10, a drift layer 12, a block layer 14, an electron transport layer 22, an electron supply layer 24, an intermediate layer 26, a shielding layer 27, a threshold adjustment layer 28, a gate electrode 32, a source electrode 34, a drain electrode 36, and a shielding electrode 38. Furthermore, the nitride semiconductor device 1 comprises an insulating film 40 and a source wiring 50. The nitride semiconductor device 1 is also provided with a first aperture 20 and a second aperture 30. The threshold adjustment layer 28, gate electrode 32, second aperture 30, and source electrode 34 are provided on both the left and right sides of the first aperture 20 in the cross-sectional view shown in Figure 1.

[0063] Nitride semiconductor device 1 is a device in which the semiconductor layer containing the channel mainly consists of a nitride semiconductor. Specifically, the drift layer 12, the block layer 14, the electron transport layer 22, the electron supply layer 24, the intermediate layer 26, the shielding layer 27, and the threshold adjustment layer 28 each mainly consist of a nitride semiconductor.

[0064] The following describes the details of each component of the nitride semiconductor device 1.

[0065] The substrate 10 has, for example, a thickness of 300 μm and a carrier concentration of 5 × 10 18 cm -3 n + This is a substrate containing GaN of a specific type as its main component.

[0066] Note that the substrate 10 does not have to be a nitride semiconductor substrate. For example, the substrate 10 may be a Si substrate, a SiC substrate, or a ZnO substrate.

[0067] The drift layer 12 is an example of an n-type first nitride semiconductor layer and is provided above the substrate 10. The drift layer 12 is, for example, an n-type first nitride semiconductor layer with a thickness of 8 μm. - This film mainly contains GaN of type 10. The donor concentration of the drift layer 12 is, for example, 1 × 10⁻⁶. 15 cm -3 The above 1 x 10 17 cm -3 The following is an example: 1 × 10 16 cm -3 Furthermore, the carbon concentration (C concentration) of the drift layer 12 is, for example, 1 × 10⁻⁶. 15 cm -3 The above 5 x 10 16 cm -3 The drift layer 12 is provided, for example, in contact with the upper surface (main surface) of the substrate 10.

[0068] The block layer 14 is an example of a p-type second nitride semiconductor layer and is provided above the drift layer 12. The block layer 14 has, for example, a thickness of 400 nm and a carrier concentration of 1 × 10⁻¹⁶ 17 cm -3This film mainly contains p-type GaN. The block layer 14 is provided in contact with the upper surface of the drift layer 12.

[0069] The block layer 14 is provided with a first opening 20. The first opening 20 penetrates the block layer 14 and reaches the drift layer 12. The first opening 20 is sometimes called a gate opening or a longitudinal conduction opening. The bottom surface 20a of the first opening 20 is part of the top surface of the drift layer 12. As shown in Figure 1, the bottom surface 20a is located below the bottom surface of the block layer 14. The bottom surface of the block layer 14 corresponds to the interface between the block layer 14 and the drift layer 12. The bottom surface 20a is, for example, parallel to the main surface of the substrate 10. When the nitride semiconductor device 1 is turned on, the drain current flows between the drain electrode 36 and the source electrode 34 through the bottom surface 20a of the first opening 20.

[0070] In this embodiment, the first opening 20 is formed such that its opening area increases as it moves away from the substrate 10. Specifically, the side surface 20b of the first opening 20 is inclined at an angle. As shown in Figure 1, the cross-sectional shape of the first opening 20 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid.

[0071] The inclination angle of the side surface 20b with respect to the bottom surface 20a is, for example, 20° to 80°, but may also be 30° to 45°. The smaller the inclination angle, the closer the side surface 20b is to the c-plane, which allows for an improvement in the film quality of the electron transport layer 22 and other layers formed along the side surface 20b by crystal regrowth. On the other hand, the larger the inclination angle, the less the first opening 20 becomes, thus enabling miniaturization of the nitride semiconductor device 1. The side surface 20b may also be perpendicular to the bottom surface 20a.

[0072] The electron transport layer 22 is provided above the substrate 10. Specifically, the electron transport layer 22 is an example of a first regrowth layer and is provided so as to cover the inner surface of the first opening 20 and the top of the block layer 14. For example, a part of the electron transport layer 22 is provided along the bottom surface 20a and side surface 20b of the first opening 20, and another part of the electron transport layer 22 is provided on the top surface 14a of the block layer 14. The thickness of the electron transport layer 22 is, for example, 50 nm to 300 nm. The electron transport layer 22 is, for example, a film mainly composed of undoped GaN with a thickness of 150 nm. The thickness of the electron transport layer 22 is considered to be the thickness in the flat portion that overlaps with the top surface 14a of the block layer 14, on the outside of the first opening 20 in a plan view of the substrate 10. In addition, although the electron transport layer 22 is assumed to be undoped, it may be partially Si-doped to make it n-type.

[0073] The electron transport layer 22 is in contact with the drift layer 12 at the bottom surface 20a and side surface 20b of the first opening 20. Furthermore, the electron transport layer 22 is in contact with the block layer 14 at the side surface 20b of the first opening 20. Additionally, the electron transport layer 22 is in contact with the top surface 14a of the block layer 14.

[0074] The electron transport layer 22 has a channel. Specifically, a channel 2DEG23 is generated near the interface between the electron transport layer 22 and the electron supply layer 24. The 2DEG23 is bent along the interface between the electron transport layer 22 and the electron supply layer 24, that is, along the inner surface of the first opening 20.

[0075] Although not shown in Figure 1, an AlN layer with a thickness of approximately 1 nm is provided as a second regrowth layer between the electron transport layer 22 and the electron supply layer 24. This suppresses alloy scattering, improves channel mobility, and reduces on-resistance. Note that the AlN layer is not strictly necessary.

[0076] The electron supply layer 24 is provided above the electron transport layer 22. Specifically, the electron supply layer 24 is an example of a third regrowth layer and is provided so as to cover the inner surface of the first opening 20 and the top of the block layer 14. Specifically, the electron supply layer 24 is provided along the top surface of the electron transport layer 22 so as to overlap the bottom surface 20a and side surface 20b of the first opening 20 and the top surface 14a of the block layer 14 in a plan view of the substrate 10.

[0077] The electron supply layer 24 has a larger band gap than the electron transport layer 22. Therefore, an AlGaN / GaN heterointerface is formed between the electron supply layer 24 and the electron transport layer 22. The electron supply layer 24 supplies electrons to the channel (2DEG23) formed in the electron transport layer 22.

[0078] The electron supply layer 24 is, for example, a film mainly composed of undoped AlGaN. The electron supply layer 24 is formed with a nearly uniform thickness in a shape that follows the upper surface of the electron transport layer 22. The thickness of the electron supply layer 24 is considered to be the thickness in the flat portion that overlaps with the upper surface 14a of the block layer 14, on the outside of the first opening 20 in a plan view of the substrate 10.

[0079] Furthermore, if the electron supply layer 24 mainly consists of AlGaN with an Al composition ratio of 20%, cracks are more likely to occur when the thickness of the electron supply layer 24 exceeds 70 nm. This can lead to deterioration of the film quality of the electron supply layer 24, causing leakage or making it impossible to generate 2DEG23 at the desired concentration. By lowering the Al composition ratio, crack occurrence can be suppressed, so the thickness of the electron supply layer 24 can be, for example, between 10 nm and 150 nm. The Al composition ratio of the electron supply layer 24 is not particularly limited, but is, for example, between 10% and 30%.

[0080] The electron supply layer 24 is provided with recesses 25. The recesses 25 are located in a position that overlaps the upper surface 14a of the block layer 14 in a plan view of the substrate 10. The recesses 25 are recesses that are indented from the upper surface 24a of the electron supply layer 24 toward the substrate 10. The sides of the recesses 25 are perpendicular to the bottom surface of the recesses 25, but they may be inclined at an angle.

[0081] The intermediate layer 26 is provided between the electron supply layer 24 and the shielding layer 27, in a position that overlaps the first opening 20 in a plan view of the substrate 10. Specifically, the intermediate layer 26 is provided in contact with the upper surface 24a of the electron supply layer 24 and the lower surface of the shielding layer 27. In this embodiment, the side surface 26b of the intermediate layer 26 is covered by the shielding layer 27. That is, the side surface 26b is in contact with and covered by the shielding layer 27. Furthermore, in a plan view of the substrate 10, the intermediate layer 26 is provided in a position that overlaps the bottom surface 20a and the side surface 20b of the first opening 20. In Figure 1, a dashed line L1 is shown as a straight line passing through the upper end of the first opening 20 and perpendicular to the main surface of the substrate 10. A portion of the intermediate layer 26 may be provided beyond the line L1 towards the source electrode 34. In other words, a portion of the intermediate layer 26 may overlap the outside of the first opening 20 in a plan view of the substrate 10, i.e., the upper surface 14a of the block layer 14. The end of the intermediate layer 26 on the source electrode 34 side may overlap the upper surface 14a of the block layer 14 in a plan view of the substrate 10. The intermediate layer 26 is formed with a substantially uniform thickness in a shape that follows the upper surface 24a of the electron supply layer 24.

[0082] The intermediate layer 26 mainly contains a nitride semiconductor. In this embodiment, the conductivity type of the intermediate layer 26 is n-type. Specifically, the intermediate layer 26 is a film mainly containing n-type GaN. The carrier concentration of the intermediate layer 26 is, for example, 2 × 10⁻⁶. 17 cm -3 That concludes the explanation. This allows for an increase in the concentration of 2DEG23. Furthermore, the carrier concentration in the intermediate layer 26 can be, for example, 1 × 10⁻⁶. 20 cm -3 The following may also apply: The concentration of 2DEG23 is such that the carrier concentration in the intermediate layer 26 is 5 × 10 18 cm-3 The range described above is generally saturated.

[0083] The thickness of the intermediate layer 26 is, for example, between 20 nm and 500 nm, and is 22 nm as an example. The concentration of 2DEG23 increases sharply when the thickness of the intermediate layer 26 is between 20 nm and 50 nm, resulting in a high reduction in on-resistance. On the other hand, the concentration of 2DEG23 is generally saturated when the thickness of the intermediate layer 26 is between 100 nm and 500 nm. Therefore, it is possible to suppress the intermediate layer 26 from becoming excessively thick, and to suppress the occurrence of step breaks in the shielding layer 27 and shielding electrode 38 formed on top. In addition, the time required for deposition of the intermediate layer 26 can be shortened.

[0084] The shielding layer 27 is an example of a shielding portion included in the p-type third nitride semiconductor layer and is provided above the electron supply layer 24. In a plan view of the substrate 10, the shielding layer 27 overlaps the first opening 20 and is electrically connected to the shielding electrode 38. As shown in Figure 1, in a plan view of the substrate 10, the shielding layer 27 is provided so as to extend from the intermediate layer 26 toward the source electrode 34. The shielding layer 27 covers the side surface 26b of the intermediate layer 26. Specifically, the shielding layer 27 is provided so as to contact and cover the upper surface and side surface 26b of the intermediate layer 26 and the upper surface 24a of the electron supply layer 24. The end of the shielding layer 27 toward the source electrode 34, i.e., the side surface 27b, overlaps the upper surface 14a of the block layer 14 in a plan view of the substrate 10. That is, a part of the shielding layer 27 is provided toward the source electrode 34 beyond the straight line L1.

[0085] The shielding layer 27 has, for example, a thickness of 50 nm and a carrier concentration of 5 × 10 17 cm -3 The film mainly contains p-type GaN. The thickness of the shielding layer 27 is, for example, 100 nm to 500 nm. Note that the thickness of the shielding layer 27 and the carrier concentration are merely examples and can be changed as appropriate. For example, the shielding layer 27 may be a film mainly containing p-type AlGaN.

[0086] The threshold adjustment layer 28 is an example of a gate portion included in the p-type third nitride semiconductor layer and is provided above the electron supply layer 24. In a plan view of the substrate 10, the threshold adjustment layer 28 overlaps the upper surface 14a of the block layer 14 and is electrically connected to the gate electrode 32. In a plan view of the substrate 10, the threshold adjustment layer 28 does not overlap the first opening 20. The threshold adjustment layer 28 is provided spaced apart from the shielding layer 27 and is electrically isolated from it.

[0087] The threshold adjustment layer 28 is provided in contact with at least a portion of the bottom surface of the recess portion 25. In this embodiment, the threshold adjustment layer 28 is provided so as to cover the recess portion 25. The length of the threshold adjustment layer 28 in the gate length direction is longer than the length of the recess portion 25 in the gate length direction. The threshold adjustment layer 28 is also provided on the outside of the recess portion 25.

[0088] The threshold adjustment layer 28 can be formed using the same process as the shielding layer 27. Therefore, the main components, composition, and carrier concentration of the threshold adjustment layer 28 are the same as those of the shielding layer 27. For example, the threshold adjustment layer 28 has a thickness of 50 nm and a carrier concentration of 5 × 10⁻¹⁶ 17 cm -3 This film mainly contains p-type GaN. Note that the thickness and carrier concentration of the threshold adjustment layer 28 are merely examples and can be changed as appropriate. For example, the threshold adjustment layer 28 may be a film mainly containing p-type AlGaN. The shielding layer 27 and the threshold adjustment layer 28 may differ from each other in at least one of their thickness, composition, and carrier concentration.

[0089] In the portion where the recess 25 is provided, the thickness of the electron supply layer 24 is reduced. As shown in Figure 1, the thickness of the portion of the electron supply layer 24 where the recess 25 is provided is thinner than the thickness of the portion where the recess 25 is not provided. By reducing the thickness of the portion where the recess 25 is provided, the concentration of 2DEG23 directly below the recess 25 decreases. This allows the transistor threshold voltage to be increased. For example, the threshold voltage can be raised above 0V, making it easier to normally-off the transistor. The transistor threshold voltage can be determined by adjusting the thickness of the portion where the recess 25 is provided. For example, the thickness of the portion where the recess 25 is provided is between 10 nm and 60 nm, and 22 nm is one example.

[0090] Furthermore, the portion of the electron supply layer 24 without recesses 25 can be made thicker without affecting the transistor threshold. As a result, the concentration of 2DEG23 increases directly below the portion without recesses 25, thus reducing the on-resistance. For example, the thickness of the portion without recesses is between 10 nm and 70 nm, with 60 nm being one example. In this way, the provision of recesses 25 makes it possible to achieve both normally-off operation and reduced on-resistance.

[0091] The second opening 30 penetrates the electron supply layer 24 and the electron transport layer 22 and reaches the block layer 14. The second opening 30 is sometimes called the source opening. In a plan view of the substrate 10, the second opening 30 is located away from both the gate electrode 32 and the threshold adjustment layer 28. Since the second opening 30 penetrates the electron transport layer 22, the 2DEG 23 is exposed on the side surface 30b of the second opening 30.

[0092] The bottom surface 30a of the second opening 30 is part of the top surface 14a of the block layer 14. The bottom surface 30a is parallel to the main surface of the substrate 10, for example. In the example shown in Figure 1, the bottom surface 30a is located below the bottom surface of the electron transport layer 22. The bottom surface of the electron transport layer 22 corresponds to the interface between the electron transport layer 22 and the block layer 14.

[0093] Furthermore, as shown in Figure 1, the second opening 30 is formed such that its opening area increases as it moves away from the substrate 10. Specifically, the side surface 30b of the second opening 30 is inclined at an angle. In this case, the inclination angle of the side surface 30b with respect to the bottom surface 30a is, for example, in the range of 30° to 60°. The inclination of the side surface 30b increases the contact area between the source electrode 34 and the 2DEG23, making ohmic connection easier. The 2DEG23 is exposed on the side surface 30b of the second opening 30 and is connected to the source electrode 34 at the exposed portion. The side surface 30b may also be perpendicular to the bottom surface 30a.

[0094] The provision of the second opening 30 reduces the ohmic contact resistance between the channel-functioning 2DEG23 and the source electrode 34. In other words, it reduces the on-resistance of the nitride semiconductor device 1.

[0095] Furthermore, the source electrode 34 and the block layer 14 are electrically connected at the bottom surface 30a of the second opening 30. As a result, the same potential as the potential applied to the source electrode 34 is supplied to the block layer 14. When a reverse voltage is applied to the pn junction formed by the block layer 14 and the drift layer 12, specifically when the drain electrode 36 becomes at a higher potential than the source electrode 34, a depletion layer extends in the drift layer 12, making it possible to increase the breakdown voltage of the nitride semiconductor device 1.

[0096] The gate electrode 32 is located above the threshold adjustment layer 28. Specifically, the gate electrode 32 is located in contact with the upper surface of the threshold adjustment layer 28 and is electrically connected to the threshold adjustment layer 28. In a plan view of the substrate 10, the gate electrode 32 is located in a position that overlaps the block layer 14 but does not overlap the first opening 20. Specifically, in a plan view of the substrate 10, the gate electrode 32 overlaps the upper surface 14a of the block layer 14.

[0097] The gate electrode 32 is formed using a conductive material such as a metal. For example, the gate electrode 32 can be made of a material that is ohmic-connected to a p-type nitride semiconductor such as p-type GaN, but is not limited to this, and a material that is Schottky-connected to a p-type nitride semiconductor may also be used. For example, Pd, Ni-based materials, WSi, Au, etc. can be used as the material for forming the gate electrode 32.

[0098] The source electrode 34 is provided above the block layer 14, away from the gate electrode 32. In this embodiment, the source electrode 34 is electrically connected to the block layer 14 via the second opening 30. The source electrode 34 is also electrically connected to the electron transport layer 22 via the second opening 30. Specifically, the source electrode 34 is provided in contact with the bottom surface 30a and the side surface 30b of the second opening 30. The source electrode 34 is in contact with the block layer 14 at the bottom surface 30a of the second opening 30. The source electrode 34 is in contact with 2DEG23 at the side surface 30b of the second opening 30. This reduces the contact resistance between the source electrode 34 and 2DEG23, thereby reducing the on-resistance of the nitride semiconductor device 1.

[0099] The source electrode 34 is formed using a conductive material such as a metal. As the material for the source electrode 34, for example, a material that can be ohmic connected to an n-type nitride semiconductor such as n-type GaN by heat treatment can be used, such as Ti / Al (a stacked structure of a Ti layer and an Al layer).

[0100] The drain electrode 36 is located below the substrate 10. Specifically, the drain electrode 36 is located in contact with the lower surface of the substrate 10.

[0101] The drain electrode 36 is formed using a conductive material such as a metal. Similar to the material of the source electrode 34, the material of the drain electrode 36 can be a material that is ohmic-connected to an n-type nitride semiconductor such as n-type GaN, such as Ti / Al.

[0102] The shielding electrode 38 is located above the shielding layer 27, in a position that overlaps the first opening 20 in a plan view of the substrate 10. The shielding electrode 38 is electrically connected to the source electrode 34 and the shielding layer 27. Specifically, the source wiring 50 is connected to the shielding electrode 38 and is set to the same potential as the source electrode 34.

[0103] The gate electrode 32 and the shielding electrode 38 are formed by removing and separating a portion of the conductive film deposited in the same process. Therefore, the gate electrode 32 and the shielding electrode 38 have the same main components. For example, the gate electrode 32 and the shielding electrode 38 each contain, as their main component, a material that is ohmic-connected to a p-type nitride semiconductor such as p-type GaN. For example, Pd, Ni-based materials, WSi, Au, etc., can be used as the materials for forming the gate electrode 32 and the shielding electrode 38.

[0104] The insulating film 40 is provided above the gate electrode 32. Specifically, the insulating film 40 is provided so as to cover the gate electrode 32, the shielding layer 27, the threshold adjustment layer 28, the electron supply layer 24, and the source electrode 34. The insulating film 40 has a laminated structure of multiple insulating films. The multiple insulating films are, for example, insulating films such as SiN, SiO2, SiON, and Al2O3. The insulating film 40 may also have a single-layer structure of one insulating film.

[0105] The source wiring 50 is provided above the insulating film 40 and is connected to the source electrode 34 and the shielding electrode 38 through an opening in the insulating film 40. The source wiring 50 is formed using a conductive material such as metal. For example, the source wiring 50 is a plated film made of, for example, gold (Au).

[0106] In the nitride semiconductor device 1 configured as described above, 2DEG23 is generated near the interface between the electron transport layer 22 and the electron supply layer 24, and can be used as a channel. In the region that overlaps with the p-type threshold adjustment layer 28 in a plan view, the potential at the conduction band edge of the channel can be increased. Therefore, the nitride semiconductor device 1 can be operated as a normally-off transistor.

[0107] Furthermore, according to the nitride semiconductor device 1 of this embodiment, the transistor threshold is determined at the flat portion of the channel outside the first aperture 20, and is no longer affected by the slope of the channel. This improves the controllability of the transistor's on and off states. In addition, by providing a shielding electrode 38 electrically connected to the source electrode 34, the electric field lines extending from the drain electrode 36 can be terminated by the shielding electrode 38. This reduces the gate-drain parasitic capacitance Cgd, enabling faster switching.

[0108] Furthermore, the source potential is supplied to the shielding layer 27 from the shielding electrode 38. Therefore, a reverse bias can be applied to the pn junction between the shielding layer 27 and 2DEG23 via the shielding electrode 38 and the drain electrode 36. This increases the breakdown voltage of the transistor. Moreover, in the region that overlaps with the p-type shielding layer 27 in a plan view, the intermediate layer 26 can suppress the influence of the p-type shielding layer 27 on the channel. In other words, the decrease in the concentration of 2DEG23 can be suppressed, and the on-resistance can be reduced.

[0109] As described above, an intermediate layer 26 is provided to reduce on-resistance, but the side surface 26b of the intermediate layer 26 may be damaged by the plasma during the formation of the insulating film 40. Therefore, there is a risk that a leakage current path may be formed at the pn junction interface between the p-type shielding layer 27 and the n-type intermediate layer 26, which may increase the leakage current. In contrast, in the nitride semiconductor device 1 according to this embodiment, the side surface 26b of the intermediate layer 26 is covered with the shielding layer 27. Since the pn junction interface is not exposed when the insulating film 40 is formed, it is difficult for a leakage current path to be formed, and the leakage current can be reduced.

[0110] The method for manufacturing the nitride semiconductor device 1 is not particularly limited, but for example, the following manufacturing methods can be used.

[0111] First, multiple nitride semiconductor films are formed on the main surface of the substrate 10 by epitaxial growth of a nitride semiconductor. Specifically, a drift layer 12 and a block layer 14 are formed on the main surface of the substrate 10 in that order. In epitaxial growth, the composition, thickness, conductivity type, and impurity concentration of the nitride semiconductor film can be adjusted by adjusting the growth conditions such as the raw material, growth temperature, and growth time.

[0112] Subsequently, the first opening 20 is formed by removing a portion of the block layer 14. For example, the block layer 14 is removed by photolithography and dry etching. At this time, by removing a portion of the surface layer of the drift layer 12 immediately following the removal of the block layer 14, the bottom surface 20a of the first opening 20 is formed below the interface between the block layer 14 and the drift layer 12, as shown in Figure 1.

[0113] Next, a nitride semiconductor is grown by a second epitaxial growth so as to cover the bottom surface 20a and side surface 20b of the first opening 20, and the top surface 14a of the block layer 14. Specifically, the electron transport layer 22, electron supply layer 24, and intermediate layer 26 are formed in this order.

[0114] Next, the second opening 30 is formed by removing a portion of each of the intermediate layer 26, the electron supply layer 24, and the electron transport layer 22. For example, each layer is removed by photolithography and dry etching. At this time, by removing a portion of the surface layer of the block layer 14, following the removal of the electron transport layer 22, the bottom surface 30a of the second opening 30 is formed below the interface between the block layer 14 and the electron transport layer 22, as shown in Figure 1. Furthermore, the intermediate layer 26 is patterned into a predetermined shape by removing a portion of the intermediate layer 26. As a result, a portion of the upper surface 24a of the electron supply layer 24 is exposed without being covered by the intermediate layer 26. Furthermore, the recess 25 is formed by removing a portion of the electron supply layer 24.

[0115] Next, a nitride semiconductor is grown by a third epitaxial growth so as to cover the intermediate layer 26 and the recess 25. Specifically, after forming a nitride semiconductor film to cover the intermediate layer 26 and the recess 25, a shielding layer 27 and a threshold adjustment layer 28 are formed by removing a portion of the formed nitride semiconductor film. At this time, the shielding layer 27 remains covering the side surface 26b of the intermediate layer 26. That is, a portion of the shielding layer 27 is formed to protrude from the intermediate layer 26 toward the source electrode 34. Note that the shielding layer 27 and the threshold adjustment layer 28 may be formed in different processes. This allows for differences in composition and impurity concentration between the shielding layer 27 and the threshold adjustment layer 28. Also, the threshold adjustment layer 28 may not be formed at all.

[0116] Next, the gate electrode 32, shielding electrode 38, and source electrode 34 are formed. For example, first, a conductive film is formed using a conductive material that is ohmic-connected to the n-type nitride semiconductor, and then the source electrode 34 is formed by patterning it into a predetermined shape. The conductive film is formed by sputtering or evaporation. The conductive film is patterned by etching or lift-off. The source electrode 34 is formed to cover the bottom surface 30a and side surface 30b of the second opening 30 in contact with it, and not to contact the threshold adjustment layer 28. Next, the gate electrode 32 and shielding electrode 38 are formed by forming a conductive film using a conductive material that is ohmic-connected to the p-type nitride semiconductor, and then the patterning it into a predetermined shape. The formation and patterning of the conductive film are the same as in the case of the source electrode 34. The gate electrode 32 is formed on the upper surface of the threshold adjustment layer 28, and not to contact the upper surface 24a of the electron supply layer 24, the source electrode 34, and the shielding layer 27. Furthermore, the shielding electrode 38 is formed on the upper surface of the shielding layer 27 so as not to come into contact with the upper surface 24a of the electron supply layer 24 and the threshold adjustment layer 28.

[0117] The gate electrode 32 and the shielding electrode 38 may be formed in different processes. The gate electrode 32 and the shielding electrode 38 may be formed before the source electrode 34. For example, after patterning the gate electrode 32, the gate electrode 32 may be used as a mask to pattern the threshold adjustment layer 28. Also, if the gate electrode 32, the shielding electrode 38 and the source electrode 34 are formed using the same conductive material, the gate electrode 32, the shielding electrode 38 and the source electrode 34 may be formed in the same process.

[0118] Next, the insulating film 40 and the source wiring 50 are formed. The insulating film 40 is formed by plasma CVD (Chemical Vapor Deposition), atomic layer deposition (ALD), or coating. After deposition, the insulating film 40 is etched to expose the source electrode 34. Then, the source wiring 50 is formed by plating or other methods. Although not shown in Figure 1, gate wiring that is electrically connected to the gate electrode 32 can be formed in the same way as the source wiring 50.

[0119] Next, a drain electrode 36 is formed on the lower surface of the substrate 10. For example, the drain electrode 36 is formed by creating a conductive film using a conductive material that is ohmic-connected to the n-type nitride semiconductor. The conductive film is formed by sputtering or vapor deposition.

[0120] Through the above process, the nitride semiconductor device 1 shown in Figure 1 can be manufactured.

[0121] (Embodiment 2) Next, Embodiment 2 will be described.

[0122] In Embodiment 2, the main difference compared to Embodiment 1 is the shape of the shielding layer. The following explanation will focus on the differences from Embodiment 1, omitting or simplifying the explanation of the common points.

[0123] Figure 2 is a cross-sectional view of the nitride semiconductor device 101 according to this embodiment. Compared to the nitride semiconductor device 1 shown in Figure 1, the nitride semiconductor device 101 shown in Figure 2 is equipped with a shielding layer 127 instead of the shielding layer 27.

[0124] The shielding layer 127 has the same configuration as the shielding layer 27, but differs in its cross-sectional shape. Specifically, the end of the shielding layer 127 on the source electrode 34 side overlaps the inclined side surface 20b of the first opening 20 in a plan view of the substrate 10. The end of the shielding layer 127 on the source electrode 34 side is the side surface 127b shown in Figure 2. Figure 2 also shows a straight line L2 on the side surface 20b of the first opening 20, passing through the lower end of the block layer 14 and perpendicular to the main surface of the substrate 10. The side surface 127b of the shielding layer 127 is located between the straight line L1 and the straight line L2. Note that the straight line L1 is a straight line passing through the upper end of the first opening 20, similar to Embodiment 1, and is perpendicular to the main surface of the substrate 10.

[0125] According to this embodiment, the area in which the shielding layer 127 contacts the electron supply layer 24 without going through the intermediate layer 26 is reduced. In other words, the area of ​​the non-overlapping portion of the shielding layer 127 that does not overlap with the intermediate layer 26 in a plan view is reduced. As a result, the decrease in the concentration of 2DEG23 can be suppressed, and the on-resistance can be reduced.

[0126] Furthermore, as the side surface 127b of the shielding layer 127 approaches the bottom surface 20a of the first opening 20 in a plan view, the overlap between the block layer 14 and the shielding layer 127 decreases, which may reduce the parasitic capacitance Cgd between the gate and the drain. The side surface 127b of the shielding layer 127 can be positioned appropriately considering the effect of reducing on-resistance and the size of the parasitic capacitance Cgd.

[0127] (Embodiment 3) Next, Embodiment 3 will be described.

[0128] Embodiment 3 differs from Embodiment 1 mainly in that the sides of the intermediate layer are covered by a threshold adjustment layer. Below, we will focus on explaining the differences from Embodiment 1, and omit or simplify the explanation of the common points.

[0129] Figure 3 is a cross-sectional view of the nitride semiconductor device 201 according to this embodiment. Compared to the nitride semiconductor device 1 shown in Figure 1, the nitride semiconductor device 201 shown in Figure 3 has an intermediate layer 226 instead of the intermediate layer 26.

[0130] The intermediate layer 226 has a similar structure to the intermediate layer 26, but differs in its cross-sectional shape. The intermediate layer 226 is provided between the electron supply layer 24 and the shielding layer 27 and the threshold adjustment layer 28. In other words, a portion of the intermediate layer 226 overlaps the threshold adjustment layer 28 in a plan view of the substrate 10. Specifically, the end of the intermediate layer 226 on the source electrode 34 side is located between the threshold adjustment layer 28 and the electron supply layer 24. The side surface 226b of the intermediate layer 226 is covered by the threshold adjustment layer 28.

[0131] In the example shown in Figure 3, the side surface 226b of the intermediate layer 226 is flush with the side surface of the recess 25, but this is not limited to this. The side surface of the recess 25 may be located closer to the source electrode 34 than the side surface 226b of the intermediate layer 226.

[0132] According to this embodiment, since the side surface 226b of the intermediate layer 226 is covered by the threshold adjustment layer 28, the leakage current through the side surface 226b of the intermediate layer 226 can be reduced. In addition, since the area of ​​the intermediate layer 226 is increased, the decrease in the concentration of 2DEG23 can be further suppressed, and the on-resistance can be further reduced.

[0133] (Embodiment 4) Next, Embodiment 4 will be described.

[0134] Embodiment 4 differs from Embodiment 3 primarily in that the intermediate layer has a laminated structure. The following explanation will focus on the differences from Embodiment 3, omitting or simplifying the explanation of the commonalities.

[0135] Figure 4 is a cross-sectional view of a nitride semiconductor device 301 according to this embodiment. Compared to the nitride semiconductor device 201 shown in Figure 3, the nitride semiconductor device 301 shown in Figure 4 includes an intermediate layer 326 instead of the intermediate layer 226. The intermediate layer 326 includes a GaN layer 326A and an AlGaN layer 326B.

[0136] The GaN layer 326A is a nitride semiconductor layer mainly composed of GaN. The GaN layer 326A is provided between the electron supply layer 24, the shielding layer 27, and the threshold adjustment layer 28. In other words, a portion of the GaN layer 326A overlaps with the threshold adjustment layer 28 in a plan view of the substrate 10. Specifically, the end of the GaN layer 326A on the source electrode 34 side is located between the threshold adjustment layer 28 and the electron supply layer 24.

[0137] The conductivity type of the GaN layer 326A is n-type. The carrier concentration of the GaN layer 326A is, for example, 2 × 10⁻⁶. 17 cm -3 That concludes the explanation. This allows for an increase in the concentration of 2DEG23. Furthermore, the carrier concentration of the GaN layer 326A can be, for example, 1 × 10⁻⁶. 20 cm -3 The following may also apply: The concentration of 2DEG23 is such that the carrier concentration of GaN layer 326A is 5 × 10 18 cm -3 The range described above is generally saturated.

[0138] The film thickness of the GaN layer 326A is, for example, between 20 nm and 500 nm, with 22 nm being one example. The concentration of 2DEG23 increases sharply in the range of 20 nm to 50 nm when the film thickness of the GaN layer 326A is between 20 nm and 50 nm, resulting in a high reduction in on-resistance. On the other hand, the concentration of 2DEG23 is generally saturated in the range of 100 nm to 500 nm when the film thickness of the GaN layer 326A is between 100 nm and 500 nm. Therefore, it is possible to suppress the GaN layer 326A from becoming thicker than necessary, and to suppress the occurrence of step breaks in the shielding layer 27, threshold adjustment layer 28, gate electrode 32, and shielding electrode 38 formed on top. In addition, the time required for deposition of the GaN layer 326A can be shortened.

[0139] The AlGaN layer 326B is a nitride semiconductor layer mainly composed of AlGaN and is provided above the GaN layer 326A. The AlGaN layer 326B is provided between the GaN layer 326A and the shielding layer 27 and the threshold adjustment layer 28. In other words, a portion of the AlGaN layer 326B overlaps the threshold adjustment layer 28 in a plan view of the substrate 10. Specifically, the end of the AlGaN layer 326B on the source electrode 34 side is located between the threshold adjustment layer 28 and the GaN layer 326A.

[0140] The conductivity type of the AlGaN layer 326B is n-type. Specifically, the carrier concentration of the AlGaN layer 326B is not particularly limited, but for example, 2 × 10⁻⁶ 17 cm -3 The above is 1 x 10 20 cm -3 The following applies: The film thickness of the AlGaN layer 326B is, for example, 50 nm or less. The Al composition ratio of the AlGaN layer 326B is not particularly limited, but is, for example, 10% to 30%.

[0141] In this embodiment, the side surface 326b of the intermediate layer 326 is covered by the threshold adjustment layer 28. That is, both the side surface of the GaN layer 326A and the side surface of the AlGaN layer 326B are covered by the threshold adjustment layer 28. This reduces the leakage current through the side surface 326b of the intermediate layer 326. Also, since the AlGaN layer 326B covers the upper surface of the GaN layer 326A, the upper surface of the GaN layer 326A does not come into contact with the threshold adjustment layer 28 and the shielding layer 27. This makes it less likely for the upper surface of the GaN layer 326A to be damaged by plasma, thus reducing the leakage current. Furthermore, in the nitride semiconductor device 301 according to this embodiment, similar to embodiment 3, the area of ​​the intermediate layer 326 is increased, which further suppresses the decrease in the concentration of 2DEG23 and further reduces the on-resistance.

[0142] The intermediate layer 326 according to this embodiment may be provided on the nitride semiconductor devices 101 and 201 according to Embodiment 1 or 2. In other words, each side surface of the GaN layer 326A and the AlGaN layer 326B may be covered with the shielding layer 27.

[0143] (Embodiment 5) Next, Embodiment 5 will be described.

[0144] Embodiment 5 differs from Embodiment 1 primarily in that the electron supply layer does not have a recess. The following explanation will focus on the differences from Embodiment 1, omitting or simplifying the explanation of the commonalities.

[0145] Figure 5 is a cross-sectional view of the nitride semiconductor device 401 according to this embodiment. Compared to the nitride semiconductor device 1 shown in Figure 1, the nitride semiconductor device 401 shown in Figure 5 is equipped with an electron supply layer 424 instead of the electron supply layer 24.

[0146] The electron supply layer 424 has a similar configuration to the electron supply layer 24, but does not have a recess 25. Specifically, the upper surface 424a of the electron supply layer 424 is flat between the source electrode 34 and the shielding layer 27, and within the range that overlaps with the upper surface 14a of the block layer 14 in a plan view of the substrate 10. In other words, within the range outside the first opening 20 in a plan view of the substrate 10, the upper surface 424a of the electron supply layer 424 is flat.

[0147] Since there is no recess 25, the threshold of the nitride semiconductor device 401 depends on the thickness of the portion of the electron supply layer 424 that overlaps with the threshold adjustment layer 28 in a plan view (i.e., the flat portion of the electron supply layer 424). If the flat portion of the electron supply layer 424 is too thick, the concentration of 2DEG23 becomes too high, making it difficult to set the threshold to 0V or higher and achieve normally-off operation. For this reason, the thickness of the flat portion of the electron supply layer 424 is, for example, 10nm to 70nm, and 22nm as an example. This makes it possible to achieve normally-off operation of the transistor.

[0148] According to the nitride semiconductor device 401, since it is not necessary to form the recess portion 25, process stability can be improved. Improved process stability allows for a stable threshold. The electron supply layer 424, which does not have the recess portion 25, may be provided instead of the electron supply layer 24 of the nitride semiconductor devices 101, 201, and 301 according to embodiments 2 to 4. Furthermore, the intermediate layer 26 of the nitride semiconductor device 401 may have a laminated structure of a GaN layer and an AlGaN layer, similar to the intermediate layer 326 according to embodiment 4.

[0149] (Embodiment 6) Next, Embodiment 6 will be described.

[0150] In Embodiment 6, the main difference from Embodiment 1 is that the source electrode is electrically connected to the p-type block layer via a p-type nitride semiconductor layer. Below, we will focus on explaining the differences from Embodiment 1, and omit or simplify the explanation of the common points.

[0151] Figure 6 is a cross-sectional view of the nitride semiconductor device 501 according to this embodiment. The nitride semiconductor device 501 shown in Figure 6 has a contact layer 514 compared to the nitride semiconductor device 1 shown in Figure 1. In addition, the nitride semiconductor device 501 is provided with a third opening 530.

[0152] The contact layer 514 is an example of a p-type fourth nitride semiconductor layer and is provided to contact the block layer 14 within the second opening 30. Specifically, the contact layer 514 contacts and covers the bottom surface 30a and side surface 30b of the second opening 30, and contacts the block layer 14 with the bottom surface 30a and a portion of the side surface 30b. The contact layer 514 may also cover the upper surface of the electron supply layer 24 near the opening end of the second opening 30.

[0153] The contact layer 514 has a thickness of 200 nm and a carrier concentration of 5 × 10⁻¹⁴. 17 cm -3This film mainly contains p-type GaN. The contact layer 514 can be formed in the same process as the shielding layer 27 and the threshold adjustment layer 28. Therefore, the composition and carrier concentration of the contact layer 514 are the same as those of the shielding layer 27 and the threshold adjustment layer 28. Note that the thickness and carrier concentration of the contact layer 514 are merely examples and can be changed as appropriate.

[0154] The contact layer 514 is formed by epitaxial growth after the formation of the second opening 30. The bottom surface 30a of the second opening 30 is etched during the formation of the second opening 30, whereas the top surface of the contact layer 514 is not etched. Therefore, when the source electrode 34 is in contact with the contact layer 514, the contact resistance can be reduced compared to when it is in contact with the block layer 14. In this way, by electrically connecting the source electrode 34 to the block layer 14 via the contact layer 514, the potential of the block layer 14 can be stabilized.

[0155] The third opening 530 is located between the second opening 30 and the first opening 20 in a plan view of the substrate 10. The third opening 530 is provided to reduce the contact resistance between the source electrode 34 and 2DEG23, and is sometimes referred to as the source opening. The third opening 530 penetrates the electron supply layer 24 and reaches the electron transport layer 22. For example, the bottom surface 530a of the third opening 530 is located below the interface between the electron transport layer 22 and the electron supply layer 24, and below the region where 2DEG23 is generated. Therefore, 2DEG23 is exposed on the side surface 530b of the third opening 530. By providing the source electrode 34 so as to cover the bottom surface 530a and side surface 530b of the third opening 530, the source electrode 34 and 2DEG23 can be brought into contact. This reduces the contact resistance between the source electrode 34 and 2DEG23.

[0156] In Figure 6, an example is shown where the side surface 530b of the third opening 530 is perpendicular to the bottom surface 530a, but the side surface 530b may be inclined with respect to the bottom surface 530a. Also, the third opening 530 does not necessarily have to penetrate the electron supply layer 24. By making the electron supply layer 24 located between the source electrode 34 and 2DEG23 thinner, the contact resistance can be reduced.

[0157] In this embodiment, the nitride semiconductor device 501 does not necessarily have to have a third opening 530. For example, the contact layer 514 does not need to cover the portion of the side surface 30b of the second opening 30 near the interface between the electron supply layer 24 and the electron transport layer 22. In this case, the source electrode 34 can be brought into contact with the 2DEG 23 exposed on the side surface 30b of the second opening 30. Even without providing the third opening 530, the contact resistance to the 2DEG 23 can be reduced.

[0158] The contact layer 514 and the third opening 530 may be provided in the nitride semiconductor devices 101, 201, 301, and 401 according to embodiments 2 to 5. Furthermore, the intermediate layer 26 of the nitride semiconductor device 501 may have a laminated structure of a GaN layer and an AlGaN layer, similar to the intermediate layer 326 according to embodiment 4.

[0159] (Other embodiments) Although nitride semiconductor devices according to one or more embodiments have been described above based on embodiments, this disclosure is not limited to these embodiments. Without departing from the spirit of this disclosure, various modifications to these embodiments that a person skilled in the art could conceive, as well as forms constructed by combining components from different embodiments, are also included within the scope of this disclosure.

[0160] For example, the intermediate layer 26 or 226 may mainly contain materials other than nitride semiconductors. For example, the intermediate layer 26 or 226 may mainly contain metal oxides such as gallium oxide or nickel oxide. Alternatively, the intermediate layer 26 or 226 may mainly contain insulating materials such as silicon oxide or silicon nitride.

[0161] Furthermore, for example, the second opening 30 may not be provided. In this case, the source electrode 34 is provided on the upper surface 24a of the electron supply layer 24 and is electrically connected to the 2DEG23 via the electron supply layer 24.

[0162] Furthermore, for example, in the nitride semiconductor devices 1, 101, 201, 301, 401, and 501 according to each embodiment, a high-resistance layer with a higher resistance than the block layer 14 may be provided between the drift layer 12 and the block layer 14. The high-resistance layer is, for example, a nitride semiconductor layer mainly composed of carbon-doped GaN (C-GaN). The carbon concentration of the high-resistance layer is, for example, 3 × 10⁻⁶. 17 cm -3 That's all, but 1 × 10 18 cm -3 The above is also acceptable. The high-resistance layer is provided in contact with each of the drift layer 12 and the block layer 14. The high-resistance layer may contain n-type impurities such as Si. The concentration of n-type impurities in the high-resistance layer is lower than the carbon and oxygen concentrations in the high-resistance layer, for example, 5 × 10⁻⁶. 16 cm -3 The following, or 2 × 10 16 cm -3 The following is also possible: By providing a high-resistance layer, punch-through can be suppressed and the breakdown voltage can be increased. When a high-resistance layer is formed, the first opening 20 penetrates the high-resistance layer. As a result, the high-resistance layer is not located in the path of the drain current when the FET is ON, so an increase in ON resistance can be suppressed.

[0163] Furthermore, for example, the drift layer 12 may have a graded structure in which the impurity concentration (donor concentration) is gradually reduced from the substrate 10 side to the block layer 14 side. The donor concentration may be controlled by the donor Si, or by the acceptor carbon that compensates for the Si. Alternatively, the drift layer 12 may have a stacked structure of multiple nitride semiconductor layers with different impurity concentrations. Specifically, the drift layer may be made into two layers, with a layer with a low donor concentration placed below the block layer, and a layer with a high donor concentration placed further below that (i.e., on the substrate side). By providing a first opening 20 so as to penetrate the layer with the low donor concentration, when the transistor is turned on, current flows through the first opening 20 to the layer with the high donor concentration, thus reducing the on-resistance. Conversely, when the transistor is turned off, a high electric field is maintained by the layer with the low donor concentration, thus achieving both low on-resistance and high breakdown voltage.

[0164] Furthermore, the conductivity type of the intermediate layers 26, 226, or 326 may be i-type. The conductivity type of the GaN layer 326A and the AlGaN layer 326B may also be i-type. This makes it possible to suppress the diffusion of p-type impurities from the p-type shielding layer 27 or 127. In other words, the intermediate layers 26, 226, or 326 may contain p-type impurities. Since the spreading of the depletion layer into the channel portion can be suppressed, the decrease in the concentration of 2DEG23 can be suppressed, and the on-resistance can be reduced.

[0165] Furthermore, the intermediate layers 26, 226, or 326 may be provided only in the portion along the inclined side surface 20b of the first opening 20. Specifically, the portion of the intermediate layers 26, 226, or 326 parallel to the main surface of the substrate 10 may not be provided. For example, if the cross-sectional shape of the intermediate layers 26, 226, or 326 is likened to a V shape, the bottom portion of the V shape and the portions extending outward from the two upper ends of the V shape may not be provided.

[0166] Furthermore, for example, the threshold adjustment layer 28 may only contact and cover a portion of the bottom surface of the recess 25. That is, the bottom surface of the recess 25 may have a portion that is not covered by the threshold adjustment layer 28 but is covered by the insulating film 40. For example, the end of the threshold adjustment layer 28 on the source electrode 34 side may be located on the bottom surface of the recess 25. In this case, 2DEG23 does not occur when the device is off in the direction directly below the bottom surface of the recess 25 that is located on the source electrode 34 side of the threshold adjustment layer 28. As a result, the area in which the threshold adjustment layer 28 and 2DEG23, which are electrically connected to the gate electrode 32, face each other becomes smaller, and the gate-source capacitance Cgs can be reduced.

[0167] Furthermore, not only the end of the threshold adjustment layer 28 on the source electrode 34 side, but also the opposite end may be located on the bottom surface of the recess 25. In other words, the threshold adjustment layer 28 may be provided so as not to contact the side surface of the recess 25. In this case as well, the area in which the threshold adjustment layer 28 and 2DEG23 face each other becomes smaller, so the gate-source capacitance Cgs can be reduced.

[0168] Furthermore, the side of the recess portion 25 on the source electrode 34 side does not need to be provided, and the bottom surface of the recess portion 25 may extend to directly below the source electrode 34. In other words, a part of the source electrode 34 may be in contact with and cover a part of the bottom surface of the recess portion 25.

[0169] Furthermore, each of the above embodiments can be modified, replaced, added, or omitted in various ways within the scope of the claims or equivalents thereof. [Industrial applicability]

[0170] The nitride semiconductor devices relating to this disclosure are useful, for example, as power devices used in power supply circuits, inverter circuits, and the like for electrical equipment. [Explanation of symbols]

[0171] 1, 101, 201, 301, 401, 501 Nitride Semiconductor Devices 10 circuit boards 12 Drift Layers 14 block layers 14a, 24a, 424a top 20 First opening 20a, 30a, 530a bottom 20b, 26b, 27b, 30b, 127b, 226b, 326b, 530b side 22 Electron transport layer 23 2DEG 24, 424 electron supply layer 25 Recessed section 26, 226, 326 mezzanine layers 27, 127 shielding layer 28. Threshold adjustment layer 30 Second opening 32 gates 34 Source electrodes 36 Drain electrode 38 Shield electrode 40 insulating film 50 Source Wiring 326A GaN layer 326B AlGaN layer 514 Contact Layer 530 Third opening

Claims

1. circuit board and An n-type first nitride semiconductor layer is provided above the substrate, A p-type second nitride semiconductor layer is provided above the first nitride semiconductor layer, An electron transport layer and an electron supply layer are provided in order from the substrate side so as to cover the inner surface of the first opening that penetrates the second nitride semiconductor layer and reaches the first nitride semiconductor layer and the area above the second nitride semiconductor layer, A p-type third nitride semiconductor layer is provided above the electron supply layer, Between the electron supply layer and the third nitride semiconductor layer, an intermediate layer is provided at a position that overlaps the first opening in a plan view of the substrate, A gate electrode is provided above the electron supply layer, in a position that overlaps the second nitride semiconductor layer but does not overlap the first opening in a plan view of the substrate, A source electrode is provided above the second nitride semiconductor layer, away from the gate electrode, A shielding electrode is provided above the third nitride semiconductor layer, in a position that overlaps the first opening in a plan view of the substrate, and is electrically connected to the source electrode, The substrate comprises a drain electrode provided below the substrate, The side surface of the intermediate layer is covered by the third nitride semiconductor layer. Nitride semiconductor devices.

2. The third nitride semiconductor layer is In a plan view of the substrate, the shielding portion overlaps the first opening and is electrically connected to the shielding electrode, The substrate includes a gate portion that overlaps the upper surface of the second nitride semiconductor layer in a plan view and is electrically connected to the gate electrode, The nitride semiconductor device according to claim 1.

3. The side surface of the intermediate layer is covered by the shielding portion. The nitride semiconductor device according to claim 2.

4. The end of the shielding portion on the source electrode side overlaps the upper surface of the second nitride semiconductor layer in a plan view of the substrate. The nitride semiconductor device according to claim 3.

5. The end of the shielding portion on the source electrode side overlaps the inclined surface of the first opening in a plan view of the substrate. The nitride semiconductor device according to claim 3.

6. The side surface of the intermediate layer is covered by the gate portion. The nitride semiconductor device according to claim 2.

7. The aforementioned intermediate layer includes a GaN layer mainly composed of GaN, and an AlGaN layer mainly composed of AlGaN, provided above the GaN layer. The nitride semiconductor device according to claim 6.

8. The Al composition ratio of the AlGaN layer is 10% or more. The nitride semiconductor device according to claim 7.

9. The electron supply layer comprises Al, The Al composition ratio of the electron supply layer is 10% or more. A nitride semiconductor device according to any one of claims 1 to 8.

10. The electron supply layer is provided with a recess portion at a position that overlaps with the upper surface of the second nitride semiconductor layer in a plan view of the substrate. The gate portion is provided in contact with at least a part of the bottom surface of the recess portion. A nitride semiconductor device according to any one of claims 2 to 8.

11. The upper surface of the electron supply layer is a flat surface between the source electrode and the shielding portion, and within the range that overlaps with the upper surface of the second nitride semiconductor layer in a plan view of the substrate. A nitride semiconductor device according to any one of claims 2 to 8.

12. The source electrode is electrically connected to the second nitride semiconductor layer via a second opening that penetrates the electron supply layer and the electron transport layer and reaches the second nitride semiconductor layer. A nitride semiconductor device according to any one of claims 1 to 8.

13. The second opening is provided with a p-type fourth nitride semiconductor layer that is in contact with the second nitride semiconductor layer, The source electrode is in contact with the fourth nitride semiconductor layer. The nitride semiconductor device according to claim 12.

14. The aforementioned intermediate layer mainly contains a nitride semiconductor. A nitride semiconductor device according to any one of claims 1 to 6.

15. The conductivity type of the intermediate layer is n-type. A nitride semiconductor device according to any one of claims 1 to 6.

16. The carrier concentration in the intermediate layer is 2 × 10 １７ cm －３ That's all. The nitride semiconductor device according to claim 15.

17. The conductivity type of the intermediate layer is i-type. A nitride semiconductor device according to any one of claims 1 to 6.

18. The aforementioned intermediate layer contains p-type impurities. The nitride semiconductor device according to claim 17.

19. The thickness of the intermediate layer is between 20 nm and 500 nm. A nitride semiconductor device according to any one of claims 1 to 6.

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