Nitride semiconductor devices

Abstract

Reduce on-resistance. [Solution] The nitride semiconductor device 1 comprises a substrate 10, an electron transport layer 22 provided above the substrate 10, an electron supply layer 24 provided above the electron transport layer 22 and having a larger band gap than the electron transport layer 22, a p-type semiconductor layer 28 provided above the electron supply layer 24, a gate electrode 32 provided above the p-type semiconductor layer 28, a source electrode 34 provided above the substrate 10 and electrically connected to the electron transport layer 22, and an intermediate layer 26 provided between the electron supply layer 24 and the p-type semiconductor layer 28. The p-type semiconductor layer 28 includes an overlapping portion 28A that overlaps with the intermediate layer 26 in a plan view of the substrate 10, and a non-overlapping portion 28B that does not overlap with the intermediate layer 26 in a plan view of the substrate 10. The shortest distance between the non-overlapping portion 28B and the source electrode 34 is shorter than the shortest distance between the overlapping portion 28A and the source electrode 34. The gate electrode 32 is electrically connected to the non-overlapping portion 28B.

Description

[Technical Field]

[0001] This disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a nitride semiconductor device that includes a two-dimensional electron gas (2DEG) as a channel. In the nitride semiconductor device disclosed in Patent Document 1, a p-type semiconductor layer is provided directly beneath the gate electrode. The p-type semiconductor layer raises the potential at the conduction band edge of the channel portion, increasing the threshold and enabling normally-off operation of the transistor. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 6511645 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, the conventional nitride semiconductor devices described above have a problem in that the concentration of 2DEG decreases due to the depletion layer extending from the p-type semiconductor layer, which increases the on-resistance.

[0005] Therefore, this disclosure provides a nitride semiconductor device that can reduce on-resistance. [Means for solving the problem]

[0006] A nitride semiconductor device according to one aspect of the present disclosure includes a substrate, a first nitride semiconductor layer provided above the substrate, a second nitride semiconductor layer provided above the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer, a p-type third nitride semiconductor layer provided above the second nitride semiconductor layer, a first electrode provided above the third nitride semiconductor layer, a second electrode provided above the substrate and electrically connected to the first nitride semiconductor layer, and an intermediate layer provided between the second nitride semiconductor layer and the third nitride semiconductor layer, wherein the third nitride semiconductor layer includes an overlapping portion overlapping the intermediate layer in a plan view of the substrate, and a non-overlapping portion not overlapping the intermediate layer in a plan view of the substrate, the shortest distance between the non-overlapping portion and the second electrode is shorter than the shortest distance between the overlapping portion and the second electrode, and the first electrode is electrically connected to the non-overlapping portion. Effects of the Invention

[0007] According to the present disclosure, on-resistance can be reduced. Brief Description of the Drawings

[0008] [Figure 1] Figure 1 is a cross-sectional view of the nitride semiconductor device according to Embodiment 1. [Figure 2] Figure 2 is a cross-sectional view of the nitride semiconductor device according to Embodiment 2. [Figure 3] Figure 3 is a cross-sectional view of the nitride semiconductor device according to Embodiment 3. [Figure 4] Figure 4 is a cross-sectional view of the nitride semiconductor device according to Embodiment 4. [Figure 5] Figure 5 is a cross-sectional view of the nitride semiconductor device according to Modification 1 of Embodiment 4. [Figure 6] Figure 6 is a cross-sectional view of the nitride semiconductor device according to Modification 2 of Embodiment 4. [Figure 7] Figure 7 is a cross-sectional view of the nitride semiconductor device according to Modification 3 of Embodiment 4. [Figure 8]Figure 8 is a cross-sectional view of a nitride semiconductor device according to Embodiment 5. [Figure 9] Figure 9 is a cross-sectional view of a nitride semiconductor device according to Embodiment 6. [Figure 10] Figure 10 is a cross-sectional view of a nitride semiconductor device according to Embodiment 7. [Modes for carrying out the invention]

[0009] (Summary of this disclosure) A nitride semiconductor device according to a first aspect of the present disclosure comprises a substrate, a first nitride semiconductor layer provided above the substrate, a second nitride semiconductor layer provided above the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer, a p-type third nitride semiconductor layer provided above the second nitride semiconductor layer, a first electrode provided above the third nitride semiconductor layer, a second electrode provided above the substrate and electrically connected to the first nitride semiconductor layer, and an intermediate layer provided between the second nitride semiconductor layer and the third nitride semiconductor layer, wherein the third nitride semiconductor layer includes an overlapping portion that overlaps the intermediate layer in a plan view of the substrate and a non-overlapping portion that does not overlap the intermediate layer in a plan view of the substrate, the shortest distance between the non-overlapping portion and the second electrode is shorter than the shortest distance between the overlapping portion and the second electrode, and the first electrode is electrically connected to the non-overlapping portion.

[0010] As a result, a 2DEG is generated near the interface between the first and second nitride semiconductor layers, which can be utilized as a channel. In the region that overlaps with the non-overlapping portion of the p-type third nitride semiconductor layer in a plan view, the potential at the conduction band edge of the channel can be increased. Therefore, the nitride semiconductor device can be operated as a normally-off transistor. Furthermore, in the region that overlaps with the overlapping portion of the third nitride semiconductor layer in a plan view, the influence of the third nitride semiconductor layer on the channel can be suppressed by the intermediate layer. The decrease in the concentration of 2DEG can be suppressed, and the on-resistance can be reduced.

[0011] A nitride semiconductor device according to a second aspect of the present disclosure is a nitride semiconductor device according to a first aspect, comprising: an n-type fourth nitride semiconductor layer provided above the substrate; a p-type fifth nitride semiconductor layer provided above the fourth nitride semiconductor layer; and a drain electrode provided below the substrate, wherein the first electrode is a gate electrode and the second electrode is a source electrode, and the first nitride semiconductor layer and the second nitride semiconductor layer are provided so as to cover the inner surface of a first opening that penetrates the fifth nitride semiconductor layer and reaches the fourth nitride semiconductor layer, and the area above the fifth nitride semiconductor layer, and the intermediate layer is provided in a position that overlaps the first opening in a plan view of the substrate.

[0012] This makes it possible to create vertical transistors with high voltage resistance.

[0013] A nitride semiconductor device according to a third aspect of the present disclosure is a nitride semiconductor device according to a second aspect, wherein the first electrode is provided at a position overlapping the first opening in a plan view of the substrate, and the non-overlapping portion is provided continuously from the overlapping portion.

[0014] As a result, the magnitude of the transistor's threshold can be determined by the sloped portion along the side of the first aperture and the flat portion outside the first aperture. Typically, the side of the first aperture is a semi-polar surface, so the concentration of 2DEG tends to be lower compared to the polar surface of the flat portion, and the threshold tends to be higher in the sloped portion compared to the flat portion. By providing an intermediate layer that overlaps the first aperture, the decrease in the concentration of 2DEG in the sloped portion can be suppressed, and the threshold can be lowered. In other words, the difference in threshold between the sloped portion and the flat portion can be reduced, improving the controllability of the transistor's on and off states.

[0015] A nitride semiconductor device according to a fourth aspect of this disclosure is a nitride semiconductor device according to a second aspect, comprising a third electrode provided above the third nitride semiconductor layer at a position overlapping the first opening in a plan view of the substrate and electrically connected to the second electrode, wherein the first electrode is provided at a position overlapping the fifth nitride semiconductor layer without overlapping the first opening in a plan view of the substrate.

[0016] This allows the transistor's threshold voltage to be determined by the flat area outside the first aperture, eliminating the influence of the sloped area. Therefore, the controllability of the transistor's on / off state can be improved. Furthermore, by providing a third electrode electrically connected to the source electrode, the electric field lines extending from the drain electrode can be terminated by the third electrode. This reduces parasitic capacitance between the gate and drain, enabling faster switching.

[0017] A nitride semiconductor device according to a fifth aspect of this disclosure is a nitride semiconductor device according to a fourth aspect, wherein the third electrode is electrically connected to the overlapping portion, and the non-overlapping portion is provided spaced apart from the overlapping portion.

[0018] This allows a reverse bias to be applied to the pn junction between the p-type overlap and 2DEG via the third electrode and the drain electrode. Therefore, the breakdown voltage of the vertical transistor can be increased.

[0019] A nitride semiconductor device according to a sixth aspect of this disclosure is a nitride semiconductor device according to any one of the second to fifth aspects, wherein the non-overlapping portion overlaps the upper surface of the fifth nitride semiconductor layer in a plan view of the substrate.

[0020] As a result, variations in the thickness of the non-overlapping portion and the second nitride semiconductor layer are suppressed in the area overlapping the upper surface of the fifth nitride semiconductor layer in a plan view, thereby stabilizing the transistor threshold.

[0021] A nitride semiconductor device according to a seventh aspect of the present disclosure is a nitride semiconductor device according to any one of the second to sixth aspects, wherein the second nitride semiconductor layer is provided with a recess portion at a position that overlaps the upper surface of the fifth nitride semiconductor layer in a plan view of the substrate, and the non-overlapping portion is provided in contact with at least a part of the bottom surface of the recess portion.

[0022] This allows the transistor threshold to be adjusted by the depth of the recess. For example, it can be easily implemented as a normally-off transistor. Furthermore, it becomes possible to increase the thickness of the second nitride semiconductor layer in areas other than the recess, allowing for a higher concentration of 2DEG in the thickened areas. Therefore, it is possible to achieve both normally-off operation and reduced on-resistance.

[0023] A nitride semiconductor device according to the eighth aspect of this disclosure is a nitride semiconductor device according to the seventh aspect, wherein the end of the non-overlapping portion on the second electrode side is located on the bottom surface of the recess portion.

[0024] This prevents the generation of 2DEG in the region directly below the recess when the device is off. Since the source electrode end of the non-overlapping portion electrically connected to the gate electrode is located on the bottom surface of the recess, the area where the non-overlapping portion and 2DEG face each other is reduced. Therefore, the parasitic capacitance between the gate and source can be reduced.

[0025] A nitride semiconductor device according to the ninth aspect of the present disclosure is a nitride semiconductor device according to any one of the fourth to eighth aspects, wherein the second nitride semiconductor layer is provided with a recess portion at a position that overlaps with the upper surface of the fifth nitride semiconductor layer in a plan view of the substrate, and the end of the non-overlapping portion on the second electrode side and the end on the opposite side from the second electrode side are located on the bottom surface of the recess portion.

[0026] This further reduces the parasitic capacitance between the gate and source.

[0027] A nitride semiconductor device according to a tenth aspect of the present disclosure is a nitride semiconductor device according to any one of the second to ninth aspects, wherein the second electrode is electrically connected to the fifth nitride semiconductor layer via a second opening that penetrates the second nitride semiconductor layer and the first nitride semiconductor layer and reaches the fifth nitride semiconductor layer.

[0028] This allows a reverse bias to be applied to the pn junction between the p-type fifth nitride semiconductor layer and the n-type fourth nitride semiconductor layer via the source and drain electrodes. Therefore, the breakdown voltage of the vertical transistor can be increased.

[0029] A nitride semiconductor device according to an eleventh aspect of the present disclosure is a nitride semiconductor device according to a tenth aspect, comprising a p-type sixth nitride semiconductor layer provided in contact with the fifth nitride semiconductor layer within the second opening, and the second electrode is in contact with the sixth nitride semiconductor layer.

[0030] Since etching damage can occur in the fifth nitride semiconductor layer when forming the second aperture, good contact may not be obtained and contact resistance may increase when the fifth nitride semiconductor layer and the source electrode are brought into contact. In contrast, according to this embodiment, the source electrode and the fifth nitride semiconductor layer are electrically connected via the sixth nitride semiconductor layer, so contact resistance can be reduced.

[0031] A nitride semiconductor device according to a twelfth aspect of the present disclosure is a nitride semiconductor device according to any one of the second to eleventh aspects, wherein the intermediate layer does not overlap at least a portion of the bottom surface of the first opening in a plan view of the substrate.

[0032] As a result, there is a portion where no intermediate layer is provided in the area overlapping the bottom surface of the first aperture in a plan view, so the electric field concentration when a reverse bias is applied between the drain and source can be mitigated by the p-type third nitride semiconductor layer.

[0033] A nitride semiconductor device according to the 13th aspect of this disclosure is a nitride semiconductor device according to any one of the 1st to 12th aspects, wherein the intermediate layer mainly comprises a nitride semiconductor.

[0034] This allows for the continuous formation of the second nitride semiconductor layer and the intermediate layer by epitaxial growth. Since defect levels are less likely to form at the interface, the operation of the transistor can be stabilized.

[0035] A nitride semiconductor device according to a fourteenth aspect of this disclosure is a nitride semiconductor device according to any one of the first to thirteenth aspects, wherein the conductivity type of the intermediate layer is n-type.

[0036] This allows the n-type intermediate layer to push down the potential at the conduction band edge of the channel, which is lifted by the p-type third nitride semiconductor layer. Therefore, the decrease in the concentration of 2DEG can be suppressed, and the on-resistance can be reduced. In addition, the n-type intermediate layer can suppress the diffusion of p-type impurities from the p-type third nitride semiconductor layer. The n-type intermediate layer can counteract the p-type conversion caused by p-type impurities, and the expansion of the depletion region is suppressed. Therefore, the decrease in the concentration of 2DEG can be suppressed, and the on-resistance can be reduced.

[0037] A nitride semiconductor device according to the 15th aspect of this disclosure is a nitride semiconductor device according to any one of the 1st to 13th aspects, wherein the conductivity type of the intermediate layer is i-type.

[0038] This allows the i-type intermediate layer to suppress the diffusion of p-type impurities from the p-type third nitride semiconductor layer. Since the expansion of the depletion region associated with the expansion of the p-type region is suppressed, the decrease in the concentration of 2DEG can be suppressed, and the on-resistance can be reduced.

[0039] A nitride semiconductor device according to the sixteenth aspect of this disclosure is a nitride semiconductor device according to the fifteenth aspect, wherein the intermediate layer contains a p-type impurity.

[0040] This allows the i-type intermediate layer to suppress the diffusion of p-type impurities.

[0041] A nitride semiconductor device according to the 17th aspect of this disclosure is a nitride semiconductor device according to any one of the 1st to 16th aspects, wherein the thickness of the intermediate layer is 22 nm or more and 150 nm or less.

[0042] This effectively suppresses the diffusion of p-type impurities.

[0043] The embodiments will be described in detail below with reference to the drawings.

[0044] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. Furthermore, any components in the following embodiments that are not described in an independent claim will be described as optional components.

[0045] Furthermore, each figure is a schematic diagram and not necessarily a strictly accurate representation. Therefore, for example, the scale may not necessarily match in each figure. Also, in each figure, substantially identical components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0046] Furthermore, in this specification, terms indicating relationships between elements such as parallel and orthogonal, terms indicating the shape of elements such as rectangles, and numerical ranges do not represent only strict meanings, but also include substantially equivalent ranges, such as differences of a few percent.

[0047] Furthermore, in this specification, the "thickness direction" of a substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layer and is also referred to as the "vertical direction." In addition, the direction parallel to the main surface of the substrate may be referred to as the "horizontal direction." A "vertical" semiconductor device means a device in which the main path of current, such as drain current or forward current, is in the vertical direction, that is, a device in which the main current passes through the substrate in the vertical direction. A "horizontal" semiconductor device means a device in which the main path of current, such as drain current or forward current, is in the horizontal direction, that is, a device in which the main current does not pass through the substrate.

[0048] Furthermore, the side of the substrate on which the heterostructure generating 2DEG is provided is considered the "upper" or "upper side," and the opposite side is considered the "lower" or "lower side." In this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather are used as terms defined by the relative positional relationship based on the stacking order in the stacked configuration. Moreover, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close contact with each other and are in touch.

[0049] Furthermore, in this specification, unless otherwise specified, "plan view" refers to a view of the semiconductor device substrate from a direction perpendicular to the main surface, that is, a view of the main surface of the substrate from the front.

[0050] Furthermore, in this specification, "A and B overlap in a plan view" means that at least a part of A and at least a part of B overlap. That is, this includes cases where only a part of A and only a part of B overlap, where all of A overlaps with B, where all of B overlaps with A, where A and B completely overlap each other, and so on.

[0051] Furthermore, n-type and p-type represent the conductivity types of semiconductors, and they are conductivity types with opposite polarities. +type represents a state in which an n-type dopant is added to a semiconductor at a high concentration, so-called heavy doping. Also, n - -type represents a state in which an n-type dopant is added to a semiconductor at a low concentration, so-called light doping. n + type and n - type are both examples of n-type, and there are cases where they are described as n-type without distinguishing between them. Also, p-type, p + -type and p - -type are the same.

[0052] Also, in the present specification, the "main component" means the component having the highest content ratio among all components constituting a member. For example, a component having a content ratio of 50% or more is a main component. The component is a material, an element, a compound, or the like.

[0053] Also, in the present specification, AlGaN refers to the ternary mixed crystal Al x Ga 1-x N (0<x<1). Hereinafter, multi-component mixed crystals are abbreviated by an array of their respective constituent element symbols, for example, AlInN, GaInN, or the like. For example, Al x Ga 1-x-y In y N (0<x<1, 0<y<1, and 0<x+y<1), which is an example of a nitride semiconductor, is abbreviated as AlGaInN. x, 1-x-y, and y each represent the composition ratio of Al, Ga, and In, respectively.

[0054] Also, in the present specification, ordinal numbers such as "first" and "second" do not mean the number or order of constituent elements unless otherwise specified, and are used for the purpose of avoiding confusion between and distinguishing between constituent elements of the same type.

[0055] (Embodiment 1) First, the configuration of a nitride semiconductor device according to Embodiment 1 will be described with reference to FIG. 1.

[0056] Figure 1 is a cross-sectional view of the nitride semiconductor device 1 according to this embodiment. In Figure 1, each component of the nitride semiconductor device 1, such as the semiconductor layer, insulating layer, and electrodes, is shaded with diagonal lines to represent its cross-section. However, the diagonal shading representing the cross-section of the electron transport layer 22 is omitted. The same applies to the other cross-sectional views from Figure 2 onward.

[0057] The nitride semiconductor device 1 shown in Figure 1 is a normally-off vertical FET (Field Effect Transistor). In the nitride semiconductor device 1, for example, the source electrode 34 is grounded and a positive potential is applied to the drain electrode 36. The potential applied to the drain electrode 36 is, for example, between 100V and 1200V, but is not limited to this. The nitride semiconductor device 1 performs modulation operation according to the potential applied to the gate electrode 32. For example, when 0V or a negative potential (for example, -5V) is applied to the gate electrode 32, no current flows between the drain electrode 36 and the source electrode 34. That is, the nitride semiconductor device 1 becomes non-conductive (off). When a positive potential (for example, +5V) is applied to the gate electrode 32, current flows from the drain electrode 36 to the source electrode 34. That is, the nitride semiconductor device 1 becomes conductive (on). The current that flows from the drain electrode 36 to the source electrode 34 when it is ON is called the drain current. The drain current flows through the substrate 10 in the direction of its thickness (i.e., the longitudinal direction).

[0058] As shown in Figure 1, the nitride semiconductor device 1 comprises a substrate 10, a drift layer 12, a block layer 14, an electron transport layer 22, an electron supply layer 24, an intermediate layer 26, a p-type semiconductor layer 28, a gate electrode 32, a source electrode 34, and a drain electrode 36. Furthermore, the nitride semiconductor device 1 comprises an insulating film 40 and a source wiring 50. The nitride semiconductor device 1 is also provided with a first opening 20 and a second opening 30.

[0059] Nitride semiconductor device 1 is a device in which the semiconductor layers containing the channel mainly consist of nitride semiconductor. Specifically, the drift layer 12, the block layer 14, the electron transport layer 22, the electron supply layer 24, the intermediate layer 26, and the p-type semiconductor layer 28 each mainly consist of nitride semiconductor.

[0060] The following describes the details of each component of the nitride semiconductor device 1.

[0061] The substrate 10 has, for example, a thickness of 300 μm and a carrier concentration of 5 × 10 18 cm -3 n + This is a substrate containing GaN of a specific type as its main component.

[0062] Note that the substrate 10 does not have to be a nitride semiconductor substrate. For example, the substrate 10 may be a Si substrate, a SiC substrate, or a ZnO substrate.

[0063] The drift layer 12 is an example of an n-type fourth nitride semiconductor layer and is provided above the substrate 10. The drift layer 12 is, for example, an n-type with a thickness of 8 μm. - This film mainly contains GaN of type 10. The donor concentration of the drift layer 12 is, for example, 1 × 10⁻⁶. 15 cm -3 The above 1 x 10 17 cm -3 The following is an example: 1 × 10 16 cm -3 Furthermore, the carbon concentration (C concentration) of the drift layer 12 is, for example, 1 × 10⁻⁶. 15 cm -3 The above 5 x 10 16 cm -3 The drift layer 12 is provided, for example, in contact with the upper surface (main surface) of the substrate 10.

[0064] The block layer 14 is an example of a p-type fifth nitride semiconductor layer and is provided above the drift layer 12. The block layer 14 has, for example, a thickness of 400 nm and a carrier concentration of 1 × 10⁻¹⁶ 17 cm -3This film mainly contains p-type GaN. The block layer 14 is provided in contact with the upper surface of the drift layer 12.

[0065] The block layer 14 is provided with a first opening 20. The first opening 20 penetrates the block layer 14 and reaches the drift layer 12. The first opening 20 is sometimes called a gate opening or a longitudinal conduction opening. The bottom surface 20a of the first opening 20 is part of the top surface of the drift layer 12. As shown in Figure 1, the bottom surface 20a is located below the bottom surface of the block layer 14. The bottom surface of the block layer 14 corresponds to the interface between the block layer 14 and the drift layer 12. The bottom surface 20a is, for example, parallel to the main surface of the substrate 10. When the nitride semiconductor device 1 is turned on, the drain current flows between the drain electrode 36 and the source electrode 34 through the bottom surface 20a of the first opening 20.

[0066] In this embodiment, the first opening 20 is formed such that its opening area increases as it moves away from the substrate 10. Specifically, the side surface 20b of the first opening 20 is inclined at an angle. As shown in Figure 1, the cross-sectional shape of the first opening 20 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid.

[0067] The inclination angle of the side surface 20b with respect to the bottom surface 20a is, for example, 20° to 80°, but may also be 30° to 45°. The smaller the inclination angle, the closer the side surface 20b is to the c-plane, which allows for an improvement in the film quality of the electron transport layer 22 and other layers formed along the side surface 20b by crystal regrowth. On the other hand, the larger the inclination angle, the less the first opening 20 becomes, thus enabling miniaturization of the nitride semiconductor device 1. The side surface 20b may also be perpendicular to the bottom surface 20a.

[0068] The electron transport layer 22 is an example of a first nitride semiconductor layer and is provided above the substrate 10. Specifically, the electron transport layer 22 is also an example of a first regrowth layer and is provided so as to cover the inner surface of the first opening 20 and the top of the block layer 14. For example, a part of the electron transport layer 22 is provided along the bottom surface 20a and side surface 20b of the first opening 20, and another part of the electron transport layer 22 is provided on the top surface 14a of the block layer 14. The thickness of the electron transport layer 22 is, for example, 50 nm to 500 nm. The electron transport layer 22 is, for example, a film mainly composed of undoped GaN with a thickness of 150 nm. The thickness of the electron transport layer 22 is considered to be the thickness in the flat portion that overlaps with the top surface 14a of the block layer 14, on the outside of the first opening 20 in a plan view of the substrate 10. In addition, although the electron transport layer 22 is assumed to be undoped, it may be partially Si-doped to make it n-type.

[0069] The electron transport layer 22 is in contact with the drift layer 12 at the bottom surface 20a and side surface 20b of the first opening 20. Furthermore, the electron transport layer 22 is in contact with the block layer 14 at the side surface 20b of the first opening 20. Specifically, the electron transport layer 22 is in contact with the top surface 14a of the block layer 14.

[0070] The electron transport layer 22 has a channel. Specifically, a channel 2DEG25 is generated near the interface between the electron transport layer 22 and the electron supply layer 24. The 2DEG25 is bent along the interface between the electron transport layer 22 and the electron supply layer 24, that is, along the inner surface of the first opening 20.

[0071] Although not shown in Figure 1, an AlN layer with a thickness of approximately 1 nm is provided as a second regrowth layer between the electron transport layer 22 and the electron supply layer 24. This suppresses alloy scattering, improves channel mobility, and reduces on-resistance. Note that the AlN layer is not strictly necessary.

[0072] The electron supply layer 24 is an example of a second nitride semiconductor layer and is provided above the electron transport layer 22. Specifically, the electron supply layer 24 is also an example of a third regrowth layer and is provided so as to cover the inner surface of the first opening 20 and the top of the block layer 14. Specifically, the electron supply layer 24 is provided along the top surface of the electron transport layer 22 so as to overlap the bottom surface 20a and side surface 20b of the first opening 20 and the top surface 14a of the block layer 14 in a plan view of the substrate 10.

[0073] The electron supply layer 24 has a larger band gap than the electron transport layer 22. Therefore, an AlGaN / GaN heterointerface is formed between the electron supply layer 24 and the electron transport layer 22. The electron supply layer 24 supplies electrons to the channel (2DEG25) formed in the electron transport layer 22.

[0074] The electron supply layer 24 is, for example, a film mainly composed of undoped AlGaN with a thickness of 22 nm. The electron supply layer 24 is formed with a nearly uniform thickness in a shape that follows the upper surface of the electron transport layer 22. The thickness of the electron supply layer 24 is considered to be the thickness in the flat portion that overlaps with the upper surface 14a of the block layer 14, on the outside of the first opening 20 in a plan view of the substrate 10.

[0075] Furthermore, if the electron supply layer 24 mainly consists of AlGaN with an Al composition ratio of 20%, cracks are more likely to occur if the thickness of the electron supply layer 24 exceeds 70 nm. This can lead to deterioration of the film quality of the electron supply layer 24, causing leakage or making it impossible to generate 2DEG25 at the desired concentration. By lowering the Al composition ratio, crack formation can be suppressed, so the thickness of the electron supply layer 24 is, for example, between 10 nm and 150 nm. The Al composition ratio of the electron supply layer 24 is not particularly limited, but is, for example, between 10% and 30%.

[0076] The intermediate layer 26 is provided between the electron supply layer 24 and the p-type semiconductor layer 28. Specifically, the intermediate layer 26 is provided in contact with the upper surface 24a of the electron supply layer 24 and the lower surface of the p-type semiconductor layer 28. In this embodiment, the side surface of the intermediate layer 26 is in contact with and covers the p-type semiconductor layer 28. In a plan view of the substrate 10, the intermediate layer 26 is provided in a position that overlaps the first opening 20. Specifically, in a plan view of the substrate 10, the intermediate layer 26 is provided in a position that overlaps the bottom surface 20a and the side surface 20b of the first opening 20. A part of the intermediate layer 26 may overlap the outside of the first opening 20 in a plan view of the substrate 10, i.e., the upper surface 14a of the block layer 14. The end of the intermediate layer 26 on the source electrode 34 side may overlap the upper surface 14a of the block layer 14 in a plan view of the substrate 10, or it may overlap the inclined side surface of the block layer 14. The intermediate layer 26 is formed with a nearly uniform thickness and in a shape that follows the upper surface 24a of the electron supply layer 24.

[0077] The intermediate layer 26 mainly contains a nitride semiconductor. In this embodiment, the conductivity type of the intermediate layer 26 is n-type. Specifically, the intermediate layer 26 is a film mainly containing n-type GaN. The carrier concentration of the intermediate layer 26 is, for example, 2 × 10⁻⁶. 17 cm -3 That's all. This allows us to increase the concentration of 2DEG25. Also, the carrier concentration in the intermediate layer 26 can be, for example, 1 × 10⁻⁶. 20 cm -3 The following may also apply: The concentration of 2DEG25 is such that the carrier concentration in the intermediate layer 26 is 5 × 10 18 cm -3 The range described above is generally saturated.

[0078] The film thickness of the intermediate layer 26 is, for example, between 22 nm and 150 nm. The concentration of 2DEG25 increases sharply when the film thickness of the intermediate layer 26 is between 22 nm and 50 nm, resulting in a high reduction in on-resistance. On the other hand, the concentration of 2DEG25 is generally saturated when the film thickness of the intermediate layer 26 is between 100 nm and 150 nm. Therefore, it is possible to suppress the intermediate layer 26 from becoming excessively thick, and to suppress the occurrence of step breaks in the p-type semiconductor layer 28 and gate electrode 32 formed above it. In addition, the time required for deposition of the intermediate layer 26 can be shortened.

[0079] The p-type semiconductor layer 28 is an example of a p-type third nitride semiconductor layer and is provided above the electron supply layer 24. As shown in Figure 1, the p-type semiconductor layer 28 includes an overlapping portion 28A and a non-overlapping portion 28B. In this embodiment, the non-overlapping portion 28B is provided continuously from the overlapping portion 28A.

[0080] The overlapping portion 28A is the part that overlaps the intermediate layer 26 in a plan view of the substrate 10. The plan view shape and size of the overlapping portion 28A are the same as those of the intermediate layer 26. The overlapping portion 28A is provided in contact with the upper surface of the intermediate layer 26 and the lower surface of the gate electrode 32.

[0081] The non-overlapping portion 28B is the portion of the substrate 10 that does not overlap with the intermediate layer 26 in a plan view. The non-overlapping portion 28B is provided in contact with the upper surface 24a of the electron supply layer 24 and the lower surface of the gate electrode 32. Note that the upper surface of the non-overlapping portion 28B does not necessarily have to be in contact with the gate electrode 32.

[0082] The p-type semiconductor layer 28 has, for example, a thickness of 50 nm and a carrier concentration of 5 × 10⁻¹⁶ 17 cm -3The film mainly contains p-type GaN. The thickness of the p-type semiconductor layer 28 is, for example, 5 nm to 500 nm. Note that the thickness and carrier concentration of the p-type semiconductor layer 28 are merely examples and can be changed as appropriate. For example, the p-type semiconductor layer 28 may be a film mainly containing p-type AlGaN. The overlapping portion 28A and the non-overlapping portion 28B may differ from each other in at least one of their thickness, composition, and carrier concentration.

[0083] As shown in Figure 1, the shortest distance D2 between the non-overlapping portion 28B and the source electrode 34 is shorter than the shortest distance D1 between the overlapping portion 28A and the source electrode 34. Both the shortest distances D1 and D2 are distances in the gate length direction. The gate length direction is the direction in which the gate electrode 32 and the source electrode 34 are aligned, and in the example shown in Figure 1, it is the left-right direction on the plane of the paper. The non-overlapping portion 28B is located between the overlapping portion 28A and the source electrode 34. In this embodiment, the non-overlapping portion 28B is the portion of the p-type semiconductor layer 28 that protrudes from the intermediate layer 26 toward the source electrode 34 in a plan view.

[0084] The second opening 30 penetrates the electron supply layer 24 and the electron transport layer 22 and reaches the block layer 14. The second opening 30 is sometimes called the source opening. In a plan view of the substrate 10, the second opening 30 is located away from both the gate electrode 32 and the p-type semiconductor layer 28. Since the second opening 30 penetrates the electron transport layer 22, the 2DEG 25 is exposed on the side surface 30b of the second opening 30. The second opening 30 and the source electrode 34 are located on both sides of the outside of the first opening 20 in the cross-sectional view shown in Figure 1.

[0085] The bottom surface 30a of the second opening 30 is part of the top surface 14a of the block layer 14. The bottom surface 30a is parallel to the main surface of the substrate 10, for example. In the example shown in Figure 1, the bottom surface 30a is located below the bottom surface of the electron transport layer 22. The bottom surface of the electron transport layer 22 corresponds to the interface between the electron transport layer 22 and the block layer 14.

[0086] Furthermore, as shown in Figure 1, the second opening 30 is formed such that its opening area increases as it moves away from the substrate 10. Specifically, the side surface 30b of the second opening 30 is inclined at an angle. In this case, the inclination angle of the side surface 30b with respect to the bottom surface 30a is, for example, in the range of 30° to 60°. The inclination of the side surface 30b increases the contact area between the source electrode 34 and the 2DEG 25, making ohmic connection easier. The 2DEG 25 is exposed on the side surface 30b of the second opening 30 and is connected to the source electrode 34 at the exposed portion. The side surface 30b may also be perpendicular to the bottom surface 30a.

[0087] The provision of the second opening 30 reduces the ohmic contact resistance between the channel-functioning 2DEG25 and the source electrode 34. In other words, it reduces the on-resistance of the nitride semiconductor device 1.

[0088] Furthermore, the source electrode 34 and the block layer 14 are electrically connected at the bottom surface 30a of the second opening 30. As a result, the same potential as the potential applied to the source electrode 34 is supplied to the block layer 14. When a reverse voltage is applied to the pn junction formed by the block layer 14 and the drift layer 12, specifically when the drain electrode 36 becomes at a higher potential than the source electrode 34, a depletion layer extends in the drift layer 12, making it possible to increase the breakdown voltage of the nitride semiconductor device 1.

[0089] The gate electrode 32 is an example of a first electrode and is provided above the p-type semiconductor layer 28. Specifically, the gate electrode 32 is provided in contact with the upper surface of the overlapping portion 28A and the upper surface of the non-overlapping portion 28B of the p-type semiconductor layer 28. The gate electrode 32 is electrically connected to the non-overlapping portion 28B. In this embodiment, since the overlapping portion 28A and the non-overlapping portion 28B are continuous, the gate electrode 32 is also electrically connected to the overlapping portion 28A. The gate electrode 32 only needs to be in contact with at least one of the overlapping portion 28A and the non-overlapping portion 28B.

[0090] The gate electrode 32 is positioned to overlap the first opening 20 in a plan view of the substrate 10. Specifically, the gate electrode 32 overlaps the bottom surface 20a and the side surface 20b of the first opening 20 in a plan view of the substrate 10. The gate electrode 32 is spaced apart from the source electrode 34 and is electrically isolated from it.

[0091] The gate electrode 32 is formed using a conductive material such as a metal. For example, the gate electrode 32 can be made of a material that is ohmic-connected to a p-type nitride semiconductor such as p-type GaN, but is not limited to this, and a material that is Schottky-connected to a p-type nitride semiconductor may also be used. For example, Pd, Ni-based materials, WSi, Au, etc. can be used as the material for forming the gate electrode 32.

[0092] The source electrode 34 is an example of a second electrode and is provided above the substrate 10. In this embodiment, the source electrode 34 is electrically connected to the block layer 14 via the second opening 30. The source electrode 34 is also electrically connected to the electron transport layer 22 via the second opening 30. Specifically, the source electrode 34 is provided in contact with the bottom surface 30a and the side surface 30b of the second opening 30. The source electrode 34 is in contact with the block layer 14 at the bottom surface 30a of the second opening 30. The source electrode 34 is in contact with 2DEG25 at the side surface 30b of the second opening 30. This reduces the contact resistance between the source electrode 34 and 2DEG25, thereby reducing the on-resistance of the nitride semiconductor device 1.

[0093] The source electrode 34 is formed using a conductive material such as a metal. As the material for the source electrode 34, for example, a material that can be ohmic connected to an n-type nitride semiconductor such as n-type GaN by heat treatment can be used, such as Ti / Al (a stacked structure of a Ti layer and an Al layer).

[0094] The drain electrode 36 is located below the substrate 10. Specifically, the drain electrode 36 is located in contact with the lower surface of the substrate 10.

[0095] The drain electrode 36 is formed using a conductive material such as a metal. Similar to the material of the source electrode 34, the material of the drain electrode 36 can be a material that is ohmic-connected to an n-type nitride semiconductor such as n-type GaN, such as Ti / Al.

[0096] The insulating film 40 is provided above the gate electrode 32. Specifically, the insulating film 40 is provided so as to cover the gate electrode 32, the p-type semiconductor layer 28, the electron supply layer 24, and the source electrode 34. The insulating film 40 has a laminated structure of multiple insulating films. The multiple insulating films are, for example, insulating films such as SiN, SiO2, SiON, and Al2O3. The insulating film 40 may also have a single-layer structure of one insulating film.

[0097] The source wiring 50 is located above the insulating film 40 and is connected to the source electrode 34 through an opening in the insulating film 40. The source wiring 50 is formed using a conductive material such as metal. For example, the source wiring 50 is a plated film made of, for example, gold (Au).

[0098] In the nitride semiconductor device 1 configured as described above, 2DEG25 is generated near the interface between the electron transport layer 22 and the electron supply layer 24 and can be used as a channel. In the region that overlaps with the non-overlapping portion 28B of the p-type semiconductor layer 28 in a plan view, the potential at the conduction band edge of the channel can be increased. Therefore, the nitride semiconductor device 1 can be operated as a normally-off transistor. Furthermore, in the region that overlaps with the overlapping portion 28A of the p-type semiconductor layer 28 in a plan view, the influence of the p-type semiconductor layer 28 on the channel can be suppressed by the intermediate layer 26. In other words, the decrease in the concentration of 2DEG25 can be suppressed, and the on-resistance can be reduced.

[0099] Furthermore, the magnitude of the transistor threshold can be determined by the sloped portion of the channel along the side surface 20b of the first aperture 20 and the flat portion of the channel outside the first aperture 20. Typically, the side surface 20b of the first aperture 20 is a semi-polar surface, so the concentration of 2DEG25 tends to decrease compared to the polar surface of the flat portion, and the threshold tends to be higher in the sloped portion compared to the flat portion. By providing an intermediate layer 26 that overlaps the first aperture 20, the decrease in the concentration of 2DEG25 in the sloped portion can be suppressed, and the threshold can be lowered. In other words, the difference in threshold between the sloped portion and the flat portion can be reduced, improving the controllability of the transistor's on and off states.

[0100] The method for manufacturing the nitride semiconductor device 1 is not particularly limited, but for example, the following manufacturing methods can be used.

[0101] First, multiple nitride semiconductor films are formed on the main surface of the substrate 10 by epitaxial growth of a nitride semiconductor. Specifically, a drift layer 12 and a block layer 14 are formed on the main surface of the substrate 10 in that order. In epitaxial growth, the composition, thickness, conductivity type, and impurity concentration of the nitride semiconductor film can be adjusted by adjusting the growth conditions such as the raw material, growth temperature, and growth time.

[0102] Subsequently, the first opening 20 is formed by removing a portion of the block layer 14. For example, the block layer 14 is removed by photolithography and dry etching. At this time, by removing a portion of the surface layer of the drift layer 12 immediately following the removal of the block layer 14, the bottom surface 20a of the first opening 20 is formed below the interface between the block layer 14 and the drift layer 12, as shown in Figure 1.

[0103] Next, a nitride semiconductor is grown by a second epitaxial growth so as to cover the bottom surface 20a and side surface 20b of the first opening 20, and the top surface 14a of the block layer 14. Specifically, the electron transport layer 22, electron supply layer 24, and intermediate layer 26 are formed in this order.

[0104] Next, the second opening 30 is formed by removing a portion of each of the intermediate layer 26, the electron supply layer 24, and the electron transport layer 22. For example, each layer is removed by photolithography and dry etching. At this time, by removing a portion of the surface layer of the block layer 14, following the removal of the electron transport layer 22, the bottom surface 30a of the second opening 30 is formed below the interface between the block layer 14 and the electron transport layer 22, as shown in Figure 1. Furthermore, the intermediate layer 26 is patterned into a predetermined shape by removing a portion of the intermediate layer 26. As a result, a portion of the upper surface 24a of the electron supply layer 24 is exposed without being covered by the intermediate layer 26.

[0105] Next, a nitride semiconductor is grown by a third epitaxial growth so as to cover the intermediate layer 26. Specifically, a p-type semiconductor layer 28 is formed so as to cover the intermediate layer 26. Then, the p-type semiconductor layer 28 is patterned into a predetermined shape by removing a portion of it. As a result, a portion of the upper surface 24a of the electron supply layer 24 is exposed without being covered by the p-type semiconductor layer 28. At this time, the p-type semiconductor layer 28 is patterned so that an overlapping portion 28A that overlaps with the intermediate layer 26 in a plan view and a non-overlapping portion 28B that does not overlap with the intermediate layer 26 remain.

[0106] Next, the gate electrode 32 and source electrode 34 are formed. For example, first, a conductive film is formed using a conductive material that is ohmic-connected to the n-type nitride semiconductor, and then the source electrode 34 is formed by patterning it into a predetermined shape. The conductive film is formed by sputtering or evaporation. The conductive film is patterned by etching or lift-off. The source electrode 34 is formed to cover the bottom surface 30a and side surface 30b of the second opening 30 in contact with it, and not to contact the p-type semiconductor layer 28. Next, the gate electrode 32 is formed using a conductive material that is ohmic-connected to the p-type nitride semiconductor, and then the gate electrode 32 is formed by patterning it into a predetermined shape. The formation and patterning of the conductive film are the same as in the case of the source electrode 34. The gate electrode 32 is formed on the upper surface of the p-type semiconductor layer 28, and not to contact the upper surface 24a of the electron supply layer 24 or the source electrode 34.

[0107] Furthermore, the gate electrode 32 may be formed before the source electrode 34. Also, for example, after patterning the gate electrode 32, the p-type semiconductor layer 28 may be patterned using the gate electrode 32 as a mask. In addition, if the gate electrode 32 and the source electrode 34 are formed using the same conductive material, the gate electrode 32 and the source electrode 34 may be formed in the same process.

[0108] Next, the insulating film 40 and the source wiring 50 are formed. The insulating film 40 is formed by plasma CVD (Chemical Vapor Deposition), atomic layer deposition (ALD), or coating. After deposition, the insulating film 40 is etched to expose the source electrode 34. Then, the source wiring 50 is formed by plating or other methods. Although not shown in Figure 1, gate wiring that is electrically connected to the gate electrode 32 can be formed in the same way as the source wiring 50.

[0109] Next, a drain electrode 36 is formed on the lower surface of the substrate 10. For example, the drain electrode 36 is formed by creating a conductive film using a conductive material that is ohmic-connected to the n-type nitride semiconductor. The conductive film is formed by sputtering or vapor deposition.

[0110] Through the above process, the nitride semiconductor device 1 shown in Figure 1 can be manufactured.

[0111] (Embodiment 2) Next, Embodiment 2 will be described.

[0112] Embodiment 2 differs from Embodiment 1 mainly in that a recess is provided in the electron supply layer. Below, we will focus on explaining the differences from Embodiment 1, and omit or simplify the explanation of the common points.

[0113] Figure 2 is a cross-sectional view of the nitride semiconductor device 101 according to this embodiment. Compared to the nitride semiconductor device 1 shown in Figure 1, the nitride semiconductor device 101 shown in Figure 2 is equipped with an electron supply layer 124 instead of the electron supply layer 24.

[0114] The electron supply layer 124 is provided with a recess 129. The recess 129 is located in a position that overlaps the upper surface 14a of the block layer 14 in a plan view of the substrate 10. Part or all of the recess 129 may overlap the side surface 20b of the first opening 20 in a plan view of the substrate 10. The recess 129 is a recess that is indented from the upper surface 124a of the electron supply layer 124 toward the substrate 10. The side surface of the recess 129 is perpendicular to the bottom surface of the recess 129, but may be inclined at an angle.

[0115] A p-type semiconductor layer 28 is provided so as to cover the recess portion 129. The intermediate layer 26 is not provided in the recess portion 129. In other words, the non-overlapping portion 28B of the p-type semiconductor layer 28 covers the recess portion 129. The length of the non-overlapping portion 28B in the gate length direction corresponds to D1-D2, and is longer than the length of the recess portion 129 in the gate length direction. In this embodiment, the end of the intermediate layer 26 on the source electrode 34 side is located away from the open end of the recess portion 129, but this is not limited to this. The end of the intermediate layer 26 on the source electrode 34 side may coincide with the open end of the recess portion 129. In other words, the side surface of the intermediate layer 26 and the side surface of the recess portion 129 may be flush.

[0116] In the portion where the recess 129 is provided, the thickness of the electron supply layer 124 is reduced. As shown in Figure 2, the thickness T2 of the electron supply layer 124 in the portion where the recess 129 is provided is thinner than the thickness T1 of the portion where the recess 129 is not provided.

[0117] As the thickness T2 decreases, the concentration of 2DEG25 directly below the recess 129 decreases. This allows the transistor threshold to be raised. For example, the threshold can be raised above 0V, making it easier to normally-off the transistor. The transistor threshold can be determined by adjusting the size of the thickness T2. For example, the thickness T2 is between 10nm and 40nm, and 22nm is one example.

[0118] Furthermore, the portion of the electron supply layer 124 without recesses 129 can be made thicker without affecting the transistor threshold. As a result, the concentration of 2DEG25 increases directly below the portion without recesses 129, thus reducing the on-resistance. For example, the thickness T1 is between 10 nm and 70 nm, with 60 nm being one example. In this way, the provision of recesses 129 makes it possible to achieve both normally-off operation and reduced on-resistance.

[0119] The recess 129 is formed by removing a portion of the electron supply layer 124 after it has been deposited but before the p-type semiconductor layer 28 has been deposited. The electron supply layer 124 is removed by etching.

[0120] (Embodiment 3) Next, Embodiment 3 will be described.

[0121] Embodiment 3 differs from Embodiment 2 mainly in that a portion of the bottom surface of the recess is not covered by the p-type semiconductor layer. Below, we will focus on explaining the differences from Embodiment 2, and omit or simplify the explanation of the common points.

[0122] Figure 3 is a cross-sectional view of the nitride semiconductor device 201 according to this embodiment. In the nitride semiconductor device 201 shown in Figure 3, the main difference is the position of the end of the p-type semiconductor layer 28 on the source electrode 34 side compared to the nitride semiconductor device 101 shown in Figure 2.

[0123] Specifically, the end of the p-type semiconductor layer 28 on the source electrode 34 side is located on the bottom surface of the recess 129. That is, a portion of the bottom surface of the recess 129 is covered by the non-overlapping portion 28B of the p-type semiconductor layer 28, and another portion of the bottom surface of the recess 129 is covered by the insulating film 40 without being covered by the p-type semiconductor layer 28. The shortest distance D3 between the recess 129 and the source electrode 34 is shorter than the shortest distance D2 between the non-overlapping portion 28B and the source electrode 34. Note that the shortest distance D3 may be 0. Also, the side surface of the recess 129 on the source electrode 34 side may not be provided. A portion of the source electrode 34 may be provided within the recess 129, separated from the p-type semiconductor layer 28.

[0124] In the nitride semiconductor device 201 according to this embodiment, the concentration of 2DEG25 decreases in the region directly below the recess 129 and can be made to disappear when the device is off. Since the area where the non-overlapping portion 28B electrically connected to the gate electrode 32 and 2DEG25 face each other is reduced, the gate-source parasitic capacitance Cgs can be reduced.

[0125] (Embodiment 4) Next, Embodiment 4 will be described.

[0126] Embodiment 4 differs from Embodiment 1 mainly in that the gate electrode is positioned so as not to overlap with the first opening in a plan view, and a shielding electrode is provided at the position where it overlaps with the first opening. Below, we will focus on explaining the differences from Embodiment 1, and omit or simplify the explanation of the common points.

[0127] Figure 4 is a cross-sectional view of the nitride semiconductor device 301 according to this embodiment. Compared to the nitride semiconductor device 1 shown in Figure 1, the nitride semiconductor device 301 shown in Figure 4 includes a shielding layer 327, a threshold adjustment layer 328, a gate electrode 332, and a shielding electrode 338 instead of the p-type semiconductor layer 28 and gate electrode 32.

[0128] The shielding layer 327 is an example of an overlapping portion of the p-type third nitride semiconductor layer, and is provided above the electron supply layer 24, overlapping the intermediate layer 26 in a plan view of the substrate 10. The shielding layer 327 overlaps the bottom surface 20a and side surface 20b of the first opening 20 in a plan view of the substrate 10. The shape and size of the shielding layer 327 in a plan view are the same as those of the intermediate layer 26. The side surface of the shielding layer 327 is flush with the side surface of the intermediate layer 26. The shielding layer 327 is provided in contact with the upper surface of the intermediate layer 26 and the lower surface of the shielding electrode 338. The shielding layer 327 is electrically connected to the shielding electrode 338.

[0129] The threshold adjustment layer 328 is an example of a non-overlapping portion of the p-type third nitride semiconductor layer, and is provided above the electron supply layer 24, positioned so as to overlap the block layer 14 without overlapping the first opening 20 in a plan view of the substrate 10. The threshold adjustment layer 328 is provided between the source electrode 34 and the shielding layer 327, spaced apart from both the source electrode 34 and the shielding layer 327. Specifically, the shortest distance D2 between the threshold adjustment layer 328 and the source electrode 34 is shorter than the shortest distance D1 between the shielding layer 327 and the source electrode 34. Both the shortest distances D1 and D2 are distances in the gate length direction. Also, the length of the threshold adjustment layer 328 in the gate length direction is shorter than D1-D2. The threshold adjustment layer 328 is electrically isolated from both the source electrode 34 and the shielding layer 327. The threshold adjustment layer 328 is electrically connected to the gate electrode 332.

[0130] The shielding layer 327 and the threshold adjustment layer 328 are formed by removing and separating a portion of the nitride semiconductor film deposited in the same process. Therefore, the shielding layer 327 and the threshold adjustment layer 328 have the same composition, thickness, and carrier concentration. For example, the shielding layer 327 and the threshold adjustment layer 328 each have a thickness of 200 nm and a carrier concentration of 5 × 10⁻¹⁶. 17 cm -3 This film mainly contains p-type GaN.

[0131] The gate electrode 332 is an example of a first electrode and is provided above the threshold adjustment layer 328. In a plan view of the substrate 10, the gate electrode 332 is provided in a position that overlaps the block layer 14 but does not overlap the first opening 20. Specifically, the gate electrode 332 is provided in contact with the upper surface of the threshold adjustment layer 328.

[0132] The shielding electrode 338 is an example of a third electrode and is located above the shielding layer 327 in a position that overlaps the first opening 20 in a plan view of the substrate 10. The shielding electrode 338 is electrically connected to the source electrode 34 and the shielding layer 327. Specifically, the source wiring 50 is connected to the shielding electrode 338 and is set to the same potential as the source electrode 34.

[0133] The gate electrode 332 and the shielding electrode 338 are formed by removing and separating a portion of the conductive film deposited in the same process. Therefore, the gate electrode 332 and the shielding electrode 338 have the same main components. For example, the gate electrode 332 and the shielding electrode 338 each contain, as their main component, a material that is ohmic-connected to a p-type nitride semiconductor such as p-type GaN. For example, Pd, Ni-based materials, WSi, Au, etc., can be used as the material for forming the gate electrode 332 and the shielding electrode 338.

[0134] In the nitride semiconductor device 301 according to this embodiment, the transistor threshold is determined at the flat portion of the channel outside the first aperture 20, and is no longer affected by the slope of the channel. Therefore, the controllability of the transistor's on and off states can be improved. Furthermore, by providing a shielding electrode 338 electrically connected to the source electrode 34, the electric field lines extending from the drain electrode 36 can be terminated by the shielding electrode 338. This reduces the gate-drain parasitic capacitance Cgd, enabling faster switching.

[0135] Furthermore, the source potential is supplied to the shielding layer 327 from the shielding electrode 338. Therefore, a reverse bias can be applied to the pn junction between the shielding layer 327 and 2DEG25 via the shielding electrode 338 and the drain electrode 36. This allows the breakdown voltage of the transistor to be increased.

[0136] Next, a modified example of Embodiment 4 will be described. In the following, the differences from Embodiment 4 will be the main focus of the explanation, and the similarities will be omitted or simplified.

[0137] <Example 1> Figure 5 is a cross-sectional view of a nitride semiconductor device 302 according to a modified example 1 of Embodiment 4. Compared to the nitride semiconductor device 301 shown in Figure 4, the nitride semiconductor device 302 shown in Figure 5 is equipped with an electron supply layer 124 having a recess 129 instead of the electron supply layer 24.

[0138] The recess 129 is the same as in Embodiment 2, the main difference being that it is covered by a threshold adjustment layer 328 instead of the non-overlapping portion 28B of the p-type semiconductor layer 28. Since the gate electrode 332 is electrically connected to the threshold adjustment layer 328, the generation and disappearance of 2DEG25 in the direction directly below the recess 129 can be controlled. Since the concentration of 2DEG25 can be reduced in the direction directly below the recess 129, the threshold of the transistor can be increased, and normally-off operation can be easily achieved.

[0139] Furthermore, since the portion of the electron supply layer 124 that does not have a recess 129 can be made thicker, the concentration of 2DEG25 near the portion that does not have a recess 129 can be increased. As a result, the on-resistance can be reduced.

[0140] Thus, the nitride semiconductor device 302 according to this modified example makes it possible to achieve both normally-off operation and reduced on-resistance.

[0141] <Modification 2> Figure 6 is a cross-sectional view of a nitride semiconductor device 303 according to a modified example 2 of Embodiment 4. The nitride semiconductor device 303 shown in Figure 6 differs from the nitride semiconductor device 302 shown in Figure 5 mainly in the size of the recess portion 129 and the position of the end of the threshold adjustment layer 328 on the source electrode 34 side.

[0142] Specifically, the end of the threshold adjustment layer 328 on the source electrode 34 side is located on the bottom surface of the recess 129. In other words, a portion of the bottom surface of the recess 129 is covered by the threshold adjustment layer 328, while another portion of the bottom surface of the recess 129 is not covered by the threshold adjustment layer 328 but is covered by the insulating film 40.

[0143] Furthermore, the recess portion 129 is formed so that its side surface and the side surface of the source electrode 34 are flush. As in Figure 3, the shortest distance between the recess portion 129 and the source electrode 34 may be greater than 0 and shorter than the shortest distance D2 between the non-overlapping portion 28B and the source electrode 34. In this modified example, the side surface of the recess portion 129 on the source electrode 34 side may not be provided. A portion of the source electrode 34 may be provided within the recess portion 129, separated from the threshold adjustment layer 328.

[0144] In the nitride semiconductor device 303 according to this modified example, the concentration of 2DEG25 decreases in the region directly below the recess 129 and can be made to disappear when the device is off. Since the area where the threshold adjustment layer 328 electrically connected to the gate electrode 32 and 2DEG25 face each other is reduced, the gate-source parasitic capacitance Cgs can be reduced.

[0145] <Variation 3> Figure 7 is a cross-sectional view of a nitride semiconductor device 304 according to a modified example 3 of Embodiment 4. The nitride semiconductor device 304 shown in Figure 7 differs from the nitride semiconductor device 303 shown in Figure 6 mainly in the size of the recess portion 129 and the position of the end of the threshold adjustment layer 328 on the shielding layer 327 side.

[0146] Specifically, the end of the threshold adjustment layer 328 on the shielding layer 327 side is located on the bottom surface of the recess 129. In other words, the bottom surface of the recess 129 includes portions of the threshold adjustment layer 328 that are not covered by the threshold adjustment layer 328, both on the source electrode 34 side and the shielding layer 327 side.

[0147] Furthermore, the side surfaces of the recess 129, the shielding layer 327, and the intermediate layer 26 are formed to be flush with each other. For example, the patterning of the shielding layer 327 and the intermediate layer 26 and the formation of the recess 129 can be performed in the same etching process, thereby simplifying the manufacturing method.

[0148] In the nitride semiconductor device 304 according to this modified example, the area in which the threshold adjustment layer 328 and 2DEG25, which are electrically connected to the gate electrode 32, face each other becomes even smaller, so that the gate-source parasitic capacitance Cgs can be further reduced.

[0149] (Embodiment 5) Next, Embodiment 5 will be described.

[0150] Embodiment 5 differs from Embodiment 1 primarily in that the source electrode is electrically connected to the p-type block layer via a p-type nitride semiconductor layer. The following explanation will focus on the differences from Embodiment 1, omitting or simplifying the explanation of commonalities.

[0151] Figure 8 is a cross-sectional view of the nitride semiconductor device 401 according to this embodiment. The nitride semiconductor device 401 shown in Figure 8 includes a contact layer 414 compared to the nitride semiconductor device 1 shown in Figure 1. In addition, the nitride semiconductor device 401 is provided with a third opening 430.

[0152] The contact layer 414 is an example of a p-type sixth nitride semiconductor layer and is provided to contact the block layer 14 within the second opening 30. Specifically, the contact layer 414 covers the bottom surface 30a and side surface 30b of the second opening 30 in contact with it, and contacts the block layer 14 with the bottom surface 30a and a portion of the side surface 30b. The contact layer 414 may also cover the upper surface of the electron supply layer 24 near the opening end of the second opening 30.

[0153] The contact layer 414 has a thickness of 200 nm and a carrier concentration of 5 × 10⁻¹⁴ 17 cm -3 This film mainly contains p-type GaN. The contact layer 414 can be formed using the same process as the p-type semiconductor layer 28. Therefore, the composition and carrier concentration of the contact layer 414 are the same as those of the p-type semiconductor layer 28. Note that the thickness and carrier concentration of the contact layer 414 are merely examples and can be changed as appropriate.

[0154] The contact layer 414 is formed by epitaxial growth after the formation of the second opening 30. The bottom surface 30a of the second opening 30 is etched during the formation of the second opening 30, whereas the top surface of the contact layer 414 is not etched. Therefore, when the source electrode 34 is in contact with the contact layer 414, the contact resistance can be reduced compared to when it is in contact with the block layer 14. In this way, by electrically connecting the source electrode 34 to the block layer 14 via the contact layer 414, the potential of the block layer 14 can be stabilized.

[0155] The third opening 430 is located between the second opening 30 and the first opening 20 in a plan view of the substrate 10. The third opening 430 is provided to reduce the contact resistance between the source electrode 34 and 2DEG 25, and is sometimes referred to as the source opening. The third opening 430 penetrates the electron supply layer 24 and reaches the electron transport layer 22. For example, the bottom surface 430a of the third opening 430 is located below the interface between the electron transport layer 22 and the electron supply layer 24, and below the region where 2DEG 25 is generated. Therefore, 2DEG 25 is exposed on the side surface 430b of the third opening 430. By providing the source electrode 34 so as to cover the bottom surface 430a and side surface 430b of the third opening 430, the source electrode 34 and 2DEG 25 can be brought into contact. This reduces the contact resistance between the source electrode 34 and 2DEG 25.

[0156] In Figure 8, an example is shown where the side surface 430b of the third opening 430 is perpendicular to the bottom surface 430a, but the side surface 430b may be inclined with respect to the bottom surface 430a. Also, the third opening 430 does not necessarily have to penetrate the electron supply layer 24. By making the electron supply layer 24 located between the source electrode 34 and 2DEG25 thinner, the contact resistance can be reduced.

[0157] In this embodiment, the nitride semiconductor device 401 does not necessarily have to have a third opening 430. For example, the contact layer 414 does not need to cover the portion of the side surface 30b of the second opening 30 near the interface between the electron supply layer 24 and the electron transport layer 22. In this case, the source electrode 34 can be brought into contact with the 2DEG 25 exposed on the side surface 30b of the second opening 30. Even without providing the third opening 430, the contact resistance to the 2DEG 25 can be reduced.

[0158] The contact layer 414 and the third opening 430 may be provided in the nitride semiconductor devices 101, 201, 301, 302, 303, or 304 according to embodiments 2 to 4 and their variations.

[0159] (Embodiment 6) Next, Embodiment 6 will be described.

[0160] Embodiment 6 differs from Embodiment 1 in that an opening is provided in the intermediate layer. Below, we will focus on explaining the differences from Embodiment 1, and omit or simplify the explanation of the common points.

[0161] Figure 9 is a cross-sectional view of the nitride semiconductor device 501 according to this embodiment. Compared to the nitride semiconductor device 1 shown in Figure 1, the nitride semiconductor device 501 shown in Figure 9 has an intermediate layer 526 instead of the intermediate layer 26.

[0162] The intermediate layer 526 has a similar configuration to the intermediate layer 26, except that it is provided with an opening 527. The opening 527 is positioned to overlap at least a portion of the bottom surface 20a of the first opening 20 in a plan view of the substrate 10. Because the opening 527 is provided, the intermediate layer 526 does not overlap at least a portion of the bottom surface 20a of the first opening 20 in a plan view of the substrate 10. In this embodiment, since the p-type semiconductor layer 28 is provided to fill the opening 527, the p-type semiconductor layer 28 is in contact with the upper surface 24a of the electron supply layer 24 within the opening 527.

[0163] Within the opening 527, since there is no intermediate layer 526 between the p-type semiconductor layer 28 and the electron supply layer 24, the electric field concentration associated with the reverse bias between the drain and source can be mitigated by the p-type semiconductor layer 28. This allows the breakdown voltage of the nitride semiconductor device 501 to be increased.

[0164] The opening 527 can be formed during the patterning process of the intermediate layer 526. In this embodiment, the opening 527 is formed so as to expose the flat portion of the upper surface of the electron supply layer 24 that is closest to the substrate 10, but it is not limited to this. The opening 527 may also be formed so as to expose a part of the inclined portion of the upper surface of the electron supply layer 24 that is continuous with the flat portion of the upper surface of the electron supply layer 24 that is closest to the substrate 10.

[0165] The intermediate layer 526, which has an opening 527, may be provided in place of the intermediate layer 26 of the nitride semiconductor device 101, 201, 301, 302, 303, 304, or 401 according to embodiments 2 to 5 and modified examples.

[0166] (Embodiment 7) Next, Embodiment 7 will be described.

[0167] Embodiment 7 differs from Embodiment 1 in that the conductivity type of the intermediate layer is type i. The following explanation will focus on the differences from Embodiment 1, omitting or simplifying the explanation of the common points.

[0168] Figure 10 is a cross-sectional view of the nitride semiconductor device 601 according to this embodiment. Compared to the nitride semiconductor device 1 shown in Figure 1, the nitride semiconductor device 601 shown in Figure 1 includes an intermediate layer 626 instead of the intermediate layer 26.

[0169] Intermediate layer 626 has a similar structure to intermediate layer 26, but differs in that its conductivity type is i-type instead of n-type. For example, intermediate layer 626 is a film mainly composed of i-type GaN. The film thickness of intermediate layer 626 is, for example, between 22 nm and 150 nm.

[0170] The intermediate layer 626 can suppress the diffusion of p-type impurities from the p-type semiconductor layer 28. For this reason, the intermediate layer 626 contains p-type impurities. A diffusion layer containing p-type impurities is formed along the upper surface of the intermediate layer 626. The concentration of p-type impurities in the diffusion layer gradually decreases, for example, from the upper surface to the lower surface.

[0171] The intermediate layer 626 suppresses the diffusion of p-type impurities, thereby suppressing channel depletion. Since the concentration of 2DEG25 tends to be lower in the sloping portion of the channel compared to the flat portion, the effect of the intermediate layer 626 in suppressing depletion is effective. This allows for a reduction in on-resistance.

[0172] Furthermore, although the intermediate layer 26 or 526 in each of the embodiments and modified examples described above has an n-type conductivity, the n-type intermediate layer 26 or 526 also has the effect of suppressing depletion. The n-type intermediate layer 26 or 526 can cancel out the positive charge caused by p-type impurities, and thus can suppress channel depletion.

[0173] The i-type intermediate layer 626 may be provided in place of the intermediate layer 26 of the nitride semiconductor devices 101, 201, 301, 302, 303, 304, or 401 according to Embodiments 2 to 5 and their variations, or in place of the intermediate layer 526 of the nitride semiconductor device 501 according to Embodiment 6.

[0174] (Other embodiments) Although nitride semiconductor devices according to one or more embodiments have been described above based on embodiments, this disclosure is not limited to these embodiments. Without departing from the spirit of this disclosure, various modifications to these embodiments that a person skilled in the art could conceive, as well as forms constructed by combining components from different embodiments, are also included within the scope of this disclosure.

[0175] For example, the intermediate layer 26 may mainly contain materials other than nitride semiconductors. For example, the intermediate layer 26 may mainly contain metal oxides such as gallium oxide or nickel oxide. Alternatively, the intermediate layer 26 may mainly contain insulating materials such as silicon oxide or silicon nitride.

[0176] Furthermore, for example, the second opening 30 may not be provided. In this case, the source electrode 34 is provided on the upper surface 24a of the electron supply layer 24 and is electrically connected to the 2DEG25 via the electron supply layer 24.

[0177] Furthermore, in the nitride semiconductor devices 1, 101, 201, 301, 302, 303, 304, 401, 501, and 601 according to each embodiment and its modified form, a high-resistance layer with a higher resistance than the block layer 14 may be provided between the drift layer 12 and the block layer 14. The high-resistance layer is, for example, a nitride semiconductor layer mainly composed of carbon-doped GaN (C-GaN). The carbon concentration of the high-resistance layer is, for example, 3 × 10⁻⁶. 17 cm -3 That's all, but 1 × 10 18 cm -3 The above is also acceptable. The high-resistance layer is provided in contact with each of the drift layer 12 and the block layer 14. The high-resistance layer may contain n-type impurities such as Si. The concentration of n-type impurities in the high-resistance layer is lower than the carbon and oxygen concentrations in the high-resistance layer, for example, 5 × 10⁻⁶. 16 cm -3 The following, or 2 × 10 16 cm -3 The following is also possible: By providing a high-resistance layer, punch-through can be suppressed and the breakdown voltage can be increased. When a high-resistance layer is formed, the first opening 20 penetrates the high-resistance layer. As a result, the high-resistance layer is not located in the path of the drain current when the FET is ON, so an increase in ON resistance can be suppressed.

[0178] Furthermore, for example, the drift layer 12 may have a graded structure in which the impurity concentration (donor concentration) is gradually reduced from the substrate 10 side to the block layer 14 side. The donor concentration may be controlled by the donor Si, or by the acceptor carbon that compensates for the Si. Alternatively, the drift layer 12 may have a stacked structure of multiple nitride semiconductor layers with different impurity concentrations. Specifically, the drift layer can be made into two layers, with a layer with a low donor concentration placed below the block layer and a layer with a high donor concentration placed on the substrate side. By providing a first opening 20 so as to penetrate the layer with the low donor concentration, when the transistor is turned on, current flows through the first opening 20 to the layer with the high donor concentration, thus reducing the on-resistance. Conversely, when the transistor is turned off, a high electric field is maintained by the layer with the low donor concentration, thus achieving both low on-resistance and high breakdown voltage.

[0179] Furthermore, for example, the nitride semiconductor device according to this disclosure may be a lateral transistor. Specifically, the gate electrode, source electrode, and drain electrode may all be provided above the substrate. In this case, the gate electrode is provided between the source electrode and the drain electrode. The nitride semiconductor device, which is a lateral transistor, does not need to include a drift layer 12 and a block layer 14.

[0180] Furthermore, each of the above embodiments can be modified, replaced, added, or omitted in various ways within the scope of the claims or equivalents thereof. [Industrial applicability]

[0181] The nitride semiconductor devices relating to this disclosure are useful, for example, as power devices used in power supply circuits, inverter circuits, and the like for electrical equipment. [Explanation of symbols]

[0182] 1, 101, 201, 301, 302, 303, 304, 401, 501, 601 Nitride Semiconductor Devices 10 circuit boards 12 Drift Layers 14 block layers 14a, 24a, 124a top surface 20 First opening 20a, 30a, 430a bottom 20b, 30b, 430b side 22 Electron transport layer 24, 124 electron supply layer 25 2DEG 26, 526, 626 (intermediate layer) 28 p-type semiconductor layer 28A Overlapping part 28B Non-overlapping part 30. Second opening 32, 332 geothermal 34 Source electrodes 36 Drain electrode 40 insulating film 50 Source Wiring 129 Recessed section 327 Shielding layer 328 Threshold adjustment layer 338 Shielding electrode 414 Contact Layer 430 Third opening 527 Opening

Claims

1. circuit board and A first nitride semiconductor layer provided above the substrate, A second nitride semiconductor layer is provided above the first nitride semiconductor layer and has a larger band gap than the first nitride semiconductor layer, A p-type third nitride semiconductor layer is provided above the aforementioned second nitride semiconductor layer, A first electrode provided above the third nitride semiconductor layer, A second electrode is provided above the substrate and electrically connected to the first nitride semiconductor layer, The present invention comprises an intermediate layer provided between the second nitride semiconductor layer and the third nitride semiconductor layer, The third nitride semiconductor layer is In a plan view of the substrate, the overlapping portion overlaps the intermediate layer, The substrate includes a non-overlapping portion that does not overlap with the intermediate layer in a plan view, The shortest distance between the non-overlapping portion and the second electrode is shorter than the shortest distance between the overlapping portion and the second electrode. The first electrode is electrically connected to the non-overlapping portion. Nitride semiconductor devices.

2. An n-type fourth nitride semiconductor layer is provided above the aforementioned substrate, A p-type fifth nitride semiconductor layer is provided above the fourth nitride semiconductor layer, The substrate comprises a drain electrode provided below the substrate, The first electrode is an electrode, The second electrode is a source electrode, The first nitride semiconductor layer and the second nitride semiconductor layer are provided so as to cover the inner surface of the first opening that penetrates the fifth nitride semiconductor layer and reaches the fourth nitride semiconductor layer, and the area above the fifth nitride semiconductor layer. The intermediate layer is provided in a position that overlaps the first opening in a plan view of the substrate. The nitride semiconductor device according to claim 1.

3. The first electrode is provided in a position that overlaps the first opening in a plan view of the substrate, The non-overlapping portion is provided continuously from the overlapping portion. The nitride semiconductor device according to claim 2.

4. The substrate is provided above the third nitride semiconductor layer at a position overlapping the first opening in a plan view, and comprises a third electrode electrically connected to the second electrode, The first electrode is positioned so as to overlap the fifth nitride semiconductor layer without overlapping the first opening in a plan view of the substrate. The nitride semiconductor device according to claim 2.

5. The third electrode is electrically connected to the overlapping portion, The non-overlapping portion is provided spaced apart from the overlapping portion. The nitride semiconductor device according to claim 4.

6. The non-overlapping portion overlaps the upper surface of the fifth nitride semiconductor layer in a plan view of the substrate. A nitride semiconductor device according to any one of claims 2 to 5.

7. The second nitride semiconductor layer is provided with a recess portion at a position that overlaps with the upper surface of the fifth nitride semiconductor layer in a plan view of the substrate. The non-overlapping portion is provided in contact with at least a part of the bottom surface of the recessed portion. A nitride semiconductor device according to any one of claims 2 to 5.

8. The end of the non-overlapping portion on the second electrode side is located on the bottom surface of the recess portion. The nitride semiconductor device according to claim 7.

9. The second nitride semiconductor layer is provided with a recess portion at a position that overlaps with the upper surface of the fifth nitride semiconductor layer in a plan view of the substrate. The end of the non-overlapping portion on the second electrode side and the end opposite to the second electrode side are located on the bottom surface of the recess portion. The nitride semiconductor device according to claim 4 or 5.

10. The second electrode is electrically connected to the fifth nitride semiconductor layer via a second opening that penetrates the second nitride semiconductor layer and the first nitride semiconductor layer and reaches the fifth nitride semiconductor layer. A nitride semiconductor device according to any one of claims 2 to 5.

11. The second opening is provided with a p-type sixth nitride semiconductor layer that is in contact with the fifth nitride semiconductor layer, The second electrode is in contact with the sixth nitride semiconductor layer. The nitride semiconductor device according to claim 10.

12. The intermediate layer does not overlap with at least a portion of the bottom surface of the first opening in a plan view of the substrate. A nitride semiconductor device according to any one of claims 2 to 5.

13. The aforementioned intermediate layer mainly contains a nitride semiconductor. A nitride semiconductor device according to any one of claims 1 to 5.

14. The conductivity type of the intermediate layer is n-type. A nitride semiconductor device according to any one of claims 1 to 5.

15. The conductivity type of the intermediate layer is i-type. A nitride semiconductor device according to any one of claims 1 to 5.

16. The aforementioned intermediate layer contains p-type impurities. The nitride semiconductor device according to claim 15.

17. The thickness of the intermediate layer is 22 nm or more and 150 nm or less. A nitride semiconductor device according to any one of claims 1 to 5.

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