Information processing device

Abstract

The present invention provides an information processing device that can suppress the transmission of excessive amounts of data to the opposing device. [Solution] The execution device generates a dataset DS which includes divided data DD obtained by dividing the target data to be transmitted from the data stored in the storage device into multiple parts, a signal requesting the storage of the divided data, and a signal requesting a reply when the reception of the divided data DD is complete. The execution device starts sequentially transmitting the multiple datasets DS to the opposing device via the communication bus from the communication port. If the execution device does not receive a signal from the opposing device indicating that the reception of the divided data DD is complete within a specified time RT after transmitting the dataset DS, it stops transmitting the dataset DS containing the divided data DD that has not been transmitted among the multiple divided data DDs of the target data to the opposing device.

Description

[Technical Field]

[0001] The present disclosure relates to an information processing apparatus. [Background Art]

[0002] Patent Document 1 describes an information processing apparatus that mutually communicates with a counterpart device via a communication bus in accordance with the PCIe (Peripheral Component Interconnect express) standard. The information processing apparatus includes a communication port connected to the communication bus. [Prior Art Literature] [Patent Documents]

[0003] [Patent Document 1] Japanese Unexamined Patent Publication No. 2010-238150 [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] In the information processing apparatus as described in Patent Document 1, when an abnormality occurs in a communication port, the information processing apparatus enters an abnormal state. In this case, if the information processing apparatus continues transmitting data to the counterpart device, there is a risk that an excessive amount of data is transmitted to the counterpart device. [Means for Solving the Problem]

[0005] An information processing device that solves the above problems is an information processing device that communicates with a counterpart device via a communication bus, and comprises a communication port to which the communication bus is connected, an execution device, and a storage device, wherein the execution device generates a dataset that includes divided data obtained by dividing the target data to be transmitted from the data stored in the storage device into multiple parts, a signal requesting the storage of the divided data, and a signal requesting a reply when the reception of the divided data is complete, starts sequentially transmitting the multiple datasets from the communication port to the counterpart device via the communication bus, and, if a signal indicating that the reception of the divided data is complete is not received from the counterpart device within a predetermined time after transmitting the multiple datasets, stops transmitting the dataset containing the divided data that has not been transmitted from the multiple divided data to the counterpart device. [Effects of the Invention]

[0006] In the above-described information processing device, if the communication port enters an abnormal state, the execution device will not receive a signal from the opposing device indicating that the reception of the target data has been completed. In this case, the information processing device will stop sending the dataset containing the segmented data that has not been transmitted to the opposing device. Therefore, the information processing device can prevent the transmission of an excessive amount of data to the opposing device. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a schematic diagram showing a vehicle equipped with a communication system according to one embodiment. [Figure 2] Figure 2 is a flowchart showing a series of processes performed by the direct storage control device of the same embodiment. [Figure 3] Figure 3 is a schematic diagram showing the target data and multiple divided data in the embodiment. [Figure 4] Figure 4 is a schematic diagram showing the dataset of the same embodiment. [Figure 5]Figure 5 is an explanatory diagram illustrating the processes performed by the communication system when the target data of this embodiment is transmitted. [Modes for carrying out the invention]

[0008] <One Embodiment> An embodiment of the information processing device will be described below with reference to the drawings. As shown in Figure 1, the vehicle 10 is equipped with a communication system 20. The communication system 20 acquires signals from each switch of the vehicle 10 and controls each actuator of the vehicle 10 based on the acquired signals.

[0009] The communication system 20 comprises multiple communication devices 30. The multiple communication devices 30 communicate with each other via a communication bus 50 in accordance with the PCIe standard. The communication device 30 is an ECU that controls each actuator in the vehicle 10 and performs calculations based on values ​​obtained from each sensor in the vehicle 10. For example, one of the multiple communication devices 30 is an engine ECU. The engine ECU controls the engine of the vehicle 10. Another example is a multimedia ECU. The multimedia ECU controls the display and audio equipment of the vehicle 10.

[0010] In this embodiment, the multiple communication devices 30 consist of two devices: an information processing device 30A and a counterpart device 30B. The information processing device 30A is the engine ECU, and the counterpart device 30B is the multimedia ECU. Therefore, the information processing device 30A communicates with the counterpart device 30B via the communication bus 50.

[0011] The information processing device 30A functions as an endpoint, while the opposing device 30B functions as a root complex. This allows the information processing device 30A to communicate with the opposing device 30B in accordance with the PCIe standard.

[0012] The communication device 30 comprises a core 31, a direct memory control device 32, a memory device 33, and a communication port 40. The core 31 is an embedded CPU on the chip. The core 31 instructs the direct memory control device 32 to execute direct memory control. The core 31 also executes various programs stored in the memory device 33 to output instruction signals for controlling the actuators of the vehicle 10 and to perform various calculations. For example, in the case of the communication device 30 being an engine ECU, the core 31 outputs instruction signals for controlling the engine.

[0013] The direct memory access controller 32 is a so-called DMAC (Direct Memory Access Controller). The direct memory access controller 32 is an execution device. Furthermore, the direct memory access controller 32 is a CPU. Therefore, the direct memory access controller 32 includes processing circuits.

[0014] The direct storage control device 32 performs direct storage control by executing the direct storage control program PR stored in the storage device 33. Direct storage control is a control that transmits the data stored in the storage device 33 to be stored in the storage device 33 of another communication device 30 with which it communicates.

[0015] The memory device 33 stores the direct memory control program PR. The direct memory control program PR is a program that, when executed by the direct memory control device 32, enables direct memory control.

[0016] The storage device 33 of the information processing device 30A stores the target data TD. The target data TD is data transmitted from the information processing device 30A to the opposing device 30B by direct storage control. The target data TD is, for example, time-series data of sensor values ​​detected by engine control.

[0017] The communication port 40 is connected to a communication bus 50. The communication port 40 transmits and receives data during mutual communication. The communication port 40 comprises a transaction layer 41, a data link layer 42, a physical layer 43, a transmission channel 44, and a reception channel 45. Therefore, the communication port 40 has a three-layer structure.

[0018] The transaction layer 41 guarantees reliable end-to-end data communication for an upper software layer consisting of upper drivers and application software. The transaction layer 41 includes a transmitting-side transaction layer 41 and a receiving-side transaction layer 41. The transmitting-side transaction layer 41 generates a transaction layer packet in accordance with a request from the core 31. The receiving-side transaction layer 41 receives transaction layer packets from another mutually communicating communication device 30.

[0019] The data link layer 42 is located between the transaction layer 41 and the physical layer 43. The data link layer 42 exchanges transaction layer packets with mutually communicating communication devices 30. The data link layer 42 performs flow control. In flow control, the data link layer 42 limits the transmission rate according to the reception processing speed of the mutually communicating communication device 30.

[0020] The physical layer 43 transmits and receives communication packets over a physical medium. The physical layer 43 includes a transmitting-side physical layer 43 and a receiving-side physical layer 43. The transmitting-side physical layer 43 transmits a packet to the transmission channel 44. The receiving-side physical layer 43 receives a packet from the reception channel 45.

[0021] In the present embodiment, the transmission channel 44 of the information processing apparatus 30A is connected to the reception channel 45 of the opposing apparatus 30B via the first lane 51 of the communication bus 50. The reception channel 45 of the information processing apparatus 30A is connected to the transmission channel 44 of the opposing apparatus 30B via the second lane 52 of the communication bus 50.

[0022] <Regarding the series of processes related to direct memory control> The following describes a series of processes related to direct storage control performed by the direct storage control device 32 of the information processing device 30A. When the direct storage control device 32 is instructed by the core 31 to execute direct storage control, the direct storage control device 32 starts executing the direct storage control program PR.

[0023] As shown in Figure 2, when the direct storage control device 32 starts executing the direct storage control program PR, the direct storage control device 32 first performs the process in step S11. In step S11, the direct storage control device 32 generates multiple divided data DDs by dividing the target data TD to be transmitted.

[0024] As shown in Figure 3, the direct storage control device 32 divides the target data TD into N parts. This allows the direct storage control device 32 to generate the first divided data DD1 to the Nth divided data DDN. For example, the direct storage control device 32 divides time-series data into predetermined time intervals to generate multiple divided data DDs.

[0025] As shown in Figure 2, in step S11, the direct storage control device 32 generates multiple partitioned data DDs, and then proceeds to step S12. In step S12, the direct storage control device 32 generates a dataset DS.

[0026] As shown in Figure 4, the dataset DS includes two partitioned data DDs, a signal requesting the storage of the two partitioned data DDs, and a signal requesting a reply when the reception of the two partitioned data DDs is complete. For example, the first dataset DS to be transmitted includes the first partitioned data DD1, a write WR signal for writing the first partitioned data DD1, the second partitioned data DD2, and a write WR signal for writing the second partitioned data DD2. As a signal requesting a reply when the reception of the two partitioned data DDs is complete, the dataset DS includes, for example, a completion flag which is a reception completion signal MS, and a read RD signal for reading the completion flag and sending a reply. The capacity of the two partitioned data DDs contained in one dataset DS is less than or equal to the capacity that the opposing device 30B can receive via the communication bus 50.

[0027] As shown in Figure 2, in step S12, after the direct storage control device 32 generates a dataset DS, the direct storage control device 32 proceeds to step S13. In step S13, the direct storage control device 32 transmits the dataset DS. That is, when the direct storage control device 32 starts the series of processes shown in Figure 2 and performs step S13 for the first time, the direct storage control device 32 starts sequentially transmitting multiple datasets DS from the communication port 40 to the opposing device 30B via the communication bus 50. After that, the direct storage control device 32 proceeds to step S14.

[0028] In step S14, the direct storage control device 32 determines whether it has received a reception completion signal MS from the opposing device 30B within a predetermined time RT after transmitting the dataset DS. The reception completion signal MS indicates that the reception of the segmented data DD included in the dataset DS has been completed.

[0029] If the direct storage control device 32 receives a reception completion signal MS before the specified time RT has elapsed (S14: YES), the direct storage control device 32 proceeds to step S15. In step S15, the direct storage control device 32 determines that the communication status with the opposing device 30B via the communication bus 50 is normal. After that, the direct storage control device 32 proceeds to step S16.

[0030] In step S16, the direct storage control device 32 determines whether the transmission of all segmented data DD has been completed. That is, the direct storage control device 32 determines whether the transmission of the target data TD to be transmitted has been completed.

[0031] If the transmission of all divided data DDs is not complete (S16: NO), the direct storage control device 32 returns to step S12. In step S12, a dataset DS is generated that includes the divided data DDs that have not yet been transmitted. In this embodiment, a dataset DS is generated that includes the third divided data DD3 and the fourth divided data DD4, which are consecutive in time series. Subsequently, steps S12 to S16 are repeated while changing the divided data DDs, and all divided data DDs are transmitted as long as the positive determination in step S14 continues. When the transmission of all divided data DDs is complete (S16: YES), the direct storage control device 32 proceeds to step S17.

[0032] In step S17, the direct storage control device 32 completes the transmission of all segmented data DD and terminates the transmission of the target data TD, which is the target of this transmission. With this, the direct storage control device 32 terminates this series of processes.

[0033] By the way, in step S14, if the direct storage control device 32 does not receive the reception completion signal MS before the specified time RT has elapsed (S14: NO), the direct storage control device 32 proceeds to step S18.

[0034] In step S18, the direct storage control device 32 determines that the communication status with the opposing device 30B via the communication bus 50 is abnormal. Subsequently, the direct storage control device 32 proceeds to step S19.

[0035] In step S19, the direct storage control device 32 stops transmitting the dataset DS, which includes the segmented data DD that has not yet been transmitted, to the opposing device 30B. After that, the direct storage control device 32 terminates this series of processes.

[0036] <Regarding each process using direct memory control in communication systems> Next, we will describe the processes in the communication system 20 when the information processing device 30A transmits the target data TD to the opposing device 30B by direct storage control. In the following explanation, we will describe an example where N is 6, that is, where the target data TD is divided into 6 partitioned data DDs.

[0037] As shown in Figure 5, the information processing device 30A first transmits a dataset DS containing the first divided data DD1 and the second divided data DD2 to the opposing device 30B. Subsequently, when the opposing device 30B receives the dataset DS, the opposing device 30B performs the processing in step S21. In step S21, the opposing device 30B stores the first divided data DD1. After that, the opposing device 30B proceeds to step S22.

[0038] In step S22, the opposing device 30B stores the second divided data DD2. Subsequently, the opposing device 30B transmits a reception completion signal MS to the information processing device 30A, indicating that it has received the first divided data DD1 and the second divided data DD2 included in the current dataset DS.

[0039] When the information processing device 30A receives the reception completion signal MS, the information processing device 30A determines that the communication status via the communication bus 50 is normal by the process in step S15 described above. Subsequently, the information processing device 30A transmits the data set DS, which includes the third divided data DD3 and the fourth divided data DD4, to the opposing device 30B.

[0040] Subsequently, when the opposing device 30B receives the dataset DS, the opposing device 30B performs the processing in step S23. In step S23, the opposing device 30B stores the third divided data DD3. After that, the opposing device 30B proceeds to step S24.

[0041] In step S24, the opposing device 30B stores the fourth segmented data DD4. Subsequently, the opposing device 30B transmits a reception completion signal MS to the information processing device 30A, indicating that it has received the third segmented data DD3 and the fourth segmented data DD4 included in the current dataset DS.

[0042] When the information processing device 30A receives the reception completion signal MS, the information processing device 30A determines that the communication status is normal via the communication bus 50 by the process in step S15 described above. Subsequently, the information processing device 30A transmits the dataset DS, which includes the fifth segmented data DD5 and the sixth segmented data DD6, to the opposing device 30B.

[0043] Subsequently, when the opposing device 30B receives the dataset DS, the opposing device 30B performs the processing in step S25. In step S25, the opposing device 30B stores the fifth partitioned data DD5. After that, the opposing device 30B proceeds to step S26.

[0044] In step S26, the opposing device 30B stores the sixth segmented data DD6. Subsequently, the opposing device 30B transmits a reception completion signal MS to the information processing device 30A, indicating that it has received the fifth segmented data DD5 and the sixth segmented data DD6, which are included in the current dataset DS.

[0045] When the information processing device 30A receives the reception completion signal MS, the information processing device 30A determines that the communication status via the communication bus 50 is normal by the process in step S15 described above. Subsequently, the information processing device 30A terminates the transmission of the target data TD by the process in step S17 described above. As a result, the communication system 20 terminates the series of processes when the target data TD is transmitted from the information processing device 30A to the opposing device 30B.

[0046] <Operation of this embodiment> In the communication system 20, if the communication status is normal, the communication system 20 performs a series of processes as shown in Figure 5, and the target data TD is transmitted from the information processing device 30A to the opposing device 30B.

[0047] On the other hand, we will now explain a case where, for example, an abnormality occurs in the data link layer 42 of the information processing device 30A, causing flow control to fail and resulting in an abnormal communication state via the communication bus 50.

[0048] In this case, even if the information processing device 30A transmits a dataset DS containing the first divided data DD1 and the second divided data DD2 to the opposing device 30B, the opposing device 30B cannot properly receive the dataset DS. Therefore, the opposing device 30B does not transmit a reception completion signal MS to the information processing device 30A. As a result, the information processing device 30A makes a negative determination in the processing of step S14.

[0049] Then, the information processing device 30A determines that the communication status is abnormal through the processing in step S18, and cancels the transmission of the target data TD through the processing in step S19. As a result, the information processing device 30A does not transmit the third divided data DD3 to the sixth divided data DD6 to the opposing device 30B.

[0050] Therefore, while the first segmented data DD1 and the second segmented data DD2 remain in the receiving buffer of the opposing device 30B without being received, the third segmented data DD3 to the sixth segmented data DD6 are not stored in the receiving buffer of the opposing device 30B.

[0051] <Effects of this embodiment> (1) If the communication port 40 in the information processing device 30A enters an abnormal state and the dataset DS is not transmitted to the opposing device 30B, the direct storage control device 32 does not receive a reception completion signal MS from the opposing device 30B. In this case, the information processing device 30A stops transmitting the dataset DS, which includes the segmented data DD that has not been transmitted, to the opposing device 30B. Therefore, the information processing device 30A can prevent the transmission of an excessive amount of data to the opposing device 30B.

[0052] (2) When the direct storage control device 32 receives the reception completion signal MS, the direct storage control device 32 transmits the dataset DS, which includes the segmented data DD that has not been transmitted, to the opposing device 30B via the communication bus 50 connected to the communication port 40. Therefore, the information processing device 30A can transmit the next dataset DS after confirming that the dataset DS has been transmitted successfully.

[0053] (3) When the information processing device 30A does not receive a reception completion signal MS from the opposing device 30B, the direct storage control device 32 determines that the communication status is abnormal. This allows the information processing device 30A to understand the communication status.

[0054] (4) The capacity of the segmented data DD included in the dataset DS is less than or equal to the capacity that the opposing device 30B can receive via the communication bus 50. When the information processing device 30A transmits one dataset DS, it can prevent the opposing device 30B from being unable to receive the segmented data DD due to insufficient capacity.

[0055] (5) When the information processing device 30A receives a reception completion signal MS from the opposing device 30B, the direct storage control device 32 determines that the communication status is normal. This allows the information processing device 30A to understand the communication status.

[0056] <Example of changes> The above embodiment can be implemented with the following modifications. The above embodiment and the following modifications can be combined with each other to the extent that they do not contradict each other technically.

[0057] - If the direct storage control device 32 receives a reception completion signal MS within a specified time RT after it has transmitted a dataset DS, the direct storage control device 32 does not need to transmit the next dataset DS. For example, when the direct storage control device 32 transmits three consecutive datasets DS sequentially, it may transmit the third dataset DS only if it has received a reception completion signal MS for the segmented data DD included in the first dataset DS transmitted. In other words, the direct storage control device 32 may transmit the second dataset DS even if it has not received a reception completion signal MS for the segmented data DD included in the first dataset DS that preceded it.

[0058] The capacity of the partitioned data DD included in the dataset DS does not have to be less than the capacity that the opposing device 30B can receive via the communication bus 50. For example, the direct storage control device 32 may generate the dataset DS such that it includes a predetermined number of partitioned data DDs, regardless of capacity.

[0059] When the information processing device 30A does not receive a reception completion signal MS from the opposing device 30B, the direct storage control device 32 does not need to determine that the communication status is abnormal. In other words, the direct storage control device 32 may omit the processing in step S18.

[0060] When the information processing device 30A receives a reception completion signal MS from the opposing device 30B, the direct storage control device 32 does not need to determine that the communication status is normal. In other words, the direct storage control device 32 may omit the processing in step S15.

[0061] In the above embodiment, the direct storage control device 32 is the execution device, but the core 31 may also be the execution device. In other words, when the core 31 transmits the target data TD to the opposing device 30B without performing direct storage control, the core 31 may execute the series of processes shown in Figure 2. [Explanation of Symbols]

[0062] 10...Vehicle 20...Communication system 30A...Information processing device 30B...Opposite device 32...Direct memory control device 33...Memory device 40...Communication port 50...Communication bus DD...Divided data DS...Data set RT...Specified time TD...Target data

Claims

1. An information processing device that communicates with a counterpart device via a communication bus, The system comprises a communication port to which the aforementioned communication bus is connected, an execution device, and a storage device. The execution device is To generate a dataset that includes divided data obtained by dividing the target data to be transmitted from the data stored in the memory device into multiple parts, a signal requesting the storage of the divided data, and a signal requesting a reply when the reception of the divided data is complete. The process of sequentially transmitting multiple datasets from the communication port to the opposing device via the communication bus is initiated. If, after transmitting multiple datasets, a signal indicating completion of reception of the divided data is not received from the opposing device within a predetermined time, the transmission of the dataset containing the divided data that has not been transmitted to the opposing device is stopped. Information processing device.

2. When the execution device receives a signal from the opposing device indicating that the reception of the divided data has been completed within the specified time after the execution device has transmitted the dataset, the execution device transmits the dataset, including the divided data that has not yet been transmitted, to the opposing device via the communication bus connected to the communication port. The information processing apparatus according to claim 1.

3. If, after the execution device transmits the dataset, it does not receive a signal from the opposing device indicating that the reception of the divided data has been completed within the specified time, the execution device determines that the communication status via the communication bus from the communication port is abnormal. The information processing apparatus according to claim 1.

4. The capacity of the divided data included in the dataset is less than or equal to the capacity that the opposing device can receive via the communication bus. The information processing apparatus according to claim 1.

5. When the execution device receives a signal from the opposing device indicating that the reception of the divided data has been completed within the specified time after the execution device has transmitted the dataset, the execution device determines that the communication status via the communication bus from the communication port is normal. The information processing apparatus according to claim 1.

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