Information processing device

Abstract

The present invention provides an information processing device that suppresses delays in the timing of when target data reaches the opposing device, even if an abnormality occurs in communication via the first communication bus. [Solution] The execution device transmits the dataset DS to the opposing device via the first communication bus from the first communication port. If the execution device does not receive a signal from the opposing device indicating that the reception of the target data has been completed via the first communication bus within a specified time RT after transmitting the dataset DS, it transmits the dataset DS to the opposing device via the second communication bus from the second communication port.

Description

[[Technical Field]]

[0001] The present disclosure relates to an information processing apparatus. [[Background Art]]

[0002] Patent Literature 1 describes an information processing apparatus that performs communication using a PCI (Peripheral Component Interconnect) bus. The information processing apparatus recovers from a PCI bus failure. [[Prior Art Documents]] [[Patent Documents]]

[0003] [[Patent Document 1]] Japanese Unexamined Patent Application Publication No. 2009-116642 [[Summary of the Invention]] [[Problem to be Solved by the Invention]]

[0004] In the information processing apparatus as described in Patent Document 1, when a failure occurs in a bus, the information processing apparatus may be unable to transmit target data to be transmitted to a counter device as a transmission destination via the failed bus for a certain period of time. This causes a delay in the timing at which the target data arrives at the counter device which is the transmission destination. [[Means for Solving the Problem]]

[0005] An information processing device that solves the above problems is an information processing device that can communicate with a peer device via a first communication bus and can communicate with the peer device via a second communication bus separate from the first communication bus, and comprises a first communication port to which the first communication bus is connected, a second communication port to which the second communication bus is connected, an execution device, and a storage device, wherein the execution device performs the following: transmits a dataset including target data to be transmitted from the storage device and a signal requesting a reply when the reception of the target data is completed, from the first communication port via the first communication bus to the peer device; and if a signal indicating that the reception of the target data has been completed is not received from the peer device via the first communication bus within a predetermined time elapsed since the transmission of the dataset, transmits the dataset from the second communication port via the second communication bus to the peer device. [Effects of the Invention]

[0006] Even if an abnormality occurs in communication via the first communication bus, the information processing device can communicate via the second communication bus, thereby suppressing delays in the timing of when the target data reaches the opposing device. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a schematic diagram showing a vehicle equipped with a communication system according to one embodiment. [Figure 2] Figure 2 is a flowchart showing a series of processes performed by the execution device of the information processing apparatus according to this embodiment. [Figure 3] Figure 3 is a schematic diagram showing the dataset of the same embodiment. [Modes for carrying out the invention]

[0008] <One Embodiment> An embodiment of the information processing device will be described below with reference to the drawings. As shown in Figure 1, the vehicle 10 is equipped with a communication system 20 and multiple cameras 60. The communication system 20 acquires signals from each switch of the vehicle 10 and controls each actuator of the vehicle 10 based on the acquired signals.

[0009] The communication system 20 includes a plurality of communication devices 30. The plurality of communication devices 30 can communicate with each other in accordance with the PCIe standard via a first communication bus 51. PCIe stands for Peripheral Component Interconnect express. The plurality of communication devices 30 can also communicate with each other in accordance with the PCIe standard via a second communication bus 52, which is separate from the first communication bus 51.

[0010] The communication device 30 is an ECU that controls each actuator in the vehicle 10 and performs calculations based on values ​​obtained from each sensor in the vehicle 10. For example, one of the multiple communication devices 30 is a camera ECU. The camera ECU acquires images from multiple cameras 60 in the vehicle 10 and performs calculations to combine the acquired images from the multiple cameras 60 into a single image. Another example of the multiple communication devices 30 is an ADASECU. ADAS stands for Advanced Driver Assistance Systems. The ADASECU performs calculations to realize advanced safety functions based on time-series data of images acquired from the camera ECU. Examples of advanced safety functions include ACC (Adaptive Cruise Control System) and FCW (Forward Collision Warning).

[0011] In this embodiment, the multiple communication devices 30 consist of two devices: an information processing device 30A and a counterpart device 30B. The information processing device 30A is a camera ECU, and the counterpart device 30B is an ADASECU. Therefore, the information processing device 30A can communicate with the counterpart device 30B via the first communication bus 51 and also via the second communication bus 52.

[0012] The information processing device 30A functions as an endpoint, while the opposing device 30B functions as a root complex. This allows the information processing device 30A to communicate with the opposing device 30B in accordance with the PCIe standard.

[0013] The communication device 30 comprises an execution device 31, a direct memory control device 32, a storage device 33, a first communication port 41, a second communication port 42, and an IOMMU (Input / Output Memory Management Unit) 43. The execution device 31 is a CPU. Therefore, the execution device 31 includes processing circuits. The execution device 31 instructs the direct memory control device 32 to execute direct memory control in order to transmit target data TD to the opposing device 30B. The execution device 31 performs various calculations and controls by executing various programs stored in the storage device 33. For example, in the case of a communication device 30 that is a camera ECU, the execution device 31 performs calculations to synthesize images acquired from multiple cameras 60.

[0014] The direct memory control device 32 is a so-called DMAC (Direct Memory Access Controller). The direct memory control device 32 is a dedicated CPU for performing direct memory control. Direct memory control is the control of transmitting data stored in the memory device 33 to be stored in the memory device 33 of another communication device 30 that communicates with it.

[0015] The storage device 33 of the information processing device 30A stores the transmission program PR, the target data TD, the first parameter P1, the second parameter P2, and the counter value CP. The transmission program PR is a program that the execution device 31 is instructed to execute, and is a program that causes the execution device 31 to perform a series of processes, including the transmission of the target data TD.

[0016] The target data TD is data to be transmitted by the information processing apparatus 30A to the opposing apparatus 30B. The target data TD is data for which a deadline for completing transmission is specified. In other words, the target data TD is data for which real-time communication is required. Specifically, it is time-series data of images obtained by combining videos from the plurality of cameras 60 acquired by the information processing apparatus 30A.

[0017] The first parameter P1 is a parameter indicating a communication state with the opposing apparatus 30B via the first communication bus 51 using the first communication port 41. The first parameter P1 has a value indicating a connected state where communication is possible, or a value indicating a blocked state where communication is not possible.

[0018] The second parameter P2 is a parameter indicating a communication state with the opposing apparatus 30B via the second communication bus 52 using the second communication port 42. The second parameter P2 has a value indicating a connected state where communication is possible, or a value indicating a blocked state where communication is not possible.

[0019] The counter value CP is a parameter that defines the value of "#" in Done# transmitted between the information processing apparatus 30A and the opposing apparatus 30B, as will be described later. The counter value CP is an integer of 0 or greater.

[0020] The first communication port 41 is connected to the first communication bus 51. The first communication port 41 transmits and receives data during mutual communication. The first communication port 41 has a three-layer structure including a transaction layer, a data link layer, and a physical layer.

[0021] The transaction layer guarantees reliable end-to-end data communication for an upper software layer including upper drivers and application software. The data link layer is located between the transaction layer and the physical layer. The data link layer performs flow control. In flow control, the data link layer limits the transmission rate in accordance with the reception processing speed of the mutually communicating communication apparatus 30. The physical layer transmits and receives communication packets on a physical medium.

[0022] The second communication port 42 is a port different from the first communication port 41. The second communication port 42 is connected to the second communication bus 52. The second communication port 42 transmits and receives data during mutual communication. Like the first communication port 41, the second communication port 42 has a three-layer structure.

[0023] In the present embodiment, the first communication port 41 of the information processing apparatus 30A is connected to the first communication port 41 of the opposite apparatus 30B via the first communication bus 51. The second communication port 42 of the information processing apparatus 30A is connected to the second communication port 42 of the opposite apparatus 30B via the second communication bus 52.

[0024] The IOMMU 43 converts addresses included in various requests from another communication apparatus 30 that performs mutual communication. Specifically, the IOMMU 43 of the information processing apparatus 30A converts an address used by the opposite apparatus 30B into an address used internally by the information processing apparatus 30A.

[0025] Therefore, when acquiring a signal, the IOMMU 43 of the opposite apparatus 30B can recognize whether the signal is acquired from the first communication port 41 or the second communication port 42. Accordingly, the opposite apparatus 30B can return a reception completion signal MS, which will be described later, from the port that has acquired the signal requesting a return.

[0026] <On a Series of Processes Related to Transmission of Target Data> Hereinafter, a series of processes related to transmission of target data TD performed by the execution device 31 of the information processing apparatus 30A for the information processing apparatus 30A to transmit the target data TD to the opposite apparatus 30B will be described.

[0027] When the information processing apparatus 30A transmits the target data TD through real-time communication, the execution device 31 of the information processing apparatus 30A starts executing the transmission program PR. As shown in Figure 2, when the execution device 31 starts executing the transmission program PR, the execution device 31 first performs the process in step S11. In step S11, the execution device 31 generates the dataset DS.

[0028] As shown in Figure 3, the dataset DS includes target data TD and a reply request signal RDM that requests a reply when the reception of target data TD is complete. Target data TD has N data points for a predetermined time period, from the first data TD1 to the Nth data TDN. The target data TD is accompanied by a write signal, which is a write request to the address of the storage device 33 of the opposing device 30B.

[0029] The reply request signal RDM is Done#. The "#" is the counter value CP of "#" stored in the memory device 33, increased by 1. When the execution device 31 generates the reply request signal RDM, it refers to the counter value CP of "#" stored in the memory device 33. Done# is accompanied by a write signal, which is a write request to the address of the memory device 33 of the information processing device 30A. In other words, the reply request signal RDM is a signal that requests that the data set DS be transferred via the first communication bus 51, which was transmitted by the IOMMU 43 of the opposing device 30B.

[0030] As shown in Figure 2, after the execution device 31 creates the dataset DS, the execution device 31 proceeds to step S12. In step S12, the execution device 31 requests the direct storage control device 32 to transmit the dataset DS from the first communication port 41 via the first communication bus 51. As a result, the direct storage control device 32 transmits the dataset DS from the first communication port 41 via the first communication bus 51 to the opposing device 30B. After that, the execution device 31 proceeds to step S13.

[0031] In step S13, the execution device 31 determines whether the first communication port 41 has received a reception completion signal MS via the first communication bus 51 within a predetermined time RT after performing the processing in step S12. The predetermined time RT is determined in advance through testing and simulation to be sufficient time to obtain a reply from the opposing device 30B when communication is successful. The reception completion signal MS is a signal indicating that the opposing device 30B has completed receiving the target data TD included in the dataset DS. Specifically, the reception completion signal MS is Done# included in the dataset DS.

[0032] In detail, when the first communication port 41 of the information processing device 30A receives Done# as a reception completion signal MS transferred from the opposing device 30B, the IOMMU 43 of the information processing device 30A identifies the address to which Done# will be written. When the IOMMU 43 of the information processing device 30A identifies the storage device 33 of the information processing device 30A as the destination for Done#, it writes Done# to the storage device 33. As a result, the counter value CP stored in the storage device 33 is updated to a value that is 1 greater. Therefore, when the information processing device 30A receives a reply from the opposing device 30B after sending the dataset DS, the value of "#" is updated by increasing by one each time.

[0033] In step S13, the execution device 31 refers to the counter value CP stored in the storage device 33 and determines that the reception completion signal MS has been received if the counter value CP is updated to a value that is 1 greater before the specified time RT has elapsed. On the other hand, the execution device 31 refers to the counter value CP stored in the storage device 33 and determines that the reception completion signal MS has not been received if the counter value CP is not updated to a value that is 1 greater before the specified time RT has elapsed.

[0034] When the first communication port 41 receives a reception completion signal MS before the specified time RT has elapsed (S13: YES), the execution device 31 proceeds to step S14. In step S14, the execution device 31 determines that the communication status with the opposing device 30B via the first communication bus 51 using the first communication port 41 is normal. The execution device 31 then updates the first parameter P1, which indicates the connection status with the opposing device 30B via the first communication bus 51, to a connection status where communication is possible. After that, the execution device 31 terminates this series of processes.

[0035] On the other hand, if the first communication port 41 does not receive a reception completion signal MS before the specified time RT has elapsed (S13: NO), the execution device 31 proceeds to step S21. In step S21, the execution device 31 determines that the communication status with the opposing device 30B via the first communication bus 51 using the first communication port 41 is abnormal. The execution device 31 then updates the first parameter P1, which indicates the connection status with the opposing device 30B via the first communication bus 51, to a value indicating a blocked state where communication is not possible. After that, the execution device 31 proceeds to step S22.

[0036] In step S22, the execution device 31 requests the direct storage control device 32 to transmit the dataset DS generated in step S11 via the second communication bus 52 from the second communication port 42. As a result, the direct storage control device 32 transmits the dataset DS to the opposing device 30B via the second communication bus 52 from the second communication port 42. After that, the execution device 31 proceeds to step S23.

[0037] In step S23, the execution device 31 determines whether the second communication port 42 has received the reception completion signal MS via the second communication bus 52 within the time specified RT has elapsed since the processing in step S22.

[0038] When the second communication port 42 receives a reception completion signal MS before the specified time RT has elapsed (S23: YES), the execution device 31 proceeds to step S24. In step S24, the execution device 31 determines that the communication status with the opposing device 30B via the second communication bus 52 using the second communication port 42 is normal. The execution device 31 then updates the second parameter P2, which indicates the connection status with the opposing device 30B via the second communication bus 52, to a value indicating a connection status where communication is possible. After that, the execution device 31 terminates this series of processes.

[0039] On the other hand, if the second communication port 42 does not receive the reception completion signal MS within the specified time RT (S23: NO), the execution device 31 proceeds to step S31. In step S31, the execution device 31 determines that the communication status with the opposing device 30B via the second communication bus 52 using the second communication port 42 is abnormal. The execution device 31 then updates the second parameter P2, which indicates the connection status with the opposing device 30B via the second communication bus 52, to a value indicating a blocked state where communication is not possible. After that, the execution device 31 proceeds to step S32.

[0040] In step S32, the execution device 31 stops transmitting the target data TD required for real-time communication. After that, the execution device 31 terminates this series of processes. Assume that the first parameter P1 is a value indicating a disconnected state and the second parameter P2 is a value indicating a connected state. In this case, until the first parameter P1 is updated to the connected state, the information processing device 30A communicates with the opposing device 30B via the second communication bus 52 from the second communication port 42. Once the predetermined recovery process is completed, the first parameter P1 is updated from a value indicating a disconnected state to a value indicating a connected state.

[0041] <Operation of this embodiment> The following describes the case in the communication system 20 where communication via the first communication bus 51 is performed normally. When the data set DS is transmitted from the information processing device 30A to the opposing device 30B via the first communication bus 51, the IOMMU 43 of the opposing device 30B transfers the target data TD to the storage device 33 and also transfers Done# to the first communication port 41. The target data TD transferred to the storage device 33 is stored in the storage device 33 by a write operation. The Done# transferred to the first communication port 41 is transmitted to the information processing device 30A via the first communication bus 51 as a reception completion signal MS. When the information processing device 30A receives Done# as a reception completion signal MS, it updates the counter value CP. In this case, the target data TD is successfully received by the opposing device 30B, and the execution device 31 understands that the target data TD has been successfully received by the opposing device 30B.

[0042] Next, we will explain the case where a failure occurs in the first communication port 41 of the information processing device 30A in the communication system 20, and communication via the first communication bus 51 does not occur normally. The direct storage control device 32 transmits the dataset DS from the first communication port 41 to the opposing device 30B via the first communication bus 51. However, because the dataset DS does not reach the opposing device 30B, the IOMMU 43 cannot transfer the target data TD to the storage device 33 and Done# to the first communication port 41. As a result, the target data TD is not stored in the opposing device 30B. Also, Done#, which is the reception completion signal MS, is not transmitted from the opposing device 30B to the information processing device 30A. Therefore, the information processing device 30A makes a negative determination in step S13 and transmits the dataset DS from the second communication port 42 via the second communication bus 52. As a result, the dataset DS is transmitted from the information processing device 30A to the opposing device 30B via the second communication bus 52. If communication via the second communication bus 52 proceeds normally, the opposing device 30B receives the dataset DS. Subsequently, the target data TD is stored in the storage device 33, and a Done# signal is sent from the second communication port 42 to the information processing device 30A via the second communication bus 52 as a reception completion signal MS. In this case, the target data TD is successfully received by the opposing device 30B, and the information processing device 30A recognizes that the target data TD has been successfully received by the opposing device 30B.

[0043] <Effects of this embodiment> (1) Even if an abnormality occurs in communication via the first communication bus 51, the information processing device 30A transmits the target data TD via the second communication bus 52. This prevents the timing of the target data TD reaching the opposing device 30B from being excessively delayed.

[0044] (2) The storage device 33 stores a first parameter P1 that indicates the connection status with the opposing device 30B via the first communication bus 51. When the execution device 31 does not receive a reception completion signal MS from the opposing device 30B via the first communication bus 51 within a specified time RT after transmitting the dataset DS, it updates the first parameter P1 to a value indicating a blocked state. Therefore, the information processing device 30A can determine whether or not communication with the opposing device 30B via the first communication bus 51 is possible by referring to the first parameter P1.

[0045] (3) After the execution device 31 transmits the dataset DS to the opposing device 30B via the first communication bus 51, if it does not receive a reception completion signal MS, it transmits the dataset DS to the opposing device 30B via the second communication bus 52. Subsequently, if the second communication port 42 does not receive a reception completion signal MS from the opposing device 30B within the specified time RT, the execution device 31 stops transmitting the target data TD.

[0046] If communication via either the first communication bus 51 or the second communication bus 52 is not possible, the information processing device 30A will cancel the transmission of the target data TD. This prevents the information processing device 30A from retransmitting an excessive amount of data on the first communication bus 51 and the second communication bus 52.

[0047] (4) The target data TD is data for which a deadline has been set for completion of transmission. When the information processing device 30A performs communication for which a deadline has been set for completion of transmission, i.e., real-time communication, it can suppress excessive delays in the timing when the target data TD arrives at the opposing device 30B.

[0048] (5) The reply request signal RDM is a signal that requests the data set DS to be transmitted via the first communication bus 51 by the IOMMU 43 of the opposing device 30B. With the above configuration, for example, the reception completion signal MS can be quickly obtained using the functions of the IOMMU 43 without processing by the execution device 31 of the opposing device 30B. As a result, the specified time RT can be set to a reasonably short length, which prevents the time required for the information processing device 30A to confirm the reception completion signal MS from becoming excessively long due to the specified time RT becoming excessively long.

[0049] <Example of changes> The above embodiment can be implemented with the following modifications. The above embodiment and the following modifications can be combined with each other to the extent that they do not contradict each other technically.

[0050] The storage device 33 of the information processing device 30A does not need to store the first parameter P1. Also, the execution device 31 may omit the processing in steps S14 and S21. The storage device 33 of the information processing device 30A does not need to store the second parameter P2. Also, the execution device 31 may omit the processing in steps S24 and S31.

[0051] The execution device 31 does not have to perform the processing in step S32. In other words, the execution device 31 does not have to cancel the transmission of the target data TD when it does not receive a reception completion signal MS from the opposing device 30B via the second communication bus 52.

[0052] • The target data TD does not have to be data with a defined deadline for completion of transmission. In other words, the target data TD is not limited to data used in real-time communication. The reply request signal RDM does not necessarily have to be a signal requesting that the data set DS be transmitted via the first communication bus 51 by the IOMMU 43 of the opposing device 30B. For example, the reply request signal RDM may be a signal requesting that the execution device 31 of the opposing device 30B send a reply.

[0053] The ECUs of the information processing device 30A and the opposing device 30B are not limited to the examples of the above embodiment. The information processing device 30A may be, for example, an engine ECU or a multimedia ECU, as long as it is a communication device that communicates with the opposing device 30B. Similarly, the opposing device 30B may be, for example, a body ECU or a memory card, as long as it is a communication device that communicates with the information processing device 30A.

[0054] If the execution device 31 makes a negative determination in the processing of step S13, before processing in step S21, the execution device 31 may send a signal to the opposing device 30B requesting retransmission of the reception completion signal MS. Subsequently, when the first communication port 41 receives the reception completion signal MS from the opposing device 30B in response to the retransmission request, the execution device 31 may proceed to step S14.

[0055] The information processing device 30A may be configured as a circuit including one or more processors that execute various processes according to a computer program (software). Alternatively, the information processing device 30A may be configured as a circuit including one or more dedicated hardware circuits, such as application-specific integrated circuits (ASICs), or a combination thereof, that execute at least some of the various processes. The processor includes a CPU and memory such as RAM and ROM. The memory stores program code or instructions configured to cause the CPU to execute the processes. Memory, i.e., computer-readable media, includes any available media accessible by a general-purpose or dedicated computer. The same applies to the opposing device 30B. [Explanation of Symbols]

[0056] 10...Vehicle 20...Communication system 30...Communication device 30A...Information processing device 30B...Opposite device 31...Execution device 32...Direct memory control device 33...Memory device 41...First communication port 42...Second communication port 43...IOMMU 50...Camera 50...Communication bus 51...First communication bus 52...Second communication bus CP...Counter value DS...Data set MS...Received completion signal P1...First parameter P2...Second parameter PR...Transmission program RT...Specified time TD...Target data

Claims

1. An information processing device that is capable of communicating with a counterpart device via a first communication bus, and is also capable of communicating with the counterpart device via a second communication bus separate from the first communication bus, It comprises a first communication port to which the first communication bus is connected, a second communication port to which the second communication bus is connected, an execution device, and a storage device. The execution device is A dataset including the target data to be transmitted from the storage device and a signal requesting a reply when the reception of the target data is complete is transmitted from the first communication port to the opposing device via the first communication bus. If, within a predetermined time elapsed since the transmission of the dataset, a signal indicating that the reception of the target data has been completed is not received from the opposing device via the first communication bus, the dataset is transmitted from the second communication port to the opposing device via the second communication bus. Information processing device.

2. The storage device stores parameters indicating the connection status with the opposing device via the first communication bus. If the execution device does not receive a signal from the opposing device indicating that the reception of the target data has been completed via the first communication bus within the specified time elapsed since the transmission of the dataset, it updates the parameter to a value indicating a communication blockage state. The information processing apparatus according to claim 1.

3. The execution device, after transmitting the dataset to the opposing device via the second communication bus, will cancel the transmission of the target data if it does not receive a signal from the opposing device indicating that the reception of the target data has been completed via the second communication bus within the specified time. The information processing apparatus according to claim 1.

4. The aforementioned data is data for which a deadline has been set for completion of transmission. The information processing apparatus according to claim 1.

5. The signal requesting a reply upon completion of receiving the aforementioned target data is a signal requesting that the data set be transmitted via the first communication bus from which the IOMMU of the opposing device transmitted it. The information processing apparatus according to claim 1.

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