Semiconductor device and method for manufacturing a semiconductor device

Abstract

To improve the crystallinity of the channel layer. [Solution] The semiconductor device of the embodiment comprises a laminate in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one layer at a time, and a pillar extending within the laminate in the stacking direction of the laminate, wherein the pillar has a first semiconductor layer extending within the laminate in the stacking direction, and a second semiconductor layer projecting from the side wall of the first semiconductor layer toward the first insulating layer at a height position of the first insulating layer located near the center of the stacking direction of the laminate among the plurality of insulating layers.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] In three-dimensional non-volatile memory, multiple memory cells, each having a channel layer, are arranged along the height of a pillar that extends in the height direction. While the memory cell characteristics are improved by crystallizing the channel layer, incomplete crystallization can lead to variations in memory cell characteristics. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2013 / 0134492 [Patent Document 2] U.S. Patent Application Publication No. 2021 / 0104541 [Patent Document 3] U.S. Patent Application Publication No. 2023 / 0091210 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] One embodiment aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can improve the crystallinity of the channel layer. [Means for solving the problem]

[0005] The semiconductor device of the embodiment comprises a laminate in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one layer at a time, and a pillar extending within the laminate in the stacking direction of the laminate, wherein the pillar has a first semiconductor layer extending within the laminate in the stacking direction, and a second semiconductor layer projecting from the side wall of the first semiconductor layer toward the first insulating layer at a height position of the first insulating layer located near the center of the stacking direction of the laminate among the plurality of insulating layers. [Brief explanation of the drawing]

[0006] [Figure 1] A diagram showing a schematic example of the configuration of a semiconductor device according to an embodiment. [Figure 2] A cross-sectional view showing an example of the configuration of a semiconductor device according to an embodiment. [Figure 3] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 4] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 5] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 6] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 7] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 8] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 9] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 10] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 11] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 12] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 13]A diagram sequentially illustrating part of the steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 14] A diagram illustrating part of the steps of a method for manufacturing a semiconductor device according to a modification of the embodiment.

Mode for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited by the following embodiments. In addition, constituent elements in the following embodiments include those that can be easily conceived by a person skilled in the art or those that are substantially the same.

[0008] [Embodiment] Hereinafter, the embodiment will be described in detail with reference to the drawings.

[0009] (Configuration Example of Semiconductor Device) FIG. 1 is a diagram showing a schematic configuration example of a semiconductor device 1 according to the embodiment. More specifically, FIG. 1(a) is a cross-sectional view of the semiconductor device 1 taken along the X direction, and FIG. 1(b) is a schematic plan view showing the layout of the semiconductor device 1.

[0010] However, hatching is omitted in FIG. 1(a) for the sake of visibility of the drawing. In addition, in FIG. 1(a), components that do not necessarily exist in the same cross-section are shown, and some upper-layer wirings and the like are omitted.

[0011] In addition, in the present specification, both the X direction and the Y direction are directions along the plane orientation of a word line WL, and the X direction and the Y direction are orthogonal to each other. Further, the electrical lead-out direction of the word line WL may be referred to as a first direction, and this first direction is a direction along the X direction. Further, a direction intersecting the first direction may be referred to as a second direction, and this second direction is a direction along the Y direction. However, since the semiconductor device 1 may include manufacturing errors, the first direction and the second direction are not necessarily orthogonal to each other.

[0012] As shown in Figure 1(a), the semiconductor device 1 comprises, in order from the bottom of the paper, an electrode film EL, a source line SL, one or more selection gate lines SGS, multiple word lines WL, one or more selection gate lines SGD, and a semiconductor substrate SB on which peripheral circuits CBA are provided.

[0013] A source wire SL is arranged on the electrode film EL via an insulating layer 60. Multiple plugs PG are arranged in the insulating layer 60, and electrical conductivity is maintained between the source wire SL and the electrode film EL via the plugs PG. Although not shown in the diagram, electrode pads for supplying power and signals to the semiconductor device 1 from the outside are provided in the same layer as the electrode film EL. A selection gate wire SGS, multiple word wires WL, and a selection gate wire SGD are stacked on the source wire SL in this order.

[0014] As shown in Figures 1(a) and 1(b), a memory area MR is located in the center of multiple word lines WL in the X direction, and stepped areas SR are located at both ends of the multiple word lines WL in the X direction. These memory areas MR and stepped areas SR are divided into multiple regions by multiple plate-shaped contacts LI that penetrate the multiple word lines WL and extend in a direction along the X direction.

[0015] Furthermore, the area located between adjacent plate-shaped contacts LI in the Y direction, and including the memory area MR and the step area SR, is called the block area BLK. As will be described later, the memory area MR contains multiple memory cells that hold data non-volatilely, and the block area BLK described above serves as the unit for erasing this data.

[0016] Furthermore, between adjacent plate-shaped contacts LI in the Y direction, multiple isolation layers SHE are arranged, extending in the direction along the X direction and penetrating the selected gate line SGD. These multiple isolation layers SHE extend in the direction along the X direction throughout the entire memory area MR, and also reach a portion of the stepped area SR at both ends in the X direction.

[0017] In the memory region MR, multiple pillars PL are arranged that penetrate the word line WL and the selection gate lines SGD and SGS in the stacking direction. The lower end of the pillars PL reaches the source line SL. Multiple memory cells are formed at the intersections of the pillars PL and the word line WL. Thus, the semiconductor device 1 is configured as a three-dimensional non-volatile memory, for example, in which memory cells are arranged three-dimensionally in the memory region MR.

[0018] In the stepped region SR, multiple word lines WL and selection gate lines SGD and SGS are processed and terminated in a stepped manner. As we move away from the memory region MR in the X direction, the multiple word lines WL and selection gate lines SGD and SGS that make up the terrace section move from the upper layer to the lower layer, causing the height of the terrace section to decrease towards the source line SL.

[0019] In this specification, the direction in which the terrace surfaces of the multiple word lines WL and the selected gate lines SGD and SGS face is defined as the upper side of the semiconductor device 1.

[0020] The aforementioned isolation layer SHE extends from the memory region MR to the stepped portion of the step region SR where the selected gate line SGD is processed in a step-like manner. As a result, within a single block region BLK, the selected gate line SGD is separated into multiple regions. In other words, the isolation layer SHE penetrates the portion above multiple word lines WL, thereby dividing these upper portions into multiple patterns of selected gate line SGD.

[0021] Each terrace section of a layer, composed of multiple word lines WL and selection gate lines SGD and SGS, has contact CCs connected to the word lines WL and selection gate lines SGD and SGS of each layer. One contact CC is connected to each layer of the word lines WL and selection gate lines SGS. For the selection gate lines SGD, one contact CC is connected to each section separated by the isolation layer SHE per layer.

[0022] Here, within a single block region BLK, multiple contacts CC are positioned on one side of the staircase region SR on both sides in the X direction. Also, looking at one side in the X direction, for example, multiple contacts CC are positioned every two block regions BLK.

[0023] In other words, in the example shown in Figure 1(b), in the block region BLK at the very top of the page, multiple contact CCs are located in the stair region SR on the left side of the page, among the stair regions SR at both ends in the X direction. Furthermore, in the block region BLK one level below and two levels below the above block region BLK, multiple contact CCs are located in the stair region SR on the right side of the page, among the stair regions SR at both ends in the X direction. Moreover, in the block region BLK at the very bottom of the page, multiple contact CCs are again located in the stair region SR on the left side of the page.

[0024] Therefore, as shown in Figure 1(a), the respective contact CCs of the stair region SR at both ends in the X direction belong to different block regions BLK and are not actually located in the same cross-section.

[0025] These contact CCs allow individual stacked word lines WLs to be drawn out. More specifically, these contact CCs apply write voltages and read voltages to memory cells included in the memory region MR at the center of multiple word lines WLs, via word lines WLs located at the same height as the memory cells.

[0026] Multiple word lines WL, selection gate lines SGD, SGS, pillar PL, and contact CC are covered by an insulating layer 50. The insulating layer 50 also extends around these components, including the multiple word lines WL, etc.

[0027] The semiconductor substrate SB above the insulating layer 50 covering the above configuration is, for example, a silicon substrate. Peripheral circuits CBA, including transistors TR and wiring, are arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cell from the contacts CC are controlled by the peripheral circuits CBA that are electrically connected to these contacts CC. In this way, the peripheral circuits CBA control the electrical operation of the memory cell.

[0028] The peripheral circuit CBA is covered with an insulating layer 40, and by joining this insulating layer 40 with an insulating layer 50 that covers multiple word lines WL, etc., a semiconductor device 1 is formed that includes multiple word lines WL, selection gate lines SGD, SGS, pillar PL, contact CC, etc., and the peripheral circuit CBA.

[0029] Next, a detailed example of the configuration of the semiconductor device 1 will be described using Figure 2. Figure 2 is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the embodiment.

[0030] More specifically, Figure 2(a) is a cross-sectional view along the Y direction in the memory region MR of the semiconductor device 1. In Figure 2(a), the structure below the insulating layer 60 and above the insulating layer 53, which will be described later, is omitted.

[0031] Figure 2(b) is an enlarged cross-sectional view of the pillar PL at the height of the selected gate wires SGD and SGS. Figure 2(c) is an enlarged cross-sectional view of the pillar PL at the height of the word wire WL. Figure 2(d) is an enlarged cross-sectional view of the pillar PL at the height of the insulating layer OLm.

[0032] As shown in Figure 2(a), the source wire SL has a multilayer structure in which, for example, a lower source wire DSLa, an intermediate source wire BSL, and an upper source wire DSLb are stacked in this order on an insulating layer 60. The lower source wire DSLa, the intermediate source wire BSL, and the upper source wire DSLb are, for example, polysilicon layers. Of these, at least the intermediate source wire BSL may be a conductive polysilicon layer in which impurities have been diffused.

[0033] The source wire SL is connected to the peripheral circuit CBA via the electrode film EL through a through-contact (not shown) that extends from the electrode film EL to the peripheral circuit CBA, within the aforementioned insulating layer 50 on the outside of the laminate LM.

[0034] A laminate LM is placed on the source line SL. The laminate LM comprises laminates LMa and LMb, in which multiple word lines WL and multiple insulating layers OL are alternately stacked one layer at a time.

[0035] The LMa laminate is positioned above the source line SL. Below the bottommost word line WL of the LMa laminate, multiple selectable gate lines SGS0 and SGS1 are arranged in this order from the top of the LMa laminate, via an insulating layer OL. The LMb laminate is positioned on top of the LMa laminate. Above the topmost word line WL of the LMB laminate, multiple selectable gate lines SGD0 and SGD1 are arranged in this order from the top of the LMB laminate, via an insulating layer OL.

[0036] However, the number of layers of these word lines WL and selective gate lines SGD,SGS in the laminate LM is arbitrary. The word lines WL and selective gate lines SGD,SGS are, for example, tungsten layers or molybdenum layers. The insulating layer OL is, for example, a silicon oxide layer.

[0037] As shown in Figure 2(d), the laminate LM contains one or more insulating layers OLm. The insulating layer OLm is a layer in which an insulating layer OLb, having a different layer quality from the insulating layer OLa, is interposed between insulating layers OLa, which are silicon oxide layers, etc.

[0038] More specifically, the insulating layer OLb is, for example, a silicon oxycarbide (SiOC) layer, a silicon germanium (SiGe) layer, or a silicon oxide (SiOx) layer with a lower density than the insulating layer OLa. As a result, the insulating layer OLb has lower resistance to dry etching, wet etching, etc., than the insulating layer OLa.

[0039] Furthermore, the insulating layer OLm, as a whole, has a thickness equal to or greater than the thickness of the other insulating layer OL, and no more than twice the thickness of the other insulating layer OL. The insulating layer OLb has a thickness of 50% to 80% of the thickness of the insulating layer OLm, and as an example, a thickness of 20 nm to 50 nm.

[0040] Such insulating layer OLm is included in place of the insulating layer OL described above, at least near the center in the lamination direction of the laminate LM, sandwiched vertically by word lines WL. However, the laminate LM may contain multiple insulating layers OLm, in which case it is preferable that they are scattered at predetermined intervals in the lamination direction of the laminate LM.

[0041] As shown in Figure 2(a), the upper surface of the laminate LM is covered in this order by insulating layers 52 and 53. Insulating layers 52 and 53 each constitute a part of the insulating layer 50 in Figure 1.

[0042] As described above, the laminate LM is divided in the Y direction by multiple plate-like contacts LI. That is, each plate-like contact LI is aligned with the others in the Y direction and extends in a direction along the stacking direction and the X direction of the laminate LM.

[0043] Thus, the plate-shaped contact LI extends continuously within the laminate LM from one end in the X direction to the other end. Furthermore, the plate-shaped contact LI penetrates the laminate LM and the upper source line DSLb, and reaches the intermediate source line BSL in the memory region MR.

[0044] Furthermore, the plate-shaped contact LI may have a tapered shape in which its width in the Y direction decreases from the upper end to the lower end, for example. Alternatively, the plate-shaped contact LI may have a bowing shape in which its width in the Y direction is maximum at a predetermined position between the upper end and the lower end.

[0045] Each plate-shaped contact LI includes an insulating layer 54 and a conductive layer 24. The insulating layer 54 is, for example, a silicon oxide layer. The conductive layer 24 is, for example, a tungsten layer or a conductive polysilicon layer.

[0046] The insulating layer 54 covers the side walls of the plate-shaped contact LI that face each other in the Y direction. The conductive layer 24 is filled further inside the insulating layer 54 that covers the side walls of the plate-shaped contact LI and is electrically connected to the source wire SL, including the intermediate source wire BSL.

[0047] However, instead of the plate-shaped contact LI, a plate-shaped member filled with an insulating layer may penetrate the laminate LM and extend in a direction along the X direction, thereby dividing the laminate LM in the Y direction.

[0048] Between adjacent plate-shaped contacts LI in the Y direction, multiple isolation layers SHE are arranged, extending in the direction along the X direction and penetrating the upper portion of the laminate LMb. These isolation layers SHE are insulating layers 56 such as silicon oxide layers that penetrate the selection gate lines SGD0 and SGD1 and reach the insulating layer OL directly below the selection gate line SGD1.

[0049] In other words, these separation layers SHE, which penetrate the upper portion of the laminated LMb, extend in the X direction between the plate-shaped contacts LI, dividing the upper portion of the laminated LMb into the aforementioned selected gate lines SGD0 and SGD1.

[0050] In the memory region MR, multiple pillars PL are distributed and arranged, penetrating the stacked structure LM, the upper source line DSLb, and the intermediate source line BSL, and reaching the lower source line DSLa.

[0051] Multiple pillars PL are arranged, for example, in a staggered pattern when viewed from the stacking direction of the laminate LM. Each pillar PL has a cross-sectional shape in the direction along the layering direction of the laminate LM, i.e., along the XY plane, such as a circular, elliptical, or oval shape.

[0052] Furthermore, the pillar PL has a tapered shape in the portion that penetrates the laminate LMa and the portion that penetrates the laminate LMb, where the diameter and cross-sectional area decrease from the upper layer side to the lower layer side. Alternatively, the pillar PL has a bowing shape in the portion that penetrates the laminate LMa and the portion that penetrates the laminate LMb, where the diameter and cross-sectional area are maximized at a predetermined position between the upper and lower layers, for example.

[0053] Each of the multiple pillar PLs has a memory layer ME extending in the stacking direction within the laminate LM, a channel layer CN extending in the stacking direction within the laminate LM inside the memory layer ME, a cap layer CP covering the upper surface of the channel layer CN, and a core layer CR which serves as the core material of the pillar PL.

[0054] The channel layer CN is in direct contact with the intermediate source line BSL at the depth of the intermediate source line BSL. That is, the memory layer ME is located on the side of the pillar PL, excluding the depth of the intermediate source line BSL. The memory layer ME is also located on the bottom surface of the pillar PL, which reaches the depth of the lower source line DSLa.

[0055] As a result, the channel layer CN is in contact with the intermediate source line BSL on its side, and further, electrically connected to the entire source line SL via the intermediate source line BSL.

[0056] The cap layer CP is positioned at the upper end of the pillar PL so as to cover at least the upper end of the channel layer CN and is connected to the channel layer CN. Furthermore, the cap layer CP is connected to the bit wire BL located in the insulating layer 53 via a plug CH located in the uppermost insulating layer OL, 52 of the laminate LM. The bit wire BL extends above the laminate LM in a direction along the Y direction so as to intersect with the drawing direction of the word wire WL.

[0057] As shown in Figures 2(b) and 2(c), the memory layer ME has a laminated structure including a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN, in that order from the outer periphery of the pillar PL. The block insulating layer BK and tunnel insulating layer TN of the memory layer ME, as well as the core layer CR, are, for example, silicon oxide layers. The charge storage layer CT is, for example, a silicon nitride layer.

[0058] The channel layer CN is a highly crystalline semiconductor layer, such as a single-crystal silicon layer. However, the channel layer CN may contain polycrystalline silicon in part. Even in this case, it is preferable that the channel layer CN has single-crystal silicon as its main component. Furthermore, the channel layer CN may contain at least one of nitrogen, boron, and carbon as an additive.

[0059] The cap layer CP is, for example, a single-crystal semiconductor layer or a polycrystalline semiconductor layer such as a polysilicon layer. If the cap layer CP is a single-crystal semiconductor layer, it may contain a polycrystalline semiconductor layer in part, and if the cap layer CP is a polycrystalline semiconductor layer, it may contain an amorphous semiconductor such as amorphous silicon in part.

[0060] As shown in Figure 2(c), with the above configuration, memory cells MC are formed in the portions of the pillar PL side surface that face each word line WL. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word line WL.

[0061] As shown in Figure 2(b), selection gate STD is formed on the side of pillar PL where it faces selection gate lines SGD0 and SGD1. Additionally, selection gate STS is formed on the side of pillar PL where it faces selection gate lines SGS0 and SGS1, which are lower than the word line WL.

[0062] By applying predetermined voltages to the selection gate lines SGD and SGS, respectively, the selection gates STD and STS can be turned on or off, thereby selecting or deselecting the memory cell MC of the pillar PL to which the selection gates STD and STS belong.

[0063] As shown in Figure 2(d), at the height of the insulating layer OLm, the semiconductor layer CS protrudes into the insulating layer OLb from the side surface of the channel layer CN. That is, one or more semiconductor layers CS are provided on the side surface of the channel layer CN, corresponding to the number and position of the insulating layer OLm in the laminate LM.

[0064] Furthermore, as described above, the memory layer ME covers the sides of the channel layer CN and continuously covers the upper and lower surfaces of the semiconductor layer CS that protrudes into the insulating layer OLb, as well as the surface facing the insulating layer OLb. As a result, the semiconductor layer CS that protrudes into the insulating layer OLb has a thickness of 15% to 25% of the thickness of the insulating layer OLb, depending on the thickness of the memory layer ME, for example, a thickness of 5 nm to 9 nm.

[0065] The semiconductor layer CS is a semiconductor layer with lower crystallinity than the channel layer CN, such as a polycrystalline silicon layer. However, the semiconductor layer CS may contain a portion of single-crystal or amorphous silicon. Even in this case, the semiconductor layer CS has polycrystalline silicon as its main component. Furthermore, the semiconductor layer CS has a different crystal orientation than the channel layer CN, which has single-crystal semiconductor as its main component.

[0066] (Method of manufacturing semiconductor devices) Next, the manufacturing method of the semiconductor device 1 according to the embodiment will be described using Figures 3 to 13. Figures 3 to 13 are diagrams illustrating, in order, some of the steps of the manufacturing method of the semiconductor device 1 according to the embodiment. Note that Figures 3 to 13, excluding Figures 8 and 9, show cross-sections along the Y direction of the region that will later become the memory region MR. Figures 8 and 9 are partially enlarged cross-sectional views at the height position of the insulating layer OLm of the pillar PL during manufacturing.

[0067] As shown in Figure 3(a), the lower source line DSLa, the intermediate sacrificial layer SCN, and the upper source line DSLb are formed on the support substrate SS in this order.

[0068] As the support substrate SS, a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate can be used. The insulating layer 60 described above (see Figure 2(a), etc.) may be formed on the upper surface of the support substrate SS. The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, which is later replaced with a polysilicon layer or the like to become the intermediate source line BSL.

[0069] On the upper source line DSLb, a laminate LMsa is formed by alternately stacking multiple insulating layers NL and multiple insulating layers OL, one layer at a time. The insulating layer NL is, for example, a silicon nitride layer and functions as a sacrificial layer that will later be replaced by a conductive material to become the word line WL or the selected gate line SGS.

[0070] Although not shown in the diagram, in a portion of the laminated LMsa, the insulating layer NL and insulating layer OL are processed in a stepped manner. This processing can be achieved by repeatedly slimming the mask pattern of the photoresist layer, etc., and etching the insulating layer NL and insulating layer OL of the laminated LMsa.

[0071] Specifically, a mask pattern is formed on the upper surface of the laminated LMsa, and the insulating layer NL and insulating layer OL in the exposed areas are etched away one layer at a time. Then, the edges of the mask pattern are receded by treatment with oxygen plasma or the like, exposing the upper surface of the laminated LMsa, and the insulating layer NL and insulating layer OL are etched away one layer at a time again. By repeating this process multiple times, a laminated LMsa with a stepped shape at both ends in the X direction is formed.

[0072] Subsequently, the stepped shape at both ends in the X direction is covered with a portion of the insulating layer 50 (see Figure 1(a)) described above.

[0073] As shown in Figure 3(b), the laminate LMsa forms multiple memory holes MHa extending in the stacking direction. These multiple memory holes MHa penetrate the laminate LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa. These memory holes MHa later become the substructure of the pillar PL.

[0074] As shown in Figure 3(c), these memory holes MHa are filled with a sacrificial layer 26, such as an amorphous silicon layer or a CVD-carbon layer. This forms a pillar PLc in which multiple memory holes MHa are filled with the sacrificial layer 26.

[0075] As shown in Figure 4(a), the laminate LMsa is covered, and a laminate LMsb is formed by alternately stacking multiple insulating layers NL and multiple insulating layers OL one layer at a time. The insulating layers NL of the laminate LMsb function as sacrificial layers that are later replaced by conductive layers to become word lines WL or selected gate lines SGD.

[0076] Furthermore, in at least one of the formation processes of the laminate LMsa shown in Figure 3(a) and the laminate LMsb shown in Figure 4(a), one or more insulating layers OLm (see Figure 2(d)) are interposed between the insulating layers NL instead of the insulating layer OL.

[0077] In this case, the insulating layer OLa can be formed using chemical vapor deposition (CVD) or the like, under the same conditions as other insulating layers OL.

[0078] When forming an insulating layer OLb, for example, a silicon oxycarbide layer, the insulating layer OLb can be interposed within the insulating layer OLa by adding carbon during the process. When forming an insulating layer OLb, for example, a silicon germanium layer, the insulating layer OLb can be interposed within the insulating layer OLa by depositing a film using silicon and germanium as materials during the process. When forming an insulating layer OLb, for example, a low-density silicon oxide layer, the insulating layer OLb can be interposed within the insulating layer OLa by changing the film deposition conditions during the process to reduce the layer density.

[0079] Although not shown in the diagram, a portion of the laminate LMsb is processed in a stepwise manner, altering the insulating layer NL and insulating layer OL. This processing can be achieved by repeatedly performing the same steps as the processing for the laminate LMsa described above: slimming the mask pattern of the photoresist layer, etc., and etching the insulating layer NL and insulating layer OL of the laminate LMsb.

[0080] At this time, the uppermost step of the stair section formed on the laminated LMsa and the lowermost step of the stair section formed on the laminated LMsb are brought into close proximity to form a stair shape that extends continuously from the lower layer of the laminated LMsa to the upper layer of the laminated LMsb. As a result, the laminated LMsa and LMsb are formed with a stair region SR having a stair shape extending from the laminated LMsa to the laminated LMsb, with the stair region SR formed at both ends in the X direction.

[0081] Subsequently, the stepped shape at both ends in the X direction is further covered with a portion of the insulating layer 50 (see Figure 1(a)) described above.

[0082] As shown in Figure 4(b), multiple memory holes MHb are formed that penetrate the laminate LMsb and connect to multiple pillars PLc that have already been formed within the laminate LMsa. The memory holes MHb are the parts that will later become the upper structure of the pillars PL.

[0083] As shown in Figure 5(a), the sacrificial layer 26 is removed from the pillar PLc at the bottom of the memory hole MHb. As a result, multiple memory holes MHa open at the bottom of multiple memory holes MHb, and multiple memory holes MH are formed that penetrate the laminate LMsb, LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa.

[0084] Furthermore, if the sacrificial layer 26 filled inside the pillar PLc is a CVD-carbon layer or the like, the sacrificial layer 26 can be removed from these pillar PLc all at once when the mask pattern used to form the memory holes MHb in Figure 4(b) above is removed by ashing using oxygen plasma or the like.

[0085] As shown in Figure 5(b), a memory layer ME is formed on the side wall of the memory hole MH and on the bottom surface where the lower source line DSLa is exposed, in the order of block insulating layer BK, charge storage layer CT, and tunnel insulating layer TN (see Figures 2(b) and 2(c)), starting from the side wall side of the memory hole MH. The memory layer ME is also formed on the top surface of the laminate LMsb.

[0086] Furthermore, the channel layer CNa and the core layer CR are formed in this order within the memory hole MH. As a result, the channel layer CN is formed on the memory layer ME that covers the sides and bottom of the memory hole MH, and the core layer CRa is filled into the center of the memory hole MH. The channel layer CNa and the core layer CR are also formed in this order on the upper surface of the laminate LMsb via the memory layer ME.

[0087] The channel layer CNa is a semiconductor layer that will later become the channel layer CN. At this point, the entire channel layer CNa is an amorphous semiconductor layer, such as an amorphous silicon layer. In the above, at least one of nitrogen, boron, or carbon may be added to the channel layer CNa.

[0088] As shown in Figure 6(a), the core layer CR formed on the upper surface of the laminate LMsb is etched back and removed, and the core layer CR inside the memory hole MH is receded to form a recess DN at the upper end of the memory hole MH.

[0089] As shown in Figure 6(b), a cap layer CPa is formed in the recess DN described above. In this case, the cap layer CPa may be an amorphous semiconductor layer such as an amorphous silicon layer, similar to the channel layer CNa. The cap layer CPa is also formed on the upper surface of the laminate LMsb via the memory layer ME and the channel layer CNa.

[0090] Subsequently, the channel layer CNa and the cap layer CPa undergo crystallization, forming, for example, single crystals of the channel layer CN and cap layer CP.

[0091] As shown in Figure 7(a), the cap layer CP, channel layer CN, and memory layer ME on the upper surface of the laminated LMsb are removed by CMP or the like, along with a portion of the insulating layer OL on the top layer of the laminated LMsb.

[0092] As shown in Figure 7(b), the insulating layer OL on the top layer of the laminated LMsb, which has been thinned by CMP or the like, is stacked again. This forms a pillar PL in which the cap layer CP is embedded in the insulating layer OL on the top layer. However, at this point, the memory layer ME covers the entire side wall of the pillar PL, and no part of the side of the channel layer CN is exposed from the memory layer ME.

[0093] Furthermore, when forming the memory layer ME, channel layer CNa, and core layer CR within the memory hole MH, the formation of the semiconductor layer CS protruding from the sidewall of the channel layer CNa is carried out in parallel. Also, as described above, after the formation of the cap layer CPa, crystallization of the channel layer CNa and the cap layer CPa is performed.

[0094] Figures 8 and 9 below show detailed examples of methods for forming the memory layer ME, channel layer CNa, and core layer CR, including the formation of the semiconductor layer CS, as well as methods for crystallizing the channel layer CNa, etc.

[0095] Figure 8(a) shows how memory holes MH are formed through the laminates LMsa and LMsb, which include the insulating layer OLm. As described above, the insulating layer OLm has a structure in which the insulating layer OLb is inserted into the insulating layer OLa, and the thickness of the insulating layer OLb is, for example, 50% to 80% of the total thickness of the insulating layer OLm.

[0096] As shown in Figure 8(b), the inside of the memory hole MH is processed using dry etching or wet etching. In this case, wet etching proceeds isotropically, and when dry etching is used, isotropic etching is performed by selecting a plasma source or adjusting the etching conditions.

[0097] As described above, the insulating layer OLb has lower etching resistance than the insulating layers OL and OLa. Therefore, as a result of the above treatment, the insulating layer OLb in the insulating layer OLm recedes by approximately equal distances from the side wall of the memory hole MH toward the periphery, and a recess RS is formed on the side wall of the memory hole MH, sandwiched between the receding end face of the insulating layer OLb and the insulating layer OLa in the vertical direction of the insulating layer OLb.

[0098] As shown in Figure 8(c), a memory layer ME is formed which includes, in this order, a block insulating layer BK covering the side wall of the memory hole MH, a charge storage layer CT, and a tunnel insulating layer TN. In this case, the memory layer ME continuously covers the side wall of the memory hole MH, the upper and lower surfaces within the recess RS, and the end face of the insulating layer OLb.

[0099] As shown in Figure 8(d), a semiconductor layer CS is formed by filling the recess RS with a polysilicon layer or the like. More specifically, a polysilicon layer or the like can be formed to cover the entire sidewall of the memory hole MH, including the portion of the recess RS, and the semiconductor layer CS filled in the recess RS can be formed by removing the polysilicon layer from the sidewall of the memory hole MH. In this case, the semiconductor layer CS is a polycrystalline semiconductor layer such as a polysilicon layer as described above. However, the semiconductor layer CS may also contain an amorphous semiconductor, such as an amorphous silicon layer, in part.

[0100] Since the size of the recess RS is reduced by the memory layer ME formed within the recess RS, the thickness of the semiconductor layer CS is, for example, 15% to 25% of the thickness of the insulating layer OLb.

[0101] As shown in Figure 8(e), a channel layer CNa is formed that covers the entire side wall of the memory hole MH. In this case, the channel layer CNa is an amorphous semiconductor layer, such as an amorphous silicon layer, as described above.

[0102] As shown in Figure 8(f), a metallic element such as nickel is introduced into the channel layer CNa. The introduction of a metallic element into the channel layer CNa can be achieved, for example, by forming a metallic layer on the channel layer CNa using chemical vapor deposition (CVD) or electroplating.

[0103] As shown in Figure 9(a), metallic elements such as nickel introduced into the channel layer CNa are randomly diffused within the channel layer CNa. Some of these may be silicided to form silicide NS such as nickel silicide.

[0104] In this state, the voids inside the memory holes MH are filled with a silicon oxide layer or the like to form the core layer CR.

[0105] Subsequently, as shown in Figures 6(a) and 6(b) above, the core layer CR formed on the upper surface of the laminate LMsb is etched back and removed, and the core layer CR inside the memory hole MH is retracted to form a recess DN at the upper end of the memory hole MH. A cap layer CPa, such as an amorphous silicon layer, is then formed in this recess DN.

[0106] As shown in Figure 9(b), the support substrate SS is heated to a predetermined temperature and the entire structure is annealed. At this time, the annealing temperature is set to a low temperature, for example, low enough that crystallization of the channel layer CNa does not occur.

[0107] On the other hand, at the interface between the semiconductor layer CS, such as a polysilicon layer, and the channel layer CNa, such as an amorphous silicon layer, the activation energy required for silicide NS formation decreases, making silicide NS formation easier. Furthermore, if the channel layer CNa contains additives such as nitrogen, boron, or carbon, these additives also facilitate the formation of silicide NS.

[0108] Therefore, silicide NS aggregates at the interface between the semiconductor layer CS and the channel layer CNa. These silicide NS molecules promote the crystallization of the channel layer CNa. In other words, silicide NS functions as a catalyst for the crystallization of the channel layer CNa.

[0109] As shown in Figure 9(c), due to the aggregation of silicide NS, crystallization of the channel layer CNa, which is such as an amorphous silicon layer, progresses in the vertical direction of the laminates LMsa and LMsb, starting from the interface between the semiconductor layer CS and the channel layer CNa.

[0110] At this time, some of the silicide NS that catalyzed the crystallization of the channel layer CNa are fragmented into metal fragments NSf and diffuse into the channel layer CNa. The channel layer CNa in the areas into which the metal fragments NSf have entered is transformed into the aforementioned channel layer CN, which is, for example, a single-crystal silicon layer.

[0111] Thus, the process of crystallizing the channel layer CNa by low-temperature annealing using silicide NS or the like as a catalyst is also called metal-assisted annealing.

[0112] Furthermore, this type of crystallization does not occur within the semiconductor layer CS, which is originally a polysilicon layer or the like. Therefore, the semiconductor layer CS, which was originally a polysilicon layer or the like, and the channel layer CN, which underwent crystallization through metal-assisted annealing, end up having different crystal orientations.

[0113] As shown in Figure 9(d), the crystallization of the channel layer CNa progresses, and the entire channel layer CNa becomes, for example, a single-crystal channel layer CN, thus completing the metal-assisted annealing process. At this time, if the cap layer CPa was formed as an amorphous semiconductor layer, the cap layer CPa may also crystallize and become a single-crystal cap layer CP.

[0114] However, the channel layer CN and the capping layer CP may contain polycrystalline semiconductors due to partial incomplete crystallization or other reasons.

[0115] Furthermore, even when multiple insulating layers OLm are formed in the laminates LMsa and LMsb, grain boundaries can be generated in the channel layer CN at height positions between these insulating layers OLm. That is, since the crystallization of the channel layer CNa progresses vertically starting from the height position of each insulating layer OLm, the channel layer CN, such as a single crystal, extending from the height position of the upper insulating layer OLm joins with the channel layer CN, such as a single crystal, extending from the height position of the lower insulating layer OLm, and grain boundaries can be generated at these interfaces.

[0116] As described above, even if a portion of the channel layer CN contains grain boundaries or polycrystalline semiconductors, a channel layer CN mainly composed of single-crystal semiconductors can be formed by annealing using metal assistance starting from the interface between the semiconductor layer CS and the channel layer CNa.

[0117] Furthermore, as described above, by positioning the semiconductor layer CS, which serves as the starting point for crystallization in the channel layer CNa, at any position within the laminate LM, it becomes possible to control the crystallization starting point and grain boundary positions within the channel layer CNa.

[0118] As shown in Figure 9(e), metal fragments NSf are segregated in the channel layer CN. A gettering layer GT, such as an amorphous silicon layer, is formed on the upper surface of this channel layer CN.

[0119] As shown in Figure 9(f), annealing causes the metal fragments NSf that were segregated in the channel layer CN to move into the gettering layer GT. This makes it possible to remove most of the metal fragments NSf from the channel layer CN.

[0120] Afterward, the gettering layer GT is removed.

[0121] As a result, a channel layer CN, which is a semiconductor layer such as a single crystal, is formed.

[0122] Furthermore, in annealing using metal assistance, crystallization is more easily promoted when the layer to be crystallized is thicker. Therefore, the channel layer CNa described above may be formed thicker than the channel layer CN that will ultimately be present in the pillar PL, and crystallization may be carried out.

[0123] If the channel layer CNa is formed thickly, after crystallizing the channel layer CNa, the cap layer CP and core layer CR can be removed, and the channel layer CN exposed in the memory hole MH can be slimmed down to the desired thickness. Then, the core layer CR is formed again in the memory hole MH, and the cap layer CP is formed on the upper end of the core layer CR, etc. The cap layer CP formed in this way is a polycrystalline semiconductor layer, such as a polysilicon layer. At this time, the cap layer CP may contain an amorphous semiconductor such as amorphous silicon in part.

[0124] Thus, even if amorphous silicon or the like is included in a portion of the cap layer CP, or if an amorphous silicon layer or the like is included in a portion of the semiconductor layer CS formed as a polysilicon layer, the cap layer CP and semiconductor layer CS may undergo various thermal histories due to subsequent processing in the manufacturing process of the semiconductor device 1. Therefore, the proportion of amorphous portions in these cap layer CP and semiconductor layer CS may be further reduced, or even disappear in the final semiconductor device 1.

[0125] As shown in Figure 10(a), a slit ST is formed that penetrates the laminates LMsb and LMsa, on which the pillar PL is formed, and the upper source wire DSLb, reaching the intermediate sacrificial layer SCN. In addition, an insulating layer 54s is formed on the side walls of the slit ST facing in the Y direction. The slit ST also extends along the X direction within the laminates LMsa and LMsb.

[0126] As shown in Figure 10(b), a removal solution for the intermediate sacrificial layer SCN, such as thermal phosphoric acid, is introduced through the slit ST, whose sidewalls are protected by the insulating layer 54s, to remove the intermediate sacrificial layer SCN sandwiched between the lower source wire DSLa and the upper source wire DSLb.

[0127] As a result, a gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. In addition, a portion of the memory layer ME on the outer periphery of the pillar PL is exposed within the gap layer GPs. At this time, since the sidewall of the slit ST is protected by the insulating layer 54s, the removal of the insulating layer NL within the laminates LMsa and LMsb is suppressed.

[0128] As shown in Figure 11(a), chemical solutions are introduced into the gap layer GPs through the slit ST as needed to sequentially remove the block insulating layer BK, charge storage layer CT, and tunnel insulating layer TN (see Figures 2(b) and 2(c)) of the memory layer ME exposed within the gap layer GPs. As a result, the memory layer ME is removed from a portion of the side wall of the pillar PL, and a portion of the inner channel layer CN is exposed within the gap layer GPs.

[0129] As shown in Figure 11(b), a raw material gas, such as amorphous silicon, is injected through the slit ST, whose sidewalls are protected by an insulating layer 54s, to fill the gap layer GPs with amorphous silicon or the like. The support substrate SS is then heat-treated to polycrystallize the amorphous silicon filled in the gap layer GPs, forming an intermediate source wire BSL containing polysilicon or the like.

[0130] As a result, a portion of the channel layer CN of the pillar PL is connected to the source line SL on the side via the intermediate source line BSL.

[0131] As shown in Figure 12(a), the insulating layer 54s on the side wall of the slit ST is removed.

[0132] As shown in Figure 12(b), a solution for removing the insulating layer NL, such as thermal phosphoric acid, is introduced into the interior of the laminates LMsa and LMsb from the slit ST from which the insulating layer 54s has been removed, thereby removing the insulating layer NL of the laminates LMsa and LMsb. This forms laminates LMga and LMgb having multiple gap layers GP from which the insulating layer NL between insulating layers OL has been removed.

[0133] Laminates LMga and LMgb, which contain multiple gap layers GP, have a fragile structure. Multiple pillars PL support these fragile laminates LMga and LMgb. This prevents the insulating layer OL remaining in the laminate from bending, and prevents the laminate LMga and LMgb from deforming or collapsing.

[0134] As shown in Figure 13(a), a conductive material raw material gas, such as tungsten or molybdenum, is injected into the interior of the laminates LMga and LMgb through the slit ST, and the gap layer GP of the laminates LMga and LMgb is filled with the conductive material to form multiple word lines WL, etc. This forms a laminate LM containing laminates LMa and LMb, in which multiple word lines WL, etc. and multiple insulating layers OL are alternately stacked one layer at a time.

[0135] As described above, the process of forming the intermediate source line BSL from the intermediate sacrificial layer SCN, and the process of forming the word line WL from the insulating layer NL, are also called replacement processes.

[0136] As shown in Figure 13(b), a conductive layer 24 is filled into the slit ST via an insulating layer 54 to form a plate-shaped contact LI. In addition, a groove is formed that penetrates one or more conductive layers, including the uppermost conductive layer of the laminate LMb, and an insulating layer 56 is filled into the groove to form a separation layer SHE that divides these conductive layers into a pattern of selected gate lines SGD.

[0137] Subsequently, although not shown in the diagram, multiple contacts CC are formed from the upper side of the staircase area SR, reaching the word lines WL and selection gate lines SGD and SGS that constitute each step of the staircase structure of the staircase area SR.

[0138] Furthermore, after forming an insulating layer 52 that covers the laminate LM, plugs CH are formed that penetrate the uppermost insulating layer OL and insulating layer 52 of the laminate LM and are connected to the cap layer CP at the upper end of the pillar PL. In addition, an insulating layer 53 is formed that covers the insulating layer 52, and bit wires BL are formed in the insulating layer 53 to which the individual plugs CH are connected.

[0139] Furthermore, the plug CH and bit wire BL may be formed collectively, for example, by using a dual damascene method.

[0140] Furthermore, peripheral circuits CBA are formed on a semiconductor substrate SB, which is separate from the support substrate SS on which the laminated structure LM is formed, and covered with an insulating layer 40. Contacts, vias, wiring, etc. are formed in the insulating layer 40 to bring the peripheral circuits CBA to the surface of the insulating layer 40, and these are connected to electrode pads etc. formed on the upper surface of the insulating layer 40.

[0141] Next, the support substrate SS and the semiconductor substrate SB are bonded together by their respective insulating layers 50 and 40, and the electrode pads in the insulating layers 50 and 40 are connected. After that, the support substrate SS is removed to expose the source wire SL, and the electrode film EL is connected via the insulating layer 60 on which the plug PG is formed.

[0142] As described above, the semiconductor device 1 of the embodiment is manufactured.

[0143] (Overview) In semiconductor devices such as 3D non-volatile memory, there is a technique for single-crystallizing the channel layer of the pillars. This improves carrier mobility in the channel layer and reduces noise because traps are not generated by grain boundaries. Crystallization of the channel layer is performed, for example, by introducing a metal element such as nickel into an amorphous channel layer and then using a metal-assisted annealing process with this element as a catalyst.

[0144] However, because metal elements are randomly diffused and silicided within the channel layer, localized crystallization proceeds at multiple locations within the channel layer, resulting in the formation of numerous grain boundaries within the channel layer. This causes variations in the grain size and grain boundary density of the channel layer from word line to word or from memory cell to memory cell, potentially leading to variations in memory cell characteristics such as cell current, threshold voltage, and operating speeds for writing and reading.

[0145] According to the semiconductor device 1 of the embodiment, the pillar PL has a semiconductor layer CS that protrudes from the side wall of the channel layer CN toward the insulating layer OLm at a height position of the insulating layer OLm located at least near the center of the stacking direction of the laminate LM. This makes it possible to control the crystallization starting point position and grain boundary position in the channel layer CN, thereby improving the crystallinity of the channel layer CN. As a result, variations in grain size and grain boundary density of the channel layer CN for each word line WL or each memory cell MC can be suppressed, and variations in memory cell characteristics can be suppressed.

[0146] According to the semiconductor device 1 of this embodiment, the insulating layer OLm includes an insulating layer OLb which is inserted at the height position of the semiconductor layer CS in the insulating layer OLm and has lower etching resistance than the insulating layer OLa. This allows the insulating layer OLb to recede from the side wall of the memory hole MH to form a recess RS, and the semiconductor layer CS, which serves as the starting point for crystallization of the channel layer CN, to be formed within the recess RS.

[0147] In the semiconductor device 1 of this embodiment, multiple semiconductor layers CS protrude from the sidewalls of the channel layer CN toward the multiple insulating layers OLm at height positions scattered in the stacking direction of the laminate LM. In this way, multiple semiconductor layers CS, which serve as the starting point for crystallization of the channel layer CN, are arranged in the laminate LM, making it possible to more reliably crystallize the entire channel layer CN.

[0148] (modified version) In the above-described embodiment, one or more semiconductor layers CS, such as polysilicon layers, are placed in the laminate LM as the starting point for crystallization of the channel layer CN. However, it is also possible to use amorphous semiconductor layers, such as amorphous silicon layers, as the starting point for crystallization.

[0149] A modified semiconductor device of the embodiment will be described below with reference to Figure 14. The modified semiconductor device differs from the above-described embodiment in that a semiconductor layer CSa, such as an amorphous silicon layer, is placed at a predetermined position in the laminate LM instead of a semiconductor layer CS such as a polysilicon layer.

[0150] Figure 14 illustrates a part of the procedure for manufacturing a semiconductor device according to a modified embodiment. More specifically, Figure 14 is a partially enlarged cross-sectional view of the height position of the insulating layer OLm of the pillar during manufacturing.

[0151] In Figure 14, components similar to those in the embodiments described above are denoted by the same reference numerals, and their descriptions may be omitted.

[0152] As shown in Figure 14(a), in the modified semiconductor device as well, a memory hole MH is formed that penetrates the laminates LMsa and LMsb containing the insulating layer OLm, the insulating layer OLb is recessed from the side wall of the memory hole MH to form a recess RS, and a memory layer ME is formed that covers the side wall of the memory hole MH containing the recess RS.

[0153] As shown in Figure 14(b), an amorphous semiconductor layer CSa, such as an amorphous silicon layer, is filled into the recess RS of the memory hole MH sidewall. At this time, at least one of nitrogen, boron, and carbon is added to the semiconductor layer CSa. The concentration of the additive in the semiconductor layer CS is, for example, 1 × 10⁻⁶. 20 atm / cm 3 The above 3 x 10 21 atm / cm 3 The following is preferably 5 × 10 20 atm / cm 3 The above 2 x 10 21 atm / cm 3Hereinafter, more preferably 9×10 20 atm / cm 3 or more and 1.5×10 21 atm / cm 3 or less.

[0154] As shown in FIG. 14(c), an amorphous channel layer CNa that covers the sidewall of the memory hole MH including the semiconductor layer CSa is formed. At this time, similar to the above-described embodiment, at least one additive selected from nitrogen, boron, and carbon may also be added to the channel layer CNa. However, in this case, it is preferable that the additive concentration of the channel layer CNa is less than the additive concentration of the semiconductor layer CS.

[0155] Further, a metal layer covering the sidewall of the channel layer CNa is formed to introduce a metal element such as nickel into the channel layer CNa.

[0156] Thereafter, the core layer CR is filled into the void remaining in the memory hole MH, the upper surface is etched back, and the cap layer CP is formed in the resulting recess.

[0157] As shown in FIG. 14(d), the entire support substrate SS is heated to perform annealing treatment at a low temperature. At this time, since the semiconductor layer CSa, which is an amorphous silicon layer or the like, contains at least one additive selected from nitrogen, boron, and carbon at a high concentration, the semiconductor layer CSa can function in the same manner as the semiconductor layer CS which is a polysilicon layer or the like in the above-described embodiment.

[0158] That is, at the interface between the semiconductor layer CSa and the channel layer CNa, the activation energy required for forming silicide NS can be reduced. Further, a similar additive contained in the channel layer CNa also promotes the formation of silicide NS.

[0159] As a result, aggregation of silicide NS occurs at the interface between the semiconductor layer CSa and the channel layer CNa.

[0160] As shown in Figure 14(e), due to the aggregation of silicide NS, crystallization of the channel layer CNa progresses from the interface between the semiconductor layer CSa and the channel layer CNa toward the vertical direction of the laminates LMsa and LMsb. Furthermore, in the modified example, since the semiconductor layer CSa is also an amorphous silicon layer, crystallization can also progress within the semiconductor layer CSa from the memory hole MH side toward the periphery of the memory hole MH.

[0161] At this time, some of the silicide NS that acted as a catalyst for the crystallization of the channel layer CNa and the semiconductor layer CSa are fragmented into metal fragments NSf, which then diffuse into the channel layer CNa and the semiconductor layer CSa. The portion of the channel layer CNa into which the metal fragments NSf have entered transforms into the aforementioned channel layer CN, which is, for example, a single-crystal silicon layer. The portion of the semiconductor layer CSa into which the metal fragments NSf have entered transforms into a semiconductor layer CSc, which is, for example, a single-crystal silicon layer.

[0162] Thus, in this modified example, crystallization proceeds in parallel in the channel layer CNa and the semiconductor layer CSa, so the crystallized channel layer CN and semiconductor layer CSc may have the same crystal orientation.

[0163] As described above, a channel layer CN, which is a semiconductor layer such as a single crystal, is formed in the modified semiconductor device as well.

[0164] According to the modified method for manufacturing a semiconductor device, the formation of the semiconductor layer CSc includes adding at least one of nitrogen, boron, and carbon to fill the recess RS of the memory hole MH sidewall with an amorphous semiconductor layer CSa. This configuration also allows the semiconductor layer CSa to function as a starting point for crystallization, achieving the same effects as in the embodiments described above.

[0165] (Other variations) In the embodiments and modifications described above, the semiconductor device 1 is provided with a laminated body LM having a 2-tier structure in which two laminated bodies LMa and LMb are stacked vertically. However, the configuration of the laminated body is not limited to 2 tiers; it may be 1 tier or 3 tiers or more.

[0166] Furthermore, in the embodiments and modifications described above, the pillar PL is connected to the source line SL on the side of the channel layer CN, but this is not limited to this configuration. For example, the pillar may be configured such that the memory layer on the bottom surface of the pillar is removed and the source line is connected at the lower end of the channel layer.

[0167] Furthermore, in the embodiments and modifications described above, the peripheral circuit CBA is positioned above the laminate LM. However, the peripheral circuit may be positioned below the laminate, or on the same layer as the laminate. When the peripheral circuit is positioned below the laminate, the laminate can be formed directly above the semiconductor substrate on which the peripheral circuit is formed. Also, when the peripheral circuit is positioned on the same layer as the laminate, the laminate can be formed at a different location on the semiconductor substrate from where the peripheral circuit is formed.

[0168] Furthermore, in the embodiments and modifications described above, the semiconductor layer crystallized by metal-assisted annealing is used as the channel layer CN of the memory cell MC in the semiconductor device 1, which is a three-dimensional non-volatile memory. However, the semiconductor layer crystallized by the methods of the embodiments and modifications described above can also be used in switching circuits or logic circuits.

[0169] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0170] 1... Semiconductor device, CN, CNa... Channel layer, CS, CSa, CSc... Semiconductor layer, LM, LMa, LMb, LMga, LMgb, LMsa, LMsb... Stack, MC... Memory cell, MR... Memory region, NL, OL, OLa, OLb, OLm... Insulating layer, PL... Pillar, SR... Stair region, SGD, SGS... Selected gate line, WL... Word line.

Claims

1. A laminate in which multiple conductive layers and multiple insulating layers are stacked alternately, The laminate comprises pillars extending within the laminate in the stacking direction, The aforementioned pillar is A first semiconductor layer extending within the laminate in the aforementioned stacking direction, The plurality of insulating layers include a second semiconductor layer that protrudes from the side wall of the first semiconductor layer toward the first insulating layer at a height position of the first insulating layer located near the center of the stacking direction of the laminate, among the plurality of insulating layers, Semiconductor equipment.

2. The first semiconductor layer mainly consists of a single-crystal semiconductor, The second semiconductor layer mainly consists of a single-crystal or polycrystalline semiconductor. The semiconductor device according to claim 1.

3. The first semiconductor layer and the second semiconductor layer have different crystal orientations. The semiconductor device according to claim 2.

4. Of the first and second semiconductor layers, The second semiconductor layer contains at least one additive of nitrogen, boron, and carbon. The semiconductor device according to claim 1.

5. The first insulating layer is The first insulating layer includes a second insulating layer inserted at the height of the second semiconductor layer and having lower etching resistance than the first insulating layer. The semiconductor device according to claim 1.

6. The first insulating layer is It is a silicon oxide layer, The second insulating layer is The silicon carbide layer, the silicon germanium layer, or the silicon oxide layer having a lower density than the first insulating layer. The semiconductor device according to claim 5.

7. The aforementioned pillar is The present invention has a plurality of second semiconductor layers, including the aforementioned second semiconductor layer, The plurality of second semiconductor layers are Among the plurality of insulating layers, at height positions of the plurality of first insulating layers scattered in the stacking direction of the laminate including the first insulating layer, each protrudes from the side wall of the first semiconductor layer toward the plurality of first insulating layers, The semiconductor device according to claim 1.

8. A laminate is formed in which multiple sacrificial layers and multiple insulating layers are stacked alternately, one layer at a time. A memory hole is formed in the laminate that extends within the laminate in the stacking direction of the laminate. A pillar including a first semiconductor layer extending within the laminate in the stacking direction is formed within the memory hole. The formation of the aforementioned pillar is At least one of the plurality of insulating layers, at a height position of the first insulating layer located near the center of the stacking direction of the laminate, a recess that enters the first insulating layer is formed on the side wall of the memory hole. Filling the recess with a second semiconductor layer, To form the first semiconductor layer that covers the side wall of the memory hole and the second semiconductor layer, This includes performing a metal-assisted annealing process on the first semiconductor layer, A method for manufacturing a semiconductor device.

9. The formation of the first semiconductor layer is The amorphous first semiconductor layer covering the sidewall of the memory hole and the second semiconductor layer is crystallized by the annealing process. The method for manufacturing a semiconductor device according to claim 8.

10. The formation of the second semiconductor layer is This includes filling the recess with the polycrystalline second semiconductor layer. The method for manufacturing a semiconductor device according to claim 9.

11. The formation of the second semiconductor layer is This includes filling the recess with the amorphous second semiconductor layer. The method for manufacturing a semiconductor device according to claim 9.

12. The formation of the second semiconductor layer is The process includes crystallizing the second semiconductor layer filled in the recess by the annealing treatment. A method for manufacturing a semiconductor device according to claim 11.

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