Marking method and semiconductor package

Abstract

This invention provides a marking method and semiconductor package that can form a mark while suppressing the package thickness. [Solution] The marking method according to this embodiment comprises forming a mark on a metal film of a semiconductor package on which a metal film is formed using a chelate reaction.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a marking method and a semiconductor package. [Background Art]

[0002] Against the background of increasing demand for mobile communication terminals driven by the spread of 5G, demand for thin and small electronic component packages (semiconductor packages) has been growing. In addition, along with the improvement of communication speed, shield packages, in which an arbitrary metal film is formed on a mold package to prevent electromagnetic wave interference inside and outside the semiconductor package, have also become widespread. Further, in order to identify semiconductor packages, a mark is formed on the semiconductor package. Marking methods for semiconductor packages are broadly classified into two main types: laser marking and ink marking. However, each method has disadvantages when it comes to ensuring a thin package thickness. [Prior Art Literature] [Patent Literature]

[0003] [Patent Literature 1] Japanese Unexamined Patent Application Publication No. 2018-160527 [Patent Literature 2] Japanese Unexamined Patent Application Publication No. 2023-177984 [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] Provided are a marking method and a semiconductor package capable of forming a mark while suppressing the thickness of the package. [Means for Solving the Problem]

[0005] The marking method according to the present embodiment comprises forming a mark on the metal film of a semiconductor package on which the metal film has been formed using a chelating reaction. [Brief Description of the Drawings]

[0006] [Figure 1] A cross-sectional view showing an example of the configuration of a semiconductor device according to the first embodiment. [Figure 2A] This is a perspective view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 2B] This is a perspective view showing an example of a semiconductor device manufacturing method, following Figure 2A. [Figure 2C] Figure 2B is a perspective view showing an example of a semiconductor device manufacturing method. [Figure 3] This figure shows an example of a chelation reaction according to the first embodiment. [Figure 4] This is a cross-sectional view showing an example of the configuration of a semiconductor device according to the first comparative example. [Figure 5] This is a cross-sectional view showing an example of the configuration of a semiconductor device according to the second comparative example. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not limiting to the present invention. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those of actual objects. In the specification and drawings, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals, and detailed explanations are omitted as appropriate.

[0008] (First Embodiment) Figure 1 is a cross-sectional view showing an example of the configuration of a semiconductor device (semiconductor package) 1 according to a first embodiment. The semiconductor device 1 comprises a wiring board 10, semiconductor chips 30-33, bonding wires 90, sealing resin 91, and a metal film 110. The semiconductor device 1 is, for example, a package for NAND flash memory.

[0009] The wiring board 10 may be a printed circuit board or an interposer including a wiring layer (not shown) and an insulating layer (not shown). For the wiring layer, a low-resistance metal such as copper (Cu), nickel (Ni), or an alloy thereof may be used. For the insulating layer, an insulating material such as glass epoxy resin may be used. The wiring board 10 may have a multilayer wiring structure composed of multiple wiring layers and multiple insulating layers stacked on top of each other. The wiring board 10 may have through electrodes that penetrate its front and back surfaces, for example, as in an interposer.

[0010] The wiring board 10 has a ground wire 11. The ground wire 11 electrically connects a metal bump 13 provided on the lower surface of the wiring board 10 to a metal film 110. The metal bump 13 is provided to electrically connect the wiring board 10 to other components (not shown).

[0011] The semiconductor chip 30 is, for example, a memory chip including a NAND flash memory. The semiconductor chip 30 has semiconductor elements (not shown) on its surface (top surface). The semiconductor elements may be, for example, a memory cell array and its peripheral circuits (CMOS circuits). The memory cell array may be a three-dimensional memory cell array in which multiple memory cells are arranged in three dimensions. A semiconductor chip 31 is bonded to the semiconductor chip 30 via an adhesive layer (not shown). A semiconductor chip 32 is bonded to the semiconductor chip 31 via an adhesive layer. A semiconductor chip 33 is bonded to the semiconductor chip 32 via an adhesive layer. Semiconductor chips 31 to 33 are, for example, memory chips including a NAND flash memory, similar to semiconductor chip 30. Semiconductor chips 30 to 33 may be the same memory chip. In the figure, four semiconductor chips 30 to 33 as memory chips are stacked. However, the number of stacked semiconductor chips may be 3 or less, or 5 or more.

[0012] The bonding wire 90 is connected to any pad on the wiring board 10 and the semiconductor chips 30-33. In order to connect with the bonding wire 90, the semiconductor chips 30-33 are stacked with an offset equal to the pad.

[0013] Further, a sealing resin (resin layer) 91 seals (covers) the semiconductor chips 30 to 33, the bonding wires 90, and the like. Accordingly, the semiconductor device 1 has the plurality of semiconductor chips 30 to 33 configured as one semiconductor package on the wiring substrate 10.

[0014] The metal film 110 covers the sealing resin 91. The metal film 110 has an upper surface (surface F110) on the opposite side from the sealing resin 91. The metal film 110 is provided on the side surfaces and the upper surface of the sealing resin 91.

[0015] Further, the metal film 110 is formed of, for example, a conductive material such as a metal. When the metal film 110 is electrically connected to a ground line of a mounting substrate via the ground line 11 and the metal bumps 13, the metal film 110 functions as a shield film that shields electromagnetic waves.

[0016] Further, the metal film 110 contains a first metal element. The first metal element is, for example, iron (Fe), but is not limited thereto. The metal film 110 is, for example, stainless steel, and contains an alloy of iron (Fe), chromium (Cr) and nickel (Ni), or an alloy of iron (Fe) and chromium (Cr).

[0017] Further, the metal film 110 has a first portion 110p. The first portion 110p is a mark, and is used, for example, to identify the semiconductor package. The first portion 110p is provided on the surface (surface F110) of the metal film 110. That is, the first portion 110p is provided so as to be exposed in a first region R1 of the upper surface (surface F110) of the metal film 110. The first portion 110p contains a chelate compound of the first metal element. The chelate compound is, for example, iron (III) gallate. When the metal film 110 contains a plurality of first metal elements, the first portion 110p may contain chelate compounds of the plurality of first metal elements.

[0018] Next, a method for forming the first portion 110p of the metal film 110 will be described.

[0019] 2A to 2C are perspective views illustrating an example of a method for manufacturing a semiconductor device 1 according to the first embodiment.

[0020] Note that FIGS. 2A to 2C show steps after forming the metal film 110 illustrated in FIG. 1. The metal film 110 is formed, for example, by sputtering.

[0021] First, as illustrated in FIG. 2A, the surface F110 of the metal film 110 is pretreated. This removes oil and oxide films on the surface (surface F110) of the metal film 110. After the pretreatment of the surface F110, a mark is formed on the metal film 110 of the semiconductor package using a chelation reaction.

[0022] Next, as illustrated in FIG. 2B, a chemical solution L is applied to a first region R1 on the surface F110. The chemical solution L is, for example, an aqueous solution of a chelating agent. The chelating agent is, for example, gallic acid (tannic acid). The application of the chemical solution L is performed, for example, by an inkjet method. In the example illustrated in FIG. 2B, the chemical solution L is ejected from an inkjet head H. Gallic acid reacts with iron contained in stainless steel to form a chelate. Iron ions contained in the formed chelate are divalent.

[0023] Next, as illustrated in FIG. 2C, a first portion 110p is formed through an oxidation reaction. The oxidation reaction is performed, for example, by air oxidation. As the oxidation reaction proceeds, iron ions change from divalent to trivalent, and a black mark is formed. The first portion 110p contains, for example, iron (III) gallate.

[0024] FIG. 3 is a diagram illustrating an example of the chelation reaction according to the first embodiment. FIG. 3 shows the chelation reaction between gallic acid and iron ions.

[0025] The left side of FIG. 3 shows the chemical formula of gallic acid. The right side of FIG. 3 shows the structural formula of iron (III) gallate.

[0026] As described above, according to the first embodiment, marks are formed on the metal film 110 of a semiconductor package using a chelation reaction. This makes it possible to form marks by treating the metal surface using a chemical reaction while suppressing the thickness of the semiconductor package.

[0027] The chelating agent is not limited to gallic acid. For example, the chelating agent may be citric acid, EDTA (ethylenediaminetetraacetic acid), DTPA (diethylenetriaminepentaacetic acid), or EDDHA (ethylenediamine-di(o-hydroxyphenylacetic acid)).

[0028] Note that the first metallic element is not limited to iron. The first metallic element may be, for example, chromium (Cr), nickel (Ni), manganese (Mn), copper (Cu), zinc (Zn), or molybdenum (Mo). Also, the color of the mark (first part 110p) may differ depending on the first metallic element.

[0029] Furthermore, the marking method according to the first embodiment is not limited to shielded packages, but can be applied to all packages with a metal surface, such as those with a heat spreader placed on silicon.

[0030] (Comparative example) Figure 4 is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the first comparative example. The first comparative example differs from the first embodiment in that a laser marking method is used.

[0031] In laser marking, the mark is formed by irradiating the surface of the sealing resin 91 with laser light to abrade or melt it before forming the metal film 110.

[0032] Laser marking raises concerns about damage to the semiconductor chip 33 due to laser light passing through the sealing resin 91, and the exposure of the bonding wires 90 or semiconductor chip 33 by engraving the sealing resin 91 with a laser; therefore, it is necessary to ensure a certain resin thickness. In other words, an increase in the thickness of the semiconductor package is expected by the thickness of the sealing resin 91 between the semiconductor chip 33 or bonding wires 90 and the top of the semiconductor package. In addition, CO2 emissions are unavoidable when using a laser for laser marking.

[0033] In contrast, in the first embodiment, the chemical reaction on the surface of the metal film 110 is unlikely to penetrate the metal film 110 or the sealing resin 91 and affect the semiconductor chip 33. Because the chemical reaction does not affect the semiconductor chip 33 inside the semiconductor package, it is possible to make the semiconductor package thinner compared to using laser marking. In addition, CO2 emissions can be suppressed. Furthermore, since the processing capacity of inkjet is higher than that of laser, the first embodiment, in which the chemical solution L is applied by the inkjet method, is also superior to laser marking in terms of cost. Moreover, in the first embodiment, unlike laser marking where the mark is applied before forming the metal film 110 which is the shielding film, the mark is formed after the shielding film is formed. This makes it possible to make the semiconductor package unique after shielding.

[0034] Figure 5 is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the second comparative example. The second comparative example differs from the first embodiment in that an ink marking method is used.

[0035] Ink marks raise concerns about increased thickness of ink 100 due to the application of a identifiable amount of ink to prevent loss of ink 100, omission of printed content, or fading due to physical friction, chemicals, or oils. In other words, an increase in the thickness of the semiconductor package by the thickness of ink 100 is expected to ensure visibility. The thickness of ink 100 is, for example, greater than 15 μm.

[0036] In contrast, in the first embodiment, the particle size of gallic acid is, for example, smaller than 10 nm. It is easily possible to increase the film thickness of the chelate compound, i.e., the thickness of the semiconductor package, to, for example, about 3 μm. Therefore, in the first embodiment, the thickness of the semiconductor package can be reduced by more than the ink marks.

[0037] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0038] 1 Semiconductor device, 30-33 Semiconductor chip, 90 Bonding wire, 91 Encapsulating resin, 110 Metal film, 110p First part, F110 Plane, R1 First region

Claims

1. A marking method comprising forming a mark on a metal film of a semiconductor package using a chelate reaction.

2. The marking method according to claim 1, wherein forming a mark using a chelating reaction comprises applying a chelating agent to a first region on the first surface of the metal film.

3. The marking method according to claim 2, wherein the chelating agent is gallic acid.

4. The marking method according to claim 2, wherein the chelating agent is applied by an inkjet method.

5. The marking method according to claim 1, wherein the metal film comprises iron (Fe).

6. Having a first surface, comprising a metal film containing a first metal element, The semiconductor package wherein the metal film is provided on the first surface and has a first portion containing a chelate compound of the first metal element.

7. The first metallic element is iron (Fe), The semiconductor package according to claim 6, wherein the chelating compound is iron(III) gallate.

8. Semiconductor chips and A resin layer covering the aforementioned semiconductor chip and the aforementioned metal film, Furthermore, The semiconductor package according to claim 6, wherein the first surface is the surface opposite to the resin layer.

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