Semiconductor equipment

Abstract

To increase the number of terminals in a semiconductor device while suppressing the package size of the semiconductor device. [Solution] The semiconductor device package comprises a plurality of die pads DP1, DP2, a semiconductor chip CP mounted on the plurality of die pads DP1, DP2, a plurality of leads LD, and a sealing portion MR. The plurality of pads PD3 and the plurality of leads LD of the semiconductor chip CP are electrically connected via a plurality of wires BW3, the pad PD1 of the semiconductor chip CP and the die pad DP1 are electrically connected via wire BW1, and the pad PD2 of the semiconductor chip CP and the die pad DP2 are electrically connected via wire BW2. The plurality of die pads DP1, DP2 are exposed from the lower surface of the sealing portion MR.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and can be suitably used, for example, in a semiconductor device obtained by resin-sealing a semiconductor chip and a plurality of leads. Background Art

[0002] A semiconductor device in the form of a semiconductor package can be manufactured by mounting a semiconductor chip on a die pad, electrically connecting a plurality of pad electrodes of the semiconductor chip and a plurality of leads respectively via a plurality of wires, and resin-sealing these components.

[0003] Japanese Patent Laid-Open No. 2002-261187 (Patent Document 1) describes a technique of electrically connecting an electrode of a semiconductor element and a tab on which the semiconductor element is mounted via a conductive wire. Prior Art Documents Patent Documents

[0004] Patent Document 1 Japanese Patent Laid-Open No. 2002-261187 Summary of the Invention Problems to be Solved by the Invention

[0005] It is desired to increase the number of terminals of a semiconductor device while suppressing the package size of the semiconductor device.

[0006] Other problems and novel features will become apparent from the description of the present specification and the accompanying drawings. Means for Solving the Problems

[0007] According to one embodiment, the semiconductor device comprises a plurality of chip mounting sections spaced apart from each other, semiconductor chips mounted on the plurality of chip mounting sections, a plurality of leads arranged to surround the plurality of chip mounting sections in a plan view, a plurality of first conductive connecting members, a second conductive connecting member, a third conductive connecting member, and a resin encapsulant that seals them. The plurality of chip mounting sections include a first chip mounting section and a second chip mounting section. The plurality of first pads of the semiconductor chip and the plurality of leads are electrically connected, respectively, via the plurality of first conductive connecting members. The second pad of the semiconductor chip and the first chip mounting section are electrically connected via the second conductive connecting member. The third pad of the semiconductor chip and the second chip mounting section are electrically connected via the third conductive connecting member. A portion of each of the plurality of leads is exposed from the resin encapsulant. The first chip mounting section and the second chip mounting section are exposed from the main surface of the resin encapsulant. [Effects of the Invention]

[0008] According to one embodiment, the number of terminals in a semiconductor device can be increased while suppressing the package size of the semiconductor device. [Brief explanation of the drawing]

[0009] [Figure 1] This is a top view of the semiconductor device according to Embodiment 1. [Figure 2] This is a plan view of the semiconductor device according to Embodiment 1. [Figure 3] This is a plan view of the semiconductor device according to Embodiment 1. [Figure 4] This is a plan view of the semiconductor device according to Embodiment 1. [Figure 5] This is a bottom view of the semiconductor device of Embodiment 1. [Figure 6] This is a cross-sectional view of the semiconductor device according to Embodiment 1. [Figure 7] This is a cross-sectional view of the semiconductor device according to Embodiment 1. [Figure 8] This is a cross-sectional view of the semiconductor device according to Embodiment 1. [Figure 9] It is a cross-sectional view showing a state where the semiconductor device according to Embodiment 1 is mounted on a wiring board. [Figure 10] It is a transparent plan view of the semiconductor device according to the first study example. [Figure 11] It is a transparent plan view of the semiconductor device according to the first study example. [Figure 12] It is a transparent plan view of the semiconductor device according to the second study example. [Figure 13] It is an explanatory diagram showing an example of connection between a semiconductor chip and a lead in the semiconductor device according to the first study example. [Figure 14] It is an explanatory diagram showing an example of connection between a semiconductor chip and a lead or a die pad in the semiconductor device according to Embodiment 1. [Figure 15] It is an explanatory diagram showing an example of connection between a semiconductor chip and a lead in the semiconductor device according to the first study example. [Figure 16] It is an explanatory diagram showing an example of connection between a semiconductor chip and a lead or a die pad in the semiconductor device according to Embodiment 1. [Figure 17] It is an explanatory diagram showing an example of connection between a semiconductor chip and a die pad in the semiconductor device according to the second study example. [Figure 18] It is an explanatory diagram showing an example of connection between a semiconductor chip and a plurality of die pads in the semiconductor device according to Embodiment 1. [Figure 19] It is an explanatory diagram showing an example of connection between a semiconductor chip and a plurality of die pads in the semiconductor device according to Embodiment 1. [Figure 20] It is an explanatory diagram showing an example of connection between a semiconductor chip and a plurality of die pads in the semiconductor device according to Embodiment 1. [Figure 21] It is a transparent plan view of the semiconductor device according to the first modification. [Figure 22] It is a transparent plan view of the semiconductor device according to the first modification. [Figure 23] It is a transparent plan view of the semiconductor device according to Embodiment 2. [Figure 24] It is a transparent plan view of the semiconductor device according to Embodiment 2. [Figure 25] It is a cross-sectional view of the semiconductor device according to Embodiment 2. [Figure 26] It is a cross-sectional view of the semiconductor device according to the second embodiment. [Figure 27] It is a cross-sectional view of the semiconductor device according to the second embodiment. [Figure 28] It is an explanatory diagram showing an example of connection between a semiconductor chip and a plurality of die pads in the semiconductor device according to the second embodiment. [Figure 29] It is an explanatory diagram showing an example of connection between a semiconductor chip and a plurality of die pads in the semiconductor device according to the second embodiment. [Figure 30] It is a perspective plan view of the semiconductor device according to the third embodiment. [Figure 31] It is a perspective plan view of the semiconductor device according to the third embodiment. [Figure 32] It is a cross-sectional view of the semiconductor device according to the third embodiment. [Figure 33] It is a cross-sectional view of the semiconductor device according to the third embodiment. [Figure 34] It is a cross-sectional view of the semiconductor device according to the third embodiment. [Figure 35] It is an explanatory diagram showing an example of connection between a semiconductor chip and a plurality of die pads in the semiconductor device according to the third embodiment. [Figure 36] It is an explanatory diagram showing an example of connection between a semiconductor chip and a plurality of die pads in the semiconductor device according to the third embodiment. MODES FOR CARRYING OUT THE INVENTION

[0010] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments. Unless otherwise specified, these are not unrelated, and one may be a modification, detail, or supplementary explanation of part or all of the other. Furthermore, when referring to the number of elements, etc. (including number, numerical value, quantity, range, etc.) in the following embodiments, unless otherwise specified or clearly limited to a specific number in principle, it is not limited to that specific number, and may be greater than or less than that number. Moreover, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified or clearly considered essential in principle. Similarly, when referring to the shape, positional relationship, etc. of constituent elements, etc. in the following embodiments, unless otherwise specified or clearly considered not to be so in principle, it shall include those that substantially approximate or resemble that shape, etc. The same applies to the numerical values ​​and ranges mentioned above.

[0011] The embodiments will be described in detail below with reference to the drawings. In all the drawings used to describe the embodiments, the same reference numerals are used for members having the same function, and repeated descriptions of them will be omitted. In addition, in the following embodiments, descriptions of the same or similar parts will not be repeated unless it is particularly necessary.

[0012] Furthermore, in the drawings used in the embodiments, hatching may be omitted even in cross-sectional views to improve readability. Conversely, hatching may be added to plan views to improve readability.

[0013] (Embodiment 1) <About the structure of semiconductor devices> Figure 1 is a top view of the semiconductor device package of this embodiment, Figures 2, 3, and 4 are plan perspective views of the semiconductor device package, Figure 5 is a bottom view (back view) of the semiconductor device package, and Figures 6, 7, and 8 are cross-sectional views of the semiconductor device package. Figure 2 shows a top view of the semiconductor device package when the sealing portion MR is viewed through. Figure 3 shows a top view of the semiconductor device package as in Figure 2, but with the wire BW viewed through (omitted). Figure 4 shows a top view of the semiconductor device package as in Figure 3, but with the semiconductor chip CP viewed through (omitted). Furthermore, the cross-sectional view of the semiconductor device package along line A1-A1 in Figure 2 roughly corresponds to Figure 6, the cross-sectional view of the semiconductor device package along line A2-A2 in Figure 2 roughly corresponds to Figure 7, and the cross-sectional view of the semiconductor device package along line A3-A3 in Figure 2 roughly corresponds to Figure 8. Also, Figures 1 to 5 show the X and Y directions. Here, the X and Y directions intersect each other, and more specifically, are orthogonal to each other.

[0014] The semiconductor device (semiconductor package) PKG of this embodiment, shown in Figures 1 to 8, is a resin-encapsulated semiconductor package, and in this case, it is a QFN (Quad Flat Non-leaded package) type semiconductor device. The configuration of the semiconductor device PKG will be described below with reference to Figures 1 to 8.

[0015] The semiconductor device package of this embodiment, shown in Figures 1 to 8, includes a semiconductor chip CP, two die pads DP1 and DP2, a plurality of wires (bonding wires) BW, a plurality of leads LD, suspension leads TL1, TL2, TL3, and TL4, and a sealing portion MR that seals these components.

[0016] The sealing portion MR, as a resin encapsulant, is made of a resin material such as a thermosetting resin material, and may also contain fillers. For example, the sealing portion MR can be formed using an epoxy resin containing fillers.

[0017] The sealing portion MR has an upper surface MRa which is one of the main surfaces, a lower surface (back surface, bottom surface) MRb which is the main surface on the opposite side of the upper surface MRa, and four side surfaces S1, S2, S3, S4 which intersect the upper surface MRa and the lower surface MRb.

[0018] Sides S1 and S3 are approximately parallel to the X direction, and side surfaces S2 and S4 are approximately parallel to the Y direction. In the sealing portion MR, side surfaces S1 and S3 are located on opposite sides, side surfaces S2 and S4 are located on opposite sides, side surface S1 intersects with side surfaces S2 and S4, and side surface S3 intersects with side surfaces S2 and S4. Also, the upper surface MRa and the lower surface MRb are approximately parallel to both the X and Y directions. The planar shape of the sealing portion MR is, for example, rectangular.

[0019] The multiple lead LDs in the semiconductor device package are arranged to surround die pads DP1 and DP2 in a plan view. No lead LDs are located between die pads DP1 and DP2 in a plan view. A plan view refers to a view taken from a plane parallel to both the X and Y directions.

[0020] Each of the multiple lead LDs in the semiconductor device package is partially exposed from the sealing portion MR. Specifically, the lower surfaces of the multiple lead LDs are exposed from the lower surface MRb of the sealing portion MR. The lower surfaces of the multiple lead LDs exposed from the lower surface MRb of the sealing portion MR each function as an external connection terminal (external terminal) of the semiconductor device package. A plating layer (not shown), such as a solder plating layer, can also be formed on the lower surfaces of the multiple lead LDs exposed from the lower surface MRb of the sealing portion MR. Furthermore, the multiple lead LDs hardly protrude from the sides S1, S2, S3, S4 of the sealing portion MR, and the end faces (cut surfaces) of the multiple lead LDs are exposed from the sides S1, S2, S3, S4 of the sealing portion MR.

[0021] In this embodiment, the case where the semiconductor device package has a QFN structure is described, but it is not limited to the QFN structure, and for example, a QFP (Quad Flat Package) structure can also be adopted. When the semiconductor device package has a QFP structure, a part of each lead LD (inner lead portion) is sealed within the sealing portion MR, and another part of each lead (outer lead portion) protrudes from the side surface of the sealing portion MR.

[0022] The semiconductor device package has multiple lead LDs, including multiple lead LD1 arranged on the side S1 side of the sealing portion MR, multiple lead LD2 arranged on the side S2 side of the sealing portion MR, multiple lead LD3 arranged on the side S3 side of the sealing portion MR, and multiple lead LD4 arranged on the side S4 side of the sealing portion MR.

[0023] Multiple leads LD1 are arranged along the side surface S1 of the sealing portion MR, each extending in the Y direction. The end face of each lead LD1 is exposed from the side surface S1 of the sealing portion MR. Multiple leads LD2 are arranged along the side surface S2 of the sealing portion MR, each extending in the X direction. The end face of each lead LD2 is exposed from the side surface S2 of the sealing portion MR. Multiple leads LD3 are arranged along the side surface S3 of the sealing portion MR, each extending in the Y direction. The end face of each lead LD3 is exposed from the side surface S3 of the sealing portion MR. Multiple leads LD4 are arranged along the side surface S4 of the sealing portion MR, each extending in the X direction. The end face of each lead LD4 is exposed from the side surface S4 of the sealing portion MR.

[0024] Die pads DP1 and DP2 are separated from each other in the Y direction, with a portion of the sealing section MR interposed between them. Therefore, die pads DP1 and DP2 are not connected via conductors and are electrically isolated from each other. Neither die pad DP1 nor DP2 is connected to either lead LD.

[0025] The semiconductor chip CP is mounted on die pads DP1 and DP2. Specifically, a common semiconductor chip CP is mounted on die pad DP1 via bonding material BD, and also on die pad DP2 via bonding material BD. Therefore, in a plan view, a portion of the semiconductor chip CP overlaps with die pad DP1, and another portion overlaps with die pad DP2. Bonding material BD is interposed between the top surface of die pad DP1 and the back surface of the semiconductor chip CP, and bonding material BD is interposed between the top surface of die pad DP2 and the back surface of the semiconductor chip CP. Each of die pads DP1 and DP2 can be considered a chip mounting area for mounting the common semiconductor chip CP.

[0026] Of the die pads DP1 and DP2, die pad DP1 is positioned near the side surface S1 of the sealing portion MR, and die pad DP2 is positioned near the side surface S3 of the sealing portion MR. That is, in the Y direction, die pad DP1 is positioned between die pad DP2 and the side surface S1 of the sealing portion MR, and die pad DP2 is positioned between die pad DP1 and the side surface S3 of the sealing portion MR.

[0027] The die pads DP1 and DP2 and the multiple leads LD are made of a conductive material, preferably a metallic material such as copper (Cu) or a copper alloy. Furthermore, it is preferable that the die pads DP1 and DP2 and the multiple leads LD are formed from the same material. This facilitates the manufacturing of semiconductor device packages using lead frames.

[0028] Die pad DP1 has a top surface on which the semiconductor chip CP is mounted, a bottom surface (back surface) opposite to the top surface, and four sides D11, D12, D13, and D14 that intersect the top and bottom surfaces. Die pad DP2 has a top surface on which the semiconductor chip CP is mounted, a bottom surface (back surface) opposite to the top surface, and four sides D21, D22, D23, and D24 that intersect the top and bottom surfaces. The top and bottom surfaces of die pad DP1 and die pad DP2 are substantially parallel to each other in both the X and Y directions. The planar shape of die pads DP1 and DP2 is, for example, rectangular.

[0029] Sides D11 and D13 of the die pad DP1 are approximately parallel to each other in the X direction, and sides D12 and D14 of the die pad DP1 are approximately parallel to each other in the Y direction. Sides D11 and D13 of the die pad DP1 are located on opposite sides to each other, and sides D12 and D14 of the die pad DP1 are located on opposite sides to each other. Side D11 intersects with sides D12 and D14, and side D13 intersects with sides D12 and D14. In a plan view, side D11 of the die pad DP1 is located between side S1 of the sealing portion MR and side D13 of the die pad DP1. Also in a plan view, side D12 of the die pad DP1 is located between side S2 of the sealing portion MR and side D14 of the die pad DP1.

[0030] Sides D21 and D23 of die pad DP2 are approximately parallel to each other in the X direction, and sides D22 and D24 of die pad DP2 are approximately parallel to each other in the Y direction. Sides D21 and D23 of die pad DP2 are located on opposite sides to each other, and sides D22 and D24 of die pad DP2 are located on opposite sides to each other. Side D21 intersects with sides D22 and D24, and side D23 intersects with sides D22 and D24. In a plan view, side D23 of die pad DP2 is located between side S3 of the sealing portion MR and side D21 of die pad DP2. Also in a plan view, side D22 of die pad DP2 is located between side S2 of the sealing portion MR and side D24 of die pad DP2. Side D13 of die pad DP1 and side D21 of die pad DP2 face each other in the Y direction via a part of the sealing portion MR.

[0031] Each die pad DP1 and DP2 is sealed within the sealing portion MR, but the lower surfaces of die pad DP1 and die pad DP2 are exposed from the lower surface MRb of the sealing portion MR. In this embodiment, the lower surfaces of die pad DP1 and die pad DP2 exposed from the lower surface MRb of the sealing portion MR can each function as external terminals of the semiconductor device package. A plating layer (not shown), such as a solder plating layer, can also be formed on the lower surfaces of die pads DP1 and DP2 exposed from the lower surface MRb of the sealing portion MR.

[0032] The suspension leads TL1 and TL4 are each integrally connected to the die pad DP1. Specifically, one end of the suspension lead TL1 is integrally connected to the corner formed by sides D11 and D12 of the die pad DP1. One end of the suspension lead TL4 is integrally connected to the corner formed by sides D11 and D14 of the die pad DP1. The suspension lead TL1 extends within the sealing portion MR from the corner formed by sides D11 and D12 of the die pad DP1 toward the corner formed by sides S1 and S2 of the sealing portion MR. The suspension lead TL4 extends within the sealing portion MR from the corner formed by sides D11 and D14 of the die pad DP1 toward the corner formed by sides S1 and S4 of the sealing portion MR.

[0033] The suspension leads TL2 and TL3 are each integrally connected to the die pad DP2. Specifically, one end of the suspension lead TL2 is integrally connected to the corner formed by sides D22 and D23 of the die pad DP2. One end of the suspension lead TL3 is integrally connected to the corner formed by sides D23 and D24 of the die pad DP2. The suspension lead TL2 extends within the sealing section MR from the corner formed by sides D22 and D23 of the die pad DP2 toward the corner formed by sides S2 and S3 of the sealing section MR. The suspension lead TL3 extends within the sealing section MR from the corner formed by sides D23 and D24 of the die pad DP2 toward the corner formed by sides S3 and S4 of the sealing section MR.

[0034] Suspension leads TL1 and TL4 are used to support the die pad DP1 to the frame of the lead frame during the manufacturing of the semiconductor device package. Suspension leads TL2 and TL3 are used to support the die pad DP2 to the frame of the lead frame during the manufacturing of the semiconductor device package. Suspension leads TL1, TL2, TL3, and TL4 do not function as external terminals of the semiconductor device package.

[0035] A semiconductor chip CP has a main surface, a back surface opposite the main surface, and multiple pads PD. The multiple pads PD are formed on the main surface of the semiconductor chip CP. The planar shape of the semiconductor chip CP is square, preferably rectangular. Bonding pads, bonding pad electrodes, pad electrodes, or electrodes are all referred to as pads.

[0036] Each pad PD of the semiconductor chip CP is electrically connected to a circuit formed within the semiconductor chip CP via its internal wiring. The semiconductor chip CP does not have backside electrodes; that is, no electrodes are formed on the back surface of the semiconductor chip CP.

[0037] The semiconductor chip CP is mounted on die pad DP1 via a bonding material (die bonding material) BD, with its back surface facing die pads DP1 and DP2, and also mounted on die pad DP2 via a bonding material (die bonding material) BD. In other words, the semiconductor chip CP is face-up bonded onto die pads DP1 and DP2. An insulating bonding material is preferred as the bonding material BD.

[0038] Here, the multiple pads PD of the semiconductor chip CP include pad PD1, pad PD2, and multiple pads PD3.

[0039] The pad PD1 of the semiconductor chip CP is electrically connected to the die pad DP1 via a wire BW. The wire BW that electrically connects the pad PD1 of the semiconductor chip CP and the die pad DP1 is referred to as wire BW1. That is, one end of wire BW1 is connected to the pad PD1 of the semiconductor chip CP, and the other end of wire BW1 is connected to the top surface of the die pad DP1.

[0040] Pad PD2 of semiconductor chip CP is electrically connected to die pad DP2 via wire BW. The wire BW that electrically connects pad PD2 of semiconductor chip CP and die pad DP2 is called wire BW2. That is, one end of wire BW2 is connected to pad PD2 of semiconductor chip CP, and the other end of wire BW2 is connected to the top surface of die pad DP2.

[0041] Multiple pads PD3 on the semiconductor chip CP are electrically connected to multiple leads LD via multiple wires BW. The wires BW that electrically connect each pad PD3 and each lead LD on the semiconductor chip CP are referred to as wires BW3. That is, one end of each of the multiple wires BW3 is connected to one of the multiple pads PD3 on the semiconductor chip CP, and the other end of each of the multiple wires BW3 is connected to the top surface of each of the multiple leads LD.

[0042] Each wire BW is a conductive wire and functions as a conductive connecting member. Each wire BW is specifically made of metal, but gold (Au) wire, copper (Cu) wire, or aluminum (Al) wire can be suitably used. Each wire BW is sealed within the sealing portion MR and is not exposed from the sealing portion MR. In each lead LD and each die pad DP1, DP2, the connection point of the wire BW is located within the sealing portion MR.

[0043] In Figure 2, one pad PD1 is electrically connected to the die pad DP1 via wire BW1, and one pad PD2 is electrically connected to the die pad DP2 via wire BW2. It is also possible to provide multiple pads PD1 on the semiconductor chip CP and electrically connect each of the multiple pads PD1 to the die pad DP1 via multiple wires BW1. Similarly, it is possible to provide multiple pads PD2 on the semiconductor chip CP and electrically connect each of the multiple pads PD2 to the die pad DP2 via multiple wires BW2.

[0044] <Regarding the mounting structure of semiconductor devices> Figure 9 is a cross-sectional view showing the semiconductor device package of this embodiment mounted on a wiring board (mounting board) PB.

[0045] As shown in Figure 9, the wiring board PB has an upper surface PB1, a lower surface PB2 opposite to the upper surface PB1, and a plurality of electrodes (terminals) TE. The plurality of electrodes TE are formed on the upper surface PB1 of the wiring board PB. The plurality of electrodes TE on the wiring board PB include electrode (terminal) TE1, electrode (terminal) TE2, and a plurality of electrodes (terminals) TE3. The semiconductor device PKG is placed on the upper surface PB1 of the wiring board PB with the lower surface MRb of the sealing portion MR facing the upper surface PB1 of the wiring board PB.

[0046] Multiple lead LDs of the semiconductor device package are electrically connected to multiple electrodes TE3 of the wiring board PB via a conductive bonding material SD. Multiple lead LDs of the semiconductor device package are facing multiple electrodes TE3 of the wiring board PB via a conductive bonding material SD. The bonding material SD is, for example, solder.

[0047] The die pad DP1 of the semiconductor device package is electrically connected to the electrode TE1 of the wiring board PB via a conductive bonding material SD. The lower surface of the die pad DP1 of the semiconductor device package faces the electrode TE1 of the wiring board PB via the conductive bonding material SD. The potential supplied from the electrode TE1 of the wiring board PB to the die pad DP1 via the conductive bonding material SD is supplied to the pad PD1 of the semiconductor chip CP via wire BW1. As will be described in detail later, the potential supplied to the pad PD1 of the semiconductor chip CP is preferably the power supply potential or the ground potential.

[0048] The die pad DP2 of the semiconductor device package is electrically connected to the electrode TE2 of the wiring board PB via a conductive bonding material SD. The lower surface of the die pad DP2 of the semiconductor device package faces the electrode TE2 of the wiring board PB via the conductive bonding material SD. The potential supplied from the electrode TE2 of the wiring board PB to the die pad DP2 via the conductive bonding material SD is supplied to the pad PD2 of the semiconductor chip CP via wire BW2. As will be described in detail later, the potential supplied to the pad PD2 of the semiconductor chip CP is preferably the power supply potential or the ground potential.

[0049] Multiple leads LD and die pads DP1 and DP2 of the semiconductor device package are electrically connected to circuits outside the semiconductor device package (other electronic devices) via multiple electrodes TE on the wiring board PB and wiring (not shown) on the wiring board PB. Therefore, pad PD1 of the semiconductor chip CP is electrically connected to circuits outside the semiconductor device package via wire BW1, die pad DP1, bonding material SD, electrode TE1, and wiring (not shown) on the wiring board PB. Pad PD2 of the semiconductor chip CP is electrically connected to circuits outside the semiconductor device package via wire BW2, die pad DP2, bonding material SD, electrode TE2, and wiring (not shown) on the wiring board PB. Each pad PD3 of the semiconductor chip CP is electrically connected to circuits outside the semiconductor device package via wire BW3, leads LD, bonding material SD, electrode TE3, and wiring (not shown) on the wiring board PB.

[0050] <Regarding the manufacturing process of semiconductor devices> Next, we will briefly explain the manufacturing process (assembly process) of the semiconductor device package of this embodiment shown in Figures 1 to 8 above.

[0051] To manufacture a semiconductor device package, a lead frame having die pads DP1 and DP2 and multiple lead LDs integrated together, and a semiconductor chip CP are prepared. Die pad DP1 is supported on the frame of the lead frame via suspension leads TL1 and TL4. Die pad DP2 is supported on the frame of the lead frame via suspension leads TL2 and TL3.

[0052] Next, the semiconductor chip CP is placed (mounted) across the top surfaces of die pad DP1 and die pad DP2 of the lead frame via a bonding material BD. At this time, the semiconductor chip CP is positioned so that its back surface faces the die pads DP1 and DP2. After that, the bonding material BD is hardened by heat treatment or the like.

[0053] Next, a wire bonding process is performed. In the wire bonding process, multiple pads PD3 of the semiconductor chip CP and multiple leads LD, pad PD1 of the semiconductor chip CP and die pad DP1, and pad PD2 of the semiconductor chip CP and die pad DP2 are electrically connected via wires BW.

[0054] Next, a resin encapsulation process (resin molding process) is performed to form a encapsulation section MR that encapsulates the die pads DP1, DP2, semiconductor chip CP, multiple wires BW, multiple leads LD, and suspension leads TL1, TL2, TL3, TL4.

[0055] Next, a plating layer (not shown) is formed as needed on the lower surfaces of the multiple leads LD exposed from the sealing portion MR and on the die pads DP1 and DP2. After that, the multiple leads LD are cut outside the sealing portion MR and separated from the frame of the lead frame.

[0056] In this way, the semiconductor device package shown in Figures 1 to 8 above is manufactured.

[0057] <Regarding the background of the consideration> Figures 10 and 11 are plan perspective views of the semiconductor device PKG101 of the first study example investigated by the present inventors. Figure 10 corresponds to Figure 2 above, and Figure 11 corresponds to Figure 4 above.

[0058] The semiconductor device PKG101 of the first example shown in Figures 10 and 11 has one die pad DP101 instead of the two die pads DP1 and DP2 described above. The die pad DP101 has a configuration in which the two die pads DP1 and DP2 described above are integrally connected. A semiconductor chip CP101 corresponding to the semiconductor chip CP described above is mounted on the single die pad DP101 via a bonding material BD. In a plan view, the semiconductor chip CP101 is enclosed within the die pad DP101.

[0059] The semiconductor device PKG101 in the first example has the same number of die pads and semiconductor chips. Therefore, one semiconductor chip CP101 is mounted on one die pad DP101. The semiconductor chip CP101 has multiple pads PD101, and the multiple pads PD101 and multiple leads LD of the semiconductor chip CP101 are electrically connected via multiple wires BW101.

[0060] In the first example of the semiconductor device PKG101, multiple lead LDs each function as an external terminal. Therefore, to increase the number of external terminals of the semiconductor device PKG101, it is necessary to increase the number of lead LDs. However, increasing the number of lead LDs leads to an increase in the package size (planar dimensions) of the semiconductor device PKG101. Therefore, it is desirable to increase the number of external terminals of the semiconductor device while suppressing the package size of the semiconductor device.

[0061] <Main Features and Effects> The semiconductor device package of this embodiment comprises a plurality of die pads DP1 and DP2 spaced apart from each other, a semiconductor chip CP mounted on the plurality of die pads DP1 and DP2, a plurality of leads LD arranged to surround the plurality of die pads DP1 and DP2 in a plan view, a plurality of wires BW, and a sealing portion MR that seals these together.

[0062] Multiple pads PD3 and multiple leads LD of the semiconductor chip CP are electrically connected via multiple wires BW3. A portion of each of the leads LD is exposed from the encapsulation portion MR. Therefore, each of the leads LD can function as an external terminal of the semiconductor device package.

[0063] In this embodiment, not only the multiple lead LDs but also the die pads DP1 and DP2 function as external terminals of the semiconductor device package. Therefore, the pad PD1 of the semiconductor chip CP and the die pad DP1 are electrically connected via wire BW1, and the pad PD2 of the semiconductor chip CP and the die pad DP2 are electrically connected via wire BW2. The die pads DP1 and DP2 are exposed from the lower surface MRb of the sealing portion MR. As a result, the multiple lead LDs exposed from the sealing portion MR, the die pad DP1 exposed from the lower surface MRb of the sealing portion MR, and the die pad DP2 exposed from the lower surface MRb of the sealing portion MR can each function as external terminals. Consequently, as shown in Figure 9, when mounting the semiconductor device package on the wiring board PB, the multiple lead LDs and die pads DP1 and DP2 of the semiconductor device package can be connected to the multiple electrodes TE (TE1, TE2, TE3) of the wiring board PB, respectively.

[0064] The die pads DP1 and DP2 in the semiconductor device PKG of this embodiment have a configuration in which the single die pad DP101 in the semiconductor device PKG101 of the first study example is divided into two die pads DP1 and DP2. Therefore, in a plan view, the semiconductor chip CP partially overlaps with each of the die pads DP1 and DP2. Consequently, dividing one die pad DP101 into two die pads DP1 and DP2 does not affect the package size (planar dimensions) of the semiconductor device.

[0065] When comparing the semiconductor device package of this embodiment with the semiconductor device package 101 of the first study example, the number of external terminals in the semiconductor device package of this embodiment can be greater than that of the semiconductor device package 101 of the first study example, because the die pads DP1 and DP2 can function as external terminals. Therefore, compared to the semiconductor device package 101 of the first study example, the number of external terminals in the semiconductor device package of this embodiment can be increased without changing the package size.

[0066] Furthermore, when comparing the semiconductor device package of this embodiment with the semiconductor device package 101 of the first study example, if the number of external terminals is the same, the number of lead LDs in the semiconductor device package of this embodiment can be reduced compared to the number of leads in the semiconductor device package 101 of the first study example. Reducing the number of leads makes it possible to reduce the package size. Therefore, compared to the semiconductor device package 101 of the first study example, the package size of the semiconductor device package of this embodiment can be reduced without changing the number of external terminals.

[0067] Therefore, in this embodiment, it is possible to increase the number of terminals of a semiconductor device while suppressing the package size of the semiconductor device. In other words, it is possible to increase the number of external terminals of the semiconductor device package and suppress the package size of the semiconductor device package at the same time.

[0068] Figure 12 is a plan view of the semiconductor device PKG201 of the second example considered by the inventors. Figure 12 corresponds to Figures 2 and 10 described above.

[0069] The semiconductor device PKG201 of the second study example shown in Figure 12 differs from the semiconductor device PKG101 of the first study example shown in Figures 10 and 11 in that the pad PD102 of semiconductor CP101 is electrically connected to the die pad DP101 via wire BW101. Therefore, in the case of the semiconductor device PKG201 of the second study example shown in Figure 12, one die pad DP101 exposed from the lower surface of the sealing portion MR can also function as an external terminal.

[0070] In contrast, in this embodiment, since the multiple (two in this case) die pads exposed from the lower surface MRb of the sealing portion MR can function as external terminals, the number of external terminals can be further increased compared to the semiconductor device PKG201 of the second study example shown in Figure 12. Therefore, compared to the semiconductor device PKG201 of the second study example, the number of external terminals in the semiconductor device PKG of this embodiment can be further increased without changing the package size. Accordingly, in this embodiment, the number of terminals in the semiconductor device can be increased while suppressing the package size of the semiconductor device. In other words, it is possible to increase the number of external terminals in the semiconductor device PKG and suppress the package size of the semiconductor device PKG at the same time.

[0071] <Regarding the connection between semiconductor chips and die pads> This section explains which of the multiple pads PD of a semiconductor chip CP is preferable to connect to the die pad via a wire BW.

[0072] In this embodiment, of the multiple pads PD of the semiconductor chip CP, pad PD1 is electrically connected to die pad DP1 via wire BW1, and pad PD2 is electrically connected to die pad DP2 via wire BW2. It is preferable that pads PD1 and PD2 are power supply pads rather than signal pads. It is preferable that each signal pad included in the multiple pads PD of the semiconductor chip CP is electrically connected to a lead LD rather than die pads DP1 and DP2 via wire BW3. For this reason, the multiple pads PD3 of the semiconductor chip CP include multiple signal pads.

[0073] Here, a pad PD that receives or outputs a signal is referred to as a signal pad. A pad PD that receives (receives) ground potential (reference potential) or power supply potential is referred to as a power supply pad. Note that power supply potential refers to a power supply potential that is higher than ground potential.

[0074] It is desirable that the signal transmission path be as free from interference from other parts (external sources) as possible. If the signal pad is connected to the die pad DP1 via wire BW, the signal transmission path formed by the die pad DP1, wire BW, and signal pad becomes more susceptible to interference from other parts due to the fact that the die pad DP1 is larger than the lead LD and that the die pad DP1 overlaps with the semiconductor chip CP in a plan view. Similarly, if the signal pad is connected to the die pad DP2 via wire BW, the signal transmission path formed by the die pad DP2, wire BW, and signal pad becomes more susceptible to interference from other parts (external sources) due to the fact that the die pad DP2 is larger than the lead LD and that the die pad DP2 overlaps with the semiconductor chip CP in a plan view. For this reason, it is preferable to connect the signal pads, which form the signal transmission path, to the lead LD via wire BW rather than to the die pads DP1 and DP2. In other words, it is preferable not to use the die pads DP1 and DP2 in the signal transmission path. This suppresses interference from other parts (external sources) to the signal transmission path. As a result, the performance of semiconductor devices can be improved.

[0075] On the other hand, it is desirable that the supply path for ground potential to the semiconductor chip CP and the supply path for power potential to the semiconductor chip CP have low resistance. For this reason, power supply pads, rather than signal pads, are preferentially connected to die pad DP1 or die pad DP2. By connecting the power supply pad to die pad DP1, which is larger than lead LD, via wire BW, the resistance of the conductive path formed by die pad DP1, the power supply pad, and the wire BW connecting them can be reduced, thereby suppressing noise generation. Similarly, by connecting the power supply pad to die pad DP2, which is larger than lead LD, via wire BW, the resistance of the conductive path formed by die pad DP2, the power supply pad, and the wire BW connecting them can be reduced, thereby suppressing noise generation. As a result, the performance of the semiconductor device can be improved.

[0076] Therefore, in this embodiment, it is preferable to supply ground potential or power potential from die pad DP1 to pad PD1 via wire BW1. It is also preferable to supply ground potential or power potential from die pad DP2 to pad PD2 via wire BW2.

[0077] Furthermore, of the pads PD to which the power supply potential is supplied (input) and the pads PD to which the ground potential is supplied (input), it is more preferable to preferentially apply the pad PD to which the ground potential is supplied to pad PD1. That is, it is more preferable to supply the ground potential from die pad DP1 to pad PD1 via wire BW1. Furthermore, of the pads PD to which the power supply potential is supplied and the pads PD to which the ground potential is supplied, it is more preferable to preferentially apply the pad PD to which the ground potential is supplied to pad PD2. That is, it is more preferable to supply the ground potential from die pad DP2 to pad PD2 via wire BW2. This stabilizes the ground potential supplied from die pad DP1 to pad PD1 via wire BW1 and the ground potential supplied from die pad DP2 to pad PD2 via wire BW2, thereby more efficiently suppressing noise generation.

[0078] Next, let's consider the circuits within a semiconductor chip (CP). Semiconductor chips can contain either digital or analog circuits. Compared to analog circuits, digital circuits generate more noise and are therefore more prone to becoming noise sources. Furthermore, analog circuits are more susceptible to noise than digital circuits. In other words, analog circuits have lower noise immunity (resistance to noise) than digital circuits. Therefore, when a semiconductor chip (CP) includes digital circuits, it is desirable to suppress the noise generated by the digital circuits as much as possible. Also, when a semiconductor chip (CP) includes both digital and analog circuits, it is desirable to minimize the impact of noise generated by the digital circuits on the analog circuits.

[0079] Therefore, when the semiconductor chip CP includes a digital circuit, it is preferable to connect one of the pads PD for supplying ground potential to the digital circuit and the pad PD for supplying power potential to the digital circuit to the die pad DP1 or die pad DP2 via a wire BW. That is, it is preferable to apply one of the pads PD for supplying ground potential to the digital circuit in the semiconductor chip CP and the pad PD for supplying power potential to the digital circuit to the pad PD1 or pad PD2. More preferably, the pad PD for supplying ground potential to the digital circuit in the semiconductor chip CP is connected to the die pad DP1 or die pad DP2 via a wire BW. That is, the pad PD for supplying ground potential to the digital circuit in the semiconductor chip CP is applied to the pad PD1 or pad PD2. This reduces the resistance of the conductive path that supplies ground potential or power potential to the digital circuit, and thus suppresses noise generated in the digital circuit within the semiconductor chip CP.

[0080] Furthermore, if the semiconductor chip CP includes a digital circuit, a pad PD for supplying ground potential to the digital circuit can be connected to one of the die pads DP1 and DP2 via a wire BW, and a pad PD for supplying power potential to the digital circuit can be connected to the other die pad DP1 and DP2 via a wire BW. In other words, a pad PD for supplying ground potential to the digital circuit within the semiconductor chip CP can be applied to one of the pads PD1 and PD2, and a pad PD for supplying power potential to the digital circuit within the semiconductor chip CP can be applied to the other pad PD1 and PD2. This further suppresses noise generated in the digital circuit within the semiconductor chip CP.

[0081] Furthermore, if the semiconductor chip CP includes both analog and digital circuits, it is preferable to preferentially connect the pad PD for supplying ground potential or power potential to the digital circuit to die pad DP1 or die pad DP2 via wire BW. In other words, if the semiconductor chip CP includes both analog and digital circuits, it is preferable to preferentially apply the pad PD for supplying ground potential or power potential to the digital circuit within the semiconductor chip CP to pad PD1 or pad PD2. This makes it possible to suppress noise generated in the digital circuit within the semiconductor chip CP.

[0082] When a semiconductor chip CP includes both analog and digital circuits, a pad PD for supplying ground potential or power potential to the digital circuit can be applied to one of pads PD1 and PD2, and a pad PD for supplying ground potential or power potential to the analog circuit can be applied to the other of pads PD1 and PD2. For example, a pad PD for supplying ground potential or power potential to the digital circuit can be electrically connected to die pad DP1 via wire BW1, and a pad PD for supplying ground potential or power potential to the analog circuit can be electrically connected to die pad DP2 via wire BW2. This makes it possible to suppress noise generated in the analog circuit within the semiconductor chip CP while simultaneously suppressing noise generated in the digital circuit.

[0083] Next, an example of connecting a semiconductor chip's pads to its leads or die pads will be described below.

[0084] Figure 13 is an explanatory diagram showing an example of connection between the pad PD101 and the lead LD of the semiconductor chip CP101 in the semiconductor device PKG101 of the first study example shown in Figures 10 and 11. Figure 14 is an explanatory diagram showing an example of connection between the pad PD and the lead LD or die pad DP1 of the semiconductor chip CP in the semiconductor device PKG of this embodiment.

[0085] In Figure 13, the semiconductor chip CP101 has multiple pads PD101, including signal pads PD101a and PD101b and a power supply pad PD101c, and multiple leads LD, including leads LDa, LDb, and LDc. The signal pad PD101a of the semiconductor chip CP101 is electrically connected to lead LDa via wire BW101, and the signal pad PD101b of the semiconductor chip CP101 is electrically connected to lead LDb via wire BW101. Furthermore, the power supply pad PD101c of the semiconductor chip CP101 is electrically connected to lead LDc via wire BW101.

[0086] In Figure 14, the semiconductor chip CP has multiple pads PD, including signal pads PDa, PDB, and PDd, and a power supply pad PDc, and multiple leads LD, including leads LDa, LDb, and LDc. The signal pad PDa of the semiconductor chip CP is electrically connected to lead LDa via wire BW, and the signal pad PDb of the semiconductor chip CP is electrically connected to lead LDb via wire BW. Furthermore, the power supply pad PDc of the semiconductor chip CP is electrically connected to die pad DP1 via wire BW, and the signal pad PDd of the semiconductor chip CP is electrically connected to lead LDc via wire BW. In other words, in Figure 14, the power supply pad PDc is applied as pad PD1, and each of the signal pads PDa, PDb, and PDd is applied as pad PD3.

[0087] In Figure 14, by connecting the power supply pad PDc of the semiconductor chip CP to the die pad DP1 via wire BW instead of the lead LDc, the lead LDc can be connected to the signal pad PDd via wire BW. As a result, compared to Figure 13, in Figure 14, the number of effective signal pads on the semiconductor chip can be increased without changing the number of lead LDs.

[0088] Figure 15 is an explanatory diagram showing an example of connection between the semiconductor chip CP101 and the lead LD in the semiconductor device PKG101 of the first study example shown in Figures 10 and 11. Figure 16 is an explanatory diagram showing an example of connection between the semiconductor chip CP and the lead LD or die pad DP1 in the semiconductor device PKG of this embodiment.

[0089] In Figure 15, the semiconductor chip CP101 has multiple pads PD101, including a signal pad PD101e and power supply pads PD101f and PD101g. The multiple leads LD include leads LDe and LDF. The semiconductor chip CP101 includes a digital circuit DT1 and an analog circuit AN1. The power supply pad PD101f is a pad PD101 for supplying ground potential to the analog circuit AN1 within the semiconductor chip CP101, and the power supply pad PD101g is a pad PD101 for supplying ground potential to the digital circuit DT1 within the semiconductor chip CP101. The signal pad PD101e of the semiconductor chip CP101 is electrically connected to lead LDe via wire BW101. The power supply pads PD101f and PD101g of the semiconductor chip CP101 are each electrically connected to a common lead LDf via wire BW101.

[0090] In Figure 16, the semiconductor chip CP has multiple pads PD, including a signal pad PDe and power supply pads PDf and PDg, and multiple leads LD, including leads LDe and LDf. The semiconductor chip CP also has a digital circuit DT1 and an analog circuit AN1. The power supply pad PDf is a pad PD for supplying ground potential to the analog circuit AN1 within the semiconductor chip CP, and the power supply pad PDg is a pad PD for supplying ground potential to the digital circuit DT1 within the semiconductor chip CP. The signal pad PDe of the semiconductor chip CP is electrically connected to lead LDe via wire BW. The power supply pad PDf of the semiconductor chip CP is electrically connected to lead LDf via wire BW, and the power supply pad PDg of the semiconductor chip CP is electrically connected to die pad DP1 via wire BW. In other words, in Figure 16, the power supply pad PDg is applied as pad PD1, and the signal pad PDe and power supply pad PDf are applied as pad PD3, respectively.

[0091] In Figure 15, both the power supply pad PD101g, which supplies ground potential to the digital circuit DT1 within the semiconductor chip CP101, and the pad PD101f, which supplies ground potential to the analog circuit AN1 within the semiconductor chip CP101, are connected to a common lead LDf via wire BW101. As a result, the power supply pad PD101g, which supplies ground potential to the digital circuit DT1, and the power supply pad PD101f, which supplies ground potential to the analog circuit AN1, are electrically connected to each other via lead LDf and wire BW101. Consequently, noise generated in the digital circuit DT1 within the semiconductor chip CP101 is easily transmitted to the analog circuit AN1 within the semiconductor chip CP101 via the power supply pad PD101g, wire BW101, lead LDf, wire BW101, and power supply pad PD101f. This is undesirable because it reduces the reliability of the semiconductor device PKG101.

[0092] In contrast, in Figure 16, a power supply pad PDg (PD1) for supplying ground potential to the digital circuit DT1 within the semiconductor chip CP is connected to the die pad DP1 via wire BW (BW1), and a power supply pad PDf for supplying ground potential to the analog circuit AN1 within the semiconductor chip CP is connected to the lead LDf via wire BW. This suppresses or prevents noise generated in the digital circuit DT1 within the semiconductor chip CP from being transmitted to the analog circuit AN1 within the semiconductor chip CP via conductors outside the semiconductor chip CP. As a result, the reliability of the semiconductor device package can be improved.

[0093] Figure 17 is an explanatory diagram showing an example of the connection between the semiconductor chip CP101 and the die pad DP101 in the semiconductor device PKG201 of the second study example shown in Figure 12. Figure 18 is an explanatory diagram showing an example of the connection between the semiconductor chip CP and the die pads DP1 and DP2 in the semiconductor device PKG of this embodiment.

[0094] In Figure 17, the multiple pads of the semiconductor chip CP101 include a power supply pad PD102f for supplying ground potential to the analog circuit AN1 within the semiconductor chip CP101, and a power supply pad PD102g for supplying ground potential to the digital circuit DT1 within the semiconductor chip CP101. The power supply pads PD102f and PD102g of the semiconductor chip CP101 are electrically connected to a common die pad DP101 via wire BW101.

[0095] In Figure 18, the multiple pads PD of the semiconductor chip CP include a power supply pad PDf for supplying ground potential to the analog circuit AN1 within the semiconductor chip CP, and a power supply pad PDg for supplying ground potential to the digital circuit DT1 within the semiconductor chip CP. The power supply pad PDf of the semiconductor chip CP is electrically connected to the die pad DP1 via wire BW, and the power supply pad PDg of the semiconductor chip CP is electrically connected to the die pad DP2 via wire BW. In other words, in Figure 18, the power supply pad PDf is used as pad PD1, and the power supply pad PDg is used as pad PD2.

[0096] In the case of Figure 17, both the power supply pad PD102g, which supplies ground potential to the digital circuit DT1 within the semiconductor chip CP101, and the pad PD102f, which supplies ground potential to the analog circuit AN1 within the semiconductor chip CP101, are connected to the common die pad DP101 via wire BW101. As a result, the power supply pad PD102g for supplying ground potential to the digital circuit DT1 and the power supply pad PD102f for supplying ground potential to the analog circuit AN1 are electrically connected to each other via die pad DP101 and wire BW101. Consequently, noise generated in the digital circuit DT1 within the semiconductor chip CP101 is easily transmitted to the analog circuit AN1 within the semiconductor chip CP101 via power supply pad PD102g, wire BW101, die pad DP101, wire BW101, and power supply pad PD102f. This is undesirable because it reduces the reliability of the semiconductor device PKG201.

[0097] In contrast, in Figure 18, a power supply pad PDg (PD2) for supplying ground potential to the digital circuit DT1 within the semiconductor chip CP is connected to die pad DP2 via wire BW (BW2), and a power supply pad PDf (PD1) for supplying ground potential to the analog circuit AN1 within the semiconductor chip CP is connected to die pad DP1 via wire BW (BW1). Since die pads DP1 and DP2 are not connected via conductors and are electrically isolated from each other, noise generated in the digital circuit DT1 within the semiconductor chip CP can be suppressed or prevented from being transmitted to the analog circuit AN1 within the semiconductor chip CP via conductors outside the semiconductor chip CP. As a result, the reliability of the semiconductor device package can be improved.

[0098] Figures 19 and 20 are explanatory diagrams showing examples of connections between a semiconductor chip CP and multiple die pads DP1 and DP2 in the semiconductor device package of this embodiment.

[0099] In the cases of Figure 19 and Figure 20, the digital circuit DT11 and analog circuits AN21, AN22, and AN23 are formed within the semiconductor chip CP. Therefore, the multiple pads PD of the semiconductor chip CP include pad 11a for supplying ground potential to the digital circuit DT11 and pad 11b for supplying power potential to the digital circuit DT11. Ground potential is supplied to the digital circuit DT11 from pad 11a, and power potential is supplied to the digital circuit DT11 from pad 11b. The multiple pads PD of the semiconductor chip CP further include pad 21a for supplying ground potential to the analog circuit AN21 and pad 21b for supplying power potential to the analog circuit AN21. Ground potential is supplied to the analog circuit AN21 from pad 21a, and power potential is supplied to the analog circuit AN21 from pad 21b. The multiple pads PD of the semiconductor chip CP further include pad 22a for supplying ground potential to analog circuit AN22, pad 22b for supplying power potential to analog circuit AN22, pad 23a for supplying ground potential to analog circuit AN23, and pad 23b for supplying power potential to analog circuit AN23. Ground potential is supplied to analog circuit AN22 from pad 22a, and power potential is supplied to analog circuit AN22 from pad 22b. Ground potential is supplied to analog circuit AN23 from pad 23a, and power potential is supplied to analog circuit AN23 from pad 23b.

[0100] In the case of Figure 19, pad 11a for supplying ground potential to the digital circuit DT11 is electrically connected to die pad DP1 via wire BW1, and pad 11b for supplying power potential to the digital circuit DT11 is electrically connected to die pad DP2 via wire BW2. That is, in the case of Figure 19, pad 11a for supplying ground potential to the digital circuit DT11 is applied as pad PD1, and pad 11b for supplying power potential to the digital circuit DT11 is applied as pad PD2. As a result, the resistance of the conductive path supplying ground potential to the digital circuit DT11 and the resistance of the conductive path supplying power potential to the digital circuit DT11 can be reduced, thereby suppressing noise generated in the digital circuit DT11 within the semiconductor chip CP. This suppresses the impact of noise generated in the digital circuit DT11 on the analog circuits AN21, AN22, and AN23.

[0101] In the case of Figure 20, pad 11a for supplying ground potential to the digital circuit DT11 is electrically connected to die pad DP1 via wire BW1, and pad 21a for supplying ground potential to the analog circuit AN21 is electrically connected to die pad DP2 via wire BW2. That is, in the case of Figure 20, pad 11a for supplying ground potential to the digital circuit DT11 is applied as pad PD1, and pad 21a for supplying ground potential to the analog circuit AN21 is applied as pad PD2. As a result, the resistance of the conductive path supplying ground potential to the digital circuit DT11 and the resistance of the conductive path supplying ground potential to the analog circuit AN21 can be reduced, thereby suppressing noise generated in the digital circuit DT11 within the semiconductor chip CP while also suppressing noise generated in the analog circuit AN21.

[0102] Figure 21 is a plan view perspective showing a first modified example of the semiconductor device package of this embodiment, and corresponds to Figure 4 above. Figure 22 is a plan view perspective showing a second modified example of the semiconductor device package of this embodiment, and corresponds to Figure 4 above.

[0103] The planar shapes of the die pads DP1 and DP2 do not have to be rectangular. For example, as shown in Figure 21 or Figure 22, the planar shapes of the die pads DP1 and DP2 may be triangular.

[0104] (Embodiment 2) Figures 23 and 24 are plan perspective views of the semiconductor device PKG1 of this second embodiment, and Figures 25, 26, and 27 are cross-sectional views of the semiconductor device PKG1 of this second embodiment. Figure 23 corresponds to Figure 2, and Figure 24 corresponds to Figure 4. Furthermore, the cross-sectional view of the semiconductor device PKG1 along line B1-B1 in Figure 23 roughly corresponds to Figure 25, the cross-sectional view of the semiconductor device PKG1 along line B2-B2 in Figure 23 roughly corresponds to Figure 26, and the cross-sectional view of the semiconductor device PKG1 along line B3-B3 in Figure 23 roughly corresponds to Figure 27.

[0105] The differences between the semiconductor device PKG1 of this second embodiment, shown in Figures 23 to 27, and the semiconductor device PKG of the first embodiment, shown in Figures 1 to 8, will be explained below.

[0106] While the semiconductor device PKG1 of Embodiment 1 had two die pads DP1 and DP2, the semiconductor device PKG1 of Embodiment 2 has three die pads DP1, DP2, and DP3.

[0107] The multiple lead LDs in semiconductor device PKG1 are arranged in a plan view to surround die pads DP1, DP2, and DP3. In a plan view, no lead LDs are positioned between die pads DP1, DP2, and DP3. Die pads DP1, DP2, and DP3 are not connected to any of the lead LDs.

[0108] Die pads DP1, DP2, and DP3 are separated from each other. In Figures 23 and 24, die pads DP1 and DP2 are separated from each other in the Y direction, die pads DP3 and DP2 are separated from each other in the Y direction, and die pads DP1 and DP3 are separated from each other in the X direction. A portion of the sealing part MR is interposed between die pads DP1, DP2, and DP3. Therefore, die pads DP1, DP2, and DP3 are not connected via conductors and are electrically isolated from each other.

[0109] The suspension lead TL1 is integrally connected to the die pad DP1, the suspension lead TL4 is integrally connected to the die pad DP3, and the suspension leads TL2 and TL3 are each integrally connected to the die pad DP2.

[0110] Specifically, one end of the suspension lead TL1 is integrally connected to the die pad DP1, and the suspension lead TL1 extends within the sealing portion MR from the die pad DP1 toward the corner formed by the sides S1 and S2 of the sealing portion MR. One end of the suspension lead TL4 is integrally connected to the die pad DP3, and the suspension lead TL4 extends within the sealing portion MR from the die pad DP3 toward the corner formed by the sides S1 and S4 of the sealing portion MR. One end of the suspension lead TL2 is integrally connected to the die pad DP2, and the suspension lead TL2 extends within the sealing portion MR from the die pad DP2 toward the corner formed by the sides S2 and S3 of the sealing portion MR. One end of the suspension lead TL3 is integrally connected to the die pad DP2, and the suspension lead TL3 extends within the sealing portion MR from the die pad DP2 toward the corner formed by the sides S3 and S4 of the sealing portion MR.

[0111] The suspension lead TL1 is used to support the die pad DP1 to the frame of the lead frame during the manufacturing of the semiconductor device PKG1. The suspension lead TL4 is used to support the die pad DP3 to the frame of the lead frame during the manufacturing of the semiconductor device PKG1. The suspension leads TL2 and TL3 are used to support the die pad DP2 to the frame of the lead frame during the manufacturing of the semiconductor device PKG1.

[0112] The semiconductor chip CP is positioned on die pads DP1, DP2, and DP3. Specifically, a common semiconductor chip CP is mounted on die pad DP1 via bonding material BD, on die pad DP2 via bonding material BD, and on die pad DP3 via bonding material BD. In a plan view, the semiconductor chip CP partially overlaps with each of the die pads DP1, DP2, and DP3. That is, in a plan view, a portion of the semiconductor chip CP overlaps with die pad DP1, another portion overlaps with die pad DP2, and yet another portion overlaps with die pad DP3. Each of die pads DP1, DP2, and DP3 can be considered a chip mounting area on which the common semiconductor chip CP is mounted.

[0113] The semiconductor chip CP has multiple pads PD, which include pad PD1, pad PD2, pad PD4, and multiple pads PD3. The semiconductor device PKG1 has multiple wires BW, which include wire BW1, wire BW2, wire BW4, and multiple wires BW3.

[0114] Pad PD1 of semiconductor chip CP is electrically connected to die pad DP1 via wire BW1. Pad PD2 of semiconductor chip CP is electrically connected to die pad DP2 via wire BW2. Pad PD4 of semiconductor chip CP is electrically connected to die pad DP3 via wire BW4. Multiple pads PD3 of semiconductor chip CP are electrically connected to multiple leads LD, respectively, via multiple wires BW3.

[0115] Each die pad DP1, DP2, and DP3 is sealed within the sealing portion MR, but the lower surfaces of die pad DP1, die pad DP2, and die pad DP3 are exposed from the lower surface MRb of the sealing portion MR. The lower surfaces of die pad DP1, die pad DP2, and die pad DP3 exposed from the lower surface MRb of the sealing portion MR can each function as external terminals of the semiconductor device PKG1. A plating layer (not shown), such as a solder plating layer, can also be formed on the lower surfaces of die pads DP1, DP2, and DP3 exposed from the lower surface MRb of the sealing portion MR.

[0116] When the semiconductor device PKG1 is mounted on the wiring board PB (see Figure 9), multiple leads LD and die pads DP1, DP2, and DP3 exposed from the lower surface MRb of the sealing portion MR are electrically connected to multiple electrodes TE of the wiring board PB via a conductive bonding material SD.

[0117] In the semiconductor device PKG1 of this second embodiment, multiple lead LDs and multiple die pads DP1, DP2, and DP3 each function as external terminals. Since the semiconductor device PKG1 has three die pads, the number of external terminals in the semiconductor device PKG1 of this second embodiment can be even greater than the number of external terminals in the semiconductor device PKG of the first embodiment. Therefore, compared to the semiconductor device PKG of the first embodiment, the number of external terminals in the semiconductor device PKG1 of this second embodiment can be further increased without changing the package size. Thus, the number of terminals in the semiconductor device can be further increased while suppressing the package size of the semiconductor device.

[0118] In addition, in the case of Figure 23, one pad PD1 is electrically connected to the die pad DP1 via wire BW1, one pad PD2 is electrically connected to the die pad DP2 via wire BW2, and one pad PD4 is electrically connected to the die pad DP3 via wire BW4. It is also possible to provide multiple pads PD1 on the semiconductor chip CP and electrically connect each of the multiple pads PD1 to the die pad DP1 via multiple wires BW1. Similarly, it is possible to provide multiple pads PD2 on the semiconductor chip CP and electrically connect each of the multiple pads PD2 to the die pad DP2 via multiple wires BW2. Similarly, it is possible to provide multiple pads PD4 on the semiconductor chip CP and electrically connect each of the multiple pads PD4 to the die pad DP3 via multiple wires BW4.

[0119] Figures 28 and 29 are explanatory diagrams showing an example of the connection between the semiconductor chip CP and multiple die pads DP1, DP2, and DP3 in the semiconductor device PKG1 of this second embodiment.

[0120] Similar to the cases of Figure 19 and Figure 20 above, in Figures 28 and 29, the digital circuit DT11 and analog circuits AN21, AN22, and AN23 are formed within the semiconductor chip CP. Therefore, similar to the cases of Figure 19 and Figure 20 above, in Figures 28 and 29, the multiple pads PD of the semiconductor chip CP include the aforementioned pads 11a, 11b, 21a, 21b, 22a, 22b, 23a, and 23b.

[0121] In the case of Figure 28, pad 11a for supplying ground potential to the digital circuit DT11 is electrically connected to die pad DP1 via wire BW1, and pad 11b for supplying power potential to the digital circuit DT11 is electrically connected to die pad DP2 via wire BW2. Also, pad 21a for supplying ground potential to the analog circuit AN21 is electrically connected to die pad DP3 via wire BW4. In other words, in the case of Figure 28, pad 11a for supplying ground potential to the digital circuit DT11 is applied as pad PD1, pad 11b for supplying power potential to the digital circuit DT11 is applied as pad PD2, and pad 21a for supplying ground potential to the analog circuit AN21 is applied as pad PD4. As a result, the resistance of the conductive path supplying ground potential to the digital circuit DT11 and the resistance of the conductive path supplying power potential to the digital circuit DT11 can be reduced, thereby suppressing noise generated in the digital circuit DT11 within the semiconductor chip CP. This suppresses the impact of noise generated in the digital circuit DT11 on the analog circuits AN21, AN22, and AN23. Furthermore, by reducing the resistance of the conductive path that supplies ground potential to the analog circuit AN21, noise generated in the analog circuit AN21 within the semiconductor chip CP can be suppressed.

[0122] In the case of Figure 29, pad 11a for supplying ground potential to the digital circuit DT11 is electrically connected to die pad DP1 via wire BW1. Also, pad 21a for supplying ground potential to the analog circuit AN21 is electrically connected to die pad DP2 via wire BW2, and pad 22a for supplying ground potential to the analog circuit AN22 is electrically connected to die pad DP3 via wire BW4. That is, in the case of Figure 29, pad 11a for supplying ground potential to the digital circuit DT11 is applied as pad PD1, pad 21a for supplying ground potential to the analog circuit AN21 is applied as pad PD2, and pad 22a for supplying ground potential to the analog circuit AN22 is applied as pad PD4. This reduces the resistance of the conductive path supplying ground potential to the digital circuit DT11, thereby suppressing noise generated in the digital circuit DT11 within the semiconductor chip CP. This suppresses the impact of noise generated in the digital circuit DT11 on the analog circuits AN21, AN22, and AN23. Furthermore, since the resistance of the conductive path supplying ground potential to analog circuit AN21 and the resistance of the conductive path supplying ground potential to analog circuit AN22 can be reduced, noise generated in analog circuits AN21 and AN22 within the semiconductor chip CP can be suppressed.

[0123] (Embodiment 3) Figures 30 and 31 are plan perspective views of the semiconductor device PKG2 of this third embodiment, and Figures 32, 33, and 34 are cross-sectional views of the semiconductor device PKG2 of this third embodiment. Figure 30 corresponds to Figure 2, and Figure 31 corresponds to Figure 4. Furthermore, the cross-sectional view of the semiconductor device PKG2 along the line C1-C1 in Figure 30 roughly corresponds to Figure 32, the cross-sectional view of the semiconductor device PKG2 along the line C2-C2 in Figure 30 roughly corresponds to Figure 33, and the cross-sectional view of the semiconductor device PKG2 along the line C3-C3 in Figure 30 roughly corresponds to Figure 34.

[0124] The differences between the semiconductor device PKG2 of this embodiment 3, shown in Figures 30 to 34, and the semiconductor device PKG of embodiment 1, shown in Figures 1 to 8, will be explained below.

[0125] The semiconductor device PKG2 of this third embodiment has four die pads DP1, DP2, DP3, and DP4.

[0126] The multiple lead LDs in the semiconductor device PKG2 are arranged in a plan view to surround die pads DP1, DP2, DP3, and DP4. In a plan view, no lead LDs are positioned between die pads DP1, DP2, DP3, and DP4. Each of the die pads DP1, DP2, DP3, and DP4 is not connected to any of the lead LDs.

[0127] Die pads DP1, DP2, DP3, and DP4 are separated from each other. In Figures 30 and 31, die pads DP1 and DP2 are separated from each other in the Y direction, die pads DP3 and DP4 are separated from each other in the Y direction, die pads DP1 and DP3 are separated from each other in the X direction, and die pads DP2 and DP4 are separated from each other in the X direction. A part of the sealing portion MR is interposed between die pads DP1, DP2, DP3, and DP4. Therefore, die pads DP1, DP2, DP3, and DP4 are not connected via conductors and are electrically isolated from each other.

[0128] The suspension lead TL1 is integrally connected to the die pad DP1, the suspension lead TL4 is integrally connected to the die pad DP3, the suspension lead TL2 is integrally connected to the die pad DP2, and the suspension lead TL3 is integrally connected to the die pad DP4.

[0129] Specifically, one end of the suspension lead TL1 is integrally connected to the die pad DP1, and the suspension lead TL1 extends within the sealing portion MR from the die pad DP1 toward the corner formed by the sides S1 and S2 of the sealing portion MR. One end of the suspension lead TL4 is integrally connected to the die pad DP3, and the suspension lead TL4 extends within the sealing portion MR from the die pad DP3 toward the corner formed by the sides S1 and S4 of the sealing portion MR. One end of the suspension lead TL2 is integrally connected to the die pad DP2, and the suspension lead TL2 extends within the sealing portion MR from the die pad DP2 toward the corner formed by the sides S2 and S3 of the sealing portion MR. One end of the suspension lead TL3 is integrally connected to the die pad DP4, and the suspension lead TL3 extends within the sealing portion MR from the die pad DP4 toward the corner formed by the sides S3 and S4 of the sealing portion MR.

[0130] The suspension lead TL1 is used to support the die pad DP1 to the frame of the lead frame during the manufacturing of the semiconductor device PKG2. The suspension lead TL4 is used to support the die pad DP3 to the frame of the lead frame during the manufacturing of the semiconductor device PKG2. The suspension lead TL2 is used to support the die pad DP2 to the frame of the lead frame during the manufacturing of the semiconductor device PKG2. The suspension lead TL3 is used to support the die pad DP4 to the frame of the lead frame during the manufacturing of the semiconductor device PKG2.

[0131] The semiconductor chip CP is positioned on die pads DP1, DP2, DP3, and DP4. Specifically, a common semiconductor chip CP is mounted on die pad DP1 via bonding material BD, on die pad DP2 via bonding material BD, on die pad DP3 via bonding material BD, and on die pad DP4 via bonding material BD. In a plan view, the semiconductor chip CP partially overlaps with each of the die pads DP1, DP2, DP3, and DP4. That is, in a plan view, a portion of the semiconductor chip CP overlaps with die pad DP1, another portion overlaps with die pad DP2, yet another portion overlaps with die pad DP3, and yet another portion overlaps with die pad DP4. Each of the die pads DP1, DP2, DP3, and DP4 can be considered a chip mounting area on which the common semiconductor chip CP is mounted.

[0132] The semiconductor chip CP has multiple pads PD, which include pads PD1, PD2, PD4, PD5, and multiple pads PD3. The semiconductor device PKG2 has multiple wires BW, which include wires BW1, BW2, BW4, BW5, and multiple wires BW3.

[0133] Pad PD1 of semiconductor chip CP is electrically connected to die pad DP1 via wire BW1. Pad PD2 of semiconductor chip CP is electrically connected to die pad DP2 via wire BW2. Pad PD4 of semiconductor chip CP is electrically connected to die pad DP3 via wire BW4. Pad PD5 of semiconductor chip CP is electrically connected to die pad DP4 via wire BW5. Multiple pads PD3 of semiconductor chip CP are electrically connected to multiple leads LD, respectively, via multiple wires BW3.

[0134] Each die pad DP1, DP2, DP3, and DP4 is sealed within the sealing portion MR, but the lower surfaces of die pads DP1, DP2, DP3, and DP4 are exposed from the lower surface MRb of the sealing portion MR. The lower surfaces of die pads DP1, DP2, DP3, and DP4 exposed from the lower surface MRb of the sealing portion MR can each function as external terminals of the semiconductor device PKG2. A plating layer (not shown), such as a solder plating layer, can also be formed on the lower surfaces of die pads DP1, DP2, DP3, and DP4 exposed from the lower surface MRb of the sealing portion MR.

[0135] When mounting the semiconductor device PKG2 onto the wiring board PB (see Figure 9), multiple leads LD and die pads DP1, DP2, DP3, and DP4 exposed from the lower surface MRb of the sealing portion MR are electrically connected to multiple electrodes TE of the wiring board PB via a conductive bonding material SD.

[0136] In the semiconductor device PKG2 of this third embodiment, multiple lead LDs and multiple die pads DP1, DP2, DP3, and DP4 each function as external terminals. Since the semiconductor device PKG2 has four die pads, the number of external terminals in the semiconductor device PKG2 of this third embodiment can be even greater than the number of external terminals in the semiconductor device PKG1 of the second embodiment. Therefore, compared to the semiconductor device PKG1 of the second embodiment, the number of external terminals in the semiconductor device PKG2 of this third embodiment can be further increased without changing the package size. Thus, the number of terminals in the semiconductor device can be further increased while suppressing the package size of the semiconductor device.

[0137] In addition, in the case of Figure 30, one pad PD1 is electrically connected to the die pad DP1 via wire BW1, one pad PD2 is electrically connected to the die pad DP2 via wire BW2, one pad PD4 is electrically connected to the die pad DP3 via wire BW4, and one pad PD5 is electrically connected to the die pad DP4 via wire BW5. It is also possible to provide multiple pads PD1 on the semiconductor chip CP and electrically connect multiple pads PD1 to the die pad DP1 via multiple wires BW1. Similarly, it is possible to provide multiple pads PD2 on the semiconductor chip CP and electrically connect multiple pads PD2 to the die pad DP2 via multiple wires BW2. Similarly, it is possible to provide multiple pads PD4 on the semiconductor chip CP and electrically connect multiple pads PD4 to the die pad DP3 via multiple wires BW4. Similarly, it is possible to provide multiple pads PD5 on the semiconductor chip CP and electrically connect multiple pads PD5 to the die pad DP4 via multiple wires BW5.

[0138] Figures 35 and 36 are explanatory diagrams showing an example of the connection between the semiconductor chip CP and multiple die pads DP1, DP2, DP3, and DP4 in the semiconductor device PKG2 of this third embodiment.

[0139] Similar to Figures 19 and 20, in Figure 35, the semiconductor chip CP contains the digital circuit DT11 and the analog circuits AN21, AN22, and AN23. Therefore, similar to Figures 19 and 20, in Figure 35, the multiple pads PD of the semiconductor chip CP include the pads 11a, 11b, 21a, 21b, 22a, 22b, 23a, and 23b described above. In Figure 36, the semiconductor chip CP contains the digital circuits DT11 and DT12 and the analog circuits AN21 and AN22. Therefore, in Figure 36, in addition to the pads 11a, 11b, 21a, 21b, 22a, and 22b described above, the multiple pads PD of the semiconductor chip CP further include a pad 12a for supplying ground potential to the digital circuit DT12 and a pad 12b for supplying power potential to the digital circuit DT12. Pad 12a supplies ground potential to the digital circuit DT12, and pad 12b supplies power potential to the digital circuit DT12.

[0140] In the case of Figure 35, pad 11a for supplying ground potential to the digital circuit DT11 is electrically connected to die pad DP1 via wire BW1, and pad 11b for supplying power potential to the digital circuit DT11 is electrically connected to die pad DP2 via wire BW2. Also, pad 21a for supplying ground potential to the analog circuit AN21 is electrically connected to die pad DP3 via wire BW4, and pad 21b for supplying power potential to the analog circuit AN21 is electrically connected to die pad DP4 via wire BW5. That is, in the case of Figure 35, pad 11a for supplying ground potential to the digital circuit DT11 is applied as pad PD1, and pad 11b for supplying power potential to the digital circuit DT11 is applied as pad PD2. Also, pad 21a for supplying ground potential to the analog circuit AN21 is applied as pad PD4, and pad 21b for supplying power potential to the analog circuit AN21 is applied as pad PD5. This reduces the resistance of the conductive path supplying ground potential to the digital circuit DT11 and the resistance of the conductive path supplying power potential to the digital circuit DT11, thereby suppressing noise generated in the digital circuit DT11 within the semiconductor chip CP. This reduces the impact of noise generated in the digital circuit DT11 on the analog circuits AN21, AN22, and AN23. Furthermore, by reducing the resistance of the conductive path supplying ground potential to the analog circuit AN21 and the resistance of the conductive path supplying power potential to the analog circuit AN21, noise generated in the analog circuit AN21 within the semiconductor chip CP can be suppressed.

[0141] In the case of Figure 36, pad 11a for supplying ground potential to digital circuit DT11 is electrically connected to die pad DP1 via wire BW1, and pad 11b for supplying power potential to digital circuit DT11 is electrically connected to die pad DP2 via wire BW2. Also, pad 12a for supplying ground potential to digital circuit DT12 is electrically connected to die pad DP3 via wire BW4, and pad 12b for supplying power potential to digital circuit DT12 is electrically connected to die pad DP4 via wire BW5. That is, in the case of Figure 36, pad 11a for supplying ground potential to digital circuit DT11 is applied as pad PD1, and pad 11b for supplying power potential to digital circuit DT11 is applied as pad PD2. Also, pad 12a for supplying ground potential to digital circuit DT12 is applied as pad PD4, and pad 12b for supplying power potential to digital circuit DT12 is applied as pad PD5. This reduces the resistance of the conductive path supplying ground potential to digital circuit DT11 and the conductive path supplying power potential to digital circuit DT11, thereby suppressing noise generated in digital circuit DT11 within the semiconductor chip CP. Furthermore, it reduces the resistance of the conductive path supplying ground potential to digital circuit DT12 and the conductive path supplying power potential to digital circuit DT12, thereby suppressing noise generated in digital circuit DT12 within the semiconductor chip CP. This prevents analog circuits AN21 and AN22 from being affected by noise generated in digital circuits DT11 and DT12.

[0142] The present invention has been described in detail above based on its embodiments, but it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence.

[0143] Taking Embodiments 1, 2, and 3 as a whole, the semiconductor device comprises a plurality of die pads spaced apart from each other, with semiconductor chips CP mounted on the plurality of die pads. In a plan view, the semiconductor chips CP partially overlap each of the plurality of die pads of the semiconductor device. The plurality of die pads of the semiconductor device are exposed from the lower surface MRb of the sealing portion MR, and in a plan view, a plurality of leads LD are arranged to surround the plurality of die pads. The plurality of die pads of the semiconductor device are electrically connected to a plurality of corresponding pads PD via a plurality of conductive connecting members (wires BW). When the semiconductor device is mounted on the wiring board PB (see Figure 9), the plurality of leads LD and the plurality of die pads exposed from the lower surface MRb of the sealing portion MR are electrically connected to a plurality of electrodes TE of the wiring board PB via a conductive bonding material SD. The potential supplied to each die pad of the semiconductor device is preferably the power supply potential or the ground potential.

[0144] In the first embodiment described above, the semiconductor device has two die pads; in the second embodiment described above, the semiconductor device has three die pads; and in the third embodiment described above, the semiconductor device has four die pads. The semiconductor device may have five or more die pads. [Explanation of Symbols]

[0145] 11a, 11b, 12a, 12b, 21a, 21b, 22a, 22b, 23a, 23b pads AN1, AN21, AN22, AN23 Analog Circuits BD bonding material BW, BW1, BW2, BW3, BW4, BW5, BW101 Wire CP, CP101 semiconductor chip D11, D12, D13, D14, D21, D22, D23, D24 Side view DP1, DP2, DP3, DP4, DP101 die pads DT1, DT11, DT12 Digital Circuits LD,LD1,LD2,LD3,LD4,LDa,LDb,LDc,LDe,LDf Lead MR sealing part MRa top surface MRb bottom side TL1, TL2, TL3, TL4 Suspension Leads PB wiring board PD, PD1, PD2, PD3, PD4, PD5, PDa, PDb, PDc, PDd, PDe, PDf, PDg, PD101, PD101a, PD101b, PD101c, PD101e, PD101f, PD101g, PD102 pads PKG, PKG1, PKG2, PKG101, PKG201 Semiconductor S1,S2,S3,S4 side SD bonding material TE, TE1, TE2, TE3 electrodes

Claims

1. Multiple chip mounting sections spaced apart from each other, A semiconductor chip having multiple pads is mounted on the aforementioned multiple chip mounting sections, In a plan view, a plurality of leads are arranged to surround the plurality of chip mounting portions, Multiple conductive connecting members, The semiconductor chip, the plurality of chip mounting sections, the plurality of conductive connecting members, and the resin encapsulant that seals the plurality of leads, Equipped with, The aforementioned plurality of pads include a plurality of first pads, a second pad, and a third pad. The aforementioned plurality of chip mounting sections include a first chip mounting section and a second chip mounting section, The plurality of conductive connecting members include a plurality of first conductive connecting members that electrically connect the plurality of first pads and the plurality of leads, a second conductive connecting member that electrically connects the second pad and the first chip mounting portion, and a third conductive connecting member that electrically connects the third pad and the second chip mounting portion. The resin encapsulant has a first main surface and a second main surface opposite to the first main surface. A portion of each of the aforementioned multiple leads is exposed from the resin encapsulant, A semiconductor device in which the first chip mounting portion and the second chip mounting portion are exposed from the second main surface of the resin encapsulant.

2. In the semiconductor device described in claim 1, In a plan view, the semiconductor chip partially overlaps each of the plurality of chip mounting areas in the semiconductor device.

3. In the semiconductor device described in claim 1, A semiconductor device wherein the plurality of leads exposed from the resin encapsulant, the first chip mounting portion exposed from the second main surface of the resin encapsulant, and the second chip mounting portion exposed from the second main surface of the resin encapsulant each function as an external terminal.

4. In the semiconductor device described in claim 1, A semiconductor device in which the plurality of conductive connecting members are each wires.

5. In the semiconductor device described in claim 1, The semiconductor chips are mounted on the upper surface of the plurality of chip mounting sections. A semiconductor device in which the lower surfaces of the plurality of chip mounting portions are exposed from the second main surface of the resin encapsulant.

6. In the semiconductor device described in claim 1, The aforementioned plurality of first pads include a plurality of signal pads, A semiconductor device in which the second pad and the third pad are power supply pads, respectively.

7. In the semiconductor device described in claim 1, The first potential supplied to the first chip mounting section is supplied to the second pad of the semiconductor chip via the second conductive connecting member. The second potential supplied to the second chip mounting section is supplied to the third pad of the semiconductor chip via the third conductive connecting member. The first potential is the first power supply potential or the first ground potential. A semiconductor device wherein the second potential is the second power supply potential or the second ground potential.

8. In the semiconductor device described in claim 1, The first ground potential supplied to the first chip mounting section is supplied to the second pad of the semiconductor chip via the second conductive connecting member. A semiconductor device wherein the second ground potential supplied to the second chip mounting portion is supplied to the third pad of the semiconductor chip via the third conductive connecting member.

9. In the semiconductor device described in claim 7, The semiconductor chip includes a digital circuit, A semiconductor device in which the first potential is supplied from the second pad to the digital circuit.

10. In the semiconductor device described in claim 7, The semiconductor chip includes a digital circuit, A semiconductor device in which the first potential and the second potential are supplied to the digital circuit from the second pad.

11. In the semiconductor device according to claim 7, The aforementioned semiconductor chip includes digital circuits and analog circuits. The first potential is supplied from the second pad to the digital circuit. A semiconductor device in which the second potential is supplied from the third pad to the analog circuit.

12. In the semiconductor device described in claim 1, The first chip mounting section is not connected to any of the multiple leads. The second chip mounting portion is a semiconductor device that is not connected to any of the multiple leads.

13. In the semiconductor device according to claim 12, A first suspension lead integrally connected to the first chip mounting section, A second suspension lead integrally connected to the second chip mounting section, Furthermore, In a plan view, the first suspension lead extends from the first chip mounting portion toward the first corner portion of the resin encapsulant within the resin encapsulant, In a plan view, the second suspension lead extends within the resin encapsulation from the second chip mounting portion toward the second corner portion of the resin encapsulation, in a semiconductor device.

14. In the semiconductor device described in claim 1, The aforementioned plurality of chip mounting sections further include a third chip mounting section, The plurality of pads further include a fourth pad, The plurality of conductive connecting members further include a fourth conductive connecting member that electrically connects the fourth pad and the third chip mounting portion. A semiconductor device in which the third chip mounting portion is exposed from the second main surface of the resin encapsulant.

15. In the semiconductor device according to claim 14, A semiconductor device wherein the plurality of leads exposed from the resin encapsulant, the first chip mounting portion exposed from the second main surface of the resin encapsulant, the second chip mounting portion exposed from the second main surface of the resin encapsulant, and the third chip mounting portion exposed from the second main surface of the resin encapsulant each function as an external terminal.

16. In the semiconductor device according to claim 14, The aforementioned plurality of chip mounting sections further include a fourth chip mounting section, The aforementioned plurality of pads further include a fifth pad, The plurality of conductive connecting members further include a fifth conductive connecting member that electrically connects the fifth pad and the fourth chip mounting portion. A semiconductor device in which the fourth chip mounting portion is exposed from the second main surface of the resin encapsulant.

17. In the semiconductor device according to claim 16, A semiconductor device wherein the plurality of leads exposed from the resin encapsulant, the first chip mounting portion exposed from the second main surface of the resin encapsulant, the second chip mounting portion exposed from the second main surface of the resin encapsulant, the third chip mounting portion exposed from the second main surface of the resin encapsulant, and the fourth chip mounting portion exposed from the second main surface of the resin encapsulant each function as an external terminal.

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