Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device with reduced contact resistance. [Solution] The present invention relates to a semiconductor device 1 and a method for manufacturing the same, comprising: a first word line structure 300 recessed from the surface of a semiconductor layer SL into the interior of the semiconductor layer SL by a first depth and extending along a first direction X; a first active region 100 disposed inside the semiconductor layer SL and extending in an oblique direction DG with respect to the first direction X and overlapping with the first word line structure 300; a first bit line pad region 430 overlapping with one end of the first active region 100, in contact with one side of the first word line structure 300, and recessed from the surface of the semiconductor layer SL into the interior of the semiconductor layer SL by a second depth shallower than the first depth; and a first storage node pad region 530 overlapping with the other end of the first active region 100, in contact with the other side of the first word line structure 300, and separated from the first bit line pad region 430 in an oblique direction DG.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a plurality of active regions. Background Art

[0002] Among semiconductor devices, a semiconductor device having a memory function is a device that can be used to store information, and may include an array including individual memory cells each containing a transistor. An example of a semiconductor device having a memory function is dynamic random access memory (DRAM). The DRAM may include bit lines and word lines that can intersect each other in perpendicular directions, the bit lines and word lines can extend across the array including the memory cells, and the bit lines and the word lines can be used to access individual memory cells.

[0003] Depending on how individual memory cells are designed and arranged, the performance, cell stability and reliability, power efficiency, process easiness and cost of the memory can vary, and continuous research has been conducted on the design of cell arrays for memory elements and methods for manufacturing the same. Summary of the Invention Problems to be Solved by the Invention

[0004] Embodiments of the present invention can provide a semiconductor device with reduced contact resistance of bit line contacts and storage node contacts. Furthermore, embodiments of the present invention can simplify the manufacturing process of a semiconductor device with reduced contact resistance of bit line contacts and storage node contacts, and achieve cost reduction. Means for Solving the Problems

[0005] A semiconductor device according to one embodiment of the present invention may include: a semiconductor layer; a first word line structure recessed from the surface of the semiconductor layer into the interior of the semiconductor layer by a first depth and extending along a first direction; a first active region disposed inside the semiconductor layer and extending diagonally with respect to the first direction and overlapping with the first word line structure; a first bit line pad region overlapping with one end of the first active region and in contact with one side of the first word line structure, recessing from the surface of the semiconductor layer into the interior of the semiconductor layer by a second depth shallower than the first depth; and a first storage node pad region overlapping with the other end of the first active region and in contact with the other side of the first word line structure, and moving away from the first bit line pad region in the diagonal direction.

[0006] The first storage node pad region of the semiconductor device according to one embodiment of the present invention may be recessed by a third depth from the surface of the semiconductor layer.

[0007] The second depth of the semiconductor device according to one embodiment of the present invention may be the same as the third depth.

[0008] A semiconductor device according to one embodiment of the present invention may further include a first bit line contact region disposed on the surface of the semiconductor layer and in contact with the first bit line pad region, and a first storage node contact region disposed on the surface of the semiconductor layer and in contact with the first storage node pad region.

[0009] The semiconductor device according to one embodiment of the present invention may further include a first bit line electrode layer disposed on the first bit line contact region, overlapping the first bit line pad region and extending in a second direction, and a first bit line spacer in contact with both sides of the first bit line electrode layer and extending in the second direction.

[0010] The second direction of the semiconductor device according to one embodiment of the present invention may be perpendicular to the first direction.

[0011] In the semiconductor device according to one embodiment of the present invention, the angle between the diagonal direction and the first direction may be acute, and the angle between the diagonal direction and the second direction may also be acute.

[0012] The semiconductor device according to one embodiment of the present invention may further include: a second active region disposed inside the semiconductor layer, extending in the diagonal direction, spaced apart from the first active region in the first direction, and overlapping with the first word line structure; a second bit line pad region overlapping with one end of the second active region, in contact with one side of the first word line structure, and recessing from the surface of the semiconductor layer into the semiconductor layer by a second depth; and a second storage node pad region overlapping with the other end of the second active region, in contact with the other side of the first word line structure, and spaced apart from the second bit line pad region in the diagonal direction.

[0013] The semiconductor device according to one embodiment of the present invention may further include a second bit line contact region disposed on the surface of the semiconductor layer and in contact with the second bit line pad region, and a second storage node contact region disposed on the surface of the semiconductor layer and in contact with the second storage node pad region.

[0014] The semiconductor device according to one embodiment of the present invention may further include a second bit line electrode layer disposed on the second bit line contact region, overlapping the second bit line pad region and extending in a second direction, and a second bit line spacer in contact with both sides of the second bit line electrode layer and extending in the second direction.

[0015] A semiconductor device according to one embodiment of the present invention may further include: a second word line structure recessed from the surface of the semiconductor layer into the interior of the semiconductor layer, extending along the first direction and moving away from the first word line structure in the second direction; a third active region disposed inside the semiconductor layer, extending in the diagonal direction, moving away from the first active region in the diagonal direction and overlapping with the second word line structure; a third bit line pad region overlapping with one end of the third active region, in contact with one side of the second word line structure, and recessed from the surface of the semiconductor layer into the interior of the semiconductor layer by the second depth; and a third storage node pad region overlapping with the other end of the third active region, in contact with the other side of the second word line structure, and moving away from the second bit line pad region in the diagonal direction.

[0016] The semiconductor device according to one embodiment of the present invention may further include a third bit line contact region disposed on the surface of the semiconductor layer and in contact with the third bit line pad region, and a third storage node contact region disposed on the surface of the semiconductor layer and in contact with the third storage node pad region.

[0017] The second bit line electrode layer of the semiconductor device according to one embodiment of the present invention is arranged on the third bit line contact region and can overlap with the second bit line pad region.

[0018] The angle between the diagonal direction and the first direction of the semiconductor device according to one embodiment of the present invention may be 30 degrees or more and 60 degrees or less.

[0019] The first bit line pad region and the first storage node pad region of the semiconductor device according to one embodiment of the present invention may each include polysilicon.

[0020] A method for manufacturing a semiconductor device according to one embodiment of the present invention may include the steps of: forming a plurality of active regions, each repeatedly spaced apart within a semiconductor layer along a first direction and a second direction, and each extending diagonally with respect to the first direction; forming a plurality of pad trenches, each overlapping with the plurality of active regions spaced apart from each other along the first direction and extending along the second direction; forming a plurality of pad regions, each in contact with the sides of the plurality of pad trenches and extending along the second direction; forming a plurality of pad insulating regions, each extending along the second direction in the center of the plurality of pad trenches and electrically separating the plurality of pad regions; and forming a plurality of wordline structures, each overlapping with the centers of the plurality of active regions arranged along the first direction, extending along the first direction, and repeatedly spaced apart along the second direction.

[0021] The step of forming the plurality of word line structures in a method for manufacturing the semiconductor device according to one embodiment of the present invention includes the operation of forming the plurality of word line structures recessed by a first depth from the surface of the semiconductor layer, and the step of forming the plurality of pad trenches may include the operation of forming the plurality of pad trenches recessed by a second depth shallower than the first depth from the surface of the semiconductor layer.

[0022] The step of forming the plurality of wordline structures in the method for manufacturing the semiconductor device according to one embodiment of the present invention may include the operation of removing a portion of each of the plurality of pad regions.

[0023] According to one embodiment of the present invention, the method for manufacturing the semiconductor device may further comprise: forming a plurality of bit line contact regions each disposed on a pad region overlapping one end of each of the plurality of active regions and respectively contacting one end of the plurality of word line structures; and forming a plurality of storage node contact regions each disposed on a pad region overlapping the other end of each of the plurality of active regions and respectively contacting the other end of the plurality of word line structures.

[0024] According to one embodiment of the present invention, the semiconductor device may further comprise a step of forming a plurality of bit line electrode layers overlapping the plurality of bit line contact regions, extending along the second direction, and being repeatedly spaced apart along the first direction. [Effects of the Invention]

[0025] The semiconductor device according to an embodiment of the present invention can ensure resistance by reducing the process burden of the bit line contact and storage node contact regions and securing the contact area. Furthermore, in the semiconductor device according to an embodiment of the present invention, contact resistance can be reduced by disposing a pad region between the bit line contact and the active region, and disposing a pad region between the storage node contact and the active region. According to the method for manufacturing a semiconductor device of an embodiment of the present invention, the manufacturing cost can be reduced and the process steps can be simplified. [Brief Description of the Drawings]

[0026] [Figure 1] It is a circuit diagram exemplarily modeling a unit cell of a semiconductor device according to an embodiment of the present invention. [Figure 2] It is a first plan view exemplarily showing a part of a semiconductor device according to an embodiment of the present invention. [Figure 3] It is a second plan view exemplarily showing a part of a semiconductor device according to an embodiment of the present invention. [Figure 4]These are illustrative cross-sectional views of a plane cut along the line A-A' in Figures 2 and 3. [Figure 5] These are illustrative cross-sectional views of a plane cut along the line B-B' in Figures 2 and 3. [Figure 6] These are illustrative cross-sectional views of a plane cut along the line C-C' in Figures 2 and 3. [Figure 7] These are illustrative cross-sectional views of a plane cut along the line D-D' in Figures 2 and 3. [Figure 8] These are illustrative cross-sectional views of a plane cut along the line E-E' in Figures 2 and 3. [Figure 9] This is a flowchart illustrating an exemplary method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10a] This is a plan view illustrating the results of performing step S10 in Figure 9. [Figure 10b] This is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 10a. [Figure 10c] This is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 10a. [Figure 10d] This is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 10a. [Figure 10e] This is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 10a. [Figure 10f] This is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 10a. [Figure 11a] This is a plan view illustrating the results of performing step S20 in Figure 9. [Figure 11b] This is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 11a. [Figure 11c] This is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 11a. [Figure 11d] This is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 11a. [Figure 11e]This is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 11a. [Figure 11f] This is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 11a. [Figure 12a] This is a plan view illustrating the results of performing step S30 in Figure 9. [Figure 12b] This is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 12a. [Figure 12c] This is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 12a. [Figure 12d] This is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 12a. [Figure 12e] This is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 12a. [Figure 12f] This is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 12a. [Figure 13a] This is a plan view illustrating the results of performing step S40 in Figure 9. [Figure 13b] This is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 13a. [Figure 13c] This is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 13a. [Figure 13d] This is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 13a. [Figure 13e] This is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 13a. [Figure 13f] This is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 13a. [Figure 14a] This is a plan view illustrating the results of performing step S50 in Figure 9. [Figure 14b] This is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 14a. [Figure 14c] This is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 14a. [Figure 14d] This is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 14a. [Figure 14e] This is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 14a. [Figure 14f] This is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 14a. [Figure 15a] This is a plan view illustrating the results of performing step S60 in Figure 9. [Figure 15b] This is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 15a. [Figure 15c] This is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 15a. [Figure 15d] This is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 15a. [Figure 15e] This is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 15a. [Figure 15f] This is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 15a. [Figure 16a] This is a plan view illustrating the results of performing step S70 in Figure 9. [Figure 16b] This is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 16a. [Figure 16c] This is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 16a. [Figure 16d] This is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 16a. [Figure 16e] This is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 16a. [Figure 16f] This is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 16a. [Figure 17a] This is a plan view illustrating the results of performing step S80 in Figure 9. [Figure 17b] This is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 17a. [Figure 17c] This is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 17a. [Figure 17d] This is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 17a. [Figure 17e] This is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 17a. [Figure 17f] This is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 17a. [Figure 18a] This is a plan view illustrating the results of performing step S90 in Figure 9. [Figure 18b] This is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 18a. [Figure 18c] This is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 18a. [Figure 18d] This is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 18a. [Figure 18e] This is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 18a. [Figure 18f] This is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 18a. [Modes for carrying out the invention]

[0027] Hereinafter, some embodiments of the present invention will be described in detail with reference to illustrative drawings. It should be noted that when assigning reference numerals to components in each drawing, efforts have been made to ensure that the same component has the same reference numeral whenever possible, even if it is shown in different drawings. Furthermore, when describing embodiments of the present invention, if it is determined that a specific description of a related known configuration or function would hinder understanding of the embodiments of the present invention, such detailed description will be omitted.

[0028] In describing the components of embodiments of the present invention, terms such as "first," "second," etc., may be used. These terms are used to distinguish the component from other components, and unless otherwise explicitly stated, they do not limit the nature, order, or sequence of the component. Furthermore, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as those generally understood by a person of ordinary skill in the art to which the present invention pertains. Terms defined in commonly used dictionaries may be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this application.

[0029] Figure 1 is a circuit diagram illustrating the unit cell UC of a semiconductor device according to one embodiment of the present invention.

[0030] Referring to Figure 1, a unit cell UC of a semiconductor device according to one embodiment of the present invention may include a transistor TX and a capacitor CAP. The unit cell UC may also be a unit for storing data within the semiconductor device. A semiconductor device according to one embodiment of the present invention can function as a data storage device that can be included in various electronic devices such as computers. According to one embodiment of the present invention, the semiconductor device may be a volatile memory device (e.g., DRAM (Dynamic Random Access Memory)) or a non-volatile memory device (e.g., NAND memory).

[0031] Transistor TX may be a switching element between bit line BL and capacitor CAP. Transistor TX may, for example, be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Transistor TX can be operated by an electric field generated by a voltage applied to its gate. When transistor TX is turned on, it can electrically connect bit line BL and capacitor CAP. When transistor TX is turned off, it can prevent the electrical connection between bit line BL and capacitor CAP.

[0032] The word line WL can control the on / off state of transistor TX. For example, if the word line signal applied to word line WL is high level, transistor TX can be turned on. Conversely, if the word line signal applied to word line WL is low level, transistor TX can be turned off.

[0033] The bit line BL may be a wiring structure that transfers data. The bit line BL can transfer charge to the capacitor CAP when the transistor TX is in the ON state. If the bit line signal applied to the bit line BL is at a high level and the transistor TX is in the ON state, the data "1" can be stored in the capacitor CAP. If the bit line signal applied to the bit line BL is at a low level and the transistor TX is in the ON state, the data "0" can be stored in the capacitor CAP.

[0034] The capacitor CAP may be a memory element for storing data. The capacitor CAP may have one of the following capacitor structures: a MIM (Metal-Insulator-Metal) capacitor, a MOM (Metal-Oxide-Metal) capacitor, or a MOS (Metal-Oxide-Semiconductor) capacitor, but the scope of the present invention is not limited thereto. When the capacitor CAP stores a charge above a predetermined level, the unit cell UC may be storing the data "1". When the capacitor CAP stores a charge below a predetermined level, the unit cell UC may be storing the data "0".

[0035] In the step of writing data "1" to unit cell UC, a high-level bit line signal can be applied to bit line BL and a high-level word line signal can be applied to word line WL. When transistor TX is turned on by the high-level word line signal, bit line BL becomes the drain terminal and capacitor CAP becomes the source terminal. The potential level of capacitor CAP rises due to the high-level bit line signal, and data "1" can be recorded to unit cell UC.

[0036] In the step of recording the data "0" in the unit cell UC, a low-level bit line signal can be applied to the bit line BL, and a high-level word line signal can be applied to the word line WL. When the transistor TX is turned on, the bit line BL becomes the source terminal and the capacitor CAP becomes the drain terminal. The potential level of the capacitor CAP decreases due to the low-level bit line signal, and the data "0" can be recorded in the unit cell UC.

[0037] In the step of reading data from a unit cell UC, the bit line signal may have a reference level located between the high level and the low level, and the word line signal may have a high level. When the data "1" is recorded (stored) in the unit cell UC, when the transistor TX is turned on, the potential level of the capacitor CAP is high, so the level of the bit line signal may rise above the reference level. When the data "0" is recorded in the unit cell UC, when the transistor TX is turned on, the potential level of the capacitor CAP is low, so the level of the bit line signal may fall below the reference level. The semiconductor device can determine whether the level of the bit line signal has risen or fallen above the reference level and read the data from the unit cell UC.

[0038] Figure 2 is a first plan view illustrating a part of a semiconductor device 1 according to one embodiment of the present invention.

[0039] Figure 3 is a second plan view illustrating a part of a semiconductor device 1 according to one embodiment of the present invention.

[0040] Referring to Figures 1, 2, and 3, the first and second plan views may be plan views illustrating the positional relationship between a plurality of main active regions 110 and peripheral structures. For example, the first plan view may be a plan view illustrating the positional relationship between a plurality of main active regions 110 and peripheral structures arranged on the surface of a predetermined semiconductor substrate. The second plan view may be a plan view illustrating the positional relationship between a plurality of main active regions 110 and peripheral structures arranged below the surface of a predetermined semiconductor substrate. The semiconductor device 1 may include a plurality of active regions 100, a cell isolation region 200, a plurality of wordline structures 300, a plurality of bitline electrode layers 410, a plurality of bitline spacers 420, a plurality of bitline pad regions 430, a plurality of storage node pad regions 530, and a plurality of storage node contact regions 540.

[0041] Each of the multiple active regions 100 may contain a semiconductor material (e.g., silicon (Si), silicon carbide (SIC), etc.). Each of the multiple active regions 100 may be surrounded by a cell isolation region 200. The multiple active regions 100 may be arranged in a matrix structure, for example. The multiple active regions 100 may be arranged in an m × n matrix structure (where m is an integer greater than or equal to 2, and n is an integer greater than or equal to 2). Each of the multiple active regions 100 may extend in a diagonal direction DG. The diagonal direction DG may be diagonal to a first direction X. Parts of the multiple active regions 100 may be repeatedly arranged, separated from each other along the first direction X. Parts of the multiple active regions 100 may be repeatedly arranged, separated from each other along a second direction Y. Parts of the multiple active regions 100 may be repeatedly arranged, separated from each other along a diagonal direction DG. The angle between the diagonal direction DG and the first direction X may be acute. The angle between the diagonal direction DG and the second direction Y may be acute. The acute angle between the first direction X and the diagonal direction DG may be between 30 and 60 degrees. Each of the multiple active regions 100 may overlap with the wordline structure 300. Each of the multiple active regions 100 may include a main active region 110 and a sub-active region 120.

[0042] The main active region 110 may be a semiconductor region extending along the diagonal direction DG. The sub-active region 120 may be a semiconductor region surrounding both ends of the main active region 110. Although the main active region 110 is illustrated in a parallelogram-like shape, the scope of the present invention is not limited to such a shape. For example, each of the four corner regions of the main active region 110 may have a rounded shape. Although the sub-active region 120 is illustrated in a rectangular shape, the scope of the present invention is not limited to such a shape. For example, the sub-active region 120 may have a shape formed by epitaxial growth from each end of the main active region 110.

[0043] The main active region 110 may include the region where the channel of transistor TX of unit cell UC is formed. A sub-active region 120 surrounding one end of the main active region 110 may, for example, overlap with a bit line electrode layer 410 to which the bit line signal of bit line BL is applied. A sub-active region 120 surrounding the other end of the main active region 110 may, for example, overlap with a storage node contact region 540 and a storage node pad region 530 connected to a capacitor CAP.

[0044] The cell isolation region 200 may include an insulating material. For example, the cell isolation region 200 may include at least one of silicon oxide or SOI (Silicon-On-Insulator). The cell isolation region 200 can surround each of the multiple active regions 100. The cell isolation region 200 can provide electrical insulation between the multiple active regions 100 that are separated from each other.

[0045] Each of the multiple wordline structures 300 can extend along a first direction X. Each of the multiple wordline structures 300 can be spaced apart from each other along a second direction Y. Each of the multiple wordline structures 300 can include a predetermined electrode layer to which a wordline signal is applied. When the wordline signal is at a high level in the electrode layer within the wordline structure 300, a predetermined channel can be formed inside the active region 100 that overlaps with the wordline structure 300. Each of the multiple wordline structures 300 can overlap each of the multiple active regions 100 that are spaced apart from each other along the first direction X. Each of the multiple wordline structures 300 can pass through the center of each of the multiple active regions 100 that are spaced apart from each other along the first direction X, but this may vary depending on process limits and variables. If misalignment occurs in the masking pattern for forming the wordline structures 300, there is room for each wordline structure 300 to be formed off-center from the center of each active region 100. The closer the center of each word line structure 300 is to the center of the active region 100 and the further it extends in the first direction X, the more the reliability of the semiconductor device 1 can be improved. The internal structure of the word line structure 300 will be explained with reference to Figure 4 and subsequent figures.

[0046] Each of the multiple bitline electrode layers 410 may include a conductive material. For example, each of the multiple bitline electrode layers 410 may include a metallic material such as aluminum, copper, or tungsten. Each of the multiple bitline electrode layers 410 may extend along a second direction Y. Each of the multiple bitline electrode layers 410 may be spaced apart from each other along a first direction X. The first direction X and the second direction Y may be perpendicular to each other. Each of the multiple bitline electrode layers 410 may be an electrode layer to which a bitline signal is applied. Each of the multiple bitline electrode layers 410 may overlap with a plurality of bitline pad regions 430 spaced apart from each other along the second direction Y. Each of the multiple bitline electrode layers 410 may intersect with a plurality of wordline structures 300. Both sides of each of the multiple bitline electrode layers 410 may be in contact with the bitline spacer 420. Each of the multiple bitline electrode layers 410 may overlap with one end of each active region 100.

[0047] Each of the multiple bit line spacers 420 may include an insulating material. For example, each of the multiple bit line spacers 420 may include an insulating material such as silicon oxide or silicon nitride. Each of the multiple bit line spacers 420 may extend along a second direction Y. Each of the multiple bit line spacers 420 may be spaced apart from each other along a first direction X. Multiple bit line spacers 420 can prevent electrical interaction between the spaced bit line electrode layers 410. Multiple bit line spacers 420 may form a pair, and a pair of bit line spacers 420 may be in contact with both sides of the bit line electrode layer 410 and surround both sides of the bit line electrode layer 410.

[0048] Each of the multiple bit line pad regions 430 may contain a conductive material. For example, each of the multiple bit line pad regions 430 may contain poly-silicon. As an example, the poly-silicon may contain certain impurities to improve conductivity. Each of the multiple bit line pad regions 430 may be configured to efficiently transmit the bit line signal applied to the bit line electrode layer 410 to the active region 100. Each of the multiple bit line pad regions 430 may be positioned between two adjacent word line structures 300. As an example, each of the multiple bit line pad regions 430 may be in contact with two opposing sides of two adjacent word line structures 300. The bit line pad region 430 may overlap with one end of the active region 100. The bit line pad region 430 may overlap with one end of the main active region 110 and the sub-active region 120 surrounding that end. In any active region 100, the bit line pad region 430 can be in contact with one side of a word line structure 300 that overlaps with the active region 100. The bit line pad region 430 can also be in contact with a word line structure 300 that overlaps with the active region 100 and is separated from it in the opposite direction of the second direction Y. Some of the multiple bit line pad regions 430 can be arranged separated from each other along the first direction X. Other parts of the multiple bit line pad regions 430 can be arranged separated from each other along the second direction Y.

[0049] Each of the multiple storage node pad areas 530 may include a conductive material. For example, each of the multiple storage node pad areas 430 may include polysilicon. The polysilicon may also include certain impurities to improve conductivity. The storage node pad areas 530 may include the same material as the bit line pad areas 430. Each of the multiple storage node pad areas 530 can be positioned between two adjacent word line structures 300. As an example, each of the multiple storage node pad areas 530 may be in contact with two sides of two adjacent word line structures 300 that face each other. The storage node pad area 530 may overlap with the other end of the active area 100 that is opposite to the one end. The storage node pad area 530 may overlap with the other end of the main active area 110 and the sub-active area 120 surrounding the other end. In any active area 100, the storage node pad area 530 may be in contact with one side of the word line structure 300 that overlaps with the active area 100. The storage node pad area 530 can also be in contact with the active area 100 and the word line structure 300 that overlaps with the active area 100 separated in the second direction Y. Some of the multiple storage node pad areas 530 can be arranged separated from each other in the first direction X. Other parts of the multiple storage node pad areas 530 can be arranged separated from each other in the second direction Y.

[0050] Each of the multiple storage node contact areas 540 may include a conductive material. For example, each of the multiple storage node contact areas 540 may include at least one of polysilicon, aluminum, copper, and titanium. In the case of polysilicon, it may include a predetermined impurity to improve conductivity. Each of the storage node contact areas 540 may be positioned between two adjacent bit lines. The storage node contact 540 may overlap with the other end of the active area 100. A portion of the storage node contact 540 may overlap with a word line structure 300 that overlaps with the active area 100. Each of the multiple storage node contact areas 540 may be positioned spaced apart from each other in a first direction X. Each of the multiple storage node contact areas 540 may be positioned spaced apart from each other in a second direction Y.

[0051] Figure 4 is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figures 2 and 3.

[0052] Referring to Figures 2, 3, and 4, the first cross-section CS1 may include a substrate region 10, a main active region 110, a sub-active region 120, a cell isolation region 200, a word line structure 300, a bit line structure 400, a storage node pad region 530, and a storage node contact region 540.

[0053] The substrate region 10 may be a semiconductor region located beneath the main active region 110 and the sub-active region 120. The substrate region 10 may contain a semiconductor material. For example, the substrate region 10 may contain at least one of silicon, silicon germanium, or a combination thereof.

[0054] The main active region 110 can be located inside the semiconductor layer SL. The main active region 110 can be located at a predetermined distance from the surface (top surface in the drawing) of the semiconductor layer SL. This predetermined distance may be substantially the same as, for example, the height of the bit line pad region 430 or the storage node pad region 530, but may vary depending on process limitations or variables. The main active region 110 can be in contact with the side and bottom surfaces of the word line structure 300. As an example, the main active region 110 can wrap around the side and bottom surfaces of the word line insulating layer 340.

[0055] The sub-active region 120 may be a region extending from the side of the main active region 110 by a predetermined thickness. One side of the sub-active region 120 can be in contact with the cell separation region 200.

[0056] The cell isolation region 200 can be in contact with the side surface of the sub-active region 120. The cell isolation region 200 can be in contact with the bit line pad region 430 or the storage node pad region 530.

[0057] The wordline structure 300 may include a first wordline electrode layer 310, a second wordline electrode layer 320, a wordline capping layer 330, and a wordline insulating layer 340. The wordline structure 300 may extend (or recess) into the semiconductor layer SL by a predetermined depth (hereinafter referred to as the first depth) along the third direction Z from the surface of the semiconductor layer SL. The wordline structure 300 may extend into the semiconductor layer SL by a predetermined depth from the central region of the main active region 110 (or active region 100). In this description, the surface of the semiconductor layer SL can be defined as being at the same position as the top surface of the wordline structure 300.

[0058] The first wordline electrode layer 310 may include a conductive material. For example, the first wordline electrode layer 310 may include tungsten, aluminum, copper, tungsten nitride, tungsten silicide, cobalt silicide, titanium silicide, tantalum nitride, or a combination thereof. The first wordline electrode layer 310 may be placed beneath the second wordline electrode layer 320. The sides and bottom of the first wordline electrode layer 310 may be surrounded by the wordline insulating layer 340.

[0059] The second wordline electrode layer 320 may include a conductive material. For example, the second wordline electrode layer 320 may include tungsten, aluminum, copper, tungsten nitride, tungsten silicide, cobalt silicide, titanium silicide, tantalum nitride, or a combination thereof. The second wordline electrode layer 320 may also be an area in which a predetermined impurity (e.g., phosphorus, germanium, etc.) is implanted. The second wordline electrode layer 320 may be placed on the first wordline electrode layer 310. The second wordline electrode layer 320 may be placed below the wordline capping layer 330. Both sides of the second wordline electrode layer 320 may be in contact with the wordline insulating layer 340.

[0060] Although not shown in the drawings, a predetermined antioxidant layer can be placed between the first and second wordline electrode layers 310 and 320. The predetermined antioxidant layer can capture impurities (e.g., oxygen) contained within the first and second wordline electrode layers 310 and 320.

[0061] The first and second word line electrode layers 310 and 320 can have a word line signal applied to them. When the word line signal is high level, a channel for charge transfer can be formed around the word line structure 300 within the main active region 110 and the sub-active region 120. When the word line signal is low level, the channel may not be formed. When the channel is formed, the bit line electrode layer 410 and the storage node contact 540 can be electrically connected. For example, in the operation of recording data "1", when a high-level bit line signal is applied to the bit line electrode layer 410 and the first and second word line electrode layers 310 and 320, charge can be transferred to the storage node contact 540 according to the bit line signal of the bit line electrode layer 410, via the bit line contact region 440, the bit line pad region 430, the channel, and the storage node pad region 530. Since the storage node contact 540 can be electrically connected to a predetermined capacitor structure (not shown), the charge can be stored in the capacitor structure via the storage node contact 540. The capacitor structure can be modeled on a circuit diagram as capacitor CAP in Figure 1.

[0062] The word line capping layer 330 may include an insulating material. For example, the word line capping layer 330 may include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. The word line capping layer 330 may be placed on the second word line electrode layer 320. The word line capping layer 330 may be a region filled with insulating material between the surface of the semiconductor layer SL and the upper surface of the second word line electrode layer 320. The word line capping layer 330 can electrically isolate the first and second word line electrode layers 310, 320 from the bit line structure 400. The word line capping layer 330 can electrically isolate the first and second word line electrode layers 310, 320 from the storage node contact 540. Although the drawing shows that the depth of the word line capping layer 330 from the surface of the semiconductor layer SL is shallower than the depth of the bit line pad area 430 or the depth of the storage node pad area 530, according to other embodiments, the depth of the word line capping layer 330 may be formed to be deeper than the depth of both the bit line pad area 430 and the storage node pad area 530.

[0063] The wordline insulating layer 340 may include insulating materials. For example, the wordline insulating layer 340 may include silicon oxide, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. The wordline insulating layer 340 may be formed along the sides and bottom of the wordline structure 300. The wordline insulating layer 340 can physically isolate the first and second wordline electrode layers 310, 320 from the main active region 110. The wordline insulating layer 340 can electrically isolate the first and second wordline electrode layers 310, 320 from the storage node pad region 530.

[0064] The bit line structure 400 may include a bit line electrode layer 410, a bit line spacer 420, a bit line pad region 430, a bit line contact region 440, and a bit line capping layer 450.

[0065] The bit line electrode layer 410 may include a conductive material. For example, the bit line electrode layer 410 may include tungsten, aluminum, copper, tungsten nitride, tungsten silicide, cobalt silicide, titanium silicide, tantalum nitride, or a combination thereof. The bit line electrode layer 410 may be positioned away from the surface of the semiconductor layer SL. The bit line electrode layer 410 may be positioned away from the bit line pad region 430. When viewed from a third direction Z, the bit line electrode layer 410 may overlap with the bit line pad region 430. The bit line electrode layer 410 may overlap with the word line structure 300. Each of the two sides of the bit line electrode layer 410 may be in contact with the bit line spacer 420. The bit line electrode layer 410 may be positioned below the bit line capping layer 450.

[0066] The bit line spacer 420 may include an insulating material. For example, the bit line spacer 420 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The bit line spacer 420 can contact both sides of the bit line electrode layer 410, respectively. The bit line spacer 420 can contact both sides of the bit line contact area 440. The bit line spacer 420 can contact both sides of the bit line capping layer 450. The bit line spacer 420 can electrically isolate the bit line electrode layer 410 from the storage node contact area 540. The bit line spacer 420 can electrically isolate the bit line contact area 440 from the storage node contact area 540.

[0067] The bit line pad region 430 may include a conductive material. For example, the bit line pad region 430 may include polysilicon. The polysilicon may include predetermined impurities. The bit line pad region 430 can be formed by recessing it to a predetermined depth (hereinafter referred to as the second depth) from the surface of the semiconductor layer SL. The lower surface of the bit line pad region 430 can be in contact with the main active region 110 and the sub-active region 120, respectively. One side surface of the bit line pad region 430 can be in contact with the word line structure 300. The second depth, which is the depth of the bit line pad region 430, may be shallower than the first depth, which is the depth of the word line structure 300.

[0068] Without the bit line pad region 430, if the word line structure 300 is formed misaligned from the center of the active region 100 toward the bit line contact region 440 (based on Figure 4, where the word line structure 300 is formed biased to the left), the contact area between the bit line contact region 440 and the active region 100 may decrease, potentially leading to increased contact resistance, decreased current capacity, and performance degradation due to temperature rise. However, when the bit line pad region 430 is formed, the upper surface of the bit line pad region 430 can ensure contact area with the bit line contact region 440, and the lower surface of the bit line pad region 430 can ensure contact area with the main active region 110 and the sub-active region 120, thereby reducing contact resistance, increasing current capacity, lowering temperature rise, and improving the performance of the semiconductor device 1.

[0069] The bit line contact region 440 may include a conductive material. For example, the bit line contact region 440 may include at least one of polysilicon, copper, aluminum, titanium, titanium nitride, or a combination thereof. The bit line contact region 440 may use the same material as the bit line electrode layer 410, or it may use different materials. If different materials are used, for example, it may be more advantageous to select a highly conductive metallic material for the bit line electrode layer 410, while it may be more advantageous to select a material for the bit line contact region 440 that is advantageous in reducing the contact resistance between the bit line electrode layer 410 and the bit line pad region 430. The bit line contact region 440 may be in contact with the underside of the bit line electrode layer 410. Each of the two sides of the bit line contact region 440 may be in contact with the bit line spacer 420. The underside of the bit line contact region 440 may be in contact with the bit line pad region 430. The bit line contact region 440 may be placed on the surface of the semiconductor layer SL.

[0070] The bit line capping layer 450 may include an insulating material. For example, the bit line capping layer 450 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The bit line capping layer 450 may be in contact with the upper surface of the bit line electrode layer 410. The bit line capping layer 450 may be in contact with the bit line spacer 420. Together with the bit line spacer 420, the bit line capping layer 450 can prevent electrical interaction between the bit line electrode layer 410 and the bit line contact region 420, which are positioned around the bit line structure 400.

[0071] The storage node pad region 530 may include a conductive material. For example, the storage node pad region 530 may include polysilicon. The polysilicon may include predetermined impurities. The storage node pad region 530 can be formed by recessing it to a predetermined depth (hereinafter referred to as the third depth) from the surface of the semiconductor layer SL. The lower surface of the storage node pad region 530 may be in contact with the main active region 110 and the sub-active region 120, respectively. One side of the storage node pad region 530 may be in contact with the word line structure 300. The third depth of the storage node pad region 530 may be shallower than the first depth of the word line structure 300. The third depth of the storage node pad region 530 may be substantially the same as the second depth of the bit line pad region 430.

[0072] Without the storage node pad area 530, if the word line structure 300 is misaligned from the center of the active area 100 toward the storage node contact area 540 (based on Figure 4, where the word line structure 300 is formed biased to the right), the contact area between the storage node contact area 540 and the active area 100 may decrease, potentially leading to increased connection resistance, decreased current capacity, and performance degradation due to temperature rise. However, when the storage node pad area 530 is formed, the upper surface of the storage node pad area 530 can ensure contact area with the storage node contact area 540, and the lower surface of the storage node pad area 530 can ensure contact area with the main active area 110 and the sub-active area 120, thereby reducing contact resistance, increasing current capacity, lowering temperature rise, and improving the performance of the semiconductor device 1.

[0073] The storage node contact area 540 may include a conductive material. For example, the storage node contact area 540 may include at least one of polysilicon, copper, aluminum, titanium, titanium nitride, or a combination thereof. The lower surface of the storage node contact area 540 may be in contact with the storage node pad area 530. One side of the storage node contact area 540 may be in contact with the bit line spacer 420. The storage node contact area 540 may be placed on the surface of the semiconductor layer SL.

[0074] In the following explanations of Figures 5 to 18f, explanations that overlap with those explained in Figures 1 to 4 will be omitted as much as possible.

[0075] Figure 5 is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figures 2 and 3.

[0076] Referring to Figures 2, 3, 4, and 5, the second cross section CS2 may include a substrate region 10, a main active region 110, a cell isolation region 200, a first word line electrode layer 310, a second word line electrode layer 320, a word line capping layer 330, a word line insulating layer 340, a bit line electrode layer 410, a bit line spacer 420, a bit line contact region 440, a bit line capping layer 450, and a contact insulating region 600.

[0077] The first wordline electrode layer 310 can extend along the first direction X. The first wordline electrode layer 310 can be placed on the wordline insulating layer 340. The second wordline electrode layer 320 can extend along the first direction X. The second wordline electrode layer 320 can be placed on the first wordline electrode layer 310. The wordline capping layer 330 can extend along the first direction X. The wordline capping layer 330 can be placed on the second wordline electrode layer 320. The wordline insulating layer 340 can extend along the first direction X. The lower surface of the wordline insulating layer 340 can be in contact with the cell isolation region 200 and the main active region 110.

[0078] Multiple bit line electrode layers 410 can be arranged spaced apart from each other along a first direction X. Both sides of each of the multiple bit line electrode layers 410 can be in contact with a bit line spacer 420. A contact insulating region 600 can be placed between bit line spacers 420 arranged on one side of different bit line electrode layers 410.

[0079] The contact insulating region 600 may include an insulating material. For example, the contact insulating region 600 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. A more detailed description of the contact insulating region 600 will be provided later with reference to Figure 8.

[0080] Figure 6 is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figures 2 and 3.

[0081] Referring to Figures 2, 3, 4, and 6, the third cross-section CS3 may include a substrate region 10, a sub-active region 120, a cell separation structure 200, a bit line electrode layer 410, a bit line spacer 420, a bit line pad region 430, a bit line contact region 440, a bit line capping layer 450, a storage node pad region 530, a storage node contact region 540, and a pad insulation region 700.

[0082] The bit line pad region 430 can be in contact with the upper surface of the sub-active region 120. One side of the bit line pad region 430 (right side, as per Figure 6) can be in contact with the cell isolation region 200. The other side of the bit line pad region 430 (left side, as per Figure 6) can be in contact with the pad insulation region 700.

[0083] The storage node pad area 530 can be in contact with the upper surface of the sub-active area 120. One side of the storage node pad area 530 (left side, as per Figure 6) can be in contact with the cell isolation area 200. The other side of the storage node pad area 530 (right side, as per Figure 6) can be in contact with the pad isolation area 700.

[0084] Each of the multiple bit line pad areas 430 and storage node pad areas 530 can be arranged alternately with respect to each other along the first direction X.

[0085] Each of the two sides of the storage node contact area 540 can be in contact with the bit line spacer 420.

[0086] Each of the multiple bit line contact areas 430 can contact the upper surface of the bit line pad area 430. On the other hand, each of the multiple storage node contact areas 540 can contact the upper surface of the storage node pad area 530.

[0087] The pad insulation region 700 may include an insulating material. For example, the pad insulation region 700 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The pad insulation region 700 may be located between adjacent bit line contact regions 430 and storage node contact regions 530. The pad insulation region 700 and the cell isolation region 200 may be arranged alternately in the space between adjacent bit line contact regions 430 and storage node contact regions 530, but the scope of the present invention is not limited thereto and may vary depending on the process method.

[0088] Figure 7 is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figures 2 and 3.

[0089] Referring to Figures 2, 3, 4, and 7, the fourth cross section CS4 may include a substrate region 10, a main active region 110, a sub-active region 120, a cell separation structure 200, a bit line pad region 430, a first word line electrode layer 310, a second word line electrode layer 320, a word line capping layer 330, a word line insulating layer 340, a bit line electrode layer 410, a bit line contact region 440, and a bit line capping layer 450.

[0090] The bitline electrode layer 410 can extend along the second direction Y. The bitline contact region 440 can extend along the second direction Y. The bitline capping layer 450 can extend along the second direction Y.

[0091] A portion of the lower surface of the wordline structure 300 can be in contact with the main active region 110 or the sub-active region 120. Another portion of the lower surface of the wordline structure 300 can be in contact with the cell isolation region 200. One side of the wordline structure 300 can be in contact with the main active region 110. The other side of the wordline structure 300 can be in contact with the cell isolation region 200.

[0092] Each of the multiple bitline pad areas 430 can be placed between adjacent wordline structures 300.

[0093] Figure 8 is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figures 2 and 3.

[0094] Referring to Figures 2, 3, 4, and 8, the fifth section CS5 may include a substrate region 10, a main active region 110, a sub-active region 120, a cell isolation structure 200, a wordline structure 300, a storage node pad region 530, a storage node contact region 540, and a contact isolation region 600.

[0095] Both sides of each of the multiple storage node contact areas 540 can be in contact with the contact isolation area 600. Both sides of each of the multiple contact isolation areas 600 can be in contact with the storage node contact area 540. The multiple storage node contact areas 540 and the multiple contact isolation areas 600 can be arranged alternately and repeatedly along the second direction Y.

[0096] The main active area 110 can be in contact with a portion of the lower surface and one side (left side in the drawing) of the wordline structure 300. The storage node pad area 530 can be in contact with the aforementioned side (left side in the drawing) of the wordline structure 300.

[0097] The cell separation region 200 can be in contact with a part of the lower surface and the other side (right side in the drawing) of the wordline structure 300.

[0098] Figure 9 is a flowchart illustrating an exemplary method for manufacturing a semiconductor device 1 according to one embodiment of the present invention.

[0099] Referring to Figures 2, 3, and 9, the manufacturing method of the semiconductor device 1 (hereinafter referred to as "this manufacturing method") may include a step (S10) of forming a plurality of active regions 100 and cell isolation regions 200 surrounding the plurality of active regions 100. This manufacturing method may include a step (S20) of forming a pad trench by etching a portion of each of the plurality of active regions 100. This manufacturing method may include a step (S30) of depositing a pad layer along the surface of the pad trench and performing crystallization. This manufacturing method may include a step (S40) of removing the pad layer located in the central part of the pad trench and physically separating the pad layer in contact with one side of the pad trench from the pad layer in contact with the other side of the pad trench. This manufacturing method may include a step (S50) of growing pad trenches in contact with both sides of the pad trench. Steps S40 and S50 can be defined as "steps of forming a plurality of pad regions". This manufacturing method may further include a step (S60) of forming a pad insulation region between adjacent pad layers. The manufacturing method may further include the step (S70) of forming a plurality of wordline structures. The manufacturing method may further include the step (S80) of forming a plurality of bitline electrode layers 410, a plurality of bitline spacers 420, a plurality of bitline contact regions (440 in Figure 10a and below), and a plurality of bitline capping layers (450 in Figure 10a and below). The manufacturing method may further include the step (S90) of forming a plurality of storage node contact regions 540.

[0100] A more detailed explanation of each of the steps S10 to S90 in Figure 9 will be provided below with reference to Figures 10a to 18f.

[0101] Figure 10a is a plan view illustrating the results of performing step S10 in Figure 9.

[0102] Referring to Figures 9 and 10a, multiple main active regions 110 can be formed. Some of the multiple main active regions 110 can be formed repeatedly, spaced apart from each other along a first direction X. Other parts of the multiple main active regions 110 can be formed repeatedly, spaced apart from each other along a second direction Y. Each of the multiple main active regions 110 can be formed in a form extending along an oblique direction DG that forms an acute angle with the first direction X and the second direction Y, respectively.

[0103] Next, multiple sub-active regions 120 can be formed from both ends of each of the multiple main active regions 110. Each of the multiple sub-active regions 120 can be formed, for example, by epitaxial growth. This epitaxial growth can be carried out by either chemical vapor deposition or molecular beam epitaxy, as an example.

[0104] Next, cell isolation regions 200 can be formed by gap-filling the remaining empty spaces other than the multiple main active regions 110 and multiple sub-active regions 120 with an insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.).

[0105] Figure 10b is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 10a.

[0106] Referring to Figures 9, 10a, and 10b, an etching trench ET can be formed to create the main active region 110. The semiconductor material of the main active region 110 can grow from the inner wall of the etching trench ET, and a sub-active region 120 can be formed.

[0107] In this description, each of the multiple main active regions 110 can be defined as a region having the same depth as the etching trench ET. In this description, the substrate region 10 is in contact with the lower surface of the multiple main active regions 110 and can be defined as the remaining region other than the main active regions 110 after the etching trench ET has been formed on the predetermined semiconductor substrate.

[0108] Figure 10c is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 10a.

[0109] Referring to Figures 9, 10a, and 10c, epitaxial growth may not occur relatively near the center of the multiple main active regions 110, and sub-active regions 120 may not be formed, although this may vary depending on process variables and limitations. The multiple main active regions 110 can be formed repeatedly along the first direction X.

[0110] Figure 10d is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 10a.

[0111] Referring to Figures 9, 10a, and 10d, the cell isolation region 200 can be formed in contact with the sides of multiple sub-active regions 120. The multiple sub-active regions 120 can be formed repeatedly along the first direction X.

[0112] Figure 10e is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 10a.

[0113] Figure 10f is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 10a.

[0114] Referring to Figures 9, 10a, 10e, and 10f, multiple main active regions 110 can be formed repeatedly along the second direction Y. Each of the multiple sub-active regions 120 can be formed by epitaxial growth from the side of the main active region 110.

[0115] The following explanation of Figures 11a to 11f will focus on the differences between them and Figures 10a to 10f.

[0116] Figure 11a is a plan view illustrating the results of performing step S20 in Figure 9.

[0117] Referring to Figures 9, 10a, and 11a, a pad trench PT can be formed over a portion of each of two adjacent active regions 100. Each of the multiple pad trenches PT can be repeatedly formed spaced apart from one another along the first direction X. Each of the multiple pad trenches PT can be formed to extend along the second direction Y.

[0118] Figure 11b is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 11a.

[0119] Referring to Figures 9, 10a, 11a, and 11b, an etching prevention layer 800 can be formed in locations where multiple pad trenches PT are not formed. Next, pad trenches PT can be formed in locations where the semiconductor layer SL is etched to a predetermined depth. The pad trenches PT may be trenches formed by etching a portion of one end of the active region 100.

[0120] Figure 11c is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 11a.

[0121] Figure 11d is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 11a.

[0122] Referring to Figures 9, 10a, 11a, 11c, and 11d, the pad trench PT may be a trench formed by etching a portion of one side surface (right side in Figure 11c) of one active region 100. The pad trench PT may also be a trench formed by etching a portion of one side surface (left side in Figure 11c) of another active region 100 separated from the first active region 100 in the first direction X. The etching prevention layer 800 can be formed to extend along the second direction Y.

[0123] Figure 11e is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 11a.

[0124] Referring to Figures 9, 10a, 11a, and 11e, the pad trench PT can be formed to extend along the second direction Y. The depth of the pad trench PT etched from the surface of the semiconductor layer SL may be substantially the same as the depth of the bit line pad region 430 in Figure 3.

[0125] Figure 11f is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 11a.

[0126] Referring to Figures 9, 10a, 11a, and 11f, the pad trench PT can be formed to extend along the second direction Y. The depth of the pad trench PT etched from the surface of the semiconductor layer SL may be substantially the same as the depth of the storage node pad region 530 in Figure 3.

[0127] The depth to which each pad trench PT recesses in the third direction Z may be shallower than the depth of the wordline structure 300 in Figure 4.

[0128] Below, we will explain Figures 12a to 12f, focusing on the differences between them and Figures 11a to 11f.

[0129] Figure 12a is a plan view illustrating the results of performing step S30 in Figure 9.

[0130] Referring to Figures 9, 11a, and 12a, a pad layer PAD can be deposited and crystallized inside the pad trench PT.

[0131] Figure 12b is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 12a.

[0132] Referring to Figures 9, 11a, 12a, and 12b, the pad layer PAD can be formed in contact with the bottom and side surfaces of each of the multiple pad trenches PT. The pad layer PAD can also be formed to cover the side and top surfaces of the etching prevention layer 800. The pad layer PAD can be formed of polysilicon, as an example.

[0133] Figure 12c is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 12a.

[0134] Figure 12d is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 12a.

[0135] Referring to Figures 9, 11a, 12a, 12c, and 12d, the pad layer PAD can extend along the first direction X. Since the pad trench PT is formed over a portion of each of two active regions 100 adjacent to each other in the first direction X, the width of the pad trench PT in the first direction X can be formed relatively wide, and considering the minimum pitch for which etching is possible, the process burden of the pad trench PT can be reduced.

[0136] Figure 12e is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 12a.

[0137] Figure 12f is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 12a.

[0138] Referring to Figures 9, 11a, 12a, 12e, and 12f, the pad layer PAD can extend along the second direction Y.

[0139] Below, we will explain Figures 13a to 13f, focusing on the differences between them and Figures 12a to 12f.

[0140] Figure 13a is a plan view illustrating the results of performing step S40 in Figure 9.

[0141] Referring to Figures 9, 12a, and 13a, the pad layer PAD in the center of each of the multiple pad trenches PT is removed, and the portion in contact with one side of each pad trench PT and the portion in contact with the other side can be physically separated from each other. The remaining pad layer PAD that remains after removing the pad layer in the center of each of the multiple pad trenches PT can overlap the edges of each active region 100. The region from which the pad layer PAD is removed can extend along the second direction Y.

[0142] Figure 13b is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 13a.

[0143] Referring to Figures 9, 12a, 13a, and 13b, a pad layer PAD may remain on one side of the active region 100. A pad layer PAD may also remain on the other side of the active region 100, separated from the aforementioned side in the diagonal direction DG.

[0144] Figure 13c is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 13a.

[0145] Figure 13d is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 13a.

[0146] Referring to Figures 9, 12a, 13a, 13c, and 13d, the pad layer PAD in contact with one side of the pad trench PT and the pad layer PAD in contact with the other side of the pad trench PT can be arranged to be spaced apart from each other in the first direction X.

[0147] The active region 100 in contact with the pad layer PAD on one side of the pad trench PT and the active region 100 in contact with the pad layer PAD on the other side of the pad trench PT may be different active regions. In order to prevent electrical interaction between the separated active regions 100, the pad layer PAD in contact with one side of the pad trench PT and the pad layer PAD on the other side of the pad trench PT must always be separated.

[0148] Figure 13e is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 13a.

[0149] Figure 13f is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 13a.

[0150] Figure 13e may be substantially identical to the cross-section of Figure 12e. Figure 13f may be substantially identical to the cross-section of Figure 12f.

[0151] Below, we will explain Figures 14a to 14f, focusing on the differences between them and Figures 13a to 13f.

[0152] Figure 14a is a plan view illustrating the results of performing step S50 in Figure 9.

[0153] Referring to Figures 9, 13a, and 14a, each of the pad layers PAD adjacent to both sides of the multiple pad trenches PT can be grown such that its width increases in the first direction X.

[0154] Figure 14b is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 14a.

[0155] Referring to Figures 9, 13a, 14a, and 14b, the width of each pad layer PAD in contact with both sides of the multiple pad trenches PT can be increased. For example, the width of the pad layer PAD can be increased to the extent that it covers one end of the active region 100 (the portion of the active region 100 etched by the pad trenches PT).

[0156] Figure 14c is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 14a.

[0157] Figure 14d is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 14a.

[0158] Referring to Figures 9, 13a, 14a, 14c, and 14d, the pad layer PAD adjacent to the left wall of the pad trench PT can grow in the first direction X. The pad layer PAD adjacent to the right wall of the pad trench PT can grow in the opposite direction to the first direction X.

[0159] Figure 14e is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 14a.

[0160] Figure 14f is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 14a.

[0161] Figure 14e may be substantially identical to the cross-section of Figure 13e. Figure 14f may be substantially identical to the cross-section of Figure 13f.

[0162] Below, we will explain Figures 15a to 15f, focusing on the differences between them and Figures 14a to 14f.

[0163] Figure 15a is a plan view illustrating the results of performing step S60 in Figure 9.

[0164] Referring to Figures 9, 10a, and 15a, a pad insulation region 700 can be formed in the empty space between adjacent pad layers PADs.

[0165] Figure 15b is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 15a.

[0166] Referring to Figures 9, 10a, 15a, and 15b, the etching prevention layer 800 can be removed and a planarization step can be performed. This planarization step can be performed before forming the pad insulating region 700. The planarization step may include the operation of flattening the surface of the semiconductor layer SL.

[0167] Figure 15c is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 15a.

[0168] Referring to Figures 9, 10a, 15a, and 15c, the pad insulation region 700 can be positioned between adjacent pad layers PAD.

[0169] Figure 15d is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 15a.

[0170] Referring to Figures 9, 10a, 15a, and 15d, along the first direction X, the space between the pad layers PADs, which are repeatedly spaced apart, can be filled by alternately arranging pad insulation regions 700 and cell isolation regions 200.

[0171] Figure 15e is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 15a.

[0172] Figure 15f is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 15a.

[0173] Referring to Figures 9, 10a, 15a, 15e, and 15f, as the process of planarizing the surface of the semiconductor layer SL is carried out, the upper surface of the pad layer PAD can be made to coincide with the surface of the semiconductor layer SL.

[0174] Below, we will explain Figures 16a to 16f, focusing on the differences between them and Figures 15a to 15f.

[0175] Figure 16a is a plan view illustrating the results of performing step S70 in Figure 9.

[0176] Referring to Figures 9, 10a, and 16a, the wordline structure 300 can be formed to extend along a first direction X. The wordline structure 300 can be formed through a pad layer PAD. The wordline structure 300 can cut through a portion of the pad layer PAD. The portion of the pad layer PAD that remains after cutting can become a bitline pad layer 430, and the other portion of the pad layer PAD that remains after cutting can become a storage node pad layer 530.

[0177] Figure 16b is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 16a.

[0178] Figure 16c is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 16a.

[0179] Referring to Figures 9, 10a, 16a, 16b, and 16c, a wordline trench WT can be formed that passes through the centers of multiple active regions 100 and extends along a first direction X. Next, a wordline insulating layer 340 can be formed in contact with the lower and side surfaces of the wordline trench WT and extending along the first direction X. Next, a first wordline electrode layer 310 can be formed on the wordline insulating layer 340 and extending along the first direction X. Next, a second wordline electrode layer 320 can be formed on the first wordline electrode layer 310 and extending along the first direction X. Next, a wordline capping layer 330 can be formed on the second wordline electrode layer 320 and extending along the first direction X.

[0180] The first depth, which is the depth to which the word line structure 300 recesses from the surface of the semiconductor layer SL in the third direction Z, may be deeper than the second depth, which is the depth to which the bit line pad region 430 recesses from the surface of the semiconductor layer SL in the third direction Z. The first depth may also be deeper than the third depth, which is the depth to which the storage node pad region 530 recesses from the surface of the semiconductor layer SL in the third direction Z. The second depth and the third depth may be the same depth.

[0181] Figure 16d is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 16a.

[0182] Figure 16d may be substantially the same cross-section as Figure 15d. The pad layer PAD in contact with one side (left side in Figure 16d) of the pad isolation region 700 can become the storage node pad region 530. The pad layer PAD in contact with the other side (right side in Figure 16d) of the pad isolation region 700 can become the bit line pad region 430.

[0183] Figure 16e is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 16a.

[0184] Referring to Figures 9, 10a, 16a, and 16e, multiple wordline structures 300 can be arranged repeatedly, spaced apart from one another along the second direction Y. One side of a wordline structure 300 can be in contact with an active region 100 that is in contact with the lower surface and side surface of the wordline structure 300, and a bitline pad region 430 that is in contact with the active region 100.

[0185] Figure 16f is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 16a.

[0186] Referring to Figures 9, 10a, 16a, and 16f, multiple wordline structures 300 can be arranged repeatedly, spaced apart from one another along the second direction Y. One side of a wordline structure 300 can be in contact with an active area 100 that is in contact with the lower surface and side surface of the wordline structure 300, and a storage node pad area 530 that is in contact with the active area 100.

[0187] Referring to Figures 12a and 16a, if pad trenches PT are formed in the areas where the bit line pad region 430 is formed and the storage node pad region 530 is formed, the width of the trenches that can be formed becomes narrower, and considering the minimum machinable pitch, it may be necessary to perform the etching process several times, which can lead to increased costs and process steps. However, as shown in Figure 12a, if the pad trenches PT are formed over parts of two adjacent active regions 100 and the pad layers PAD are formed simultaneously, there is no risk of hitting the limits of the process technology, the etching process can be carried out only once, and manufacturing costs can be reduced.

[0188] Below, we will explain Figures 17a to 17f, focusing on the differences between them and Figures 16a to 16f.

[0189] Figure 17a is a plan view illustrating the results of performing step S80 in Figure 9.

[0190] Figure 17b is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 17a.

[0191] Referring to Figures 9, 10a, 17a, and 17b, a bit line contact region 440 can be formed in contact with the upper surface of the bit line pad region 430. Next, a bit line electrode layer 410 can be formed on the bit line contact region 440. The bit line electrode layer 410 can be formed to extend in the second direction Y. Next, a bit line capping layer 450 can be formed on the bit line electrode layer 410. Bit line spacers 420 can be formed in contact with both sides of the bit line electrode layer 410, the bit line contact region 440, and the bit line contact capping layer 450.

[0192] Figure 17c is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 17a.

[0193] Referring to Figures 9, 10a, 17a, and 17c, multiple bit line contact regions 440 can be formed spaced apart from each other in the first direction X. Multiple bit line electrode layers 410 can be formed spaced apart from each other in the first direction X. Multiple bit line capping layers 450 can be formed spaced apart from each other in the first direction X. Multiple bit line spacers 420 can be in contact with the bit line electrode layers 410 on their respective sides in the first direction X and the opposite direction of the first direction X.

[0194] Figure 17d is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 17a.

[0195] Referring to Figures 9, 10a, 17a, and 17d, a portion of the bit line spacer 420 can be positioned on the pad isolation area 700. Another portion of the bit line spacer 420 can be positioned on the cell isolation area 200.

[0196] Figure 17e is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 17a.

[0197] Referring to Figures 9, 10a, 17a, and 17e, the bit line contact region 440, the bit line electrode layer 410, the bit line capping layer 450, and the bit line spacer 420 can each be formed to extend along the second direction Y.

[0198] Figure 17f is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 17a.

[0199] Figure 17f may be substantially identical to Figure 16f.

[0200] Below, we will explain Figures 18a to 18f, focusing on the differences between them and Figures 17a to 17f.

[0201] Figure 18a is a plan view illustrating the results of performing step S90 in Figure 9.

[0202] Figure 18b is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 18a.

[0203] Referring to Figures 9, 10a, 18a, and 18b, each of the multiple storage node contact areas 540 can be formed to overlap with a portion of the active area 100. One end of the active area 100 can be formed to overlap with the bit line pad area 430. The other end of the active area 100 can be formed to overlap with the storage node contact area 540. The storage node contact 540 can be in contact with the upper surface of the storage node pad area 530.

[0204] Figure 18c is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 18a.

[0205] Referring to Figure 18c, multiple contact isolation regions 600 can be positioned between bit line spacers 420. For example, a contact isolation region 600 can be in contact with a bit line spacer 420 in a first direction X. A contact isolation region 600 can be in contact with a bit line spacer 420 in the opposite direction to the first direction X.

[0206] Figure 18d is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 18a.

[0207] Referring to Figure 18d, multiple storage node contact areas 540 can be positioned between bit line spacers 420. For example, a storage node contact area 540 can be in contact with a bit line spacer 420 in a first direction X. A storage node contact area 540 can be in contact with a bit line spacer 420 in the opposite direction to the first direction X.

[0208] Figure 18e is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 18a.

[0209] Figure 18e may be substantially identical to Figure 17e.

[0210] Figure 18f is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 18a.

[0211] Referring to Figure 18f, multiple storage node contact areas 540 and multiple contact isolation areas 600 can be formed alternately and repeatedly along the second direction Y. Both sides of each of the multiple storage node contact areas 540 can be in contact with the contact isolation area 600. Both sides of each of the multiple contact isolation areas 600 can be in contact with the storage node contact area 540. As an example, a storage node contact area 540 can be in contact with the contact isolation area 600 in the second direction Y. A storage node contact area 540 can be in contact with the contact isolation area 600 in the opposite direction of the second direction Y. Also, a contact isolation area 600 can be in contact with a storage node contact area 540 in the second direction Y. A contact isolation area 600 can be in contact with a storage node contact area 540 in the opposite direction of the second direction Y.

[0212] The above description is merely illustrative of the technical idea of ​​the present invention, and various modifications and variations are possible for those with ordinary skill in the art to which the present invention pertains, without departing from the essential characteristics of the present invention. The embodiments disclosed herein are for illustrative purposes only, not to limit the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by the embodiments. The scope of protection of the present invention should be interpreted as defined by the claimed claims, and all technical ideas within an equivalent scope should be interpreted as being included within the scope of the rights of the present invention. [Explanation of Symbols]

[0213] 100 active area 110 Main active region 120 Sub-active regions 200-cell isolation area 300 Wordline Structures 310 First Word Line Electrode Layer 320 Second Wordline Electrode Layer 330 Wordline Capping Layer 340 Wordline Insulation Layer 400 bit line structure 410 bit line electrode layer 420 bit line spacer 430-bit line pad area 440-bit line contact area 450-bit line capping layer 530 Storage Node Pad Area 540 Storage Node Contact Area 600 Contact Insulation Area 700 pad insulation area 800 Etching prevention layer SL semiconductor layer WL Wardline BL Bitline TX transistor CAP Capacitor UC unit cell X 1st direction Y Second direction Z 3rd direction DG diagonal direction

Claims

1. A semiconductor layer, a first word line structure that recesses from the surface of the semiconductor layer into the interior of the semiconductor layer by a first depth and extends along a first direction, A first active region is disposed inside the semiconductor layer, extends diagonally with respect to the first direction, and overlaps with the first word line structure, A first bit line pad region overlaps one end of the first active region, is in contact with one side of the first word line structure, and recesses from the surface of the semiconductor layer into the interior of the semiconductor layer by a second depth shallower than the first depth, A semiconductor device comprising a first storage node pad region that overlaps with the other end of the first active region, is in contact with the other side of the first word line structure, and is spaced apart from the first bit line pad region in the diagonal direction.

2. The semiconductor device according to claim 1, wherein the first storage node pad region is recessed by a third depth from the surface of the semiconductor layer.

3. The semiconductor device according to claim 2, wherein the second depth is the same as the third depth.

4. A first bit line contact region is disposed on the surface of the semiconductor layer and is in contact with the first bit line pad region, The semiconductor device according to claim 1, further comprising a first storage node contact region disposed on the surface of the semiconductor layer and in contact with the first storage node pad region.

5. A first bit line electrode layer is disposed on the first bit line contact region, overlaps with the first bit line pad region, and extends in a second direction. The semiconductor device according to claim 4, further comprising a first bit line spacer that is in contact with both sides of the first bit line electrode layer and extends in the second direction.

6. The semiconductor device according to claim 5, wherein the second direction is perpendicular to the first direction.

7. The semiconductor device according to claim 5, wherein the angle between the diagonal direction and the first direction is acute, and the angle between the diagonal direction and the second direction is acute.

8. A second active region is disposed inside the semiconductor layer, extends in the diagonal direction, is separated from the first active region in the first direction, and overlaps with the first word line structure, A second bit line pad region overlaps one end of the second active region, is in contact with one side of the first word line structure, and recesses from the surface of the semiconductor layer into the interior of the semiconductor layer by the second depth, The semiconductor device according to claim 5, further comprising a second storage node pad region that overlaps with the other end of the second active region, is in contact with the other side of the first word line structure, and is spaced apart from the second bit line pad region in the diagonal direction.

9. A second bit line contact region is disposed on the surface of the semiconductor layer and is in contact with the second bit line pad region, The semiconductor device according to claim 8, further comprising a second storage node contact region disposed on the surface of the semiconductor layer and in contact with the second storage node pad region.

10. A second bit line electrode layer is positioned on the second bit line contact region, overlaps with the second bit line pad region, and extends in a second direction. The semiconductor device according to claim 9, further comprising a second bit line spacer that is in contact with both sides of the second bit line electrode layer and extends in the second direction.

11. A second word line structure recesses from the surface of the semiconductor layer into the interior of the semiconductor layer, extends along the first direction, and separates from the first word line structure in the second direction, A third active region is disposed inside the semiconductor layer, extends in the diagonal direction, is separated from the first active region in the diagonal direction, and overlaps with the second word line structure, A third bit line pad region overlaps one end of the third active region, is in contact with one side of the second word line structure, and recesses from the surface of the semiconductor layer into the interior of the semiconductor layer by the second depth, The semiconductor device according to claim 10, further comprising a third storage node pad region that overlaps with the other end of the third active region, is in contact with the other side of the second word line structure, and is spaced apart from the second bit line pad region in the diagonal direction.

12. A third bit line contact region is disposed on the surface of the semiconductor layer and is in contact with the third bit line pad region, The semiconductor device according to claim 11, further comprising a third storage node contact region disposed on the surface of the semiconductor layer and in contact with the third storage node pad region.

13. The semiconductor device according to claim 12, wherein the second bit line electrode layer is disposed on the third bit line contact region and overlaps with the second bit line pad region.

14. The semiconductor device according to claim 1, wherein the angle between the aforementioned diagonal direction and the first direction is 30 degrees or more and 60 degrees or less.

15. The semiconductor device according to claim 1, wherein each of the first bit line pad region and the first storage node pad region includes polysilicon.

16. The steps include: each being arranged repeatedly and spaced apart along a first direction and a second direction within the semiconductor layer, and each forming a plurality of active regions extending diagonally with respect to the first direction; The steps include: each overlapping with the plurality of active regions that are spaced apart from each other along the first direction, and forming a plurality of pad trenches extending along the second direction; The steps include: each of them contacts the side surface of the plurality of pad trenches and forms a plurality of pad regions extending along the second direction; The steps include each of the following: forming a plurality of pad insulating regions that extend along the second direction in the center of the plurality of pad trenches and electrically separate the plurality of pad regions; A method for manufacturing a semiconductor device, comprising the step of forming a plurality of word line structures, each overlapping with the centers of a plurality of active regions arranged along the first direction, extending along the first direction, and repeatedly spaced apart along the second direction.

17. The step of forming the plurality of word line structures includes the operation of forming the plurality of word line structures that are recessed by a first depth from the surface of the semiconductor layer, The method for manufacturing a semiconductor device according to claim 16, wherein the step of forming the plurality of pad trenches includes the operation of forming the plurality of pad trenches that recess from the surface of the semiconductor layer to a second depth shallower than the first depth.

18. The method for manufacturing a semiconductor device according to claim 16, wherein the step of forming the plurality of word line structures includes the operation of removing a portion of each of the plurality of pad regions.

19. The steps include forming a plurality of bit line contact regions, each overlapping one end of the plurality of active regions and positioned on a pad region that is in contact with one end of the plurality of word line structures, The method for manufacturing a semiconductor device according to claim 18, further comprising the step of forming a plurality of storage node contact regions, each of which overlaps the other end of each of the plurality of active regions and is positioned on a pad region that is in contact with the other end of each of the plurality of wordline structures.

20. The method for manufacturing a semiconductor device according to claim 19, further comprising the step of forming a plurality of bit line electrode layers that overlap the plurality of bit line contact regions, extend along the second direction, and are repeatedly spaced apart along the first direction.

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