Semiconductor equipment

Abstract

To improve the yield of semiconductor devices. [Solution] The semiconductor device according to the embodiment includes a substrate having a first region and a second region provided so as to surround the outer periphery of the first region when viewed in a first direction; a semiconductor circuit provided in the first region on the substrate; a plurality of first conductive pillars provided in the second region on the substrate, each extending in a first direction, electrically insulated from each other and insulated from the semiconductor circuit, spaced apart from each other so as to surround the first region; and an insulating layer provided in the first region on the side of the substrate opposite to the semiconductor circuit and the plurality of first conductive pillars in a first direction, and overlapping the semiconductor circuit in a first direction, wherein at least a portion of the plurality of first conductive pillars do not overlap the insulating layer in a first direction.

Description

[[Technical Field]]

[0001] Embodiments relate to a semiconductor device. [[Background Art]]

[0002] As a semiconductor device, a semiconductor memory device including a NAND flash memory capable of non-volatilely storing data is known. In NAND flash memories, a three-dimensional memory structure may be employed for higher integration and larger capacity. [[Prior Art Documents]] [[Patent Documents]]

[0003] [[Patent Document 1]] Japanese Unexamined Patent Application Publication No. 2023-141616 [[Patent Document 2]] Japanese Unexamined Patent Application Publication No. 2023-116095 [[Summary of the Invention]] [[Problem to be Solved by the Invention]]

[0004] An object of the present invention is to improve the yield of semiconductor devices. [[Means for Solving the Problem]]

[0005] A semiconductor device according to an embodiment comprises: a substrate having a first region and a second region provided so as to surround an outer periphery of the first region when viewed in a first direction; a semiconductor circuit provided in the first region on the substrate; a plurality of first conductive pillars provided in the second region on the substrate, each of the first conductive pillars extending in the first direction, being electrically insulated from each other and insulated from the semiconductor circuit, and arranged spaced apart from each other so as to surround the first region; and an insulator layer provided in the first region on an opposite side of the semiconductor circuit and the plurality of first conductive pillars from the substrate in the first direction, the insulator layer overlapping the semiconductor circuit in the first direction, wherein at least a part of the plurality of first conductive pillars does not overlap the insulator layer in the first direction. [[Brief Description of the Drawings]]

[0006] [Figure 1] Figure 1 is a block diagram showing an example of the configuration of a memory system according to an embodiment. [Figure 2] Figure 2 is a cross-sectional view showing an example of the cross-sectional structure of the memory system according to the embodiment. [Figure 3] Figure 3 is a perspective view showing an example of the appearance of a semiconductor memory device according to the embodiment. [Figure 4] Figure 4 is a circuit diagram showing an example of the circuit configuration of a memory cell array in a semiconductor memory device according to the embodiment. [Figure 5] Figure 5 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array in a semiconductor memory device according to the embodiment. [Figure 6] Figure 6 is a cross-sectional view along the line VI-VI in Figure 5, showing an example of the cross-sectional structure of a memory pillar in a semiconductor memory device according to the embodiment. [Figure 7] Figure 7 is a plan view showing an example of a planar layout of a semiconductor memory device according to an embodiment. [Figure 8] Figure 8 is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to this embodiment. [Figure 9] Figure 9 is a plan view showing an example of the connection between a semiconductor memory device and a wiring board according to the embodiment. [Figure 10] Figure 10 is a cross-sectional view showing an example of the connection between a semiconductor memory device and a wiring board according to the embodiment. [Figure 11] Figure 11 is a plan view showing an example of a planar layout when performing characteristic evaluation in a semiconductor memory device according to the embodiment. [Figure 12] Figure 12 is a plan view showing an example of a planar layout of a semiconductor memory device according to a first modified embodiment. [Figure 13] Figure 13 is a plan view showing an example of a planar layout of a semiconductor memory device according to a second modified embodiment. [Figure 14] Figure 14 is a plan view showing an example of a planar layout of a semiconductor memory device according to a third modified embodiment. [Modes for carrying out the invention]

[0007] Embodiments are described below with reference to the drawings. The drawings are schematic, and the dimensions and proportions shown are not necessarily the same as those of actual objects. In the following description, components having substantially the same function and configuration are denoted by the same reference numeral. When elements with similar configurations are to be specifically distinguished, different letters or numbers may be added to the end of the same reference numeral.

[0008] In the following description, "connected" to another second element means that the first element is connected to the second element indirectly, either through an intermediate element that is always or selectively conductive, or directly without an intermediate element.

[0009] In the following section, a semiconductor memory device having a three-dimensional memory structure will be described as an example of a semiconductor device according to the embodiment.

[0010] 1. Structure 1.1 Memory System A semiconductor memory device according to an embodiment will be described. Figure 1 is a block diagram showing an example of the configuration of a memory system according to an embodiment. Memory system 1 is a memory device configured to be connected to an external host device (not shown). Memory system 1 is, for example, an SD TM The memory is a card-like memory card, UFS (Universal Flash Storage), or SSD (Solid State Drive). The memory system 1 includes a memory controller 2 and a semiconductor storage device 3.

[0011] The memory controller 2 is configured with an integrated circuit such as an SoC (System on a Chip), for example. The memory controller 2 controls the semiconductor memory device 3 based on requests from an external host device. Specifically, the memory controller 2 writes, into the semiconductor memory device 3, data that an external host device has requested to be written. The memory controller 2 also reads, from the semiconductor memory device 3, data that an external host device has requested to be read, and outputs the data to the external host device.

[0012] The semiconductor memory device 3 is, for example, a NAND flash memory capable of non-volatile storage of data.

[0013] Communication between the memory controller 2 and the semiconductor memory device 3 conforms to, for example, an SDR (Single Data Rate) interface, a toggle DDR (Double Data Rate) interface, or an ONFI (Open NAND Flash Interface).

[0014] 1.2 Semiconductor Memory Device Next, the internal configuration of the semiconductor memory device 3 according to the embodiment will be described with reference to the block diagram shown in FIG. 1. The semiconductor memory device 3 includes, for example, a memory cell array 10, an input / output circuit 11, a logic control circuit 12, a register 13, a sequencer 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0015] The memory cell array 10 is a collection of memory cell transistors and components connected to the memory cell transistors. The memory cell array 10 includes multiple blocks BLK0 to BLKn (where n is an integer greater than or equal to 1). A block BLK is a collection of multiple memory cell transistors capable of storing data non-volatilely. A block BLK is used, for example, as an erasure unit when erasing data stored by a memory cell transistor. The memory cell array 10 is also provided with multiple bit lines and multiple word lines. Each memory cell transistor is associated, for example, with a combination of one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0016] The input / output circuit 11 is an interface circuit that controls the transmission and reception of input / output signals between it and the memory controller 2. The input / output signals include, for example, data DAT, command CMD, address information ADD, and status information STA. The input / output circuit 11 inputs and outputs data DAT between the sense amplifier module 17 and the memory controller 2, respectively. The input / output circuit 11 outputs command CMD and address information ADD, each transferred from the memory controller 2, to register 13. The input / output circuit 11 outputs status information STA, transferred from register 13, to the memory controller 2.

[0017] The logic control circuit 12 receives control signals input from the memory controller 2. Based on these control signals, the logic control circuit 12 controls the input / output circuit 11 and the sequencer 14, respectively. For example, the logic control circuit 12 notifies the input / output circuit 11 that the input / output signal it has received is a command CMD or address information ADD, etc. The logic control circuit 12 commands the input / output circuit 11 to input or output the input / output signal. The logic control circuit 12 controls the sequencer 14 to enable the semiconductor memory device 3. The logic control circuit 12 also outputs a signal to the memory controller 2 indicating whether the semiconductor memory device 3 is ready or busy.

[0018] Register 13 temporarily stores command CMD, address information ADD, and status information STA. Command CMD includes, for example, instructions to cause the sequencer 14 to perform read, write, erase, etc. Address information ADD includes, for example, block address BA, page address PA, and column address CA. For example, block address BA, page address PA, and column address CA are used for selecting block BLK, word lines, and bit lines, respectively. Status information STA is updated based on the control of the sequencer 14 and transferred to the input / output circuit 11.

[0019] The sequencer 14 controls the overall operation of the semiconductor memory device 3. For example, based on the command CMD stored in register 13, the sequencer 14 controls the driver module 15, the row decoder module 16, the sense amplifier module 17, etc., and performs read operations, write operations, erase operations, etc.

[0020] The driver module 15 generates multiple voltages of different magnitudes used in read, write, and erase operations. The driver module 15 supplies the generated voltages to the row decoder module 16 and the sense amplifier module 17, etc. The driver module 15 also applies the generated voltages to the signal lines corresponding to the word lines selected based on the page address PA stored in register 13, for example.

[0021] The row decoder module 16 selects a corresponding block BLK in the memory cell array 10 based, for example, on the block address BA stored in register 13. The row decoder module 16 then transfers, for example, the voltage of the signal line applied by the driver module 15 to the selected word line in the selected block BLK.

[0022] The sense amplifier module 17 includes a sense amplifier capable of determining data based on the voltage of the associated bit line, and a latch circuit for temporarily storing data. In a write operation, the sense amplifier module 17 applies a desired voltage to each bit line according to the write data DAT received from the input / output circuit 11. In a read operation, the sense amplifier module 17 determines the data stored in the memory cell transistor based on the magnitude of the bit line voltage. Subsequently, the sense amplifier module 17 transfers the determination result as read data DAT to the input / output circuit 11.

[0023] 1.3 Structure of the Memory System Figure 2 is a cross-sectional view showing an example of the cross-sectional structure of a memory system according to an embodiment. As shown in Figure 2, the memory system 1 according to the embodiment further includes a wiring board 4, an adhesive layer 5, wiring 6, and a resin layer 7. Figure 2 shows how the semiconductor memory device 3 is provided on the wiring board 4.

[0024] In the following description, the plane on which the wiring board 4 extends is defined as the XY plane. The direction in which the semiconductor memory device 3 is installed, as viewed from the wiring board 4, is defined as the Z1 direction or upward direction. The direction in which the wiring board 4 is installed, as viewed from the semiconductor memory device 3, is defined as the Z2 direction or downward direction. When the Z1 and Z2 directions are not distinguished, they are simply referred to as the Z direction. The Z direction is approximately perpendicular to the wiring board 4.

[0025] The semiconductor memory device 3 includes pads 30. Although only one pad 30 is shown in Figure 2, multiple pads 30 are actually provided. The semiconductor memory device 3 is connected to the memory controller 2 and an external power supply, etc., via the pads 30.

[0026] The wiring board 4 is, for example, a printed circuit board or interposer containing glass epoxy resin. The semiconductor memory device 3 is provided on the upper surface of the wiring board 4 via an adhesive layer 5. The adhesive layer 5 is a paste-like or film-like resin, and includes, for example, NCP (Non Conductive Paste) or DAF (Die Attach Film).

[0027] The wiring board 4 includes pads 40 and electrodes 41. The pads 40 are provided on the upper surface of the wiring board 4. The pads 40 are connected to circuits provided inside the wiring board 4 and function as terminals of the wiring board 4. The pads 40 are connected to semiconductor memory devices 3 and memory controllers 2 (not shown) provided on the wiring board 4. The electrodes 41 are, for example, bump electrodes. The electrodes 41 are provided on the lower surface of the wiring board 4. The electrodes 41 are connected to wiring provided inside the wiring board 4 and function as terminals of the wiring board. The electrodes 41 are connected to host equipment and power supplies (not shown) provided outside the memory system 1.

[0028] The wiring 6 is a bonding wire, and includes, for example, copper (Cu), gold (Au), or silver (Ag). The wiring 6 connects the pads 30 of the semiconductor memory device 3 to the pads 40 of the wiring board 4. Although not shown in the diagram, multiple wirings 6 are provided, corresponding to the number of pads 30.

[0029] The resin layer 7 seals and protects the semiconductor memory device 3 and wiring 6 on the wiring board 4. The resin layer 7 includes, for example, a thermosetting resin such as epoxy resin or acrylic resin.

[0030] In the example shown in Figure 2, only one semiconductor memory device 3 is provided on the wiring board 4, but multiple semiconductor memory devices 3 may be provided. In that case, one semiconductor memory device 3 may be provided on top of another semiconductor memory device 3. Although not shown in Figure 2, a memory controller 2 is also provided on the wiring board 4. The memory controller 2 and the semiconductor memory devices 3 are connected to each other via wiring provided inside the wiring board 4.

[0031] 1.4 Appearance of semiconductor memory devices The semiconductor memory device 3 according to this embodiment is formed by bonding two semiconductor substrates, each having a semiconductor structure formed on it, together, and then separating the bonded semiconductor substrates into individual chips. That is, the semiconductor memory device 3 according to this embodiment includes a structure formed by bonding semiconductor substrates W1 and W2 together. Each of the semiconductor substrates W1 and W2 is a silicon substrate. The following describes the case in which the semiconductor substrate W2 is removed during the manufacturing process of the semiconductor memory device 3. Depending on the structure of the semiconductor memory device 3, a portion of the semiconductor substrate W2 may remain after bonding.

[0032] Figure 3 is a perspective view showing an example of the appearance of a semiconductor memory device according to the embodiment. Hatching has been added to Figure 3 to improve the visibility of the drawing, but this does not necessarily relate to the material or characteristics of the components to which the hatching has been added. As shown in Figure 3, the semiconductor memory device 3 has a structure in which, for example, a semiconductor substrate W1, a control circuit layer 100, a junction layer B1, a junction layer B2, a memory layer 200, and a wiring layer 300 are stacked in this order.

[0033] The control circuit layer 100 includes a control circuit formed using a semiconductor substrate W1. The semiconductor substrate W1 has impurity diffusion regions, etc., according to the design of the control circuit. The control circuit layer 100 includes, for example, an input / output circuit 11, a logic control circuit 12, a register 13, a sequencer 14, a driver module 15, a low decoder module 16, and a sense amplifier module 17.

[0034] The bonding layer B1 is provided on the control circuit layer 100. The bonding layer B1 is formed using the semiconductor substrate W1. The bonding layer B1 includes a plurality of bonding pads that are electrically connected to the control circuit provided on the control circuit layer 100 and form part of the semiconductor circuit.

[0035] The junction layer B2 is provided on the junction layer B2. The junction layer B2 is formed using a semiconductor substrate W2 (not shown). The junction layer B2 includes a plurality of junction pads that are electrically connected to the memory cell array 10 provided on the memory layer 200 and form part of the semiconductor circuit. The plurality of junction pads included in the junction layer B2 are each connected to the plurality of junction pads included in the junction layer B1. The interface between the junction layers B1 and B2 corresponds to the boundary, i.e., the junction surface, between the layer formed using the semiconductor substrate W1 and the layer formed using the semiconductor substrate W2.

[0036] The memory layer 200 is provided on the junction layer B2. The memory layer 200 is formed using a semiconductor substrate W2 (not shown). The memory layer 200 includes, for example, a memory cell array 10.

[0037] The wiring layer 300 is provided on the memory layer 200. The wiring layer 300 is formed in the portion where the semiconductor substrate W2 is removed after the semiconductor substrates W1 and W2 have been bonded together. The wiring layer 300 includes, for example, wiring connected to semiconductor circuits provided on the memory layer 200, and a plurality of pads 30.

[0038] Although the semiconductor memory device 3 is shown as a rectangular parallelepiped in Figure 3, the shape of the semiconductor memory device 3 is not limited to a rectangular parallelepiped. For example, it may have a structure in which the area near the dicing line is recessed relative to other parts.

[0039] 1.5 Circuit configuration of a memory cell array Figure 4 is a circuit diagram showing an example of the circuit configuration of a memory cell array in a semiconductor memory device according to the embodiment. Figure 4 shows one block BLK. The block BLK includes, for example, four string units SU0 to SU3.

[0040] Each string unit SU includes multiple NAND strings NS, each associated with a bit line BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS includes, for example, eight memory cell transistors MT0 to MT7 and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage film, and stores data nonvolatilously based on the amount of charge in the charge storage film. Selection transistors ST1 and ST2 are used to select the string unit SU during various operations.

[0041] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series in this order. The drain of selection transistor ST1 is connected to the associated bit line BL, and the source of selection transistor ST1 is connected to the drain of memory cell transistor MT7. The drain of selection transistor ST2 is connected to the source of memory cell transistor MT0, and the source of selection transistor ST2 is connected to the source line SL.

[0042] Within the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of selection transistors ST1 within string units SU0 to SU3 are connected to selection gate lines SGD0 to SGD3, respectively. The gate of selection transistor ST2 is connected to selection gate line SGS.

[0043] Each bit line BL0 to BLm is assigned a different column address CA. Each bit line BL is shared by a NAND string NS, which is assigned the same column address CA across multiple block BLKs. Each word line WL0 to WL7 is provided for each block BLK. The source line SL is shared, for example, across multiple block BLKs.

[0044] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is called, for example, a cell unit CU. For instance, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data." A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0045] The circuit configuration of the memory cell array 10 in the semiconductor memory device 3 according to this embodiment is not limited to the above description. For example, the number of string units SU included in each block BLK can be designed to any number. The number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can each be designed to any number.

[0046] 1.6 Structure of a memory cell array Figure 5 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array in a semiconductor memory device according to the embodiment. Figure 5 shows the cross-sectional structure of the memory layer 200 and the junction layer B2 corresponding to the memory cell array 10. In Figure 5, the Z1 direction (upward) is shown at the bottom of the page, and the Z2 direction (downward) is shown at the top of the page. In the following description, the direction in which the word lines WL0 to WL7 extend is referred to as the X direction, and the direction in which the bit line BL extends is referred to as the Y direction.

[0047] The memory cell array 10 includes a semiconductor layer 201, a plurality of insulating layers 202, a plurality of conductive layers 203, conductive layers 204 and 205, insulating layers 210 and 220, a conductor 221, contacts CV, V1 and V2, a plurality of memory pillars MP, and a component SLT. The memory cell array 10 is formed using a semiconductor substrate W2. A semiconductor layer 201 is provided on the Z2-direction plane of the semiconductor substrate W2. The semiconductor layer 201 functions as a source line SL. The semiconductor layer 201 includes, for example, silicon. A plurality of insulating layers 202 and a plurality of conductive layers 203 are alternately stacked one layer at a time on the Z2-direction plane of the semiconductor layer 201. In the example shown in Figure 5, 10 layers of insulating layers 202 and 10 layers of conductive layers 203 are alternately stacked one layer at a time. In other words, a plurality of conductive layers 203 are provided below (above the plane of the paper) the semiconductor layer 201, stacked apart in the Z direction. Multiple conductive layers 203 extend in the X direction and function, in order from the semiconductor substrate W2 side, as selection gate line SGS, word lines WL0 to WL7, and selection gate line SGD, respectively. The insulating layer 202 contains, for example, silicon oxide (SiO). The conductive layer 203 contains, for example, tungsten (W) or molybdenum (Mo). Below the lowest conductive layer 103 in the Z2 direction (above the paper), a conductive layer 204 is provided via an insulating layer 210. The conductive layer 204 extends in the Y direction and functions as a bit line BL. The conductive layer 204 contains, for example, copper (Cu). Contact CV extends in the Z direction between the insulating layers 210 and connects the semiconductor film 231 of the memory pillar MP (described later) to the conductive layer 204. Below the conductive layer 204 (above the paper), a conductive layer 205 is provided via an insulating layer 210. Contact V1 extends in the Z direction between the insulating layers 210 and connects conductive layers 204 and 205. Below the conductive layer 205 (above the paper), a bonding layer B2 is provided via an insulating layer 210. Bonding layer B2 includes an insulating layer 220 and a conductor 221. The conductor 221 corresponds to a bonding pad provided on bonding layer B2. Contact V2 extends in the Z direction between the insulating layers 210 and connects conductive layer 205 and conductor 221. That is, conductive layer 204 is connected to conductor 221 via conductive layer 205, and contacts V1 and V2.

[0048] Multiple memory pillars MP have a cylindrical shape extending in the Z direction. One memory pillar MP corresponds to one NAND string NS. Multiple memory pillars MP are arranged to intersect with multiple conductive layers 203. The portion of a memory pillar MP that intersects with the conductive layer 203 corresponding to the selection gate line SGS functions as a selection transistor ST2. The portions of a memory pillar MP that intersect with multiple conductive layers 203 corresponding to word lines WL0 to WL7 each function as memory cell transistors MT0 to MT7, respectively. The portion of a memory pillar MP that intersects with the conductive layer 203 corresponding to the selection gate line SGD functions as a selection transistor ST1.

[0049] Each memory pillar MP includes a core film 230, a semiconductor film 231, and a multilayer film 232. The core film 230 is provided stretched along the Z direction. For example, the Z1 end of the core film 230 is located within the semiconductor layer 201, and the Z2 end of the core film 230 is located within the insulating layer 210. The core film 230 includes an insulator, such as silicon oxide. The semiconductor film 231 covers the periphery of the core film 230, for example. On the side surface near the Z1 end of the memory pillar MP, a portion of the semiconductor film 231 contacts and electrically connects with the semiconductor layer 201. The Z2 end of the semiconductor film 231 connects to contact CV. The semiconductor film 231 includes, for example, silicon (Si). The multilayer film 232 covers the side and top surface (the surface below the plane of the paper) of the semiconductor film 231, except for the portion where the semiconductor film 231 and the semiconductor layer 201 are in contact.

[0050] Figure 6 is a cross-sectional view along the line VI-VI in Figure 5, showing an example of the cross-sectional structure of a memory pillar in a semiconductor memory device according to the embodiment. More specifically, Figure 6 shows the cross-sectional structure of a memory pillar MP in a layer including a conductive layer 203. As shown in Figure 6, the laminated film 232 includes, for example, a tunnel insulating film 233, a charge storage film 234, and a block insulating film 235.

[0051] In a cross-section including the conductive layer 203, the core film 230 is provided, for example, in the central part of the memory pillar MP. The semiconductor film 231 surrounds the sides of the core film 230. The tunnel insulating film 233 surrounds the sides of the semiconductor film 231. The charge storage film 234 surrounds the sides of the tunnel insulating film 233. The block insulating film 235 surrounds the sides of the charge storage film 234. The conductive layer 203 surrounds the sides of the block insulating film 235.

[0052] The semiconductor film 231 is used as the channel (current path) for the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. The tunnel insulating film 233 and the block insulating film 235 each contain, for example, silicon oxide. The charge storage film 234 contains, for example, silicon nitride (SiN). With this configuration, the memory pillar MP can function as a single NAND string NS.

[0053] As shown in Figure 5, the member SLT has a wall-like structure extending in the XZ plane, dividing multiple insulating layers 202 and multiple conductive layers 203 in the Y direction. For example, the Z1 end of the member SLT is located within the semiconductor layer 201, and the Z2 end of the member SLT is located within the insulating layer 210. The Z-direction positions of the memory pillar MP and the ends of the member SLT may or may not be aligned. The member SLT includes an insulator 240. The insulator 240 includes, for example, silicon oxide. Although not shown, multiple member SLTs are provided arranged in the Y direction. Each of the regions divided in the Y direction by the multiple member SLTs functions as one block BLK.

[0054] 1.7 Structure of semiconductor memory devices The structure of the semiconductor memory device 3 according to the embodiment is described below. Hatching has been added to the plan views referred to below to improve the visibility of the drawings, but this does not necessarily relate to the material or properties of the components to which the hatching has been added.

[0055] 1.7.1 Planar Layout Figure 7 is a plan view showing an example of a planar layout of a semiconductor memory device according to an embodiment. As shown in Figure 7, the semiconductor memory device 3 includes, for example, a core region CR, a peripheral region PR, a wall region WR, and a kerf region KR.

[0056] The core region CR is, for example, a rectangular region located near the center of the semiconductor memory device 3. The core region CR is provided with, for example, a memory cell array 10, registers 13, a sequencer 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0057] The peripheral region PR is a rectangular ring-shaped region that surrounds the outer periphery of the core region CR. For example, input / output circuits 11 and logic control circuits 12 are provided in the peripheral region PR. Furthermore, contacts and wiring for connecting wiring provided in the wiring layer 300 to circuits provided in the control circuit layer 100 or memory layer 200 are provided in the peripheral region PR. In addition, a plurality of pads 30 are provided in the peripheral region PR.

[0058] The wall region WR is a rectangular ring-shaped region that surrounds the outer perimeter of the surrounding region PR. The wall region WR is provided with edge seals ES1 and ES2 that surround the outer perimeter of the surrounding region PR. In addition, edge seals ES3 and ES4 are provided that surround the outer perimeter of edge seals ES1 and ES2. Edge seals ES1 to ES4 include, for example, tungsten. The number of edge seals corresponding to edge seals ES1 and ES2 is arbitrary; there may be one or three or more. The number of edge seals corresponding to edge seals ES3 and ES4 is also arbitrary; there may be one or three or more. Details of edge seals ES1 to ES4 will be described later.

[0059] The kerf region KR is a rectangular ring-shaped region that surrounds the outer periphery of the wall region WR. The kerf region KR is in contact with the outermost periphery of the semiconductor memory device 3. Alignment marks and TEG (Test Element Group) structures used in the manufacturing process of the semiconductor memory device 3 are placed in the kerf region KR. For example, a pad 400 may be provided in the kerf region KR. The pad 400 is part of the TEG structure and is used when characterizing the semiconductor memory device 3. Note that the alignment marks and TEG structure including the pad 400 in the kerf region KR are not necessarily required. The structure of the kerf region KR may be removed during the dicing process, which separates the semiconductor substrate W1 into individual chips (semiconductor memory devices 3).

[0060] 1.7.2 Cross-sectional structure Figure 8 is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the embodiment. Figure 8 shows the core region CR, peripheral region PR, and wall region WR after semiconductor substrates W1 and W2 have been bonded together. In the example shown in Figure 8, semiconductor substrate W2 has been removed after bonding semiconductor substrates W1 and W2, and a wiring layer 300 has been formed in the area where semiconductor substrate W2 was removed.

[0061] 1.7.2.1 Cross-sectional structure of the control circuit layer The cross-sectional structures of the control circuit layer 100 and the junction layer B1 will now be described. The control circuit layer 100 includes an insulator layer 110, a gate insulating film 101, a gate electrode 102, conductor layers 103, 103W, 104, and 104W, and a plurality of contacts C0, C1, C1W, C2, and C2W. The junction layer B1 includes an insulator layer 120 and conductors 121 and 121W. In addition, the control circuit layer 100 is provided with transistor TR1 in the core region CR and transistor TR2 in the peripheral region PR.

[0062] The insulating layer 110 is provided on the semiconductor substrate W1. The insulating layer 110 covers at least a portion of the wiring, contacts, elements, etc. provided on the control circuit layer 100. The insulating layer 110 includes, for example, TEOS (Tetra Ethoxy Silane). The insulating layer 110 may be composed of multiple types of insulating films. The insulating layer 120 is provided on the insulating layer 110. The insulating layer 120 covers the side surface of the bonding pad provided on the bonding layer B1. The insulating layer 120 includes, for example, silicon oxide.

[0063] In the core region CR, the gate insulating film 101 is provided on the semiconductor substrate W1. The gate electrode 102 is provided on the gate insulating film 101. The gate insulating film 101 is used as the gate insulating film of transistor TR1, and the gate electrode 102 is used as the gate electrode of transistor TR1. The conductive layer 103 is provided above the gate electrode 102. Contact C0 connects the gate electrode 102 and the conductive layer 103. Contact C1 connects the impurity diffusion region of transistor TR1 provided on the semiconductor substrate W1 to the conductive layer 103. The conductive layer 103 is connected to the conductor 121 via at least one contact C2 and at least one conductive layer 104. The conductor 121 corresponds to the junction pad provided on the junction layer B1.

[0064] In the peripheral region PR, the gate insulating film 101, gate electrode 102, conductive layers 103 and 104, conductor 121, and contacts C0, C1, and C2 are provided in the same manner as in the core region CR. Specifically, the gate insulating film 101 is used as the gate insulating film of transistor TR2, and the gate electrode 102 is used as the gate electrode of transistor TR2. Contact C1 connects the impurity diffusion region of transistor TR2 provided on the semiconductor substrate W1 to the conductive layer 103.

[0065] Within the wall region WR, the semiconductor substrate W1 includes a P-type well region PW and an N-type well region NW. The P-type well region PW is provided near the upper surface of the semiconductor substrate W1 with P-type impurities (p +This is the diffusion region of N-type impurities (n + This is the diffusion region. In the wall region WR, conductive layers 103W and 104W, a conductor 121W, and contacts C1W and C2W are provided, corresponding to edge seals ES1 and ES2, respectively. Specifically, contact C1W, corresponding to edge seal ES1, connects the P-type well region PW and the conductive layer 103W. Contact C1W, corresponding to edge seal ES2, connects the P-type well region PW and the conductive layer 103W. In addition, conductive layers 103 and 104, a conductor 121, and contacts C1 and C2 are provided, corresponding to edge seals ES3 and ES4, respectively. Contact C1, corresponding to edge seals ES3 and ES4, is in contact with the semiconductor substrate W1 on its lower surface, but since the contact area is not doped with impurities, it is not electrically connected. The conductive layers 103 and 104, the conductor 121, and the contacts C1 and C2 corresponding to the edge seals ES3 and ES4 are arranged in a continuous line in the Z direction to form a pillar structure PLa. The multiple pillar structures PLa have, for example, cylindrical or elliptical structures with a circular or elliptical cross-section in the XY plane. However, the shape of the multiple pillar structures PLa is not limited to this. For example, the multiple pillar structures PLa may have a rectangular prism shape. Note that the gate insulating film 101 and gate electrode 102 are not provided in the wall region WR.

[0066] 1.7.2.2 Cross-sectional structure of the memory layer The cross-sectional structures of the memory layer 200 and the junction layer B2 will now be described. The memory layer 200 includes insulator layers 202 and 210, semiconductor layers 201, 211, and 213, conductive layers 203, 204, 205, 205W, 206, and 206W, sacrificial member 212, and contacts C3, C3W, CV, V1, V1W, V2, and V2W. The junction layer B2 includes an insulator layer 220 and conductive members 221 and 221W.

[0067] The insulating layer 220 is provided on the insulating layer 120. The insulating layer 220 covers the side surface of the bonding pad provided on the bonding layer B2. The insulating layer 220 contains, for example, silicon oxide. The insulating layer 210 is provided on the insulating layer 220. The insulating layer 210 covers at least a portion of the wiring, contacts, elements, etc. provided on the memory layer 200. The insulating layer 210 contains, for example, TEOS. The insulating layer 210 may be composed of multiple types of insulating films. For example, the insulating layer 210 may have a structure in which layers containing silicon oxide and layers containing silicon nitride are alternately stacked.

[0068] The conductor 221 corresponds to the bonding pad provided in bonding layer B2. The control circuit layer 100 and the memory layer 200 are bonded together such that the conductors 121 and 221 are connected to each other at the interface between bonding layers B1 and B2.

[0069] A memory cell array 10 is provided in the core region CR. The memory pillars MP included in the memory cell array 10 are connected to transistor TR1 via conductive layers 103, 104, 204, and 205, conductors 121 and 221, and contacts CV, C1, C2, C3, V1, and V2.

[0070] In the peripheral region PR, conductive layers 205 and 206, semiconductor layers 211 and 213, sacrificial member 212, conductor 221, and contacts C3, V1, and V2 are provided. Semiconductor layers 211 and 213, and sacrificial member 212 are provided corresponding to the positions in the Z direction where semiconductor layer 201 is provided in the core region CR. On the insulating layer 210, semiconductor layer 211, sacrificial member 212, and semiconductor layer 213 are stacked in this order. Semiconductor layer 201 in the core region CR corresponds to a structure in which the sacrificial member 212 is replaced with a conductor after semiconductor layer 211, sacrificial member 212, and semiconductor layer 213 have been stacked. Each of the semiconductor layers 211 and 213 contains, for example, polysilicon. Sacrificial member 212 contains, for example, silicon nitride. Conductive layer 206 is wiring provided at the same height as conductive layer 204. At least one contact C3 is provided above the conductive layer 206. The upper end of each contact C3 reaches at least the height of the semiconductor layer 211 and is provided so as to be covered by the conductive layer 303 of the wiring layer 300, which will be described later, and is electrically connected to the conductive layer 303. The conductive layer 206 is connected to the conductor 221 via the conductive layer 205 and contacts V1 and V2. As a result, the conductive layer 303 is connected to the transistor TR2 via conductive layers 103, 104, 205, and 206, conductors 121 and 221, and contacts C1, C2, C3, V1, and V2.

[0071] In the wall region WR, conductive layers 205W and 206W, a conductor 221W, and contacts C3W, V1W, and V2W are provided, corresponding to edge seals ES1 and ES2, respectively. The upper ends of contacts C3W, corresponding to edge seals ES1 and ES2, reach at least the height of the semiconductor layer 211 and are provided so as to be covered by the conductive layer 303 of the wiring layer 300, which will be described later, and are electrically connected to the conductive layer 303. In addition, conductive layers 205 and 206, a conductor 221, and contacts C3, V1, and V2 are provided, corresponding to edge seals ES3 and ES4, respectively. The upper ends of contacts C3, corresponding to edge seals ES3 and ES4, penetrate, for example, the insulating layer 302 in the wiring layer 300, which will be described later, and are exposed on the surface of the semiconductor memory device 3. Note that not all of the contacts C3 corresponding to edge seals ES3 and ES4 are necessarily exposed on the surface of the semiconductor memory device 3. For example, the upper end of a portion of the contact C3 corresponding to the edge seal ES3 may be covered by insulating layers 302, 304, 305, or 306, etc., as described later. The conductive layers 205 and 206, the conductor 221, and the contacts C3, V1, and V2 corresponding to the edge seals ES3 and ES4 are arranged in a continuous line in the Z direction to form a pillar structure PLb. The multiple pillar structures PLb have, for example, a cylindrical or elliptical columnar structure with a circular or elliptical cross-section in the XY plane. However, the shape of the multiple pillar structures PLb is not limited to this. For example, the multiple pillar structures PLb may have a rectangular prism shape.

[0072] 1.7.2.3 Cross-sectional structure of the wiring layer The cross-sectional structure of the wiring layer 300 will now be described. The wiring layer 300 includes insulating layers 301, 302, 304, 305, and 306, and a conductive layer 303. The insulating layer 301 is provided on semiconductor layers 201 and 213. The insulating layer 302 is provided penetrating the insulating layer 301, semiconductor layer 213, sacrificial member 212, and semiconductor layer 211 in part of the peripheral region PR, part of the wall region WR, and the kerf region KR, respectively. The upper surface of the insulating layer 302 may be aligned with the upper surface of the insulating layer 301, or a step may be formed between the insulating layers 301 and 302. The conductive layer 303 is laminated above the insulating layers 301 and 302 in part of the core region CR, the peripheral region PR, and the wall region WR. The conductive layer 303 is separated (insulated) at least between the peripheral region PR and the wall region WR, and may have a portion that is continuously provided between the core region CR and the peripheral region PR. The insulating layers 304, 305, and 306 are laminated in this order above the insulating layer 301 or conductive layer 303 in the core region CR, the peripheral region PR, and a part of the wall region WR. In other words, there may be areas in a part of the wall region WR and the kerf region KR where the insulating layers 304, 305, and 306 are not provided. Specifically, the insulating layers 304, 305, and 306 are not provided above the edge seals ES3 and ES4 and in the kerf region KR. The insulating layers 301, 302, and 304 include, for example, silicon oxide. The insulating layer 305 includes, for example, silicon nitride. The insulating layer 306 includes, for example, polyimide. The insulating layers 305 and 306 function as passivation films that protect the surface of the semiconductor memory device 3.

[0073] An opening VA is provided in the core region CR. The opening VA is a groove formed to penetrate the insulating layer 301. The conductive layer 303 is electrically connected to the semiconductor layer 201 through the opening VA. The conductive layer 303, as well as the insulating layers 304, 305, and 306, have portions provided along the opening VA.

[0074] In the peripheral region PR, openings VB and TV are provided. Opening VB is provided above a plurality of contacts C3 connected to transistor TR2 and is a groove formed to penetrate the insulating layer 301, the sacrificial member 212, and the semiconductor layers 211 and 213. The conductive layer 303 is electrically connected to the contacts C3 through opening VB. In this case, the conductive layer 303 is provided to cover the upper part of the contacts C3. The sides of opening VB are covered by insulating layer 302, so that the conductive layer 303 and the semiconductor layers 211 and 213 are insulated from each other. The conductive layer 303 and insulating layers 302, 304, 305, and 306 have portions provided along opening VB. Opening TV is a groove formed to penetrate the insulating layers 304, 305, and 306. At the bottom of opening TV, the conductive layer 303 is exposed. The portion of the conductive layer 303 exposed at the bottom of the aperture TV functions as a pad 30. Below the portion of the conductive layer 303 whose surface is exposed at the bottom of the aperture TV, an insulating layer 302 is provided. In other words, the portion of the conductive layer 303 whose surface is exposed at the bottom of the aperture TV does not overlap with the semiconductor layers 201, 211, and 213 in the Z direction. The aperture VB and TV may be provided in positions that do not overlap each other in the Z direction, or they may be provided in positions that overlap each other in the Z direction.

[0075] An opening VC is provided in the wall region WR. The opening VC is provided above a plurality of contacts C3W corresponding to edge seals ES1 and ES2, and is a groove formed to penetrate the insulating layer 301, the sacrificial member 212, and the semiconductor layers 211 and 213. The conductive layer 303 is electrically connected to the contacts C3W corresponding to edge seals ES1 and ES2 via the opening VC. In this case, the conductive layer 303 is provided so as to cover the upper part of the contacts C3W. The sides of the opening VC are covered by the insulating layer 302, so that the conductive layer 303 and the semiconductor layers 211 and 213 are insulated from each other. The conductive layer 303 and the insulating layers 302, 304, 305, and 306 have portions provided along the opening VC.

[0076] 1.7.3 Edge seal structure The structure of edge seals ES1 to ES4 will be explained using Figures 7 and 8.

[0077] As shown in Figure 8, the conductors 121W and 221W corresponding to edge seal ES1 are connected to each other at the boundary between bonding layers B1 and B2, respectively. That is, edge seal ES1 has a wall-like structure that extends from the control circuit layer 100 to the memory layer 200 and is composed of conductive layers 103W, 104W, 205W, and 206W, conductors 121W and 221W, and contacts C1W, C2W, C3W, V1W, and V2W. Similarly, the conductors 121W and 221W corresponding to edge seal ES2 are connected to each other at the boundary between bonding layers B1 and B2, respectively. In other words, the edge seal ES2 has a wall-like structure that extends from the control circuit layer 100 to the memory layer 200 and is composed of conductive layers 103W, 104W, 205W, and 206W, conductors 121W and 221W, and contacts C1W, C2W, C3W, V1W, and V2W.

[0078] Conductors 121 and 221, corresponding to edge seal ES3, are connected to each other at the boundary between bonding layers B1 and B2, respectively. That is, pillar structures PLa and PLb, corresponding to edge seal ES3, are connected in the Z direction, forming a single pillar structure PL. Similarly, conductors 121 and 221, corresponding to edge seal ES4, are connected to each other at the boundary between bonding layers B1 and B2, respectively. That is, pillar structures PLa and PLb, corresponding to edge seal ES4, are connected in the Z direction, forming a single pillar structure PL.

[0079] As shown in Figure 7, the edge seals ES1 and ES2 are rectangular annular conductors extending in the XZ plane or the YZ plane. Specifically, at positions aligned with the peripheral region PR in the X direction, the edge seals ES1 and ES2 extend in the YZ plane direction. At positions aligned with the peripheral region PR in the Y direction, the edge seals ES1 and ES2 extend in the XZ plane direction. The edge seal ES1 is provided continuously to surround the peripheral region PR. The edge seal ES2 is provided continuously to surround the edge seal ES1.

[0080] The edge seals ES3 and ES4 have a structure in which multiple pillar structures PL, which are pillar-shaped conductors extending in the Z direction, are spaced apart from each other and arranged in the X or Y direction. Specifically, at positions aligned with the peripheral region PR in the X direction, the edge seals ES3 and ES4 have a structure in which multiple pillar structures PL are spaced apart from each other and arranged in the Y direction. At positions aligned with the peripheral region PR in the Y direction, the edge seals ES3 and ES4 have a structure in which multiple pillar structures PL are spaced apart from each other and arranged in the X direction. In the following description, the direction in which multiple pillar structures PL are aligned will be called the alignment direction. Multiple pillar structures PL corresponding to edge seal ES3 and multiple pillar structures PL corresponding to edge seal ES4 are arranged, for example, in a staggered pattern. Edge seal ES3 is provided so as to surround edge seal ES2 in a rectangular ring shape. Edge seal ES4 is provided so as to surround edge seal ES3 in a rectangular ring shape.

[0081] Each of the multiple pillar structures PL included in the edge seals ES3 and ES4 has, in a plan view, for example, a circular shape with a diameter of 200 nm to 400 nm, or an elliptical shape with similar major and minor axes. More preferably, it has a circular shape with a diameter of 250 nm to 350 nm, or an elliptical shape with similar major and minor axes. In this case, as shown in Figure 7, the distance L between the nearest pillar structures PL aligned in the alignment direction of the multiple pillar structures PL is within a distance of about 100 nm to 300 nm. More preferably, the distance L between the nearest pillar structures PL aligned in the alignment direction of the multiple pillar structures PL is within a distance of about 150 nm to 250 nm. In this embodiment, the diameter of the multiple pillar structures PL is 300 nm, and the distance between the nearest pillar structures PL aligned in the alignment direction is at a pitch of 200 nm.

[0082] The length of the diameter of each of the multiple pillar structure PLs is less than or equal to the width of the wiring 6. Furthermore, the shape of each of the multiple pillar structure PLs is not restricted, as long as the length of the diameter in the alignment direction of the portion exposed to the outside is less than or equal to the width of the wiring 6. For example, each of the multiple pillar structure PLs may have a square or rectangle in plan view.

[0083] The edge seals ES1 to ES4 function as crack stoppers, suppressing the intrusion of defects such as film peeling and chipping that occur during dicing into the core region CR and the surrounding region PR. In addition, edge seals ES1 and ES2 have the effect of suppressing the intrusion of moisture, ionic molecules, etc., from outside the semiconductor memory device 3 into the core region CR and the surrounding region PR. Furthermore, edge seals ES1 and ES2 play a role in releasing positive and negative charges generated inside and outside the wall region WR to the semiconductor substrate W1.

[0084] Furthermore, each of the multiple pillar structures PL included in edge seals ES3 and ES4 does not necessarily have to be electrically connected in the Z direction. For example, the conductors 121 and 221 corresponding to edge seals ES3 and ES4 do not need to be provided. A portion of the pillar structures PL included in edge seals ES3 and ES4 may be separated in the Z direction by an insulator.

[0085] 2. Explanation of Effects The semiconductor memory device 3 according to this embodiment can improve yield. This effect will be described in detail below.

[0086] Figure 9 is a plan view showing an example of the connection between a semiconductor memory device and a wiring board according to the embodiment. Figure 10 is a cross-sectional view showing an example of the connection between a semiconductor memory device and a wiring board according to the embodiment. Note that some structures are omitted in Figures 9 and 10 for simplification. As shown in Figures 9 and 10, the pads 30 of the semiconductor memory device 3 and the pads 40 of the wiring board 4 are electrically connected via the wiring 6.

[0087] The manufacturing process for semiconductor memory devices includes a dicing process in which multiple semiconductor memory devices formed on a single wafer are separated into individual pieces. In the dicing process, a common method is to physically cut along a dicing line using a blade, but defects such as film peeling and chipping may occur near the cut surface. If these defects progress to the core components of the semiconductor memory device (for example, the memory cell array and control circuit located in the core region), it may adversely affect the performance of the semiconductor memory device 3.

[0088] To prevent defects such as delamination and chipping from progressing to the core components of the semiconductor memory device, multiple edge seals are formed around the outer periphery of the core components of the semiconductor memory device to prevent delamination and chipping. The edge seals include, for example, a metal such as tungsten and are provided to form a wall that surrounds the outer periphery of the core components of the semiconductor memory device. The edge seals can suppress the intrusion of defects such as delamination and chipping into the core components of the semiconductor memory device 3.

[0089] However, depending on the structure of the semiconductor memory device, it may be necessary to place some edge seals in areas where they cannot be covered by a passivation film or the like. In the semiconductor memory device 3 according to this embodiment, as shown in Figures 9 and 10, the upper ends of edge seals ES1 and ES2 are covered by insulating layers 304 to 306 and are not exposed. On the other hand, insulating layer 306 is not provided above edge seals ES3 and ES4. This is because insulating layer 306 would hinder dicing during the dicing process, so an area without insulating layer 306 is formed at a certain distance from the dicing line. Furthermore, insulating layers 302, 304, and 305 provided above edge seals ES3 and ES4 are removed by over-etching when forming the aperture TV. Therefore, the upper ends of edge seals ES3 and ES4 are exposed.

[0090] Multiple wires 6 connecting pad 30 and pad 40 on the wiring board 4 may pass over edge seals ES3 and ES4. In this case, as shown in Figures 9 and 10, some of the multiple wires 6 may come into contact with the exposed portion of the upper end of edge seal ES3 or ES4.

[0091] If the structures corresponding to edge seals ES3 and ES4 are provided in a wall-like manner, similar to edge seals ES1 and ES2, then when multiple wirings 6 come into contact with the upper end of edge seal ES3 or ES4, the multiple wirings 6 in contact will become electrically connected to each other. As a result, pads 30 with different potentials will short-circuit, potentially damaging the circuit wiring.

[0092] On the other hand, in the semiconductor memory device 3 according to this embodiment, the edge seals ES3 and ES4 have a structure in which multiple pillar structures PL are arranged, and each pillar structure PL is electrically insulated from each other. Therefore, as shown in Figure 9, even when multiple wirings 6 (wirings 6a and 6b) come into contact with the upper end of the edge seal ES3 or ES4, if the pillar structures PL that come into contact are different from each other, the multiple wirings 6 are not electrically connected to each other. Furthermore, since the length of the upper end of each pillar structure PL in the alignment direction is less than or equal to the width of the wiring 6, the number of wirings 6 that pass through a position overlapping with the pillar structure PL in the Z direction is at most one. Therefore, short circuits between pads 30 having different potentials can be prevented, and damage to the circuit wiring can be suppressed. In other words, the yield of the semiconductor memory device 3 can be improved.

[0093] Furthermore, the semiconductor memory device 3 according to this embodiment can improve the accuracy when performing characteristic evaluation. Figure 11 is a plan view showing an example of a planar layout when performing characteristic evaluation in the semiconductor memory device according to this embodiment. Note that the semiconductor memory device 3 shown in Figure 11 shows a state in which multiple chips (semiconductor memory devices 3a and 3b) are formed side by side on a single semiconductor substrate W1 before the dicing process.

[0094] For example, a TEG structure is used to characterize a semiconductor memory device. The pad 400 corresponding to the TEG structure is connected to an external power supply or evaluation equipment, etc., via wiring 401. The wiring 401 is, for example, a bonding wire having a width similar to that of wiring 6. In this case, multiple wirings 401 may pass over edge seals ES3 and ES4. In this case, as shown in Figure 11, some of the multiple wirings 401 may come into contact with the exposed portion of the upper end of edge seal ES3 or ES4.

[0095] In the semiconductor memory device 3 according to this embodiment, the edge seals ES3 and ES4 have a structure in which multiple pillar structures PL are arranged in a row, and each pillar structure PL is electrically insulated from each other. Therefore, as shown in Figure 11, even when multiple wirings 401 (wirings 401a and 401b) come into contact with the upper end of the edge seal ES3 or ES4, if the pillar structures PL that come into contact are different from each other, the multiple wirings 401 are not electrically connected to each other. Furthermore, since the length in the alignment direction in a plan view of the upper end of each pillar structure PL is sufficiently small, the number of wirings 401 passing above each pillar structure PL is at most one. Therefore, short circuits between pads 400 having different potentials can be prevented. Thus, proper characterization of the semiconductor memory device 3 can be performed.

[0096] 3. Variations The semiconductor memory device 3 according to the embodiment described above can be modified in various ways. Below, the differences between the first, second, and third modifications of the embodiment and the embodiment will be described.

[0097] 3.1 First Variation Figure 12 is a plan view showing an example of a planar layout of a semiconductor memory device according to a first modified embodiment. Figure 12 corresponds to a part of Figure 7 in the embodiment.

[0098] As shown in Figure 12, in the semiconductor memory device 3 according to the first modified embodiment, the arrangement of the multiple pillar structures PL corresponding to the edge seals ES3 and ES4 is in a square arrangement. That is, the multiple pillar structures PL corresponding to the edge seal ES3 and the multiple pillar structures PL corresponding to the edge seal ES4 are arranged to be aligned in the X direction or the Y direction.

[0099] The semiconductor memory device 3 according to the first modified embodiment can improve yield, similar to the semiconductor memory device 3 according to the embodiment.

[0100] 3.2 Second Variation Figure 13 is a plan view showing an example of a planar layout of a semiconductor memory device according to a second modified embodiment. Figure 13 corresponds to a part of Figure 7 in the embodiment.

[0101] As shown in Figure 13, in the semiconductor memory device 3 according to the second modified embodiment, a plurality of pillar structures PL corresponding to the edge seals ES3 and ES4 are arranged alternately in groups of several. In the example shown in Figure 13, a plurality of pillar units, each consisting of three pillar structures PL arranged in a row, are arranged alternately in the edge seals ES3 and ES4 when viewed from the X or Y direction. The plurality of pillar units are arranged, for example, at a pitch of 800 nm to 1700 nm in the alignment direction. The arrangement of the plurality of pillar structures PL, the number of pillar structures PL forming a pillar unit, and the pitch between pillar units are determined, for example, according to the size of the pads 30 and the spacing (pitch) between the plurality of pads 30.

[0102] The semiconductor memory device 3 according to the second modified embodiment can improve yield, similar to the semiconductor memory device 3 according to the embodiment.

[0103] 3.3 Third Modified Example Figure 14 is a plan view showing an example of a planar layout of a semiconductor memory device according to a third modified embodiment. Figure 14 corresponds to a part of Figure 7 in the embodiment.

[0104] As shown in Figure 14, in the semiconductor memory device 3 according to the third modified embodiment, the edge seal ES3 includes a pillar portion ES3p and a wall portion ES3w. The edge seal ES4 includes a pillar portion ES4p and a wall portion ES4w. The pillar portions ES3p and ES4p of the edge seals ES3 and ES4 have the same structure as the edge seals ES3 and ES4 in the semiconductor memory device 3 according to the embodiment. That is, the pillar portions ES3p and ES4p have a structure in which a plurality of pillar structures PL are arranged in the X direction or the Y direction. The pillar portions ES3p and ES4p are formed, for example, in a region over which wiring 6 passes. The wall portions ES3w and ES4w of the edge seals ES3 and ES4 have the same structure as the edge seals ES1 and ES2 in the semiconductor memory device 3 according to the embodiment. That is, the wall portions ES3w and ES4w have a wall-like structure formed by connecting conductors extending in the X direction or the Y direction in the Z direction. The wall sections ES3w and ES4w are formed, for example, in areas where the wiring 6 does not pass above. The edge seal ES3 is provided so as to surround the edge seal ES2 in a rectangular ring shape with the pillar section ES3p and the wall section ES3w. The edge seal ES4 is provided so as to surround the edge seal ES3 in a rectangular ring shape with the pillar section ES4p and the wall section ES4w.

[0105] The semiconductor memory device 3 according to the third modified embodiment can improve yield, similar to the semiconductor memory device 3 according to the embodiment. Furthermore, in the regions where the wall portions ES3w and ES4w of the edge seals ES3 and ES4 are provided, the edge seals ES3 and ES4 can suppress the intrusion of moisture, ion molecules, etc. from outside the semiconductor memory device 3, thereby further improving the yield of the semiconductor memory device 3.

[0106] In the example shown in Figure 14, one row of pillar structure PLs was provided in the pillar section ES3p or ES4p for each wall section ES3w or ES4w. However, multiple rows of pillar structure PLs may be provided in the pillar section ES3p or ES4p. Furthermore, another row of pillar structure PLs may be provided between the pillar sections ES3p and ES4p.

[0107] 4. Others In the embodiments and several modifications described above, the structure of a semiconductor memory device was described as an example of a semiconductor device, but it is not limited to this. The function of the semiconductor device is arbitrary, as long as it has a structure that surrounds the outer periphery of the core part of the semiconductor device, corresponding to the edge seals ES1 to ES4 in the embodiments.

[0108] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0109] 1…Memory system 2…Memory controller 3, 3a, 3b...Semiconductor storage device 4…Wiring board 5...adhesive layer 6, 6a, 6b, 401, 401a, 401b… wiring 7… Resin layer 10…Memory cell array 11…Input / Output Circuits 12…Logic control circuits 13…Register 14… Sequencer 15…Driver module 16… Raw Decoder Module 17…Sense Amp Module 30, 40, 400... pads 41...Electrode 100...Control circuit layer 101...Gate Insulator 102… Guard Post 103, 103W, 104, 104W, 203, 204, 205, 205W, 206, 206W, 303...Conductor layer 110, 120, 202, 210, 220, 301, 302, 304, 305, 306… Insulating layer 121, 121W, 221, 221W…Conductor 200...Memory layer 201, 211, 213… Semiconductor layers 230... Core film 231... Semiconductor film 232… Multilayer film 233...Tunnel insulating film 234...Charge storage film 235… Block insulating film 300...Wiring layer B1, B2…bonding layer BL...bit line BLK...block CV, C0, C1, C1W, C2, C2W, C3, C3W, V1, V1W, V2, V2W… Contact CR…Core Area CU... Cell Unit ES1, ES2, ES3, ES4… Edge seals ES3p, ES4p... Pillar section ES3w, ES4w... Wall section KR...Calf area MP...Memory Pillar MT...Memory cell transistor NS...NAND string NW...N-type well region PL, PLa, PLb... Pillar structure PR... Related fields PW...P-type well area SGD, SGS... Selectable gate lines SL…Source Line SLT... component ST1, ST2…Selection transistor SU... String Unit TR1, TR2... Transistors TV, VA, VB, VC…Aperture W1, W2… Semiconductor substrates WL...Word line WR…Wall area

Claims

1. A substrate having a first region and a second region provided so as to surround the outer periphery of the first region when viewed in a first direction, A semiconductor circuit provided in the first region on the substrate, A plurality of first conductive pillars are provided in the second region on the substrate, each extending in the first direction, electrically insulated from each other and insulated from the semiconductor circuit, and arranged spaced apart from each other so as to surround the first region. In the first region, an insulating layer is provided on the side opposite to the substrate in the first direction relative to the semiconductor circuit and the plurality of first conductive pillars, and overlaps the semiconductor circuit in the first direction. Equipped with, A semiconductor device wherein at least a portion of the plurality of first conductive pillars does not overlap with the insulating layer in the first direction.

2. The substrate further comprises a third region provided between the first region and the second region, such that it surrounds the outer periphery of the first region when viewed in the first direction. The third region on the substrate further comprises a first conductor that is insulated from the plurality of first conductive pillars, extends in the first direction, and is continuously provided in a wall-like manner surrounding the first region. The insulating layer overlaps the first conductor in the first direction, The plurality of first conductive pillars are provided outside the first conductor with respect to the first region. The semiconductor device according to claim 1.

3. In the first region, a plurality of pads are provided in each of a plurality of openings passing through the insulating layer in the first direction, each of which is connected to the semiconductor circuit, Multiple wires, one end of which is connected to each of the multiple pads and the other end of which is connected to any external terminal, Furthermore, The plurality of wirings pass through a position that overlaps with any of the plurality of first conductive pillars in the first direction. The number of the multiple wirings overlapping in the first direction in each of the multiple first conductive pillars is at most one. The semiconductor device according to claim 1.

4. Each of the plurality of first conductive pillars has a circular or elliptical shape when viewed in the first direction. The semiconductor device according to claim 1.

5. Each of the plurality of first conductive pillars has a diameter of 250 nm to 350 nm when viewed in the first direction. The semiconductor device according to claim 4.

6. Each of the plurality of first conductive pillars includes a portion that is separated in the first direction and electrically insulated. The semiconductor device according to claim 1.

7. The substrate further comprises a plurality of second conductive pillars arranged spaced apart from each other and surrounding the first region, each extending in the first direction, electrically insulated from each other and insulated from the plurality of first conductive pillars and the semiconductor circuit. The plurality of second conductive pillars are provided outside the plurality of first conductive pillars with respect to the first region. The semiconductor device according to claim 1.

8. The plurality of first conductive pillars and the plurality of second conductive pillars are arranged in a staggered pattern when viewed in the first direction. The semiconductor device according to claim 7.

9. The plurality of first conductive pillars and the plurality of second conductive pillars are arranged in a square orientation when viewed in the first direction. The semiconductor device according to claim 7.

10. It further includes a plurality of first pillar units formed by arranging several adjacent first conductive pillars, and a plurality of second pillar units formed by arranging several adjacent second conductive pillars, The plurality of first pillar units and the plurality of second pillar units are arranged alternately when viewed in the first region. The semiconductor device according to claim 7.

11. The second conductor is provided in the second region, is insulated from the plurality of first conductive pillars, extends in the first direction, and is continuously provided in a wall-like manner that surrounds the first region together with the plurality of first conductive pillars. The semiconductor device according to claim 1.

12. In the first region, a plurality of pads are provided in each of a plurality of openings passing through the insulating layer in the first direction, each of which is connected to the semiconductor circuit, Multiple wires, one end of which is connected to each of the multiple pads and the other end of which is connected to any external terminal, Furthermore, The plurality of wirings pass through a position that overlaps with any of the plurality of first conductive pillars in the first direction, and do not pass through a position that overlaps with the second conductor in the first direction. The number of the multiple wirings overlapping in the first direction in each of the multiple first conductive pillars is at most one. The semiconductor device according to claim 11.

13. The insulating layer includes polyimide, The semiconductor device according to claim 1.

14. The semiconductor device is a semiconductor memory device. The semiconductor device according to claim 1.

15. A substrate having a first region and a second region provided so as to surround the outer periphery of the first region when viewed in a first direction, A semiconductor circuit provided in the first region on the substrate, A first conductive pillar extending in the first direction is provided in the second region on the substrate, In the first region, an insulating layer is provided on the side opposite to the substrate in the first direction relative to the semiconductor circuit and the first conductive pillar, and overlaps the semiconductor circuit in the first direction. In the first region, a pad is provided in an opening through which the insulating layer passes in the first direction and is connected to the semiconductor circuit, A wire having one end connected to the pad and the other end connected to any external terminal, Equipped with, The first conductive pillar does not overlap with the insulating layer in the first direction. The wiring passes through a position that overlaps with the first conductive pillar in the first direction, The length of the diameter of the first conductive pillar as viewed in the first direction is less than or equal to the width of the wiring. Semiconductor equipment.

16. The second region on the substrate is provided with a plurality of conductive pillars, including the first conductive pillar, that extend in the first direction. The plurality of conductive pillars do not overlap with the insulating layer in the first direction. The wiring passes through a position that overlaps with one of the plurality of conductive pillars in the first direction, The length of the diameter of each of the plurality of conductive pillars as viewed in the first direction is less than or equal to the width of the wiring. At least some of the plurality of conductive pillars are provided in the second region on the substrate, electrically insulated from each other and spaced apart from each other so as to surround the first region. The semiconductor device according to claim 15.

17. The substrate further comprises a third region provided between the first region and the second region, such that it surrounds the outer periphery of the first region when viewed in the first direction. The third region on the substrate further comprises a first conductor that is insulated from the first conductive pillar, extends in the first direction, and is continuously provided in a wall-like manner surrounding the first region. The insulating layer overlaps the first conductor in the first direction, The first conductive pillar is provided outside the first conductor with respect to the first region. The semiconductor device according to claim 15.

18. The first conductive pillar includes a portion that is divided in the first direction and electrically insulated. The semiconductor device according to claim 15.

19. The insulating layer includes polyimide, The semiconductor device according to claim 15.

20. The semiconductor device is a semiconductor memory device. The semiconductor device according to claim 15.

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