Semiconductor substrate manufacturing method

Abstract

This invention provides a selective growth method for forming a wide device layer. [Solution] The semiconductor substrate 10 comprises a template substrate TS including a first seed region S1 and a growth suppression region DA aligned in a first direction X1, and a first semiconductor portion 8A located above the template substrate. The first semiconductor portion has a first base portion B1 located on the first seed region and a first wing portion F1 connected to the first base portion and facing the growth suppression region via a first void. The first wing portion includes a wing edge E1 located above the growth suppression region, and the ratio of the width WJ in the first direction to the thickness TJ below the wing edge of the first void J1 is 5.0 or more.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor substrates, etc. [Background technology]

[0002] Development is progressing on technologies for forming semiconductor devices using GaN (gallium nitride) on silicon and sapphire substrates. However, when a GaN layer is deposited on a dissimilar substrate, the sapphire substrate yields 10 8 cm -2 On the silicon substrate, 10 9 cm -2 At high defect densities, through-dislocations were generated at the interface between dissimilar materials (the interface between the substrate and the deposited film), degrading the properties and reliability of devices formed on them. Therefore, the ELO (Epitaxial Lateral Overgrowth) method has been investigated as a technique for forming low-defect-density GaN layers on dissimilar substrates. For example, by forming a mask pattern on a base substrate containing a dissimilar substrate and a seed layer (such as a GaN layer) where the GaN layer does not grow, and using the seed layer exposed in the opening without a mask as a growth starting point, the GaN layer can be grown laterally on the mask, thereby reducing the defect density of the GaN layer on the mask (Patent Document 1). However, the laterally growing GaN layer comes into contact with the mask, which can lead to a decrease in the flatness of the GaN layer depending on the deposition conditions.

[0003] In Patent Document 2, a semiconductor layer is grown laterally on a void, and a device layer (semiconductor multilayer film) is also formed on the underside (backside) of the semiconductor layer. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2013-251304 [Patent Document 2] Special Publication No. 2017-535051 [Overview of the project] [Problems that the invention aims to solve]

[0005] The technology described in Patent Document 2 has the problem that it is difficult to form a wide device layer. [Means for solving the problem]

[0006] The semiconductor substrate according to this disclosure comprises a template substrate including a first seed region and a growth suppression region aligned in a first direction, and a first semiconductor portion located above the template substrate, wherein the first semiconductor portion has a first base portion located on the first seed region and a first wing portion connected to the first base portion and facing the growth suppression region via a first void, the first wing portion includes a wing end located above the growth suppression region, and the ratio of the width of the first void in the first direction to the thickness below the wing end is 5.0 or more. [Effects of the Invention]

[0007] A wide device layer (functional layer) can be formed. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view showing the configuration of the semiconductor substrate according to this embodiment. [Figure 2] This is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. [Figure 3] This is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. [Figure 4] This is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. [Figure 5] This is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. [Figure 6] This is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. [Figure 7] This is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. [Figure 8] This is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. [Figure 9] 1 is a plan view showing the configuration of a semiconductor substrate according to the present embodiment. [Figure 10A] It is a flowchart showing a method for manufacturing a semiconductor substrate according to the present embodiment. [Figure 10B] It is a flowchart showing a method for manufacturing a semiconductor substrate according to the present embodiment. [Figure 11] It is a block diagram showing an apparatus for manufacturing a semiconductor substrate according to the present embodiment. [Figure 12] It is a cross-sectional view showing the configuration of a semiconductor substrate according to Example 1. [Figure 13] It is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to Example 1. [Figure 14] These are Raman spectra of a base portion and a wing portion of an ELO layer according to a comparative example. [Figure 15] These are Raman spectra of a base portion and a wing portion of an ELO layer (semiconductor portion) according to Example 1. [Figure 16] It is a plan view of a semiconductor substrate including an upper layer portion. [Figure 17] It is a cross-sectional view of a semiconductor substrate including an upper layer portion. [Figure 18] It is a plan view showing a method for element isolation in Example 1. [Figure 19] It is a cross-sectional view showing a method for element isolation in Example 1. [Figure 20] It is a schematic diagram showing the configuration of an electronic apparatus according to Example 1. [Figure 21] It is a cross-sectional view showing the configuration of a semiconductor substrate of Example 4. [Figure 22] It is a graph showing the results of XRD reflection scan measurement for an ELO layer of a comparative example. [Figure 23] It is a graph showing the results of XRD reflection scan measurement for a semiconductor portion of Example 1. [Figure 24] It is a plan view showing the configuration of a semiconductor substrate of Example 5. [Figure 25] It is a cross-sectional view showing the configuration of a semiconductor substrate of Example 5. [Figure 26]Figure 25 is a cross-sectional view showing a method for manufacturing a semiconductor substrate. [Figure 27] Figure 25 is a cross-sectional view showing the manufacturing method of the template substrate. [Figure 28] This is a cross-sectional view showing a method for manufacturing a template substrate. [Figure 29] This is a cross-sectional view showing a method for manufacturing a template substrate. [Figure 30] This is a cross-sectional view showing the configuration of the semiconductor substrate in Embodiment 6. [Figure 31] This is a cross-sectional view showing the configuration of the semiconductor substrate in Embodiment 6. [Figure 32] This is a cross-sectional view showing the configuration of the semiconductor substrate in Example 7. [Figure 33] This is a flowchart showing the method for manufacturing the semiconductor device according to Example 8. [Figure 34] This is a cross-sectional view showing the method for manufacturing the semiconductor device according to Example 8. [Modes for carrying out the invention]

[0009] Figure 1 is a plan view showing the configuration of a semiconductor substrate according to this embodiment. Figure 2 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. As shown in Figures 1 and 2, the semiconductor substrate 10 comprises a template substrate TS including a first seed region S1 and a growth suppression region (non-seed region) DA aligned in a first direction X1, and a first semiconductor portion 8A located above the template substrate TS. The first semiconductor portion 8A has a first base portion B1 located on the first seed region S1 and a first wing portion F1 connected to the first base portion B1 and facing the growth suppression region DA via a first void J1. The first wing portion F1 includes an edge (wing end) E1 located above the growth suppression region DA. The first void J1 has a ratio (aspect ratio of the void) of 5.0 or more to the width WJ in the first direction X1 and the thickness TJ. This allows a wide device layer (functional layer) to be formed on the first wing portion F1. The thickness TJ may be the thickness below the wing end E1 in the first void J1 (the c-axis length between the lower surface of the wing end E1 and the surface of the template substrate TS). The width of the first wing portion F1 in the first direction X1 may be 5.0 times or more the thickness TJ of the first void J1.

[0010] The template substrate TS may have a mask pattern 6 that includes a mask portion 5 that functions as a growth suppression region DA and a first opening K1 that functions as a first seed region S1 (exposing the upper surface of the seed 3 as the first seed region S1). Specifically, the surface (upper surface) of the mask portion 5 becomes the growth suppression region DA. The template substrate TS may include a main substrate 1 (different type of substrate) with a different lattice constant from the first semiconductor portion 8A, and a seed portion 3. The template substrate TS has a ridge portion R on its upper side, and the first seed region S1 may be located on the upper surface of the ridge portion R. Specifically, the surface (upper surface) of the seed portion 3 becomes the first seed region S1.

[0011] The first void J1 is the space sandwiched between the growth inhibition region DA and the first wing portion F1. The orientation from the main substrate 1 to the first semiconductor portion 8A is defined as "upward." Viewing an object with a line of sight parallel to the normal direction of the semiconductor substrate 10 (including the case of perspective viewing) is called "planar view." The first seed region S1 (surface of seed portion 3) and the growth inhibition region DA (surface of mask portion 5) are in different positions in the thickness direction (vertical direction) of the substrate, but it is sufficient that they are aligned in the first direction X1 (direction perpendicular to the thickness direction of the substrate) in planar view.

[0012] The first semiconductor section 8A contains a nitride semiconductor as its main component. Nitride semiconductors can be expressed as, for example, AlxGayInzN (0≦x≦1;0≦y≦1;0≦z≦1;x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.

[0013] The first semiconductor section 8A may be doped (e.g., n-type including a donor) or undoped. A semiconductor substrate means a substrate containing a semiconductor, and the main substrate 1 of the template substrate TS may contain a semiconductor (e.g., silicon, silicon carbide) or it may not contain a semiconductor. An example of a main substrate 1 that does not contain a semiconductor is a sapphire substrate. The main substrate 1 may be a self-supporting substrate (wafer). The main substrate 1 and the seed section 3 together are sometimes called the base substrate. The template substrate TS including the base substrate and the mask pattern 6 is sometimes called a growth substrate.

[0014] The first direction X1 may be the a-axis direction (<11-20> direction) of the first semiconductor part 8A (nitride semiconductor such as GaN). The second direction X2 may be the m-axis direction (<1-100> direction) of the first semiconductor part 8A. The thickness direction Z of the semiconductor substrate 10 is the c-axis direction of the first semiconductor part 8A. <0001> It can be a direction.

[0015] The first semiconductor portion 8A can be formed by the ELO (Epitaxial Lateral Overgrowth) method, starting from the seed portion 3 exposed below the first aperture K1. Of the first semiconductor portion 8A, the base portion B1 located above the first aperture K1 becomes a dislocation inheritance portion with many through dislocations, while the first wing portion F1 located above the mask portion 5 becomes a low-defect portion with a smaller through dislocation density compared to the dislocation inheritance portion. The second semiconductor portion 8C grows laterally on the mask portion 5, starting from the seed portion 3 exposed below the second aperture K2, and its growth is stopped before it meets the first semiconductor portion 8A.

[0016] In this way, by forming the edge E1 of the first wing portion F1 above the growth suppression region DA and setting the aspect ratio of the first void J1 (the ratio of the width W1 in the first direction X1 to the thickness TJ) to 5.0 or more, a wide first wing F1 with high crystallinity (low defect density) can be quickly formed, and the flatness of the first wing F1 can be improved. Furthermore, when forming an upper layer (device layer, functional layer) including an active layer on the first semiconductor portion 8A, the phenomenon of the upper layer material wrapping around to the back surface of the first wing portion F1 can be suppressed. The upper layer may, for example, have a nitride semiconductor layer (including an active layer).

[0017] The semiconductor substrate 10 may include a second semiconductor portion 8C located above the template substrate TS. The template substrate TS may have a second seed region S2 adjacent to the first seed region S1 via a growth suppression region DA in a plan view. The second semiconductor portion 8C has a second base portion B2 located on the second seed region S2 and a second wing portion F2 connected to the second base portion B2 and facing the growth suppression region DA via a second void J2. The first wing portion F1 and the second wing portion F2 are aligned in a first direction X1 via a gap GP, and the ratio of the width WJ of the second void J2 to the thickness TJ may be 5.0 or more. The thickness TJ may be the thickness below the wing end E2 in the second void J2.

[0018] In the following, the first semiconductor section 8A and the second semiconductor section 8C may be collectively referred to as semiconductor section (semiconductor layer) 8, the first wing section F1 and the second wing section F2 as wing section F, the first base section B1 and the second base section B2 as base section B, the first void J1 and the second void J2 as void section J, the first opening K1 and the second opening K2 of the mask pattern 6 as opening section K, and the first seed region S1 and the second seed region S2 as seed region S.

[0019] The first wing portion F1 may have a width-to-thickness ratio of 2.0 or more, 5.0 or more, 10 or more, 20 or more, 50 or more, 100 or more, or 200 or more. By setting the width-to-thickness ratio of the first wing portion F1 to 1 / 2 or less, the deviation between the c-axis direction of the first base portion B1 and the c-axis direction of the tip of the first wing portion F1 can be kept to 0.2° or less. The first wing portion F1 may have a width in the first direction X1 of 7.0 [μm] or more, 10.0 [μm] or more, 20.0 [μm] or more, 40.0 [μm], or 100 [μm] or more. It is preferable that the width in the first direction X1 of the first wing portion F1 be 80.0 [μm] or less. This reduces the risk of the semiconductor portion 8 bending in the substrate direction due to gravity. The thickness of the first wing portion F1 may be, for example, 10.0 [μm] or less, 5.0 [μm] or less, or 2.0 [μm] or less. As shown in Figure 2, the width of the gap GP may be greater than the thickness of the first void J1. The ratio of the width of the first wing portion F1 to the width of the first base portion B1 may be 3.0 or more. The thickness of the first void J1 may be 3.0 [μm] or less. The thicknesses of the first wing portion F1 and the first base portion B1 may be the same. The thickness of the mask portion 5 may be 1 [μm] or less, or 50 [nm] or less. The seed portion 3 contains argon or oxygen in a quantity of 2 × 10⁻¹⁶. 18 / cm 3 It may be composed of nitride semiconductors containing the above (AlN, AlON, GaN-based semiconductors, etc.).

[0020] As shown in Figure 1, the first seed region S1 and the growth inhibition region DA may each have a shape in which the second direction X2, which is orthogonal to the first direction X1, is the longitudinal direction. The main substrate 1 is a silicon substrate, a sapphire substrate, or a silicon carbide substrate, and the first semiconductor portion 8A may include a nitride semiconductor (for example, a GaN-based semiconductor).

[0021] As shown in Figure 2, the template substrate TS has a ridge portion R on its upper side, and the seed portion 3 may be included in the ridge portion R. The upper surface of the ridge portion R may be composed of the seed portion 3, and the side surface of the ridge portion R may be composed of the mask portion 5. That is, the upper surface of the ridge portion R may have the seed portion 3, and the side surface of the ridge portion R may have the mask portion 5. Alternatively, the upper surface of the ridge portion R may have the seed portion 3, and the side surface of the ridge portion R may be composed of the mask portion 5, without having the seed portion 3. The seed portion 3 may be locally arranged on the ridge portion R and may not be located below the mask portion 5.

[0022] The main substrate 1 includes a protrusion Q on its upper surface, and the seed portion 3 may be located on the protrusion Q. The side surface of the ridge portion R does not have to be in contact with the first wing portion F1. The entire side surface of the ridge portion R may face the first void J1. This reduces the contact area between the ridge portion R and the wing portion F1, thereby reducing defects in the wing portion F1. The seed portion 3 does not have to be located below the mask portion 5. The nitride semiconductor included in the first semiconductor portion 8A is a GaN-based semiconductor, and the first void J1 may have a width-to-thickness ratio of 20.0 or more. The first semiconductor portion 8A may have two paired first wing portions F1 extending from the first base portion B1 in a first direction X1 and its opposite direction.

[0023] Figure 3 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. As shown in Figure 3, the ridge portion R may include a buffer portion 2 and a seed portion 3. In this case, the base portion consisting of the buffer portion 2 and the seed portion 3 may be arranged in a stripe pattern.

[0024] Figure 4 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. As shown in Figure 4, the first wing portion F1 may be thicker than the first base portion B1. The side surface of the ridge portion R (mask portion 5) may be in contact with the first wing portion F1. As long as the first wing portion F1 does not come into contact with the growth suppression region DA (mask portion 5), a void J1 can be formed, so there is no problem.

[0025] Figure 5 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. As shown in Figure 5, the ridge portion R may be located on the flat upper surface of the main substrate 1.

[0026] Figure 6 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. As shown in Figure 6, the buffer portion 2 includes a lower portion 2a and an upper portion 2b, the lower portion 2a being planar, and the seed portion 3 and upper portion 2b are not located below the mask portion 5, although the lower portion 2a may be located there. The ridge portion R may include the upper portion 2b of the buffer portion 2.

[0027] Figure 7 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. As shown in Figure 7, the first wing portion F1 may be separated into a plurality of parts PA arranged in a second direction X2 that is orthogonal to the first direction X1.

[0028] Figure 8 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. Figure 9 is a plan view showing the configuration of a semiconductor substrate according to this embodiment. As shown in Figures 8 and 9, the semiconductor substrate 10 may be located above the first semiconductor portion 8A and may include an upper layer 9 containing an active layer and a p-type layer. An anode EA and a cathode EC may be provided on the upper layer 9.

[0029] Figure 10A is a flowchart showing a method for manufacturing a semiconductor substrate according to this embodiment. The method for manufacturing a semiconductor substrate according to this embodiment includes a step S10 of preparing a template substrate TS including a first seed region S1 and a growth suppression region DA aligned in a first direction X1, and a step S20 of growing a first semiconductor portion 8A having a first base portion B1 located on the first seed region S1 and a first wing portion F1 connected to the first base portion B1 and facing the growth suppression region DA via a first void J1, such that the width of the first wing portion F1 in the first direction X1 is 5.0 times or more the thickness of the first void J1. A step S30 may be performed to stop the growth of the first wing portion F1 and the second wing portion F2 before they meet, before the first wing portion F1 and the second wing portion F2 growing in a direction approaching the first wing portion F1 meet. The template substrate TS has a seed portion 3 including the first seed region S1, and the seed portion 3 may be formed by sputtering.

[0030] Figure 10B is a flowchart illustrating a method for manufacturing a semiconductor substrate according to this embodiment. As shown in Figure 10B, after step S10, a step S20B may be performed to grow a first semiconductor portion 8A having a first base portion B1 located on a first seed region S1 and a first wing portion F1 connected to the first base portion B1 and facing a growth suppression region DA via a first void J1, such that the width (Ws) of the first semiconductor portion 8A (including both wings) in the first direction X1 is 5.0 times or more the thickness (Th) of the first semiconductor portion 8A.

[0031] Figure 11 is a block diagram showing a semiconductor substrate manufacturing apparatus according to this embodiment. The semiconductor substrate manufacturing apparatus 50 includes an apparatus M10 that performs process S10 in Figure 10, an apparatus M20 that performs process S20A in Figure 10A (process S20B in Figure 10B), and a control device MC that controls apparatus M10 and apparatus M20. Apparatus M20 may be an MOCVD apparatus, and the control device MC may perform process S30 via apparatus M20.

[0032] [Example 1] As the main substrate 1, silicon substrates, silicon carbide substrates (4H-SiC, 6H-SiC substrates), sapphire substrates, nitride substrates (GaN, AlN substrates, etc.), ScMgAlO substrates, etc. can be used.

[0033] The seed portion 3 is formed above the main substrate 1 and serves as the starting point for the growth of the semiconductor portion 8. The seed portion 3 only needs to be formed in a part of the opening K (of the mask pattern 6), and may be planar or patterned (for example, striped). As the seed portion 3, a GaN layer, AlN layer, AlGaN layer, AlInN layer, AlGaInN, Al, etc., formed at a low temperature (500°C or below) may be used. The thickness of the seed portion 3 is approximately 10 nm to 500 nm.

[0034] A buffer portion 2 may be formed between the main substrate 1 and the seed portion 3 (e.g., a GaN layer), and the buffer portion 2 improves the crystallinity and flatness of the seed portion 3. The buffer portion 2 may be planar or patterned (e.g., stripe-shaped) to match the seed portion 3. As the buffer portion 2, a GaN layer, AlN layer, AlGaN layer, AlInN layer, AlGaInN, Al, etc., formed at low temperatures (500°C or below) may be used. The thickness of the buffer portion 2 is approximately 10 nm to 500 nm. When a silicon substrate is used for the main substrate 1, it is desirable that the buffer portion 2 in contact with the silicon substrate does not contain gallium in order to suppress meltback.

[0035] The layer between the main substrate 1 and the semiconductor portion 8 is sometimes referred to as the underlayer (including at least one of the buffer portion 2 and the seed portion 3). A GaN layer may be formed as the underlayer (e.g., the seed portion 3) by sputtering. In this case, for example, a sputtering target mainly composed of gallium nitride (containing 25 atm% or more gallium) with an oxygen content of 5 atm% or less may be used, and the sputtering gas pressure may be less than 0.3 Pa. As for the sputtering method, DC sputtering, RF sputtering, AC sputtering, DC magnetron sputtering, ECR (Electron cyclotron Resonance) sputtering, RF magnetron sputtering method, PSD (Pulse sputter deposition) method, laser ablation method, etc., can be appropriately selected.

[0036] The sputtering target used has an oxygen content that enhances the overall crystallinity of the film. The oxygen content may be 5 atm% or less, 3 atm% or less, or 1 atm% or less. Higher purity is desirable, and the metal impurity content may be less than 0.1% or less than 0.01%. When forming a GaN layer by sputtering, using a gallium nitride target with low oxygen content can improve surface flatness, crystallinity, and suppress the formation of surface hillocks (protrusions).

[0037] When forming a nitride semiconductor (AlN, GaN, etc.) as a base layer by sputtering, the vacuum level inside the apparatus before film deposition should be 3 × 10⁻¹⁰ -5 Pa or less or 1 × 10⁻⁶ -5It may be not more than Pa. By pretreating the underlying substrate (such as a main substrate, a main substrate with a buffer, etc.) before film formation, organic layers and irregularities on the surface of the underlying substrate may be removed to enable epitaxial growth. Specific examples of the pretreatment include reverse sputtering treatment, acid treatment, UV treatment, etc., and reverse sputtering treatment is preferable from the viewpoint of preventing reattachment of impurities and the like after the treatment. Reverse sputtering treatment is a method of cleaning the surface of the underlying substrate by causing plasma-generated atoms to collide with the underlying substrate side. The substrate temperature during film formation may be room temperature, but the film quality can be further improved by performing the film formation while heating the substrate (for example, 400°C to 1000°C).

[0038] The power density during discharge is 5 W / cm 2 or less, or 1.5 W / cm 2 or less. The lower limit of the power density may be 0.1 W / cm 2 or 0.3 W / cm 2 The power density is obtained by dividing the power applied during discharge by the area of the sputtering target. If the power density is too high, the raw material may be sputtered from the target in a clustered state.

[0039] In Example 1, an underlayer (for example, a seed portion) which is a GaN layer was formed by an RF sputtering method. A gallium nitride target (oxygen content: 0.4 atom%) was used, the film formation pressure was set to 0.1 Pa, and nitrogen gas at 20 to 40 sccm was introduced. Although argon gas is not used in Example 1, argon gas may of course be introduced. The discharge density was 125 W / cm 2 , and the film formation temperature was room temperature.

[0040] When forming a base layer (including at least one of the buffer portion 2 and the seed portion 3) using sputtering, laser ablation, or the like, the internal stress can be controlled from compressive stress to tensile stress depending on the film deposition conditions, thus enabling control of the stress on the semiconductor portion 8. The internal stress can also be controlled by the amount of argon incorporated into the base layer. The stress on the semiconductor portion 8 may also be controlled by forming the base layer locally (in a pattern) on the substrate.

[0041] The mask pattern 6 is formed on the base substrate using a material that suppresses the longitudinal growth (growth in the c-axis direction) of the nitride semiconductor, and enables lateral growth (for example, growth in the a-axis direction). The opening K of the mask pattern 6 (the exposed part of the seed part 3) becomes the starting point for the growth of the semiconductor part 8. Examples of materials for the mask part 5 of the mask pattern 6 include silicon nitride, silicon carbide, silicon carbonitride, diamond-like carbon, silicon oxide, silicon oxynitride, etc., as well as silicon-free materials such as titanium nitride, molybdenum nitride, tungsten nitride, tantalum carbide, and high-melting-point metals (molybdenum, tungsten, platinum, etc.). The mask part 5 may be a single layer film made of one of these materials, or a multilayer film made by combining multiple of these materials. The thickness of the mask part 5 may be about 5 nm to 2 μm.

[0042] Figure 12 is a cross-sectional view showing the configuration of a semiconductor substrate according to Embodiment 1. In Figure 12, a silicon substrate is used as the main substrate 1, and a seed portion 3 is formed on a part of the upper surface of the main substrate 1. A ridge portion R, including the seed portion 3 and the main substrate 1, is formed in a stripe shape. A mask portion 5 is formed on the side surface of the ridge portion R and the surface of the main substrate 1. The mask pattern 6 has a first opening K1 on at least a part of the upper surface of the ridge portion R. A first semiconductor portion 8A is formed on the first opening K1, and a first void J1 is located below the first wing portion F1. That is, the first wing portion F1 is spaced apart from the mask portion 5 (growth suppression region DA). The width WJ of the first void J1 is the distance in the first direction X1 from the side surface of the ridge R to the edge E of the first semiconductor portion 8A. The thickness (height) TJ of the first void is the distance from the upper surface of the mask portion 5 to the lower surface (back surface) of the first semiconductor portion 8A. The ridge width WR was 5 μm, and the ridge pitch width PR was 55 μm.

[0043] Figure 13 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to Example 1. The semiconductor substrate of Example 1 can be manufactured as follows. A silicon substrate (Si(111) plane) is used as the main substrate 1, and an AlN film (seed portion 3) is deposited on the silicon substrate using a sputtering method. By using a sputtering method such as parallel plate sputtering, magnetron sputtering, or pulse sputtering, low-temperature and low-cost film deposition is possible. Furthermore, by using the MOCVD method, a highly crystalline AlN film can be formed.

[0044] The thickness of the seed portion 3 is set to 100 nm. At high temperatures, there is a problem of silicon and gallium reacting with each other (so-called meltback), and to suppress this, the thickness of the seed portion 3 may be set to 50 to 500 nm.

[0045] The deposition temperature in seed section 3 was 400°C, a mixed gas of argon and nitrogen (gas ratio approximately 1:1) was used, the input power was 500W, and the back pressure during deposition was 0.3 Pa. When using a sapphire substrate, AlN is deposited directly, but when depositing an AlN layer on a silicon substrate, a layer of several nanometers (buffer section 2) is formed first, and then the AlN layer is formed. This allows for the formation of a high-quality AlN layer without nitriding the silicon substrate. In forming the Al layer, the Al target is sputtered with Ar gas only (without introducing nitrogen). This makes it possible to continuously deposit the Al layer and AlN layer within the same chamber without inserting or removing the substrate. When forming the Al layer and AlN layer with an MOCVD apparatus, a layer of several nanometers of Al is first formed on the silicon substrate by introducing only TMA (trimethylaluminum), and then NH3 is introduced to obtain a layered structure of Si substrate / Al layer / AlN layer.

[0046] Next, a stripe-shaped resist Z with a width of approximately 3 μm is formed on the upper part of the seed portion 3 using a photolithography process, and a ridge portion R is formed using a dry etching process. At this time, the seed portion 3 and a part of the main substrate 1 are etched. For example, if the etching thickness of the seed portion 3 (AlN layer) is set to approximately 100 nm and the etching thickness of the main substrate to approximately 300 nm, the ridge R will be formed with a ridge height of approximately 400 nm. Here, the resist Z is not removed, and a silicon nitride film SF (for example, 10 nm) which will become the mask portion 5 is formed on the resist Z.

[0047] When the ELO layer is in contact with the mask portion (growth inhibition region), the thickness of the mask portion must be at least 100 nm, and interference between the mask portion and the ELO layer may impair the surface flatness of the ELO layer. However, in Example 1, the wing portion F is floating in the hollow and does not come into contact with the mask portion 5, so even if the mask portion 5 is made very thin in this way, the growth of the wing portion F is not inhibited. By making the mask portion 5 thin, the flatness of the back surface of the wing portion F is improved. Flatness is improved when the thickness of the mask portion 5 is 50 nm or less, and it can also be set to 30 nm or less.

[0048] Next, the resist Z is removed to lift off the silicon nitride film SF on the ridge portion R, and the first opening K1 is formed, thereby creating a template substrate TS (selective growth substrate). By fabricating the template substrate TS in this way without using the MOCVD method, significant cost reductions can be achieved, resulting in substantial industrial benefits.

[0049] Furthermore, when the AlN layer (underlayer) is deposited by sputtering, Ga does not adhere to the silicon substrate surface. When the AlN layer is deposited using an MOCVD apparatus used for depositing the GaN layer, Ga in the furnace may adhere to the silicon substrate surface during the heating process before deposition, causing meltback, which leads to a decrease in yield. As a result, maintenance of the MOCVD apparatus (e.g., cleaning of internal components such as trays and covers) becomes frequent, leading to high costs. On the other hand, this embodiment is a method in which the semiconductor part 8 is deposited using an MOCVD apparatus, and the AlN layer (underlayer) and mask layer are formed using a sputtering apparatus different from that apparatus. When introduced into the MOCVD apparatus, the silicon substrate surface is covered with AlN (underlayer) and the mask, so there is no decrease in yield due to meltback, which offers significant industrial advantages.

[0050] Next, the template substrate TS is transported into the MOCVD apparatus, and the semiconductor portion 8 is formed on the template substrate TS by the ELO method. In Example 1, the semiconductor portion 8 is a GaN layer, with a growth temperature of 1000-1200 degrees Celsius, a V / III ratio of 500-20000, and a growth pressure of 50 kPa. To make the semiconductor portion 8 n-type, it may be doped by flowing SiH4 through it. Even without introducing SiH4, it is possible to dope with Si by using a Si-containing material, such as SiO2 or SiN, in the mask portion, and using Si evaporated from there. It is preferable to set the film deposition conditions in at least two stages. In the first stage, the film deposition temperature is set to about 1030 degrees Celsius, and the V / III ratio is set to about 2000 to form growth nuclei (vertical growth portions) of the ELO layer (semiconductor portion 8) on the opening K. The thickness (height) of the growth nuclei is set to approximately 0.2 to 3.0 [μm], and its width may be approximately the same as the width of the ridge R, or slightly exceeding the width in the a-axis direction (<11-20> direction). In the second stage, the deposition temperature is raised to approximately 100°C to grow the GaN layer laterally (in the a-axis direction) from the growth nuclei, and growth is stopped when the width of the gap GP between the semiconductor parts 8 (GaN layers) growing in the opposite direction on the void reaches a specified value (10 μm or less). The semiconductor substrate 10 obtained in this manner (with the semiconductor parts 8 exposed) may be removed from the MOCVD apparatus and stored, or an upper layer including an active layer may be formed in the MOCVD apparatus thereafter.

[0051] In Example 1, it was found that even if the crystallinity above the opening K was poor, this poor crystallinity was not easily carried over to the wing portion F above the void (above the mask portion), and the crystallinity of the wing portion F improved (defect density became significantly lower). Furthermore, when a nitride semiconductor layer is formed on a seed layer formed by sputtering without using the ELO method, defects in the seed layer are entirely carried over to the nitride semiconductor layer, making it difficult to obtain a high-quality device.

[0052] Figure 14 shows the Raman spectra of the base and wing portions of the ELO layer in the comparative example. The ELO layer in the comparative example is formed on a seed layer formed by the MOCVD method. Figure 15 shows the Raman spectra of the base and wing portions of the ELO layer (semiconductor portion) in Example 1. The seed layer is formed by the sputtering method. From Figure 14, it can be seen that in the comparative example, the full width at half maximum of the GaN spectrum at the base is 2.2 cm. -1 The full width at half maximum of the GaN spectrum on the wing section is 2.0 cm. -1 It was found that the following was the case. From Figure 15, in Example 1, the full width at half maximum of the spectrum of the GaN at the base was 2.8 cm. -1 The full width at half maximum of the GaN spectrum on the wing section is 2.0 cm. -1 The wing portion was found to be of very high quality, comparable to the comparative example (where the seed portion was formed by the MOCVD method). This is a very industrially significant discovery, as it allows for the production of high-quality semiconductor components using an inexpensive silicon substrate and a low-cost template substrate that includes a base layer (seed portion or a laminated portion of buffer and seed portion) formed using non-MOCVD equipment such as a sputtering apparatus or EB apparatus.

[0053] By forming at least an active region (e.g., a light-emitting region) above the wing portion of the upper layer 9 (device layer, functional layer) formed on the semiconductor portion 8, a very high-quality device can be manufactured. In Example 1, the template substrate TS is formed without using an MOCVD apparatus, and the semiconductor portion 8 and upper layer 9 can be continuously formed using an MOCVD apparatus, which is another advantage.

[0054] Figure 16 is a plan view of the semiconductor substrate including the upper layer. Figure 17 is a cross-sectional view of the semiconductor substrate including the upper layer. The upper layer 9 may be formed on the semiconductor portion 8 after stopping the growth of the semiconductor portion 8 by changing the film deposition conditions (for example, by lowering the film deposition temperature by about 100°C). In addition to the active layer, the upper layer 9 may include at least one of a p-type layer, an n-type layer, and an electron blocking layer. Even when the upper layer 9 is formed on the semiconductor substrate 10, the back-side flow phenomenon, in which the upper layer material is supplied to the back side of the semiconductor portion 8, is greatly suppressed, and problems such as light absorption caused by the back-side flow phenomenon are also resolved.

[0055] In the semiconductor substrate 10 shown in Figures 16 and 17, the anode EA and cathode EC are formed above the wing portion F of the semiconductor portion 8. In a typical LED, the active region (light-emitting region) is directly below the anode EA, which is composed of a transparent electrode such as ITO (indium tin oxide). In Example 1, the back-turn phenomenon is suppressed, thus eliminating the problem of light emitted from the active region being absorbed on the back surface of the wing portion F. At least a portion of the anode EA may be located above the wing portion F, or the entire anode EA may be located above the wing portion F. Since the area directly below the cathode is generally not an active region, the cathode EC may be formed above the ridge R. In Figures 16 and 17, the anode EA and cathode EC are formed above the same wing portion F, but this is not the case. As shown in Figure 8, the anode EA may be formed above one of two wing portions F facing each other across the ridge R, and the cathode EC may be formed above the other.

[0056] In conventional ELO methods, cracks may occur in the semiconductor layer due to differences in the thermal expansion coefficients of dissimilar substrates and semiconductor layers. On the other hand, in Example 1, the fact that adjacent semiconductor parts 8 do not meet (they have a gap GP) and that the semiconductor parts 8 are located on the void and are physically separated from the mask part 5 allows for effective relaxation of internal stress and suppression of crack formation, even when using dissimilar substrates (Si substrates, SiC substrates, etc.). Stress relaxation by the wing part F can be achieved by widening the width of the wing part F (for example, to 7 μm or more).

[0057] In Example 1, the width WJ of the void J was 20 μm, the ridge height was 300 nm, and the width of the gap GP was 10 μm. Since the back surface of the semiconductor portion 8 was at the same level as the top surface of the ridge R, the thickness of the void J was 300 nm, and the aspect ratio of the void J was 66.6. An upper layer 9 was formed on the semiconductor portion 8, but no lamination of the active layer material or the like was observed on the back surface of the semiconductor portion 8, indicating that the back-side lamination phenomenon was suppressed.

[0058] The width WR of the ridge portion R, which is the starting point for growth, may be 1 μm to 20 μm, or 2 μm to 10 μm. The thickness TJ of the void may be 5 μm or less, 2 μm or less, 1 μm or less, 0.6 μm or less, or 0.3 μm or less. The thickness TJ of the void should preferably be 0.05 μm (50 nm) or more. This makes it easier to remove the mask portion 5. The pitch PR of the ridge portion may be 20 μm or more. The thickness TJ of the void should preferably be less than 0.5 μm (500 nm). This reduces morphology formation on the back surface and improves the quality of the device formed on the wing portion F. The aspect ratio of the void J can be 5.0 or more, 10 or more, 20 or more, 30 or more, 50 or more, or 100 or more. This allows the upper layer 9 to be formed on the wide wing portion F while suppressing the back surface phenomenon, and a high-quality semiconductor element (for example, one with high light extraction efficiency) can be formed. The aspect ratio of the gap J may be, for example, 100 to 1000. This reduces the risk of the semiconductor portion 8 bending upward due to gravity. Furthermore, by making the width of the gap GP 30 μm or less, or 10 μm or less, the back-turning phenomenon can be suppressed more effectively. In other words, there is no stacking of active layer material on the back surface of the wing portion F formed in this way. Therefore, there is little risk of current leakage occurring in the device formed on the wing portion F. The width of the gap GP can be 1 / 5 to 1 / 100 of the width of the wing portion F. This allows for the formation of a wide wing portion F while suppressing the back-turning phenomenon, thereby increasing the degree of freedom of the device.

[0059] Figure 18 is a plan view showing the method of element separation in Example 1. Figure 19 is a cross-sectional view showing the method of element separation in Example 1. As shown in Figures 18 and 19, the element body 20 (including the wing portion F, upper layer portion 9, anode EA, and cathode EC) is separated from the template substrate. Because there is a gap J under the wing portion F, by applying downward pressure to the element body 20 with an adhesive pressing body YS (adhesive plate, adhesive sheet, etc.), the base portion of the element body 20 (the connection portion with the template substrate TS) easily breaks, and the element body 20 is separated from the template substrate TS. Specifically, the element body 20 is peeled off the template substrate TS while being held by the pressing body YS. In this way, the gap J also functions effectively in element separation, and the element body 20 can be peeled off without damaging the element body 20.

[0060] Specific examples of the element 20 include light-emitting diodes (LEDs), semiconductor lasers, Schottky diodes, photodiodes, and transistors (including power transistors and high electron mobility transistors).

[0061] Figure 20 is a schematic diagram showing the configuration of an electronic device according to Embodiment 1. The electronic device 30 includes an element body 20, a drive board 23 on which the element body 20 is mounted, and a control circuit 25 that controls the drive board 23. The control circuit 25 may also include a processor. Examples of the electronic device 30 include a display device, a laser emitter (including Fabry-Perot type and surface-emitting type), a lighting device, a communication device, an information processing device, a sensing device, a power control device, and the like.

[0062] In Figure 20, the element body 20 is bonded and electrically connected to the drive substrate 23 while detached from the template substrate TS. However, it is also possible for the element body 20 to be bonded and electrically connected to the drive substrate 23 while not detached (the template substrate TS and the element body 20 on it).

[0063] [Example 2] In Example 2, the semiconductor substrate 10 shown in Figure 3 was formed. Specifically, a silicon substrate was used as the main substrate 1, and a 3 nm thick Al layer (not shown) was formed on the main substrate 1. Then, a 200 nm thick AlN layer was deposited as a buffer portion 2 using the sputtering method. The deposition temperature was 400°C, and a mixed gas of argon and nitrogen was used. The gas ratio was approximately 1:1, the input power was 500 W, and the back pressure during deposition was 0.3 Pa. Next, using a GaN target, a GaN layer, which is the seed portion 3, was deposited on the buffer portion 2 (AlN layer) with a thickness of 400 nm using the sputtering method. After that, the ridge portion R and SiN film were formed using the method described above, and the SiN film on the ridge portion was lifted off to create a template substrate TS (selective growth substrate) including the mask pattern 6. The bottom surface of the ridge portion R reached the main substrate 1, and the main substrate 1 was extruded by approximately 400 nm. Subsequently, a semiconductor substrate 10 was obtained by forming a semiconductor portion 8 on a template substrate TS using the MOCVD method.

[0064] In Example 2, the height of the ridge portion R was 200 nm (thickness of the AlN layer) + 400 nm (thickness of the GaN layer) + 400 nm (depth of the main substrate extrusion) = 1000 nm (1.0 μm). The width of the ridge portion R was 3 μm, the pitch width of the ridge portion was 40 μm, the width of the gap GP was 5 μm, and the width of the void J WJ was 16 μm. Since the height of the top surface of the ridge portion R and the back surface of the semiconductor portion 8 were the same, the thickness TJ of the void J was 1 μm, and the aspect ratio of the void J was 16.0.

[0065] In Example 2, by changing the film deposition conditions of the ELO method (for example, by changing the partial pressure of nitrogen and hydrogen in the gas flow and increasing the amount of hydrogen), the configuration shown in Figure 4, in which the height of the back surface of the wing portion F is lower than the upper surface of the ridge portion R, can be achieved. In this case, since the film deposition was completed at a position where the back surface of the wing portion F was about 600 nm lower than the upper surface of the ridge portion R, the thickness TJ of the void J became 400 nm. The width of the ridge portion R was 8 μm, the pitch width of the ridge portion was 78 μm, and the width of the gap GP was 30 μm. Therefore, the width WJ of the void J was 20 μm, and the aspect ratio of the void J was 50.

[0066] [Example 3] In Example 3, the semiconductor substrate 10 shown in Figure 2 was formed. Specifically, a sapphire substrate was used as the main substrate 1, and a 200 nm thick AlN layer was deposited on the main substrate 1 as a seed portion 3 using the sputtering method. The deposition temperature was 500°C, and a mixed gas of argon and nitrogen was used. The gas ratio was approximately 1:1, the input power was 500 W, and the back pressure during deposition was 0.3 Pa. Subsequently, the ridge portion R and SiN film were formed using the method described above, and the SiN film on the ridge portion was lifted off to create a template substrate TS (selective growth substrate) including the mask pattern 6. The bottom surface of the ridge portion R reached the main substrate 1 (sapphire substrate), and the main substrate 1 was extruded by about 10 nm. After that, the semiconductor portion 8 was formed on the template substrate TS using the MOCVD method.

[0067] In Example 3, the height of the ridge portion R was 200 nm (thickness of the AlN layer) + 10 nm (depth of the main substrate extrusion) = 210 nm. The width of the ridge portion R was 2 μm, the pitch width of the ridge portion was 30 μm, the width of the gap GP was 2 μm, and the width of the void J WJ was 13 μm. Since the height of the top surface of the ridge portion R and the back surface of the semiconductor portion 8 were the same, the thickness TJ of the void J was 200 nm, and the aspect ratio of the void J was 65. An upper layer 9 was formed on the semiconductor portion 8, but no lamination of active layer material, etc., on the back surface of the semiconductor portion 8 was observed, indicating that the back-side layering phenomenon was suppressed.

[0068] [Example 4] Figure 21 is a cross-sectional view showing the configuration of the semiconductor substrate of Example 4. In Example 4, a seed portion 3 with a two-layer structure consisting of an AlGaN layer (2 μm) and a GaN layer (1.5 μm) was formed on the AlN layer (200 nm), which is the buffer portion 2, of the template substrate TS by MOCVD. The height of the ridge portion R is 300 nm, and the bottom surface of the ridge portion R is located within the GaN layer (the lower layer of the seed portion 3). A semiconductor portion 8 was formed on the template substrate TS using the MOCVD method.

[0069] In Example 4, the width WR of the ridge R was 3 μm, the pitch width PR of the ridge was 55 μm, the width of the gap GP was 10 μm, and the width WJ of the void J was 21 μm. The back surface of the wing F was about 50 nm lower than the top surface of the ridge R, and the thickness TJ of the void J was 250 nm, so the aspect ratio of the void J was 84.

[0070] Figure 22 is a graph showing the results of XRD reflection scan measurement for the ELO layer of the comparative example. The ELO layer of the comparative example was grown laterally so as to be in contact with the mask. Figure 23 is a graph showing the results of XRD reflection scan measurement for the semiconductor portion of Example 1. In Figure 22, three peaks corresponding to the base and the two wing portions (paired wing portions) flanking it are detected. The central peak is the peak of the base, and the crystal axis of the c-plane (c-axis) is substantially perpendicular to the surface of the mask. In Figure 22, the angular difference Δ between the peaks from both wing portions was 1.1 degrees. From this result, it can be seen that in the comparative example, the c-axis of both wing portions is shifted approximately 0.5 degrees each to the opposite side from the center. Such a tilt of the c-axis indicates low flatness of the ELO layer. On the other hand, in Figure 23, the angular difference Δ between the peaks from both wing portions was 0.17 degrees, which is less than 1 / 5 of that of the comparative example. From this result, it can be seen that the flatness of the semiconductor portion 8 in Example 1 is significantly improved compared to the comparative example. Furthermore, values ​​of Δ = 0.2 degrees or less were obtained in other embodiments as well. This is thought to be due to the growth of the wing portion F on the void J and the formation of the gap GP without bringing adjacent semiconductor portions 8 together. The fact that such good flatness was obtained in the wide (e.g., 7 μm or more) wing portion F resulted in uniform in-plane incorporation of In (indium) during the formation of the upper layer 9 (see, for example, Figure 17), and it was found that the quality (e.g., luminous efficiency) and yield of the device body 20 were greatly improved.

[0071] [Example 5] Figure 24 is a plan view showing the configuration of the semiconductor substrate of Example 5. Figure 24 is a cross-sectional view showing the configuration of the semiconductor substrate of Example 5. As shown in Figures 24 and 25, the semiconductor substrate comprises a template substrate TS including a first seed region S1 and a growth suppression region (non-seed region) DA aligned in a first direction X1, and a first semiconductor portion 8A located above the template substrate TS. The first semiconductor portion 8A has a first base portion B1 located above the first seed region S1 and a first wing portion F1 connected to the first base portion B1 and facing the growth suppression region DA via a first void J1. The first wing portion F1 includes a wing end (edge) E1 located above the growth suppression region DA, and the ratio of the width in the first direction X1 to the thickness TJ of the first void J1 is 5.0 or more. In this way, a wide device layer (functional layer) can be formed on the first wing portion F1. The thickness TJ of the first void J1 may be the thickness below the wing end E1 in the first void J1.

[0072] In the semiconductor substrate 10, the template substrate TS includes a main substrate 1 and a base layer 4. In the first seed region S1, the base layer 4 is unmodified, while in the growth suppression region DA, the base layer 4 is modified. Furthermore, the first semiconductor portion 8A includes a first raised portion R1 located on the first seed region S1, and a growth suppression film 7 is provided in contact with the first raised portion R1. The first raised portion R1 is formed in a mesa shape on the first seed region S1 and connected to the first base portion B1. The growth suppression film 7 may be in contact with the side and top surfaces of the first raised portion R1, and may be located on the growth suppression region DA.

[0073] Figure 26 is a cross-sectional view showing the manufacturing method of the semiconductor substrate shown in Figure 25. Figure 26 includes the steps of: preparing a template substrate TS including a first seed region S1 and a growth inhibition region DA; forming a first raised portion R1 from the first region S1 on top of the template substrate TS; forming a growth inhibition film 7 in contact with the first raised portion R1; and forming a first base portion B1 located above the first raised portion R1, and a first wing portion F1 connected to the first base portion B1, separated from the growth inhibition region DA, and located on a void J1.

[0074] As shown in Figure 26, the first base B1 and the first wing F1 may be formed with the corner RC of the first raised portion R1 as the growth starting point. While the corner RC may be used as the growth starting point in this way, the method is not limited to this. Defects (e.g., minute openings) can also be formed in the growth-inhibiting film 7 on the first raised portion R1, and these defects in the growth-inhibiting film 7 can be used as the growth starting points for the first base B1 and the first wing F1.

[0075] The first raised portion R1, the growth-inhibiting film 7, and the first base portion B1 and first wing portion F1 may be continuously formed using an MOCVD apparatus. The first raised portion R1 may contain a GaN-based semiconductor, and the growth-inhibiting film 7 may be silicon nitride. The first raised portion R1 may be formed by supplying a gallium source raw material (organic raw material such as trimethylgallium (TMG) or triethylgallium (TEG)) and a nitrogen source raw material (ammonia gas (NH3)). The growth-inhibiting film 7 may be formed by maintaining the supply of the nitrogen source raw material, stopping the supply of the gallium source raw material, and supplying a silicon-based material (e.g., SiH4). The first base portion B1 and the first wing portion F1 may contain a GaN-based semiconductor. The first base portion B1 and the first wing portion F1 may be formed by maintaining the supply of the nitrogen source raw material, stopping the supply of the silicon-based material, and supplying a gallium source raw material. Alternatively, a small amount of silicon-based material may be continued to be supplied at a doping level. Because the first raised portion R1 is made of the same GaN-based semiconductor as the first wing portion F1, lattice defects caused by the difference in lattice constants between the first raised portion R1 and the first wing portion F1 are reduced.

[0076] By forming the growth-inhibiting film 7 in this manner, the film can be continuously deposited while forming the first void J1 under the wing portion F without removing it from the MOCVD apparatus, thereby reducing manufacturing time and costs. By forming the first void J1 and forming the wing portion F so as not to come into contact with the underlying layer 4 (growth-inhibiting region DA), stresses on the semiconductor portion 8 from the main substrate 1 and the underlying layer 4 can be effectively relieved.

[0077] Figure 27 is a cross-sectional view showing a method for manufacturing the template substrate shown in Figure 25. As shown in Figure 27, the template substrate TS shown in Figure 25 may be obtained by performing the following steps: forming a base layer 4 containing a base material, depositing a resist RZ on the base layer 4, patterning the resist RZ, applying plasma treatment to the exposed base material, and removing the resist RZ. The base layer 4 may also be formed by sputtering.

[0078] In plasma treatment, for example, the surface of the irradiated area is modified by irradiating the exposed surface 4D of the underlying layer 4 with argon plasma, thereby forming a growth-inhibiting region DA. By introducing oxygen gas, nitrogen gas, hydrogen gas, etc., in addition to argon gas, the plasma treatment can also use oxygen plasma, nitrogen plasma, hydrogen plasma, or a mixture thereof. As a result, the growth-inhibiting region DA may contain argon, oxygen, or nitrogen as impurities. In such cases, the underlying material may be aluminum nitride, and the growth-inhibiting region DA may be aluminum oxynitride. Alternatively, the underlying material may be AlScN (aluminum scandium nitride), and the growth-inhibiting region DA may be AlScON (aluminum scandium oxynitride).

[0079] Figure 28 is a cross-sectional view showing a method for manufacturing a template substrate. As shown in Figure 28, the manufacturing process may include the steps of: patterning a resist RZ on a base layer 4 (e.g., an AlN layer); forming a coating CM (e.g., a silicon nitride film of about 10 nm) covering the base layer 4 and the resist RZ; removing the resist RZ (lift-off patterning of the coating CM); annealing the coating CM and the base layer 4 (e.g., heat treatment at 1000°C); and removing the coating CM (e.g., removing the silicon nitride film by BHF). In this way, due to the interdiffusion phenomenon between the coating CM and the base layer 4 during annealing, a growth-inhibiting region DA located beneath the coating CM can be formed on the surface of the base layer 4. Alternatively, the surface modification beneath the coating CM can be performed without annealing by sputtering the coating CM. The base material may be AlScN, ScN, ZnO, CrN, etc., containing dissimilar materials such as Sc (scandium), Zn, Cr, etc. (for example, metal elements other than Group III). The base layer 4 may be a single layer or a multilayer structure. It may also be a multilayer structure including a periodic structure.

[0080] Figure 29 is a cross-sectional view showing a method for manufacturing a template substrate. As shown in Figure 29, the method may include steps of patterning a resist RZ on a base layer 4 (e.g., an AlN layer), implanting impurity ions into the exposed base material, and removing the resist RZ. Examples of impurities include Si (silicon), Fe (iron), Mg (magnesium), etc. In the implantation process, surface modification is performed by embedding impurity ions into the exposed surface 4D of the base layer 4 to form a growth-inhibiting region DA. The base material may be AlScN, ScN, ZnO, CrN, etc., containing dissimilar materials such as Sc (scandium), Zn, Cr, etc. (e.g., metal elements other than group III). The base layer 4 may be a single-layer structure or a multilayer structure. It may also be a multilayer structure including a periodic structure.

[0081] [Example 6] Figures 30 and 31 are cross-sectional views showing the configuration of the semiconductor substrate of Example 6. As shown in Figures 30 and 31, the substrate comprises a template substrate TS including a first seed region S1 and a growth suppression region (non-seed region) DA aligned in a first direction X1, and a first semiconductor portion 8A located above the template substrate TS. The first semiconductor portion 8A has a first base portion B1 located above the first seed region S1 and a first wing portion F1 connected to the first base portion B1 and facing the growth suppression region DA via a first void J1. The first wing portion F1 includes a wing end (edge) E1 located above the growth suppression region DA, and the ratio of the width (WJ) of the first direction X1 to the thickness TJ of the first void J1 is 5.0 or more. The width (wing width Wf) of the first wing portion F1 in the first direction X1 may be 5.0 times or more the thickness TJ of the first void J1. The thickness TJ may be the thickness below the wing end E1 in the first void J1, or it may be the distance (spacing) from the growth suppression region DA to the wing end E1. In this way, a wide device layer (upper layer, functional layer) can be formed on the first wing portion F1. The penetration dislocation density of the first wing portion F1 is 5 × 10⁻⁶ 6 [pcs / cm 2 The following conditions may apply: The first wing section F1 may have a ratio of the width in the first direction X1 (wing width Wf) to the thickness Th (wing thickness) of 5.0 or more.

[0082] The template substrate TS in Figure 30 includes a main substrate 1, a buffer portion (planar buffer layer) 2, and a seed portion 3. The buffer portion 2 is a growth suppression layer (a layer that suppresses the growth of nitride semiconductor crystals) and includes a ridge portion (protrusion) R1. The buffer portion 2 may include at least one of a 4H-SiC layer, a 6H-SiC layer, a 3C-SiC layer, a sapphire layer, a diamond layer, and a ScAlMgO layer. A seed portion 3 (e.g., AlN) including a first seed region S1 is formed on the ridge portion R1, and the region of the upper surface of the buffer portion 2 that does not overlap with the seed portion 3 functions as a growth suppression region DA. The main substrate 1 can be a silicon substrate, a silicon carbide substrate, a sapphire substrate, etc.

[0083] The template substrate TS in Figure 31 includes a main substrate 1 and a seed portion 3. The main substrate 1 is a growth-inhibiting substrate (a substrate that inhibits the growth of nitride semiconductor crystals) and includes a ridge portion (protrusion) R1. The main substrate 1 may be a 4H-SiC substrate, a 6H-SiC substrate, a 3C-SiC substrate, a sapphire substrate, a diamond substrate, or a ScAlMgO substrate. A seed portion 3 (for example, AlN) including a first seed region S1 is formed on the ridge portion R1, and the region of the upper surface of the main substrate 1 that does not overlap with the seed portion 3 functions as a growth-inhibiting region DA.

[0084] [Example 7] Figure 32 is a cross-sectional view showing the configuration of a semiconductor substrate of Example 7. The semiconductor substrate 10 in Figure 32 comprises a template substrate TS including a first seed region S1 and a first semiconductor portion 8 located above the template substrate TS. The first semiconductor portion 8 has a first base portion B1 located on the first seed region S1 and a first wing portion F1 adjacent to the first base portion B1 in a first direction X1 and connected to the first base portion B1. The template substrate TS includes a growth suppression region DA facing the first wing portion F1 via a first void J1. The first wing portion F1 includes a wing end (edge) E1 located above the growth suppression region DA. The ratio of the length WJ of the first void J1 in the first direction X1 to the thickness TJ of the first void J1 is 5.0 or greater.

[0085] The template substrate TS includes a main substrate 1 with a different lattice constant from the first semiconductor portion 8, and a seed portion 3 located above the main substrate 1, wherein the upper surface of the seed portion 3 is the first seed region S1, and the sides of the seed portion 3 may be covered with the same material as the growth suppression region DA.

[0086] As shown in Figure 32, a flat buffer portion 2 (for example, a planar AlN layer) may be formed on the main substrate 1, and a mesa-shaped seed portion 3 (ridge portion R1) including a first seed region S1 may be formed on the buffer portion 2. The seed portion 3 may be a GaN-based semiconductor. By making the seed portion 3 the same GaN-based semiconductor as the first semiconductor portion 8, lattice defects caused by the difference in lattice constants between the seed portion 3 and the first semiconductor portion 8 are reduced. In the example shown in Figure 32, the thickness TJ below the wing end in the first void J1 is 482 [nm], the width of the first void J1 is 20.1 [μm], the width of the opening K is 3.06 [μm], the total width (length in the first direction) Ws of the first semiconductor portion 8 including both wings is 44.1 [μm], and the thickness (wing thickness) Th of the first semiconductor portion 8 is 2.22 [μm]. Regarding the thickness of the first void J1, the thickness below the wing root may differ from the thickness below the wing end by about 0-5%, and in this case, the thickness of the first void J1 may be the thickness below the wing end (TJ), or it may be the minimum thickness over the entire first void J1.

[0087] [Example 8] Figure 33 is a flowchart showing the method for manufacturing a semiconductor device according to Example 8. Figure 34 is a cross-sectional view showing the method for manufacturing a semiconductor device according to Example 8. As shown in Figures 33 and 34, an element body 20 (semiconductor device) may be obtained by performing the steps of preparing a semiconductor substrate 10 (step S60), forming an upper layer 9 above the first wing portion F1 (step S70), and peeling the first wing F1 from the template substrate TS while the first wing portion F1 and the upper layer 9 are held on the transfer substrate PS (step S80), or a semiconductor device 21 including the element body 20 and the transfer substrate PS may be obtained. In step S70, it is not necessary to form the upper layer 9 below (on the back side) of the first wing F1. The upper layer 9 (functional layer) may be, for example, a nitride semiconductor layer including an active layer (for example, a GaN-based semiconductor layer), and electrodes, insulating films, etc. may be provided on the upper layer 9. The semiconductor devices (20 and 21) may include electrodes, insulating films, etc.

[0088] In the semiconductor substrate 10 shown in Figure 35, the growth-inhibiting film 7 is located on the first raised portion R1, resulting in a weak bond between the first raised portion R1 and the first wing portion F1, making it easy to peel off the first wing portion F1. Since the first raised portion R1 and the first base portion B1 are nitride semiconductor crystals, cleavage may occur at their boundary.

[0089] (Appendix) The foregoing disclosures are for illustrative and explanatory purposes only, and not for limitation. Many variations will be obvious to those skilled in the art based on these examples and descriptions, and therefore, these variations are also included in the embodiments. [Explanation of symbols]

[0090] 1 Main board 2 Buffer section 3. Seed section 4 Base layer 5 Mask section 6 Mask Patterns 8A First Semiconductor Section 8C Semiconductor Section 2 9. Upper Management 10 Semiconductor substrates 20 Element (Semiconductor Device) 21 Semiconductor devices 50 Semiconductor substrate manufacturing equipment R Ridge Section E1 Edge B1 1st base B2 2nd base F1 1st Wing F2 Second Wing Section J1 1st cavity J2 2nd gap S1 1st Seed Area S2 Second Seed Area DA growth suppression area TS template substrate

Claims

1. A step of preparing a template substrate including a first seed region and a non-seed region aligned in a first direction, A method for manufacturing a semiconductor substrate, comprising the step of growing a first semiconductor portion having a first base portion located on the first seed region and a first wing portion connected to the first base portion and facing a non-seed portion through a first void, such that the width of the first wing portion in the first direction is 5.0 times or more the thickness of the first void.

2. A method for manufacturing a semiconductor substrate according to claim 1, further comprising the step of stopping the growth of the first wing portion before the first wing portion and the second wing portion growing toward the first wing portion meet.

3. The method for manufacturing a semiconductor substrate according to claim 2, wherein the first void after the growth of the first wing portion has stopped has a width in the first direction with a ratio of 5.0 or more to the thickness below the wing end.

4. The second wing portion faces the non-seed portion via the second gap, The method for manufacturing a semiconductor substrate according to claim 2, wherein the second void after the growth of the second wing portion has stopped has a width in the first direction that is 5.0 or more in relation to the thickness below the wing end.

5. The method for manufacturing a semiconductor substrate according to claim 1, wherein the template substrate has a mask pattern including a mask portion that functions as the non-seed portion and an opening that overlaps with the first seed region in a plan view.

6. A method for manufacturing a semiconductor substrate according to any one of claims 1 to 5, wherein the first semiconductor portion includes a nitride semiconductor.

7. The method for manufacturing a semiconductor substrate according to claim 6, wherein the first direction is the a-axis direction of the nitride semiconductor.

8. The method for manufacturing a semiconductor substrate according to claim 2, wherein the width of the gap between the first wing portion and the second wing portion after the growth of the first wing portion has stopped is greater than the thickness of the first void below the wing end.

9. The template substrate has a seed portion including the first seed region, A method for manufacturing a semiconductor substrate according to any one of claims 1 to 5, wherein the seed portion is formed by a sputtering method.

10. The template substrate has a seed portion including the first seed region, The aforementioned seed section contains argon in 2 × 10 １８ / cm ３ A method for manufacturing a semiconductor substrate according to any one of claims 1 to 5, comprising a nitride semiconductor containing the above-mentioned components.

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