Two-dimensional material as a barrier layer in the metallization of semiconductor devices, and method for forming it.

Abstract

A semiconductor device comprising at least one barrier-protected metal feature and a related fabrication method are described. The method for forming the semiconductor device comprises forming a barrier layer, comprising the steps of providing a metal precursor layer and converting the metal precursor layer into one or more two-dimensional monolayers comprising at least one chalcogenide. The method also comprises contacting the barrier layer with at least one metal feature in an effective manner for providing at least one barrier-protected metal feature.

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims priority to U.S. Provisional Patent Application No. 63 / 467,833, filed on May 19, 2023, entitled "2 - DIMENSIONAL MATERIALS AS CAPPING LAYERS IN METALLIZATION OF SEMICONDUCTOR DEVICES AND METHOD OF FORMING", and the entire content of the above - mentioned provisional patent application is incorporated herein by reference for all purposes.

[0002] The present invention relates to semiconductor devices incorporating metallization features and methods for manufacturing such semiconductor devices, and more particularly to the use of ultra - thin chalcogenide materials, preferably two - dimensional (2D) monolayer chalcogenide - based semiconductor materials, as barrier layers in semiconductor device metallization.

Background Art

[0003] Metal features in microelectronic devices include contacts and interconnects (i.e., wiring). Metal features in semiconductor devices can be formed by strategies such as the damascene technique and / or metal patterning techniques. In the damascene technique, trenches and vias are formed in a dielectric material by etching or the like, and then the trenches and vias are filled with a metal such as copper or other metals. Patterning techniques typically involve patterning a metal film by etching to form patterned or raised metal features. In contrast to other conductive metals used to form interconnects and contacts in semiconductor devices, copper (Cu) is difficult to etch. Thus, the damascene strategy is often used to form copper features. The damascene or patterning techniques are used with other metals.

[0004] Damascene techniques include dual damascene, single damascene, and semi-damascene strategies. The "single" damascene process involves first creating and filling trenches (or vias), and then proceeding to fill the trenches (or vias). Etching and filling are then repeated for the vias (or trenches). The "dual" damascene technique involves simultaneously forming trenches and vias, and then simultaneously filling both trenches and vias.

[0005] As semiconductor device feature sizes continue to shrink, reducing device contact resistance has become a major challenge, particularly for narrow metal pitches using conventional dual or single damascene flow strategies. Several aspects of next-generation metallization utilize semi-damascene or removal-type metal etching flows. In these, Cu (and / or other metals) and damascene techniques are used to form some metal features, while a more easily etchable metal, such as Al, Mo, Ru, and / or W, is deposited and then etched as an alternative to Cu to form patterned metal features. In short, the semi-damascene strategy uses patterning to form some metal features, and other metal features are formed using damascene techniques. While semi-damascene flows can enable narrower pitch dimensions, they still have drawbacks, including inelastic electron surface scattering.

[0006] Copper and other metals face other challenges when used in semiconductor device fabrication to form metallic features such as interconnects and contacts. One of these challenges is electromigration, a phenomenon in which metal atoms are moved under the influence of high current densities. This can cause diffusion of metal atoms into the surrounding dielectric material, potentially degrading device performance. Copper (Cu) is a typical metal used to form semiconductor interconnects and is an example of a material that tends to penetrate conventional materials in a variant form of the damascene process.

[0007] To address these issues, both metal patterning processes and damascene processes utilize a barrier layer. The barrier serves one or more purposes, including: 1) preventing metal atoms, such as copper atoms, from diffusing into the surrounding material; and 2) maintaining the structural and performance integrity of the device. Without such a barrier, the diffusion of metals like copper into nearby dielectrics can lead to problems such as increased resistance and leakage current, significantly impacting the reliability and lifespan of the device.

[0008] Barrier layers are prone to drawbacks such as the inelastic electron surface scattering described above. Inelastic electron surface scattering is thought to involve at least some electrons interacting with or generating phonons, which are quanta of vibrational energy in the material, rather than conducting. Inelastic surface scattering has become a major challenge in optimizing the contact resistance of such diffusion barriers.

[0009] Furthermore, the generation of phonons within the material lattice due to inelastic scattering is thought to have a twofold effect on conductivity. The scattering process itself removes energy from electrons, reducing their mobility and thus decreasing the conductivity of the material. In addition, increased phonon activity (i.e., vibrations within the lattice) is thought to scatter other electrons further, resulting in additional resistance to the flow of current. These effects become particularly important in nanoscale materials. As the size of a material decreases, the ratio of surface area to volume increases. This tends to make surface scattering effects relatively dominant. This is one reason why the electrical properties of nanostructured materials can differ significantly from those of their bulk materials.

[0010] Another issue concerns the use of barrier layers with smaller metal features at smaller nodes. Traditional strategies for forming barrier layers may not leave enough space to form effective metal features. In other words, traditional barrier layers can be too thick and may occupy excessive volume within trenches and vias for smaller nodes and correspondingly narrower spacing requirements.

[0011] The emergence of two-dimensional (2D) materials with atomically thin monolayer structures is of interest in the field of microelectronics. These 2D monolayer materials possess electronic and optical properties useful for applications in semiconductor devices. 2D monolayer structures are formed from a variety of materials, ranging from metalloid graphene to semiconductive transition metal dichalcogenides (TMDs) of sulfur, selenium, and / or tellurium, as well as insulating hexagonal boron nitride (h-BN).

[0012] Several 2D diffusion barriers have been studied for use in semiconductor metallization. However, challenges and drawbacks remain, including excessive consumption of the underlying metal, limited metallization options, and limitations on control to the bulk material. See, for example, Lo et. Al., Opportunities and challenges of 2D Materials in back-end-of-line interconnect scaling, J.Appl.Phys.128,080903(2020), https: / / doi.org / 10.1063 / 5.0013737. However, controlling the depth of such surface modification and ensuring consistent formation of 2D surface modifications is difficult.

[0013] Therefore, there is a particular need in the art for very thin barrier layers useful for microelectronics metallization that address the shortcomings of prior art and reduce, avoid, or in some way minimize drawbacks such as inelastic surface electron scattering while providing conductance and beneficial characteristics for semiconductor applications. There is a strong demand for the ability to form effective barrier layers, particularly 2D barrier layers, with greater precision, control, and uniformity. This need is strongest with respect to smaller nodes (e.g., less than 10 nm, or even less than 5 nm), where the key objectives are to maximize the volume available for metallization features and minimize the amount of such volume occupied by the barrier material. [Overview of the project] [Means for solving the problem]

[0014] The present invention provides a strategy that enables the formation of ultrathin barrier layers (e.g., layers having a maximum thickness of approximately 10 nm, or approximately 8 nm, or approximately 5 nm, or approximately 2 nm) more easily, with greater precision and control. The barrier layer is particularly useful as a barrier in metallization for smaller nodes (e.g., nodes up to 20 nm, or 10 nm, or 5 nm, or 4 nm, or 3 nm, or even smaller).

[0015] Aspects of the present invention involve forming a barrier layer comprising one or more metal chalcogenides comprising one or more of S, Se, and / or Te, preferably dichalcogenides comprising one or more of S, Se, and / or Te, and more preferably transition metal dichalcogenides comprising one or more of S, Se, and / or Te. In exemplary embodiments, the transition metal dichalcogenides useful for the practice of the present invention are semiconductors. The strategy of the present invention involves forming a thin precursor coating (e.g., metal, metal oxide, metal nitride, metal oxynitride, etc.) and then converting at least a portion of the precursor coating into one or more chalcogenides. The use of a precursor layer allows for more precise control of the barrier layer thickness than, for example, if a metallization feature is directly reacted with chalcogen to achieve surface modification, or if chalcogenides are directly deposited. In practical effect, the interface between the precursor layer and the adjacent material is very useful in allowing the precursor material to be converted into the desired barrier material with useful selectivity for the adjacent material. In other words, the presence of an interface and a precursor coating allows for better control of the depth and characteristics of chalcogenization than when the precursor coating is not used. Even when the precursor material and the adjacent material are similar, the interface helps provide improved chalcogenization control, but when the precursor material is different from the adjacent material, the interface provides even more beneficial selectivity.

[0016] Advantageously, the strategies of the present invention are useful for forming barrier layers in the form of 2D monolayers or stacks of such 2D monolayers formed from at least one chalcogenide. In some embodiments, each 2D monolayer in the stack may incorporate a different chalcogenide composition from the other layers in the stack in order to customize the properties exhibited by different regions of the barrier layer.

[0017] Traditionally, chalcogens have included oxygen (O), sulfur (S), selenium (Se), and tellurium (Te). However, in practice of the present invention, oxygen is not considered a chalcogen. However, metal oxides are useful as dielectric materials or as at least part of the precursor material in the formation of chalcogenides containing one or more of S, Se, and / or Te, as described below.

[0018] The principles of the present invention are useful for providing a 2D monolayer-based material as a barrier layer in any metallization method, for example, with respect to patterned metal features and / or damascene-machined metal features. The practice of the present invention helps to alleviate problems associated with narrower pitch dimensions related to damascene and patterning techniques by reducing inelastic electron surface scattering and electromigration, among other things. Barrier layers incorporating 2D monolayer-based materials also help to relax narrow spacing constraints and thus improve upon conventional metal and metal nitride barrier and liner layers.

[0019] A first aspect of this disclosure discloses a method for fabricating a semiconductor device comprising at least one barrier-protected metal feature. According to the first aspect, the method comprises a) 1) forming a barrier layer, comprising providing a metal precursor layer, and 2) converting the metal precursor layer into one or more two-dimensional monolayers comprising at least one chalcogenide. The method also comprises b) bringing the barrier layer into contact with at least one metal feature in a manner effective in providing at least one barrier-protected metal feature.

[0020] A second aspect of this disclosure discloses a method for forming a semiconductor device. According to the second aspect, the method comprises a) providing a metal feature on a substrate. The method also comprises b) forming a metal precursor layer on the exposed surface of the metal feature. The method further comprises c) chalcogenizing at least a portion of the metal precursor layer under conditions effective in providing a barrier layer comprising at least one two-dimensional monolayer, thereby providing a barrier-protected metal feature, wherein at least one two-dimensional monolayer comprises a metal chalcogenide.

[0021] A third aspect of this disclosure discloses a method for forming a semiconductor device. According to the third aspect, the method includes providing a dielectric feature on a substrate. The method also includes forming a metal precursor layer on the exposed surface of the dielectric feature. The method further includes providing a barrier-protected dielectric feature by chalcogenizing at least a portion of the metal precursor layer under conditions effective in providing a barrier layer comprising at least one two-dimensional monolayer, wherein the at least one two-dimensional monolayer comprises a chalcogenide. The method also includes providing a conductive metal in contact with the barrier layer by a damascene process.

[0022] According to a fourth aspect of the present disclosure, a semiconductor device is disclosed. According to the fourth aspect, the semiconductor device includes metal features on a substrate. The semiconductor device also includes a barrier layer in contact with the surface of the metal features, and the barrier layer includes one or more monolayers of a two-dimensional material including a chalcogenide. According to the fourth aspect, the barrier is formed on the surface of the metal features by providing a metal precursor layer on the surface of the metal features and converting the metal precursor layer into one or more two-dimensional monolayers including a chalcogenide.

[0023] These and various other features and advantages will become apparent upon reading the following detailed description.

[0024] The present invention will be further described with reference to the accompanying drawings. In the drawings, like structures are represented by like numbers throughout several figures.

Brief Description of the Drawings

[0025] [Figure 1A-1H] FIG. schematically shows the steps of a method of the present invention for applying a barrier coating of the present invention on a patterned metal feature. [Figure 2A-2H] FIG. schematically shows the steps of an alternative method of the present invention for applying a barrier coating of the present invention on a patterned metal feature. [Figure 3A-3D] FIG. schematically shows the steps of a method of the present invention for applying a barrier layer of the present invention as a cap on a patterned metal feature. [Figure 4A-4D] FIG. schematically shows the steps of an alternative method of the present invention for applying a barrier layer of the present invention as a cap on a patterned metal feature. [Figure 5] FIG. is a flowchart schematically showing a method of integrating the principle of the present invention into a metallization strategy. [Figures 6A-6F] FIG. schematically shows the steps of a method of the present invention for forming a barrier layer between a patterned dielectric material and metal features in a damascene process. [Figure 7] This flowchart schematically illustrates a method for integrating the principles of the present invention into a damascene metallization strategy. [Modes for carrying out the invention]

[0026] The present invention will now be further described with reference to the following exemplary embodiments. The embodiments of the present invention described below are not intended to be exhaustive, nor are they intended to limit the invention to the exact forms disclosed in the following detailed description. Rather, the purpose of the selected and described embodiments is to make the principles and practices of the present invention readily understandable to those skilled in the art.

[0027] According to exemplary embodiments of the present invention, Figures 1A to 1H schematically illustrate, in cross-sectional views, a method for forming an ultrathin barrier in the metallization of a semiconductor device. Each figure shows the device as a workpiece in the manufacturing stage for achieving metallization. Preferably, the barrier comprises at least one chalcogenide comprising one or more of S, Se, and / or Te. Preferably, the chalcogenide is a metallic chalcogenide comprising one or more of S, Se, and / or Te. More preferably, the chalcogenide is a metallic dichalcogenide comprising one or more of S, Se, and / or Te. In exemplary embodiments, the chalcogenide is a semiconductor.

[0028] The methods shown in Figures 1A to 1H describe forming such chalcogenide barriers as barrier layers for raised metal features in semiconductor devices, preferably in a form comprising one or more monolayers of 2D chalcogenide material. Advantageously, the presence of a barrier layer, particularly in a preferred embodiment comprising one or more monolayers of 2D material, can reduce inelastic surface scattering and can replace conventional metal and metal nitride barrier and liner layers.

[0029] As is known in the field of microelectronics, 2D materials are materials having a monolayer structure, preferably a monolayer structure in which atoms in the monolayer are held together by relatively strong in-plane covalent bonds. When stacks of such 2D monolayers are used, the in-plane interlayer bonds tend to be stronger than the relatively weaker out-of-plane interlayer bonds. Out-of-plane bonds between monolayers are thought to include van der Waals bonds to help bond one monolayer to an adjacent monolayer (if any). See, for example, U.S. Patent No. 11,688,605; U.S. Patent Application Publication No. 2021 / 0376134. When a stack of 2D monolayers is formed, one or more individual monolayers in the stack of monolayers can be easily removed, for example, by breaking van der Waals bonds, if present, because the interlayer bonds are relatively weak.

[0030] According to the teachings of the present invention, 2D monolayers containing chalcogenides (e.g., semiconductors in some embodiments) are ultrathin, yet can provide excellent barrier properties for metallization when used alone or in stacks of monolayers. A single sheet (layer) of 2D material may be only a few angstroms thick, yet can still adequately provide a good diffusion energy barrier to metals and metal ions, such as Cu. 2D materials can also reduce the effects of surface scattering in electron transport, which can lower electrical resistivity.

[0031] Due to their ultrathin nature, such barriers occupy a relatively small volume. This is advantageous as it leaves more space to provide the metallic features protected by the barrier. The ability of ultrathin materials to form effective barriers is particularly advantageous at smaller nodes where space for features is limited. 2D, transition metal dichalcogenide (TMD) based materials are generally conductive or semiconducting. Furthermore, 2D monolayer materials containing at least one transition metal dichalcogenide tend to have relatively high diffusion energies, making it difficult for other elements to interact with such 2D monolayers.

[0032] While various embodiments described herein discuss the presence of 2D monolayers or laminated layers thereof, it should be understood that the barrier materials of the present invention may also contain only partially 2D material. However, more preferably, the barrier materials of the present invention are as close as possible to a complete 2D monolayer base in order to help achieve more optimal performance.

[0033] Figures 1A–1H schematically illustrate a method for forming a single 2D monolayer as a barrier layer 120. In some embodiments, if a barrier layer 120 comprising a stack of two or more such 2D monolayers is desired, the steps in Figures 1C and 1D are repeated for each desired additional monolayer. This method may be advantageous for providing multiple monolayers of the same or different 2D composition. In some embodiments, if a barrier layer 120 comprising a stack of two or more such 2D monolayers is desired, a thicker precursor layer can be formed in step 1C, and the process proceeds to step 1D to provide a stack of two or more monolayers. For example, the steps in Figures 1C and 1D may be carried out in an effective manner to provide at least one monolayer or at least two or more monolayers, e.g., 2–35 monolayers, or 2–20 monolayers, or 2–10 monolayers, or 2–8 monolayers.

[0034] A surplus number of monolayers can be formed, and then one or more of these surplus monolayers can be removed to achieve the desired final form and thickness. This enables the formation of a highly uniform barrier layer 120 with exactly the same thickness within and across the device, which further provides highly uniform device performance. The relatively weak bonds connecting the 2D monolayers to each other, compared to the much stronger bonds within each 2D monolayer, allow for the precise removal of entire 2D monolayers.

[0035] Figure 1A schematically illustrates the steps of providing a semiconductor device 100 under manufacture (a portion of the semiconductor device 100 is shown). The partially manufactured device 100 includes a film structure containing a metal layer 112 on a substrate 110. The substrate 110 can be any device in progress during the manufacturing stage, including metallization. For example, the substrate 110 may include various parts and components, including contacts, transistors, capacitors, interconnects, other circuit configurations, or parts thereof.

[0036] The metal layer 112 may contain one or more conductive metals suitable for forming metal features such as contacts and interconnects in semiconductor devices. The metals may contain one or more transition metals. For example, the metal layer 112 may contain one or more of the following metals: copper (Cu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), tungsten (W), nickel (Ni), hafnium (Hf), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), manganese (Mn), cobalt (Co), nickel (Ni), zinc (Zn), yttrium (Y), zirconium (Zr), niobium (Nb), technetium (Tc), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), or combinations thereof. Alloys of such metals may also be used. For example, the metal layer 112 may contain NiAl alloys and / or CuAl alloys. In a preferred embodiment, the metal layer 112 comprises one or more of the following metals: copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), molybdenum (Mo), tungsten (W), nickel (Ni), rhodium (Rh), iridium (Ir), or alloys thereof, or combinations thereof.

[0037] As schematically shown in Figure 1B, the method further includes patterning a metal layer 112 to form raised metal features 114 on a substrate 110 to provide a workpiece structure 101. As schematically shown, the metal features 114 are patterned to include voids 116, which extend through the metal layer 112 to the substrate 110, exposing the substrate surface 111. However, some voids 116 may only partially extend through the metal layer 112 (not shown).

[0038] The patterning technique used to form structure 101 may include the steps of forming a photoresist layer on a metal layer 112, forming a mask layer by patterning the photoresist layer using a lithography technique, forming a patterned metal feature 114 on a substrate 110 using the resulting mask layer and a removal technique such as metal etching, and then removing the mask material (not shown). The resulting raised metal feature 114 includes a top surface 115 and side walls 117.

[0039] As schematically shown in Figure 1C, the method further includes the step of selectively forming a metal precursor layer 118 on the exposed surface of the metal feature 114, thereby converting structure 101 to 102. The metal precursor layer 118 may be selectively provided on the metal feature 114 with respect to the exposed surface 111 of the underlying substrate 110.

[0040] Therefore, instead of directly forming the barrier layer 120 in Figure 1D on the metal feature 114, the method of the present invention proceeds via a metal precursor layer 118 in Figure 1C as an intermediate, which is then converted into the desired barrier layer 120. By using the method that proceeds via the metal precursor layer 118 as an intermediate, the 2D monolayer is formed more easily and with greater uniformity, control, and precision compared to methods that attempt to form the barrier more directly by surface modifying the metal feature 114 itself, or by direct deposition of the 2D structure onto the metal feature 114. Another advantage is that the practice of the present invention avoids excessive consumption of the metal feature 114, which further avoids an excessive increase in the resistivity of the metal wire.

[0041] A further advantage is the increased flexibility of the choices for providing 2D materials. For example, the practice of the present invention may enable 2D dichalcogenides such as MoS2 on a Ru metal wire; or a stack of MoS2 / WS2 on a Ru metal wire; or TaS2 on the side and HfS2 on a Ru metal wire. As alternatives to Mo, W, Ta, and Hf used in these examples, any other metals listed herein, in particular transition metals, can be used for the chalcogenides. Furthermore, instead of just S used in the dichalcogenides of these examples, the dichalcogenides may include Se or Te, or a combination of S, Se, and / or Te. As an alternative to Ru used in the metal wires of this example, any other metals listed herein may be used in place of Ru or in combination with Ru.

[0042] Using various selective deposition techniques, a metal precursor layer 118 can be selectively grown on metal features 114 on the exposed surface 111 of the substrate 110. This has the advantage that a mask or other protection is not required to protect the exposed surface of the substrate 110. For example, the metal precursor layer 118 can be deposited using any appropriately selective process, such as gas exposure of a metal-containing precursor in chemical vapor deposition (CVD) or atomic layer deposition (ALD), certain types of physical vapor deposition (PVD) (including angled PVD), the use of inhibitor molecules, or the use of selective etching. Using such processes, the selective formation of the metal precursor layer 118 is achieved, at least in part, by a delayed or substantially slower rate of metal deposition on the exposed substrate surface 111 and a faster rate of deposition of the metal precursor layer 118 on the raised metal features 114.

[0043] Continuing to refer to Figure 1C, the metal precursor layer 118 may have a metallic composition containing one or more metals. In some examples, the metals may include one or more transition metals. For example, the metal precursor layer 118 may contain one or more of the following metals: copper (Cu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), tungsten (W), nickel (Ni), hafnium (Hf), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), manganese (Mn), cobalt (Co), nickel (Ni), zinc (Zn), yttrium (Y), zirconium (Zr), niobium (Nb), technetium (Tc), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), or combinations thereof. Alloys of such metals may also be used. For example, the metal precursor layer 118 may contain NiAl alloys and / or CuAl alloys. In some embodiments, the metal precursor layer 118 includes aluminum (Al), ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), cobalt (Co), tantalum (Ta), titanium (Ti), hafnium (Hf), or mixtures, alloys, combinations, or laminates thereof. In some embodiments, the metal precursor layer 118 includes W, Mo, or Ta, or combinations thereof. In another example, the metal precursor layer 118 includes any suitable transition metal.

[0044] The metal precursor layer 118 may have the same or a different metal composition as the metal feature 114. Even if the metal composition is the same, the use of the metal precursor layer 118, and the interface between the metal precursor layer 118 and the underlying metal feature 114, helps enable a more controlled conversion of the metal precursor layer 118 to a barrier layer having a 2D monolayer structure containing one or more monolayers of 2D material. In the case of the same metal composition (or even if the composition is different), the metal precursor layer 118 may have a different degree of crystallinity than the metal feature 114. The difference in crystallinity may help control the reaction between the metal precursor layer 118 and one or more reaction gases (described below with respect to Figure 1D) so that the 2D material is formed at least substantially solely from the reaction of the metal precursor layer 118 and not excessively from the reaction of the underlying metal feature 114. Thus, the raised metal feature 114 is less likely to be disturbed and / or have its width / height reduced by the reaction described with respect to Figure 1D. Alternatively, the metal precursor layer 118 may have the same or similar degree of crystallinity as the metal feature 114.

[0045] In other implementations, the metallic composition of the metal precursor layer 118 differs from that of the metallic feature 114. This compositional difference, optionally combined with crystalline differences between the metallic feature 114 and the metal precursor layer 118, is another way to help control the formation of the 2D monolayer material. The reaction between the metal precursor layer 118 and the reaction gas (described below with respect to Figure 1D) can be tuned so that the 2D material is formed at least substantially solely from the reaction of the metal precursor layer 118 and not from the reaction of the underlying metallic feature 114. Thus, the raised metallic feature 114 is less likely to be disturbed or have its width / height reduced.

[0046] Therefore, the use of a precursor strategy helps to protect the valuable volume of the metal feature 114, avoiding excessive conversion of the metal feature to chalcogenides and the resulting excessive loss of conductive metal. Avoiding such losses means that the electrical performance of the resulting device is better protected than with other methods that do not use a precursor strategy.

[0047] Furthermore, when different compositions are used, one or more metals in the metal precursor layer 118 are converted to (e.g., semiconductor) chalcogenide materials, as described below. Therefore, the metal composition of the metal precursor layer 118 can be customized and selected to provide chalcogenides with desired barrier and electrical properties. When barrier formation is attempted by direct chalcogenization of the metal feature itself, the resulting chalcogenides are limited to only the chalcogenides of the metals present in the metal feature, and there are no beneficial interfaces to control barrier formation. As discussed herein, direct chalcogenization (without a precursor step) can also excessively consume a portion of the metal feature 114, which can excessively increase the overall resistivity of the metal feature 114.

[0048] The metal precursor layer 118 preferably has a thickness suitable for conversion to the ultrathin barrier layer 120 shown in Figure 1D, particularly conversion to a chalcogenide monolayer having a 2D structure. In some examples, the thickness of the metal precursor layer 118 may be in the range of about 1 nm to about 10 nm, about 1 nm to about 5 nm, or about 1 nm to about 2 nm. A thinner layer is more preferable for forming a barrier layer having a 2D monolayer structure.

[0049] As schematically shown in Figure 1D, the method further includes a step of converting the metal precursor layer 118 of structure 102 (Figure 1C) to structure 103 of Figure 1D, which has a barrier layer 120 comprising at least one metal chalcogenide, preferably a transition metal dichalcogenide. Advantageously, the 2D monolayer may tend to have a relatively high diffusion energy, providing barrier properties because other materials are less likely to interact with the 2D metal chalcogenide monolayer. The step sequence carrying out the method step in Figure 1C, and the subsequent method step in Figure 1D, illustrates a one-step conversion of the metal precursor layer 118 to the barrier layer 120. Figures 2A–2H, described below, describe a two-step conversion of the metal precursor layer 118 to a desired barrier material. The first step of the conversion can alter the surface energy of the metal precursor layer 118, which may further help provide faster and / or higher density formation of the 2D material in the second step of the conversion.

[0050] Generally, the method steps in Figure 1D preferably involve chalcogenizing one or more metals in the metal precursor layer 118 to form one or more chalcogenides, in a manner that is effective for forming one or more monolayers of a 2D chalcogenide material. Exemplary chalcogenization and transformation preferably form dichalcogenides having a 2D monolayer structure. Although not desired to be constrained, it is thought that any metal in such a monolayer can bond to two chalcogens to form, for example, transition metal dichalcogenides (TMDs), etc.

[0051] In practice of the present invention, the chalcogenide is a sulfide, selenide, and / or telluride of one or more metals in the metal precursor layer 118. In some embodiments, the resulting chalcogenide material, preferably the 2D material, comprises one or more dichalkogenides of formula MX2, where M is a metal and X is one or more of S, Se, and / or Te. For example, when M is selected from one or more of aluminum (Al), ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), cobalt (Co), tantalum (Ta), titanium (Ti), and hafnium (Hf), the corresponding sulfur, selenium, and tellurid dichalkogenides are aluminum disulfide, aluminum diselenium, aluminum ditelluride, ruthenium disulfide, ruthenium diselenium, and nitryl This material includes ruthenium disulfide, molybdenum disulfide, molybdenum diselenide, molybdenum ditelluride, tungsten disulfide, tungsten diselenide, tungsten ditelluride, copper disulfide, copper diselenide, copper ditelluride, cobalt disulfide, cobalt diselenide, cobalt ditelluride, tantalum disulfide, tantalum diselenide, tantalum ditelluride, titanium disulfide, titanium diselenide, titanium ditelluride, hafnium disulfide, hafnium diselenide, and hafnium ditelluride.

[0052] The reaction to convert the metal precursor layer 118 to the barrier layer 120 generally involves reacting the metal precursor layer 118 with at least one chalcogen-containing reactant (e.g., gas or plasma) under conditions that are effective in forming a chalcogenide product having a 2D monolayer structure. The reactant may include elemental forms of S, Se, and / or Te, and / or gas or plasma compounds of S, Se, and / or Te. An example compound is of formula R2-X mAlternatively, the compound comprises R-XH, where each R is independently an organic substituent such as an alkyl moiety containing 1 to 5, preferably 1 to 3, more preferably 1 to 2 carbon atoms, m is 1 or 2, and each X is independently S, Se, and / or Te. For example, exemplary gaseous compounds of sulfur include one or more of H2S, SO2, (CH3)2S, (CH3)2S2, (CH3CH2)2S, or (CH3CH2)2S2, CH3SH, and / or CH3CH2SH. In addition to the reactants, the reaction environment may further contain other gases or plasma materials such as diluent gases, reducing gases, oxidizing gases (described below), nitriding gases (described below), or combinations thereof.

[0053] Oxidizing, reducing, or nitriding gases may not be present simultaneously with any chalcogen used to form the barrier layer 120. The oxidizing, reducing, or nitriding gases are preferably used for pretreatment or surface modification before chalcogenization. Such optional surface treatments can beneficially reduce the energy of formation. This makes it possible to provide different types of barrier compositions on different surfaces of the metallization. This allows for selective surface modification, for example, pretreatment of only the sidewalls, trench bottoms, or top surfaces of the precursor layer 118, and then proceeding to chalcogenization of the selectively pretreated regions to form a 2D monolayer.

[0054] This reaction may consume the entire metal precursor layer 118, or only a portion of its thickness. Consuming only a portion of the metal precursor layer 118 is advantageous as it helps to avoid excessive conversion, and therefore loss, of the underlying metal features 114.

[0055] The reaction between the reactant material and the metal precursor layer 118 may be self-limiting and may halt when a single layer of the 2D material is formed, or when a stack of two or more 2D single layers is formed, if the metal precursor layer 118 is sufficiently thick. If the precursor layer 118 is sufficiently thick, a stack containing two or more single layers may be formed. During the formation of 2D single layers of the barrier layer 120, the thickness of the precursor layer 118 may affect single-layer formation, including the number of single layers formed from the chalcogenidization of the precursor layer 118. In addition, process adjustments and / or controls can be used to control the transformation of the precursor layer 118 and the resulting 2D single-layer formation of the barrier layer 120. Alternatively, the progress of the reaction may be monitored and controlledly stopped when a desired transformation is achieved. For example, such chalcogenidization may be stopped when a desired number or thickness of 2D single layers are formed on the underlying metal feature 114. In self-limiting or controlled reaction strategies, the use of the metal precursor layer 118 enhances the ability to restrict the reaction to the metal precursor layer 118 and protect the underlying metal features 114.

[0056] In an exemplary reaction strategy, 2D formation is achieved by reacting a metal precursor layer 118 with one or more chalcogen-containing gas reactants using a relatively low-temperature plasma process, during which the reaction gas is excited in the gas phase and then reacts with the precursor metal layer 118 in the excited state. Possible excitation methods include plasma excitation, ultraviolet (UV) excitation, electron beam (e-beam) excitation, ion beam excitation, and high-temperature filament excitation, in which the reaction gas is flowed near a high-temperature filament. Examples of possible plasma sources include microwave sources, VHF plasma sources, inductively coupled plasma (ICP) sources, or capacitively coupled plasma (CCP) sources in the processing chamber of a plasma processing system. According to other embodiments, plasma excitation of the reaction gas may be omitted.

[0057] A wide range of reaction temperatures is suitable for carrying out the chalcogenidization step in Figure 1D in an effective manner for forming chalcogenide materials, including those having a 2D monolayer structure. In some embodiments, the reaction temperature may be in the range of about 100°C to about 800°C. In some embodiments, the reaction temperature is in the range of 400°C to 800°C. In other embodiments, the reaction temperature is in the range of 200°C to 400°C. In some embodiments, the reaction temperature is in the range of 100°C to 200°C. In some embodiments, the reaction temperature is 100°C or even less.

[0058] In one example, multiple 2D material layers may be formed by a single set of steps in Figures 1C and 1D, or by repeating the steps in Figures 1C and 1D, thereby providing a stack of 2D monolayers. When such a stack is formed, the steps in Figure 1D may further include a method for removing one or more monolayers of the 2D material, for example by using an etch-back process, until the desired thickness of the remaining 2D material is achieved. The desired thickness may include, for example, one, two, three, or more monolayers of the 2D material, e.g., up to eight monolayers, up to ten monolayers, up to twenty monolayers, or even up to 35 or more monolayers. By forming excess monolayers and then removing some, it becomes possible to form barrier layers 120 with a precise number of monolayers, and therefore thickness, on a single metal feature, across multiple metal features within the same device, and across multiple devices, resulting in very uniform performance across the entire family of devices.

[0059] The appropriate thickness of the barrier layer 120 may be in the range of approximately 3 angstroms to approximately 10 nm (100 angstroms), or approximately 3 angstroms to approximately 5 nm, or approximately 3 angstroms to approximately 2 nm, or approximately 3 angstroms to approximately 1 nm. When formed from one or more 2D monolayers, the resulting barrier layer 120 preferably has a thickness equivalent to one monolayer or a stack of two or more 2D monolayers. For example, the barrier layer 120 may consist of at least one monolayer, and up to several monolayers, to avoid excessively restricting the width and / or height of the underlying metal feature 114. In some examples, a stack of 2D monolayers may end up containing 1 to 35 monolayers, 1 to 20 monolayers, 1 to 10 monolayers, 1 to 5 monolayers, 1 to 3 monolayers, 1 to 2 monolayers, or even just one monolayer.

[0060] In addition to protection against inelastic scattering and diffusion, the resulting 2D barrier layer 120 offers many other advantages with respect to metallization. For example, such 2D monolayer materials may have inherent flexibility and lack excessive dangling bonds. Furthermore, they are only weakly bonded in the vertical direction by van der Waals bonds, making selective removal of layers practical (see Figure 2E below). This makes it possible to remove individual monolayers from a stack of monolayers to achieve a final barrier layer 120 with a precise number of monolayers having a highly uniform, precisely controlled thickness within a single feature, across multiple features in a device, and across multiple devices.

[0061] Once the structure 103 in Figure 1D is formed, the barrier layer 120 can be evaluated to determine the properties of the 2D monolayer structure. Various techniques can be used to evaluate the properties of the 2D monolayer structure. The 2D monolayer structure is associated with unique optical emission and other spectroscopic properties. Therefore, spectroscopic techniques can determine or confirm the presence of 2D monolayers, the number of monolayers, the composition of the monolayers, the thickness of the monolayers, etc., individually or collectively.

[0062] For example, atomic force microscopy (AFM), scanning tunneling microscopy (STM), and transmission electron microscopy (TEM) can reveal structural properties such as surface roughness, height, defects, and lattice structure of 2D-TMDs at atomic resolution. Kim, Youngbum and Kim, Jeongyong. “Near-field optical imaging and spectroscopy of 2D-TMDs” Nanophotonics, vol. 10, no. 13, 2021, pp. 3397-3415, https: / / doi.org / 10.1515 / nanoph-2021-0383; H. Li, G. Lu, Z. Yin, et al.., “Optical identification of ACS See Appl.Mater.Interfaces, vol.7, pp.11921-11929, 2015. https: / / doi.org / 10.1021 / acsami.5b01778; and L.Fei, S.Lei, and W.-B.Zhang, “Direct TEM observations of growth mechanisms of two-dimensional MoS2 flakes,” Nat.Commun., vol.7, p.12206, 2016. https: / / doi.org / 10.1038 / ncomms12206. In addition, techniques such as near-field scanning microscopy (NSOM), tip-enhanced photovoltaic lamination (TEPL), and Raman spectroscopy (TERS) are used to obtain nanoscale optical images of 2D-TMDs.Y. Lee, S. Park, H. Kim, et al..,“Characterization of the structural defects in CVD-grown monolayered MoS2 using near-field photoluminescence imaging,” Nanoscale, vol. 7, pp. 11909-11914, 2015. https: / / doi.org / 10.1039 / c5nr02897c; resonance Raman scattering,” ACS Nano, vol. 12, pp. 9982-9990, 2018, https: / / doi.org / 10.1021 / acsnano.8b04265; nano-optical antenna-tip Purcell effect,”Nat.Nanotechnol.,vol.13,pp.59–64,2018.

[0063] As schematically shown in Figure 1E, the method optionally further includes the step of depositing a blanket dielectric layer 124 on the structure 103 in Figure 1D, thereby providing the structure 104. The dielectric layer 124 is formed filling the voids 116 in Figure 1D, preferably having an excess portion 125. The excess portion 125 is shown as the dielectric material of the dielectric layer 124 above the feature height line 122. Thus, the barrier-protected metal feature 114 is embedded within the blanket dielectric layer 124 in this step. Although not illustrated, it is also conceivable to utilize voids instead of the dielectric layer 124 and at least some of the associated steps. In various embodiments, utilizing a void substitute may involve partially filling the voids 116 with the dielectric layer 124, and non-conformal deposition (e.g., sputter deposition) forms keyholes (voids) between adjacent metal features 114. Since air has a relative permittivity of 1, which is much lower than that of low-k materials, the presence of voids reduces the relative permittivity of the filler.

[0064] As schematically shown in Figure 1F, following the steps in Figure 1E, optionally a method step is performed which includes removing excess material 125 from structure 104 to feature height line 122 to expose at least a portion of the top of the barrier-protected metal feature 114. This provides structure 105 having a reduced dielectric layer 127. In one example, this step includes performing planarization, etching, and / or other reduction processes 128 to remove the dielectric excess material 125 and leave the reduced dielectric layer 127. Selective etching can be performed which strongly prioritizes the removal of dielectric material over the chalcogenide material of the barrier layer 120. Thus, the barrier layer 120 and the barrier-protected metal feature 114 are less likely to be disturbed or their thickness excessively reduced.

[0065] Figures 1E and 1F show a two-step sequence for converting structure 103 in Figure 1D to structure 105 in Figure 1F, which includes a dielectric material 124. Figure 1G schematically shows an alternative scheme for achieving the conversion of structure 103 in Figure 1D to structure 106 in Figure 1G, as an alternative to the steps in Figures 1E and 1F.

[0066] As schematically shown in Figure 1G, after the method steps schematically shown in Figure 1D, the method optionally further includes depositing dielectric material 127 in a bottom-up deposition 130 to fill the void 116 (Figure 1D), thereby forming structure 106. Bottom-up deposition 130 can be practiced using a strategy of depositing dielectric material 127 by delayed or relatively slow dielectric deposition on the 2D material of the barrier layer 120 and by a faster rate of dielectric deposition on the exposed surface 111 of the substrate 110, and selectively on the dielectric material 127 to be deposited, as the thickness of dielectric material 127 is built between the barrier-protected metal features 114. Bottom-up dielectric deposition 130 may be carried out until the void 116 is filled to a desired extent, such as when the dielectric material 127 is completely filled up to the feature height line 122.

[0067] After completing the steps shown in Figures 1E-1F or optionally Figure 1G, the resulting structure 105 or 106 may optionally undergo further processing, fabrication steps, or other treatment as desired (such as proceeding to further fabrication steps). Figure 1H shows an example of an optional further fabrication step relating to converting structure 105 of Figure 1F to structure 107 of Figure 1H. Structure 107 shows the result of the additional selective deposition of one or more features made of another material 121 (e.g., dielectric material) which is carried out on the exposed surface of the dielectric layer 127 and preferably substantially not on the portion of the barrier layer 120 associated with the metal feature 114. The deposition of material 121 may be guided, prevented, or delayed on the barrier 120, at least in part due to differences in the properties of the barrier layer 120 compared to the dielectric layer 127.

[0068] The additional material 121 helps selectively deposit a layer on the underlying dielectric material, using a 2D material for suppression. For example, selective deposition of dielectric material on the underlying dielectric material may be used to guide upper metallization and help form features such as self-aligned vias. For example, feature 121 may be a layer selectively deposited on the dielectric layer 127 relative to the barrier layer 120, using a 2D barrier layer 120 as a deposition boundary and for suppression. Selectively providing dielectric material 121 on the underlying dielectric layer 127 may be used to guide various upper metallization steps, such as performing a so-called "perfectly self-aligned via" step.

[0069] According to an alternative embodiment of the present invention, Figures 2A–2H schematically illustrate, in cross-sectional views, a method for forming an ultrathin chalcogenide barrier in the metallization of a semiconductor device. Each figure shows the device as a workpiece in the manufacturing stage for achieving metallization. The methods of Figures 2A–2H describe forming such a chalcogenide barrier as a barrier layer for raised metallic features in a semiconductor device, preferably in a form comprising one or more monolayers of 2D chalcogenide material. Advantageously, the presence of a barrier layer, particularly in a preferred embodiment comprising one or more monolayers of 2D material, can reduce inelastic surface scattering and can replace conventional metal and metal nitride barriers and liner layers.

[0070] The methods shown in Figures 2A-2H are similar to those in Figures 1A-1H, but instead of a one-step transformation, they use the two-step transformation strategy shown in Figures 2D and 2E to transform the precursor layer 118 in Figure 2C into the desired barrier layer 220 in Figure 2E.

[0071] Figures 2A, 2B, and 2C schematically illustrate the same method steps as those shown in Figures 1A, 1B, and 1C, respectively. The above statements applicable to Figures 1A, 1B, and 1C also apply to Figures 2A, 2B, and 2C, respectively.

[0072] Figure 2D schematically illustrates the steps of converting structure 102 in Figure 2C to structure 203 in Figure 2D. The conversion includes modifying the surface of at least the metal precursor layer 118 to provide a modified metal precursor layer 219 as an intermediate reaction product. The result of the modification shown in Figure 2D is the provision of structure 203 including the modified precursor layer 219. Surface modification can advantageously change the surface energy of the modified metal precursor layer 119 relative to the metal precursor layer 118, which can further provide faster and / or higher density formation of the 2D material from the modified metal precursor layer 219 in the subsequent conversion step.

[0073] Such modification to provide a modified metal precursor layer 219 may include reducing, oxidizing, or nitriding the surface of at least the metal precursor layer 118. This modification tends to convert at least a portion of the metal in the metal precursor layer 118 into oxides and / or nitrides. This can be achieved by exposing the metal precursor layer 118 to a reducing gas, an oxygen-containing gas, a nitrogen-containing gas, or both an oxygen-containing gas and a nitrogen-containing gas under conditions effective in forming oxide modification and / or nitride modification, or other desired modification.

[0074] As schematically shown in Figure 2E, the method further includes a step of converting structure 203 to structure 204. This includes converting the modified metal precursor layer 219 to a barrier layer 220 containing at least one chalcogenide. The method step in Figure 2E is carried out in the same manner as described above with respect to the conversion step in relation to Figure 1D, and all the descriptions and features of the step in Figure 1D also apply to Figure 2E, except that the modified metal precursor layer 219 is converted to the barrier layer 220 instead of the metal precursor layer 118 being converted to the barrier layer 120.

[0075] Generally, the method step in Figure 2E includes chalcogenizing one or more metals in the modified metal precursor layer 219 to form a barrier layer 220 containing one or more chalcogenides. Preferably, this conversion is carried out in a manner effective in forming a monolayer of 2D chalcogenide material as a component of the barrier layer 220. The chalcogenides are sulfides, selenides, and / or tellurides of one or more metals in the modified metal precursor layer 219. In some embodiments, the resulting chalcogenide material, preferably 2D material, comprises one or more dichalkogenides of formula MX2, where M is a metal and X is one or more of S, Se, and / or Te. For example, if M is selected from one or more of the following metals: aluminum (Al), ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), cobalt (Co), tantalum (Ta), titanium (Ti), and hafnium (Hf), then the corresponding sulfur, selenium, and telluridicalcogenides are aluminum disulfide, aluminum diselenide, aluminum ditelluride, ruthenium disulfide, ruthenium diselenide, and ditelluride. This material includes ruthenium disulfide, molybdenum disulfide, molybdenum diselenide, molybdenum ditelluride, tungsten disulfide, tungsten diselenide, tungsten ditelluride, copper disulfide, copper diselenide, copper ditelluride, cobalt disulfide, cobalt diselenide, cobalt ditelluride, tantalum disulfide, tantalum diselenide, tantalum ditelluride, titanium disulfide, titanium diselenide, titanium ditelluride, hafnium disulfide, hafnium diselenide, and hafnium ditelluride.

[0076] The reaction to convert the modified metal precursor layer 219 into the barrier layer 220 generally involves reacting the modified metal precursor layer 219 with at least one chalcogen-containing reactant (e.g., gas or plasma) under conditions effective in forming a chalcogenide product having a 2D monolayer structure. The reactant may include elemental forms of S, Se, and / or Te, and / or compounds of S, Se, and / or Te. An example gaseous compound is of formula R m -X qThe compound comprises R'-XH, where each R and R' is an organic substituent such as H or an alkyl moiety containing 1 to 3, preferably 1 to 2, carbon atoms, m is 1 or 2, n is 1 or 2, and each X is independently S, Se, and / or Te. For example, the sulfur gaseous compound includes one or more of H2S, SO2, (CH3)2S, (CH3)2S2, (CH3CH2)2S, or (CH3CH2)2S2, CH3SH, and / or CH3CH2SH. In addition to the reactants, the reaction environment may further contain additional gases or plasma materials such as diluent gases, reducing gases, oxidizing gases (described below), nitriding gases (described below), or combinations thereof. Oxidation, nitriding, and reduction are preferably carried out as pretreatments before chalcogenidation.

[0077] The reaction may consume the entire modified metal precursor layer 219, or only a portion of the thickness of the modified metal precursor layer 219. Consuming only a portion of the modified metal precursor layer 219 is advantageous as it helps to avoid excessive conversion, and therefore loss, of the underlying metal features 114.

[0078] The reaction between the reaction gas and the modified metal precursor layer 219 may be self-limiting, and the reaction may halt when a single layer of 2D material is formed, or when a stack of two or more 2D single layers is formed if the metal precursor layer 219 is sufficiently thick. Alternatively, the reaction may be monitored and controlled to halt when the desired transformation is achieved. For example, such chalcogenidization may halt when a desired number or thickness of 2D single layers are formed on the underlying metal feature 114. Self-limiting or controlled reaction strategies enhance the ability to limit the reaction to the modified metal precursor layer 219 and protect the underlying metal feature 114.

[0079] In an exemplary reaction strategy, 2D formation is achieved by reacting a metal precursor layer 118 with one or more chalcogen-containing gas reactants using a relatively low-temperature plasma process, during which the reaction gas is excited in the gas phase and then reacts with the modified metal precursor layer 219 in the excited state. Possible excitation methods include plasma excitation, UV excitation, electron beam (e-beam) excitation, ion beam excitation, and high-temperature filament excitation, in which the reaction gas is flowed near a high-temperature filament. Examples of possible plasma sources include microwave sources, VHF plasma sources, inductively coupled plasma (ICP) sources, or capacitively coupled plasma (CCP) sources in the processing chamber of a plasma processing system. According to other embodiments, plasma excitation of the reaction gas may be omitted.

[0080] A wide range of reaction temperatures is suitable for carrying out the chalcogenidization step in Figure 2E in an effective manner for forming chalcogenide materials containing a 2D monolayer structure. In some embodiments, the reaction temperature may be in the range of about 100°C to about 800°C. In some embodiments, the reaction temperature is in the range of 400°C to 800°C. In other embodiments, the reaction temperature is in the range of 200°C to 400°C. In some embodiments, the reaction temperature is in the range of 100°C to 200°C. In some embodiments, the reaction temperature is 100°C or even less.

[0081] In one example, multiple 2D material layers may be formed by a single set of steps in Figures 2C-2E, or by repeating the steps in Figures 2C-2E, thereby providing a stack of 2D monolayers. When such a stack is formed, the steps in Figure 2E may further include a method for removing one or more monolayers of the 2D material, for example by using an etch-back process, to remove one or more layers of the 2D material until the desired thickness of the remaining 2D material is achieved. The desired thickness may include, for example, one, two, three, or more monolayers of the 2D material, e.g., up to eight monolayers, up to ten monolayers, up to twenty monolayers, or even up to 35 or more monolayers. By forming excess monolayers and then removing some, it becomes possible to form barrier layers 120 with a precise number of monolayers, and therefore thickness, on a single metal feature, across multiple metal features within the same device, and across multiple devices, resulting in very uniform performance across the entire family of devices.

[0082] The appropriate thickness of the barrier layer 220 may be in the range of approximately 3 angstroms to approximately 10 nm (100 angstroms), or approximately 3 angstroms to approximately 5 nm, or approximately 3 angstroms to approximately 2 nm, or approximately 3 angstroms to approximately 1 nm. When formed from one or more 2D monolayers, the resulting barrier layer 220 preferably has a thickness equivalent to one monolayer or a stack of two or more 2D monolayers. For example, the barrier layer 220 may consist of at least one monolayer, and up to several monolayers, to avoid excessively restricting the width and / or height of the underlying metal feature 114. In some examples, a stack of 2D monolayers may end up containing 1 to 35 monolayers, 1 to 20 monolayers, 1 to 10 monolayers, 1 to 5 monolayers, 1 to 3 monolayers, 1 to 2 monolayers, or even just one monolayer.

[0083] In addition to protection against inelastic scattering and diffusion, the resulting 2D barrier layer 220 offers other advantages with respect to metallization. For example, such 2D monolayer materials possess inherent flexibility and do not have excessive dangling bonds. Furthermore, they are only weakly bonded in the vertical direction by van der Waals bonds, making selective removal of layers practical. This makes it possible to remove individual monolayers from a stack of monolayers to achieve a final barrier layer 220 with a precise number of monolayers having a very uniform, precisely controlled thickness within a single feature, across multiple features in a device, and across multiple devices.

[0084] As schematically shown in Figure 2F, the method optionally further includes the step of depositing a blanket dielectric layer 224 on the structure 204 of Figure 2E, thereby providing the structure 205 of Figure 2F. The dielectric layer 224 is formed to fill the void 116 of Figure 2E and preferably has an excess portion 225 above the feature height line 222. Thus, the barrier-protected metal feature 114 is embedded within the dielectric layer 224 in this step.

[0085] As schematically shown in Figure 2G, following the steps in Figure 2F, a method step is performed which includes removing the excess portion 225 from the structure 205 to the feature height line 222 to expose at least a portion of the top of the barrier-protected metal feature 114. This provides the structure 206. In one example, this step includes performing planarization, etching, and / or other reduction processes 228 to remove the excess portion 225. Selective etching can be performed which strongly prioritizes the removal of dielectric material over the chalcogenide material of the barrier layer 220. Thus, the barrier layer 220 and the barrier-protected metal feature 114 are less likely to be disturbed or their thickness excessively reduced.

[0086] Figures 2F and 2G show a two-step sequence for converting structure 204 in Figure 2E to structure 206 in Figure 2G, which includes the dielectric material 224. Figure 2H schematically shows an alternative scheme for achieving the conversion of structure 204 in Figure 2E to structure 207 in Figure 1G, as an alternative to the steps in Figures 2F and 2G.

[0087] As schematically shown in Figure 2H and after the method steps schematically shown in Figure 2E, the method further includes depositing dielectric material 227 in a bottom-up deposition 230 to fill voids 116 (Figure 2E) within the metal features 114, thereby forming a structure 207. The bottom-up deposition 230 can be practiced using a strategy of depositing the dielectric material 227 by delayed or relatively slow dielectric deposition on the 2D material of the barrier layer 220 and by faster rates of dielectric deposition on the exposed surface 111 (see Figure 2E) of the substrate 110 and selectively on the dielectric material 227 to be deposited, as the thickness of the dielectric material 227 is built up between the barrier-protected metal features 114. The bottom-up dielectric deposition 230 can be carried out until the voids 116 are filled to a desired extent, such as when the dielectric material 227 is completely filled up to the feature height line 222.

[0088] Following Figure 2G or optionally Figure 2H, the resulting structure 206 or 207 may, optionally, undergo further processing, fabrication steps, or other treatment as desired (such as proceeding to further fabrication steps). As an example, either structure 206 or 207 may be used in the method step of Figure 1H instead of structure 105 or 106 to form a feature 121 similar to that shown in structure 107 of Figure 1H.

[0089] According to exemplary embodiments of the present invention, Figures 3A to 3D schematically illustrate, in cross-sectional views, a method for forming an ultrathin (e.g., semiconductor) chalcogenide barrier in the form of a barrier preferably comprising at least one 2D material-based monolayer during the metallization of a semiconductor device in a manufacturing stage including metallization. Specifically, the method includes forming a capping layer during the metallization of a semiconductor device according to one embodiment of the present invention. Each figure shows the device as a workpiece in the manufacturing stage for realizing capped metallization.

[0090] Figure 3A schematically illustrates the steps of providing a semiconductor device 300 during the fabrication stage in which metallization is performed. The device 300 includes a metal feature 302 and a dielectric material 306 supported on a substrate 304. In some examples, the metal feature 302 includes contacts and interconnects. In this example, the structure 300 may be planarized so that the metal feature 302 and the dielectric material 306 are coplanar along the feature height line 322. In the context of Figure 3A, optionally, a barrier layer (not shown) may be interposed at the interface between the metal feature 302 and the dielectric material 306. The combination of the metal feature 302 and the dielectric material 306 may be formed on the substrate 302 using patterning and / or damascene techniques.

[0091] Figure 3B schematically illustrates a step that involves converting the structure 300 of Figure 3A to the structure 301 of Figure 3B. This step involves selectively forming a metal precursor cap 314 on the exposed surface of the metal feature 114 relative to the surface 310 of the dielectric material 306. By using a method that proceeds via the metal precursor cap 314 as an intermediate, the final barrier cap 316 (Figure 3C) containing one or more 2D monolayers can be formed more easily and with better control and precision compared to methods that attempt to directly surface modify the metal feature 302 itself, or by direct deposition of a 2D structure onto the metal feature 302.

[0092] Using various selective deposition techniques, a metal precursor layer 314 can be selectively grown on a metal feature 302 against an exposed surface 310 of the dielectric material 306. This has the advantage that a mask or other protection is not required to protect the exposed surface 310 of the dielectric material 306. For example, the metal precursor cap 314 can be deposited using any appropriately selective process, such as gas exposure of a metal-containing precursor in chemical vapor deposition (CVD) or atomic layer deposition (ALD), certain types of physical vapor deposition (PVD) (including angled PVD), the use of inhibitor molecules, or the use of selective etching. Using such processes, the selective formation of the metal precursor cap 314 is at least partially achieved by a delayed or substantially slower rate of metal deposition on the exposed dielectric surface 310 and a faster rate of deposition of the metal precursor cap 314 on the exposed surface of the metal feature 302.

[0093] The metal precursor cap 314 may have a metallic composition containing one or more metals. For example, the metal precursor cap 314 may contain one or more of the following metals: copper (Cu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), tungsten (W), nickel (Ni), hafnium (Hf), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), manganese (Mn), cobalt (Co), nickel (Ni), zinc (Zn), yttrium (Y), zirconium (Zr), niobium (Nb), technetium (Tc), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), or combinations thereof. Alloys of such metals may also be used. For example, the metal precursor cap 314 may include NiAl alloy and / or CuAl alloy. In some embodiments, the metal precursor cap 314 includes aluminum (Al), ruthenium (Ru) metal, molybdenum (Mo) metal, tungsten (W) metal, copper (Cu) metal, cobalt (Co) metal, tantalum (Ta) metal, titanium (Ti) metal, hafnium (Hf) metal, rhodium (Rh), indium (Ir), or mixtures, alloys, combinations, or laminates thereof. In some embodiments, the metal precursor cap 314 includes W, Mo, or Ta, or combinations thereof. In another example, the metal precursor cap 314 includes any transition metal.

[0094] The metal precursor cap 314 may have the same or a different metallic composition as the metal feature 302. Even if the metallic composition is the same, the presence of the metal precursor cap 314 and the interface between the metal precursor cap 314 and the underlying metal feature 302 allows for a more controlled conversion of the metal precursor cap 314 to a barrier cap 316 (Figure 3C) having a 2D monolayer structure containing one or more monolayers. In the case of the same metallic composition (or even if the compositions are different), the metal precursor cap 314 may have a different degree of crystallinity than the metal feature 302. The difference in crystallinity may help control the reaction between the metal precursor cap 314 and one or more reaction gases (described below with respect to Figure 3C) so that the 2D material is formed at least substantially solely from the reaction of the metal precursor cap 314 and not excessively from the reaction of the underlying metal feature 302. Thus, the metal feature 302 is less likely to be disturbed and / or have its width / height reduced by the reaction described with respect to Figure 3C. Alternatively, the metal precursor cap 314 may have the same or similar degree of crystallinity as the metal feature 302.

[0095] In other implementations, the metallic composition of the metal precursor cap 314 differs from that of the metallic feature 302. This compositional difference is another way to help control the formation of the 2D monolayer material. In this example, the reaction between the metal precursor cap 314 and the reaction gas (described below with respect to Figure 3C) can be tuned so that the 2D material is formed at least substantially solely from the reaction of the metal precursor cap 314 and not from the reaction of the underlying metallic feature 302. Thus, the metallic feature 302 is less likely to be disturbed or have its width / height reduced. Therefore, the use of a precursor strategy helps to protect the valuable volume of the metallic feature 302 and avoids excessive conversion of the metallic feature to chalcogenides and the resulting excessive loss of conductive metal. Avoiding such losses means that the electrical performance of the resulting device is better protected than in other methods that do not use a precursor strategy.

[0096] Furthermore, when different compositions are used, one or more metals in the metal precursor cap 314 are converted into chalcogenide material, as described below. Therefore, the metal composition of the metal precursor cap 314 can be customized and selected to provide a chalcogenide with the desired barrier and electrical properties. When barrier formation is attempted by direct chalcogenization of the metal feature itself, the resulting chalcogenide is limited to only the chalcogenides of the metals present in the metal feature, and there are no beneficial interfaces to control barrier formation.

[0097] The metal precursor cap 314 preferably has a thickness suitable for conversion to an ultrathin barrier layer, particularly to a chalcogenide monolayer having a 2D structure. In some examples, the thickness of the metal precursor cap 314 may be in the range of about 1 nm to about 10 nm, about 1 nm to about 5 nm, or about 1 nm to about 2 nm. A thinner layer is more preferable for forming a barrier layer having a 2D monolayer structure.

[0098] As schematically shown in Figure 3C, the method further includes a step of converting the metal precursor cap 314 of structure 301 (Figure 3B) to the barrier cap 316 of structure 303 (Figure 3C), the barrier cap 316 comprising at least one chalcogenide. The step sequence for carrying out the method step in Figure 3B and the subsequent method step in Figure 3C demonstrates a one-step conversion of the metal precursor cap 314 to the barrier cap 316.

[0099] Generally, the method steps in Figure 3C involve chalcogenizing one or more metals in the metal precursor cap 314 to form one or more chalcogenides, in a manner that is effective for forming a monolayer of the 2D chalcogenide material. In practice of the present invention, the chalcogenides are sulfides, selenides, and / or tellurides of one or more metals in the metal precursor cap 314. In some embodiments, the resulting chalcogenide material, preferably the 2D material, comprises one or more dichalkogenides of formula MX2, where M is a metal and X is one or more of S, Se, and / or Te. For example, if M is selected from one or more of the following metals: aluminum (Al), ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), cobalt (Co), tantalum (Ta), titanium (Ti), and hafnium (Hf), then the corresponding sulfur, selenium, and telluridicalcogenides are aluminum disulfide, aluminum diselenide, aluminum ditelluride, ruthenium disulfide, ruthenium diselenide, and ditelluride. This material includes ruthenium disulfide, molybdenum disulfide, molybdenum diselenide, molybdenum ditelluride, tungsten disulfide, tungsten diselenide, tungsten ditelluride, copper disulfide, copper diselenide, copper ditelluride, cobalt disulfide, cobalt diselenide, cobalt ditelluride, tantalum disulfide, tantalum diselenide, tantalum ditelluride, titanium disulfide, titanium diselenide, titanium ditelluride, hafnium disulfide, hafnium diselenide, and hafnium ditelluride.

[0100] The reaction to convert the metal precursor cap 314 to the barrier cap 316 generally involves reacting the metal precursor cap 314 with at least one chalcogen-containing reactant (e.g., gas or plasma) under conditions that are effective in forming a chalcogenide product having a 2D monolayer structure. The reaction gas may include elemental forms of S, Se, and / or Te, and / or gas or plasma compounds of S, Se, and / or Te. An example gas compound is of formula R m -X qThe compound comprises R'-XH, where each R and R' is an organic substituent such as H or an alkyl moiety containing 1 to 3, preferably 1 to 2, carbon atoms, m is 1 or 2, n is 1 or 2, and each X is independently S, Se, and / or Te. For example, exemplary gaseous compounds of sulfur include one or more of H2S, SO2, (CH3)2S, (CH3)2S2, (CH3CH2)2S, or (CH3CH2)2S2, CH3SH, and / or CH3CH2SH. In addition to the reactants, the reaction environment may further contain other gases or plasma materials such as diluent gases, reducing gases, oxidizing gases (described below), nitriding gases (described below), or combinations thereof.

[0101] This reaction may consume the entire metal precursor cap 314, or only a portion of its thickness. Consuming only a portion of the metal precursor cap 314 is advantageous as it helps to avoid excessive conversion, and therefore loss, of the underlying metal feature 302.

[0102] The reaction between the reactant material and the metal precursor cap 314 may be self-limiting, and the reaction may halt when a single layer of the 2D material is formed, or when a stack of two or more 2D single layers is formed if the metal precursor cap 314 is sufficiently thick. Alternatively, the reaction may be monitored and controlled to halt when the desired transformation is achieved. For example, such chalcogenidization may halt when a desired number or thickness of 2D single layers is formed on the underlying metal feature 302. In self-limiting or controlled reaction strategies, the use of the metal precursor cap 314 enhances the ability to limit the reaction to the metal precursor cap 314 and protect the underlying metal feature 302.

[0103] In an exemplary reaction strategy, 2D formation is achieved by reacting a metal precursor cap 314 with one or more chalcogen-containing gas reactants using a relatively low-temperature plasma process, during which the reaction gas is excited in the gas phase and then reacts with the precursor metal cap 314 in the excited state. Possible excitation methods include plasma excitation, UV excitation, electron beam (e-beam) excitation, ion beam excitation, and high-temperature filament excitation, in which the reaction gas is flowed near a high-temperature filament. Examples of possible plasma sources include microwave sources, VHF plasma sources, inductively coupled plasma (ICP) sources, or capacitively coupled plasma (CCP) sources in the processing chamber of a plasma processing system. According to other embodiments, plasma excitation of the reaction gas may be omitted.

[0104] A wide range of reaction temperatures is suitable for carrying out the chalcogenidization step in Figure 3C in an effective manner for forming chalcogenide materials, including those having a 2D monolayer structure. In some embodiments, the reaction temperature may be in the range of about 100°C to about 800°C. In some embodiments, the reaction temperature is in the range of 400°C to 800°C. In other embodiments, the reaction temperature is in the range of 200°C to 400°C. In some embodiments, the reaction temperature is in the range of 100°C to 200°C. In some embodiments, the reaction temperature is 100°C or even lower.

[0105] In one example, multiple 2D monolayers may be formed by a single set of steps in Figures 3B and 3C, or by repeating the steps in Figures 3B and 3C, thereby providing a stack of 2D monolayers. When such a stack is formed, the steps in Figure 3C may further include a method for removing one or more monolayers of the 2D material, for example by using an etch-back process, to remove one or more layers of the 2D material until the desired thickness of the remaining 2D material is achieved. The desired thickness may include, for example, one, two, three, or more monolayers of the 2D material, for example, up to eight monolayers, up to ten monolayers, up to twenty monolayers, or even up to 35 or more monolayers. By forming excess monolayers and then removing some, it becomes possible to form barrier layers 316 with a precise number of monolayers and therefore thickness on a single metal feature, across multiple metal features within the same device, and across multiple devices, resulting in very uniform performance across the entire family of devices.

[0106] The appropriate thickness of the barrier cap 316 may be in the range of approximately 3 angstroms to approximately 10 nm (100 angstroms), or approximately 3 angstroms to approximately 5 nm, or approximately 3 angstroms to approximately 2 nm, or approximately 3 angstroms to approximately 1 nm. When formed from one or more 2D monolayers, the resulting barrier cap 316 preferably has a thickness equivalent to one monolayer or a stack of two or more 2D monolayers. For example, the barrier cap 316 may consist of at least one monolayer, and up to several monolayers, to avoid excessively restricting the width and / or height of the underlying metal feature 302. In some examples, a stack of 2D monolayers may end up containing 1 to 35 monolayers, 1 to 20 monolayers, 1 to 10 monolayers, 1 to 5 monolayers, 1 to 3 monolayers, 1 to 2 monolayers, or even just one monolayer.

[0107] In addition to protection against inelastic scattering and diffusion, the resulting 2D barrier cap 316 offers other advantages with respect to metallization. For example, such 2D monolayer materials may possess inherent flexibility and lack excessive dangling bonds. Furthermore, they are only weakly bonded in the vertical direction by van der Waals bonds, making selective removal of layers practical. This makes it possible to remove individual monolayers from a stack of monolayers to obtain a final barrier cap 316 with a precise number of monolayers having a highly uniform, precisely controlled thickness within a single feature, across multiple features in a device, and across multiple devices.

[0108] After Figure 3C, the resulting structure 303 may, if applicable, undergo further processing, fabrication steps, or other treatment as desired (such as proceeding to further fabrication steps). Figure 3D shows an example of further fabrication steps relating to converting structure 303 of Figure 3C to structure 305 of Figure 3D. Structure 305 shows the additional selective deposition of another material 318 (e.g., dielectric material) which is carried out on the exposed surface of the dielectric material 306 and preferably not on the barrier cap 316. The deposition of material 318 may be prevented or delayed on the barrier cap 316 due to the difference in properties of the barrier cap 316 compared to the dielectric layer 306.

[0109] According to exemplary embodiments of the present invention, Figures 4A-4D schematically illustrate, in cross-sectional views, a method for forming an ultrathin chalcogenide barrier in the metallization of a semiconductor device, preferably in the form of a barrier comprising at least one 2D monolayer. Specifically, the method includes forming a capping layer in the metallization of a semiconductor device according to one embodiment of the present invention, in which a two-step sequence is used to convert a precursor into a desired barrier. Each figure shows the device as a workpiece in the manufacturing stage for achieving capped metallization.

[0110] Figure 4A schematically illustrates the steps to provide structure 301 as shown in Figure 3B. The above discussion applicable to Figure 3B also applies to Figure 3B, and to the method of obtaining structure 301 from structure 300 in Figure 3A. Following the steps schematically shown in Figure 4A, Figures 4B and 4C schematically illustrate the two-step conversion of the metal precursor cap 314 to the barrier cap 420 in Figure 4C.

[0111] Figure 4B schematically illustrates the steps of converting structure 301 in Figure 4A to structure 403 in Figure 4B. The conversion includes modifying the surface of at least the metal precursor cap 314 to provide a modified metal precursor cap 419 as an intermediate reaction product. The result of the modification shown in Figure 4B is to provide structure 403 containing the modified precursor cap 419. Surface modification can advantageously change the surface energy of the modified metal precursor cap 419 relative to the metal precursor cap 314, which can further provide faster and / or higher density formation of 2D material from the modified metal precursor cap 419 in the subsequent conversion step.

[0112] Such modification to provide a modified metal precursor cap 419 may involve reducing, oxidizing, or nitriding the surface of at least the metal precursor cap 314. This modification tends to convert at least a portion of the metal in the metal precursor cap 314 into oxides and / or nitrides. This can be achieved by exposing the metal precursor cap 314 to a reducing gas, an oxygen-containing gas, a nitrogen-containing gas, or both an oxygen-containing gas and a nitrogen-containing gas under conditions effective in forming oxide modification and / or nitride modification, or other desired modification.

[0113] Figure 4C schematically shows method steps similar to those in Figure 3C, but these method steps are performed on structure 403 to convert the modified precursor cap 419 into a desired barrier layer 420. Generally, the method steps in Figure 4C involve chalcogenizing one or more metals in the modified metal precursor cap layer 419 to form one or more chalcogenides, which is an effective method for forming a monolayer of 2D chalcogenide material.

[0114] In some embodiments, the resulting chalcogenide material within the barrier cap 420, preferably in the form of a 2D single-layer material, comprises one or more dichalkogenides of formula MX2, where M is a metal and X is one or more of S, Se, and / or Te. For example, when M is selected from one or more of aluminum (Al), ruthenium (Ru) metal, molybdenum (Mo) metal, tungsten (W) metal, copper (Cu) metal, cobalt (Co) metal, tantalum (Ta) metal, titanium (Ti) metal, and hafnium (Hf) metal, the corresponding sulfur, selenium, and telluridichalcogenides are aluminum disulfide, aluminum diselenium, aluminum ditelluride, ruthenium disulfide, ruthenium diselenium, and nitryl This material includes ruthenium disulfide, molybdenum disulfide, molybdenum diselenide, molybdenum ditelluride, tungsten disulfide, tungsten diselenide, tungsten ditelluride, copper disulfide, copper diselenide, copper ditelluride, cobalt disulfide, cobalt diselenide, cobalt ditelluride, tantalum disulfide, tantalum diselenide, tantalum ditelluride, titanium disulfide, titanium diselenide, titanium ditelluride, hafnium disulfide, hafnium diselenide, and hafnium ditelluride.

[0115] The reaction shown in Figure 4C generally involves reacting a modified metal precursor cap 419 with at least one chalcogen-containing reactant (e.g., gas or plasma) under conditions that are effective in forming a chalcogenide product having a 2D monolayer structure. The reactants may include elemental forms of S, Se, and / or Te, and / or compounds of S, Se, and / or Te. An example compound is of formula R m -X q Alternatively, the compound comprises R'-XH, where each R and R' is an organic substituent such as H or an alkyl moiety containing 1 to 3, preferably 1 to 2, carbon atoms, m is 1 or 2, n is 1 or 2, and each X is independently S, Se, and / or Te. For example, the sulfur gaseous compound includes one or more of H2S, SO2, (CH3)2S, (CH3)2S2, (CH3CH2)2S, or (CH3CH2)2S2, CH3SH, and / or CH3CH2SH. In addition to the reactants, the reaction environment may further contain other gases or plasma materials such as diluent gases, reducing gases, oxidizing gases (described below), nitriding gases (described below), or combinations thereof. Examples of oxidation, nitriding, and reduction may be used as pretreatment for surface modification, preferably before exposing the metal precursor layer 219 to a chalcogenidizing gas.

[0116] The reaction may consume the entire modified metal precursor cap 419, or only a portion of the thickness of the modified metal precursor cap 419. Consuming only a portion of the modified metal precursor cap 419 is advantageous as it helps to avoid excessive conversion, and therefore loss, of the underlying metal feature 302.

[0117] The reaction between the reactant material and the modified metal precursor cap 419 may be self-limiting, and the reaction may halt when a single layer of the 2D material is formed, or when a stack containing two or more 2D single layers is formed, if the precursor cap 419 is sufficiently thick. Alternatively, the reaction may be monitored and controlled to halt when the desired transformation is achieved. For example, such chalcogenidization may halt when a desired number or thickness of 2D single layers are formed on the underlying metal feature 302. In self-limiting or controlled reaction strategies, the use of the modified metal precursor cap 419 enhances the ability to limit the reaction to the modified metal precursor cap 419 and protect the underlying metal feature 302.

[0118] In an exemplary reaction strategy, 2D formation is achieved by reacting a modified metal precursor cap 419 with one or more chalcogen-containing gas reactants using a relatively low-temperature plasma process, during which the reaction gas is excited in the gas phase and then reacts with the modified metal precursor cap 419 in the excited state. Possible excitation methods include plasma excitation, UV excitation, electron beam (e-beam) excitation, ion beam excitation, and high-temperature filament excitation, in which the reaction gas is flowed near a high-temperature filament. Examples of possible plasma sources include microwave sources, VHF plasma sources, inductively coupled plasma (ICP) sources, or capacitively coupled plasma (CCP) sources in the processing chamber of a plasma processing system. According to other embodiments, plasma excitation of the reaction gas may be omitted.

[0119] A wide range of reaction temperatures is suitable for carrying out the chalcogenidization step in Figure 4C in an effective manner for forming chalcogenide materials, including the formation of a 2D monolayer structure. In some embodiments, the reaction temperature may be in the range of about 100°C to about 800°C. In some embodiments, the reaction temperature is in the range of 400°C to 800°C. In other embodiments, the reaction temperature is in the range of 200°C to 400°C. In some embodiments, the reaction temperature is in the range of 100°C to 200°C. In some embodiments, the reaction temperature is 100°C or even lower.

[0120] In one example, multiple 2D material layers may be formed by a single set of steps in Figures 4A-4C, or by repeating the steps in Figures 4A-4C, thereby providing a stack of 2D monolayers. When such a stack is formed, the steps in Figure 4C may further include a method for removing one or more monolayers of the 2D material, for example by using an etch-back process, to remove one or more layers of the 2D material until the desired thickness of the remaining 2D material is achieved. The desired thickness may include, for example, one, two, three, or more monolayers of the 2D material, for example, up to eight monolayers, up to ten monolayers, up to twenty monolayers, or even up to 35 or more monolayers. By forming the excess monolayers and then removing some, it becomes possible to form a barrier layer 420, a precise number of monolayers, and therefore thickness, on a single metal feature, across multiple metal features within the same device, and across multiple devices, resulting in very uniform performance across the entire family of devices.

[0121] The appropriate thickness of the barrier layer 420 may be in the range of approximately 3 angstroms to approximately 10 nm (100 angstroms), or approximately 3 angstroms to approximately 5 nm, or approximately 3 angstroms to approximately 2 nm, or approximately 3 angstroms to approximately 1 nm. When formed from one or more 2D monolayers, the resulting barrier layer 420 preferably has a thickness equivalent to one monolayer or a stack of two or more 2D monolayers. For example, the barrier layer 420 may consist of at least one monolayer, and up to several monolayers, to avoid excessively restricting the width and / or height of the underlying metal feature 114. In some examples, a stack of 2D monolayers may end up containing 1 to 35 monolayers, 1 to 20 monolayers, 1 to 10 monolayers, 1 to 5 monolayers, 1 to 3 monolayers, 1 to 2 monolayers, or even just one monolayer.

[0122] In addition to protection against inelastic scattering and diffusion, the resulting 2D barrier layer 420 offers other advantages with respect to metallization. For example, such 2D monolayer materials may possess inherent flexibility and lack excessive dangling bonds. Furthermore, they are only weakly bonded in the vertical direction by van der Waals bonds, making selective removal of layers practical. This makes it possible to remove individual monolayers from a stack of monolayers to achieve a final barrier layer 420 with a precise number of monolayers having a highly uniform, precisely controlled thickness within a single feature, across multiple features in a device, and across multiple devices.

[0123] After the completion of the steps shown in Figure 4C, the resulting structure 404 can undergo further processing, fabrication steps, or other treatment as desired (such as proceeding to further fabrication steps). Figure 4D shows an example of further fabrication steps relating to converting structure 404 in Figure 4C to structure 405 in Figure 4D. Structure 405 shows the result of additional selective deposition of another material 422 (e.g., dielectric material) carried out on the exposed surface of the dielectric material 306 and preferably not on the barrier cap 420. The deposition of material 422 may be prevented or delayed on the barrier cap 420 due to the difference in properties of the barrier cap 420 compared to the dielectric layer 306.

[0124] Figure 5 is a flowchart schematically illustrating method 500, which integrates the principles of the present invention into a metallization strategy. Method step 510 includes providing a structure comprising a metal layer on a substrate. Exemplary embodiments of method step 510 are schematically illustrated and described herein with reference to Figures 1A and 2A.

[0125] Method step 514 includes patterning a metal layer to provide a patterned metal feature. Exemplary embodiments of method step 514 are schematically illustrated and described herein with reference to Figures 1B and 2B.

[0126] Method step 516 includes providing a metal precursor layer on a patterned metal feature. Exemplary embodiments of method step 512 are schematically illustrated and described herein with reference to Figures 1C and 2D.

[0127] Method step 518 includes converting a metal precursor layer into a 2D monolayer of one or more chalcogenides, thereby providing a barrier layer on top of patterned metal features. Method step 518 may be carried out using a one-step or two-step method. In a one-step method, step 520 shows that this conversion may occur by chalcogenizing the precursor material to form a desired barrier material. Exemplary embodiments of this one-step conversion are described herein with respect to Figures 1D and 3C. When a two-step conversion is used, the conversion includes a first step of oxidizing and / or nitriding at least a portion of the precursor material to provide a modified precursor material. In a second step, the modified precursor material is converted into a (e.g., semiconductor) chalcogenide. Exemplary embodiments of this two-step conversion are described herein with respect to Figures 2C-2E and 4A-4C. Following other one-step or two-step conversions, the thickness of the barrier material can optionally be reduced to provide a barrier layer having a desired final thickness.

[0128] Step 530 indicates that further fabrication or handling may be carried out following metallization.

[0129] The principles of the present invention are also useful for providing barriers in metallization using damascene strategies, including single damascene, dual damascene, and semi-damascene strategies. For example, the exemplary methods in Figures 6A–6F describe the formation of an ultrathin chalcogenide barrier, preferably comprising one or more monolayers of 2D material, where a damascene-based process is used to carry out metallization in the fabrication of a semiconductor device. Each figure shows the device as a workpiece in the manufacturing stage for achieving metallization.

[0130] Figure 6A schematically illustrates the steps for providing a microelectronic device 600 under fabrication. For illustrative purposes, a portion of the semiconductor device 600 is shown. The partially fabricated device 600 includes a structure comprising a dielectric layer 610 on a substrate 605 having the same features and properties as the substrate 110 in Figure 1A. The dielectric layer 610 may include, for example, silicon dioxide, and / or any low-k and / or high-k dielectric material, or combinations thereof suitable for use in semiconductor devices. As used herein, a high-k dielectric refers to a material having a dielectric constant greater than 3.9, and a low-k dielectric refers to a material having a dielectric constant of 3.9 or less (silicon dioxide has a dielectric constant of 3.9). Examples of dielectric materials include oxides, nitrides, and oxynitrides of one or more metals, and combinations thereof. Exemplary metallic components of dielectric materials include Si, Hf, Ta, Ba, Sr, Pb, Mg, Mo, Zr, Bi, and combinations thereof. Specific examples of dielectric materials include organic substituent-containing dielectrics such as SiO2 and TEOS, hafnium oxide, hafnium nitride, hafnium oxynitride, silicon oxynitride, hafnium nitride silicate, nanoporous silica, hydrogen silsesquioxane, polytetrafluoroethylene, silicon oxyfluoride, silicon nitride, tantalum oxide, tantalum nitride, tantalum oxynitride, barium strontium titanate, magnesium lead niobate and other perovskite metal oxides, zirconium lead titanate, bismuth strontium tantalate, combinations thereof, or any other suitable dielectric material.

[0131] Figure 6B schematically illustrates the steps of converting structure 600 in Figure 6A to structure 601 in Figure 6B. This conversion includes patterning a dielectric layer 610 to form patterned dielectric features 612 on a substrate 605. The patterning technique used to form structure 601 may include the steps of forming a photoresist layer on the dielectric layer 610, patterning the photoresist layer using a lithography technique to form a mask layer, forming patterned dielectric features 612 on a substrate 110 using the resulting mask layer and a removal technique such as etching, and then removing the mask material (not shown). The resulting dielectric features 612 include a top surface 615 and sidewall surfaces 617.

[0132] Figure 6B shows voids 614 between features 612 that extend throughout to the substrate 605, although some voids (not shown) may be shallower and extend only partially within the depth of the patterned dielectric material features 612. In some embodiments, voids 614 may correspond to vias and trenches, and contacts (not shown) and interconnections (not shown) may be later formed within the vias and trenches by filling the voids 614 with conductive metallic material, as described below.

[0133] As schematically shown in structure 602 in Figure 6C, the method further includes selectively forming a metal precursor layer 616 on the exposed surface of the patterned dielectric feature 612 and on the exposed portion of the substrate within the gap 614. The metal precursor layer 616 lining the dielectric feature 612 and the void 614 can be prepared using the precursor formation techniques and features described above with respect to Figures 1C and 2C.

[0134] As schematically shown in Figure 6D, the method further includes the step of converting the metal precursor layer 616 of Figure 6C into the barrier layer 618 of Figure 6D, which contains at least one (e.g., semiconductor) chalcogenide, to provide the structure 603. The barrier layer 618 lining the dielectric feature 612 and void 614 may be prepared using the one-step barrier formation technique and features described above with respect to Figure 1D. Alternatively, the barrier layer 618 may be formed using the two-step barrier formation technique and features described above with respect to Figures 2D and 2E.

[0135] As schematically shown in structure 604 of Figure 6E, the method further comprises filling the barrier-lined void 614 of structure 603 of Figure 6D with a conductive metallic material 623 to provide structure 604 in Figure 6E. Since metallization is achieved in Figure 6E by filling the void 614 with the metallic material, in the semiconductor field this method is called a damascene metallization strategy. The steps in Figure 6E may include using a damascene strategy, including semi-damascene, single-damascene, and / or dual-damascene techniques.

[0136] Figure 6E shows an optional strategy for filling the void 614 with an excess portion 621 of metallic material above the line 622. Figure 6F schematically shows a step of reducing the excess portion 621 to provide a planar structure 606, preferably on the line 622. In an alternative embodiment, the void 614 is filled with metallic material 623 without the excess portion 621.

[0137] The methods shown in Figures 6A-6F illustrate a strategy in which the barrier layer 618 is formed before the introduction of the metallic material to be protected by the barrier material. This sequence is typical of the damascene strategy. In the metallic patterning strategies described above, the barrier layer 618 is generally formed after several metallic features have been present.

[0138] After the steps shown in Figures 6E and 6F are completed, the resulting structure 606 can undergo further processing, fabrication steps, or other handling as desired (such as proceeding to further fabrication steps).

[0139] The metallic material 623 used to fill the void 614 in the method step of Figure 6E may include one or more conductive metallic materials, including one or more transition metals, that are suitable for forming metallic features such as contacts and interconnects in semiconductor devices. For example, metallic material 623 may include one or more of the following metals: copper (Cu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), tungsten (W), nickel (Ni), hafnium (Hf), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), manganese (Mn), cobalt (Co), nickel (Ni), zinc (Zn), yttrium (Y), zirconium (Zr), niobium (Nb), technetium (Tc), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), or combinations thereof. Alloys of such metals may also be used. For example, metallic material 623 may include NiAl alloys and / or CuAl alloys. In a preferred embodiment, the metallic material 623 includes one or more of the following metals: copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), molybdenum (Mo), tungsten (W), nickel (Ni), or a combination thereof.

[0140] The metallic material 623 may have the same or a different metallic composition as the metallic precursor layer 616 in Figure 6D. Even if the metallic compositions are the same (or different), the metallic material 623 and the metallic precursor layer 616 may have different degrees of crystallinity. In other embodiments, the metallic composition of the metallic precursor layer 616 is different from that of the metallic material 623. Alternatively, the metallic precursor layer 616 may have the same or a similar degree of crystallinity as the metallic material 623.

[0141] Figure 7 is a schematic flowchart illustrating Method 700, which integrates the principles of the present invention into a damascene metallization strategy. Method step 710 includes providing a structure comprising a metal layer on a substrate. Exemplary embodiments of Method step 710 are schematically illustrated and described herein with reference to Figure 6A.

[0142] Method step 714 includes patterning a dielectric layer to provide a patterned dielectric feature. Exemplary embodiments of method step 714 are schematically illustrated and described herein with reference to Figure 6B.

[0143] Method step 716 includes providing a metal precursor layer on a patterned dielectric feature. Exemplary embodiments of method step 716 are schematically illustrated and described herein with reference to Figure 6C.

[0144] Method step 718 includes converting a metal precursor layer into a 2D monolayer of one or more chalcogenides, thereby providing a barrier layer on a patterned dielectric feature. Method step 718 may be carried out using a one-step or two-step method. In a one-step method, step 720 shows that this conversion may occur by chalcogenizing the precursor material to form a desired barrier material. Exemplary embodiments of this one-step conversion are described herein with respect to Figures 1D and 3C. When a two-step conversion is used, the conversion includes a first step of oxidizing and / or nitriding at least a portion of the precursor material to provide a modified precursor material. In a second step, the modified precursor material is converted into a (e.g., semiconductor) chalcogenide. Exemplary embodiments of this two-step conversion are described herein with respect to Figures 2C-2E and 4A-4C. Following other one-step or two-step conversions, the thickness of the barrier material can optionally be reduced to provide a barrier layer having a desired final thickness.

[0145] Step 730 indicates that further fabrication or handling may be carried out following metallization.

[0146] The present invention has been described above with reference to several embodiments thereof. The above detailed description and examples are provided for the sake of clarity and should not be used to derive any unnecessary limitations. It will be apparent to those skilled in the art that many modifications can be made to the described embodiments without departing from the scope of the invention. The above-described and other implementations are within the scope of the following claims.

Claims

1. A method for manufacturing a semiconductor device comprising at least one barrier-protected metal feature, a) A step of forming a barrier layer, wherein the barrier layer is 1) The step of providing a metal precursor layer, 2) The step of converting the metal precursor layer into one or more two-dimensional monolayers containing at least one chalcogenide. A step formed by having a step, b) The step of bringing the barrier layer into contact with the at least one metal feature in an effective manner for providing the at least one barrier-protected metal feature, A method having

2. The method according to claim 1, wherein the at least one chalcogenide comprises at least one semiconductor chalcogenide.

3. The method according to claim 1, wherein the at least one chalcogenide includes a transition metal dichalcogenide.

4. Furthermore, prior to step a), there is a step of providing multiple metal features to the substrate, The method according to claim 1, wherein step a) comprises the step of forming the metal precursor layer on the plurality of metal features.

5. The method according to claim 1, wherein the at least one metal feature is formed after the barrier layer is formed.

6. The at least one metal feature includes a plurality of barrier-protected metal features, and the method further includes 1) A step of providing a substrate having a patterned dielectric layer having a plurality of voids, 2) The step of forming the barrier layer on the surface of the void to provide barrier-lined voids, 3) Filling the barrier-lined void with at least one metal composition to provide the plurality of barrier-protected metal features, The method according to claim 1, comprising:

7. The aforementioned at least one metal feature includes a plurality of metal features, and the method further includes 1) The step of forming the plurality of metal features on the substrate, 2) The step of forming the barrier layer on the plurality of metal features to provide a plurality of barrier-protected metal features, The method according to claim 1, comprising:

8. Step b) further, The step of chalcogenizing at least a portion of the metal precursor layer to provide the barrier layer comprising the at least one two-dimensional monolayer, under conditions effective in providing the barrier layer, to provide the barrier-protected metal feature. It has, The method according to claim 1, wherein the at least one two-dimensional monolayer comprises a semiconductor chalcogenide.

9. A method for forming a semiconductor device, the method is a) The step of providing a metal feature to the substrate, b) The step of forming a metal precursor layer on the exposed surface of the metal feature, c) The step of providing a barrier-protected metal feature by chalcogenizing at least a portion of the metal precursor layer under conditions effective in providing a barrier layer comprising at least one two-dimensional monolayer, It has, The method wherein the at least one two-dimensional monolayer comprises a metal chalcogenide.

10. The method according to claim 9, wherein step c) is a step of reacting the metal precursor layer with a reactant comprising at least one chalcogen.

11. The method according to claim 10, wherein the reactant comprises sulfur (S), selenium (Se), and / or tellurium (Te).

12. The reactant is H ２ S, SO ２ , (CH ３ ) ２ S, (CH ３ ) ２ S ２ , (CH ３ CH ２ ) ２ S, and / or (CH ３ CH ２ ) ２ S ２ The method according to claim 11, selected from the group consisting of

13. Furthermore, before step c), A step of modifying at least a portion of the metal precursor layer by exposure to a reducing gas, an oxygen-containing gas, a nitrogen-containing gas, or at least one of an oxygen and nitrogen-containing gas. The method according to claim 9, having the following characteristics.

14. The modification step is performed selectively on a portion of the metal precursor layer. The method according to claim 13, further comprising the step of selectively chalcogenizing the selectively modified metal precursor layer to form the at least one two-dimensional monolayer.

15. The method according to claim 9, wherein the metal feature comprises at least one metallic material selected from the group consisting of copper (Cu) metal, cobalt (Co) metal, ruthenium (Ru) metal, molybdenum (Mo) metal, tungsten (W) metal, nickel (Ni) metal, aluminum (Al), niobium (Nb), iridium (Ir), rhodium (Rh) metal, alloys thereof, and combinations thereof.

16. The method according to claim 9, wherein the metal precursor layer comprises at least one metallic material selected from the group consisting of ruthenium (Ru) metal, molybdenum (Mo) metal, tungsten (W) metal, copper (Cu) metal, cobalt (Co) metal, tantalum (Ta) metal, titanium (Ti) metal, hafnium (Hf) metal, alloys thereof, and combinations thereof.

17. The method according to claim 9, wherein the barrier layer and the barrier-protected metal feature comprises at least one different metal or element.

18. The aforementioned metal chalcogenide is a dichalcogenide, and the formula is MX ２ The method according to claim 9, comprising one or more dicalcogenides, where M is a metal and X is one or more of S, Se, and / or Te.

19. After step c), further, The step of depositing a dielectric material on the barrier-protected metal feature and / or the exposed surface of the substrate. The method according to claim 9, having the following characteristics.

20. The method according to claim 19, further comprising the step of selectively depositing additional features on the exposed surface of the dielectric material, wherein the additional features include the dielectric material.

21. It is a semiconductor device, Metal features on the substrate, A barrier layer in contact with the surface of the metal feature, comprising one or more single layers of a two-dimensional material containing a chalcogenide, It has, The aforementioned barrier, To provide a metal precursor layer on the surface of the metal feature, Converting the metal precursor layer into one or more two-dimensional monolayers containing the chalcogenide, A semiconductor device formed on the surface of the metal feature as a result.

22. The device according to claim 21, wherein the metal feature includes copper (Cu) metal, cobalt (Co) metal, ruthenium (Ru) metal, molybdenum (Mo) metal, tungsten (W) metal, nickel (Ni) metal, aluminum (Al) metal, alloys thereof, or combinations thereof.

23. The device according to claim 21, wherein the barrier layer is formed by chalcogenizing a metal precursor layer containing ruthenium (Ru) metal, molybdenum (Mo) metal, tungsten (W) metal, copper (Cu) metal, cobalt (Co) metal, tantalum (Ta) metal, titanium (Ti) metal, hafnium (Hf) metal, alloys thereof, or combinations thereof.

24. The device according to claim 21, wherein the two-dimensional material comprises a transition metal dichalcogenide.

25. The aforementioned chalcogenide is a dichalkogenide, and the formula is MX ２ The device according to claim 21, comprising one or more dicalcogenides, where M is a metal and X is one or more of S, Se, and / or Te.

26. Furthermore, the device according to claim 21, wherein a dielectric material is provided between the metal features.

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