Conductive wires for interconnection in stacked device structures

Abstract

A microelectronic device structure includes a device having (i) a bottom surface, (ii) an upper surface opposite to the bottom surface, and (iii) a side surface extending between the bottom and upper surfaces. An integrated circuit structure further includes a conductive wire having (i) a first portion on the upper surface, (ii) a second portion on the side surface, and (iii) a third portion on the bottom surface. In one example, the first and second portions of the conductive wire are monolithic conductive structures with no seams or interfaces between the first and second portions. Additionally or alternatively, in one example, the second and third portions of the conductive wire are monolithic conductive structures with no seams or interfaces between the second and third portions.

Description

Technical Field

[0001]

[0001] This disclosure generally relates to integrated circuits, and more particularly, to interconnections between stacked integrated circuit devices.

Background Art

[0002]

[0002] In a vertically stacked integrated circuit device configuration, an upper device is stacked above a lower device, and there may be one or more additional devices above and / or below the combination of the upper and lower devices. The devices can be integrated circuit dies and / or integrated circuit packages. The lowermost device in the stack can be coupled to a circuit board such as a printed circuit board (PCB). To facilitate communication between the upper device and the PCB, wire bonding technology may be used, and the upper device is coupled to the PCB via a plurality of wire bonds. In another example, through-silicon vias (TSVs) may be formed in the lower device, the TSVs extend from the top surface to the bottom surface of the lower device, and the upper device is coupled to the underlying PCB via the TSVs, solder balls, solder bumps, and / or other integrated components.

Brief Description of the Drawings

[0003] [Figure 1]

[0003] FIG. 1 illustrates a cross-sectional view of an integrated circuit structure according to an embodiment of the present disclosure, including (i) a first device, (ii) a second device above the first device, (iii) a third device below the first device, (iv) conductive lines extending on the top surface, bottom surface, and side surfaces of the first device, (v) a first interconnect component coupled between the second device and a portion of the conductive line on the top surface of the first device, and (vi) a second interconnect component coupled between the third device and another portion of the conductive line on the bottom surface of the first device. [Figure 2]

[0004] FIG. 2 illustrates the conductive lines and the first device of FIG. 1 in more detail according to an embodiment of the present disclosure. [Figure 3]

[0005] Figure 3 shows a plan view or top view of the first device of Figures 1 and 2, having corresponding portions of a plurality of conductive wires on the top surface of the first device according to one embodiment of the present disclosure. [Figure 4]

[0006] Figure 4 shows a perspective view of the first device of Figures 1 to 3, which has a plurality of conductive wires on one or more surfaces of the first device according to one embodiment of the present disclosure. [Figure 5]

[0007] Figure 5 illustrates another perspective view of the first device shown in Figures 1 to 4, which has a plurality of conductive wires on one or more surfaces of the first device according to one embodiment of the present disclosure. [Figure 6A]

[0008] Figure 6A shows an enlarged view of a portion of the first conductive wire described with respect to Figures 1 to 5, according to one embodiment of the present disclosure. [Figure 6B] Figure 6B shows an enlarged view of a portion of a second conductive wire that may be formed using an additive process according to one embodiment of the present disclosure. [Figure 6C] Figure 6C shows an enlarged view of a portion of a third conductive wire that may be formed using a lithography process according to one embodiment of the present disclosure. [Figure 7]

[0009] Figure 7 illustrates a flowchart illustrating a method 700 for forming conductive wires in the integrated circuit structure shown in Figures 1 to 5, according to one embodiment of the present disclosure. [Figure 8A1]

[0010] Figure 8A1 collectively illustrates exemplary integrated circuit structures at various stages of processing according to the method of Figure 7, according to one embodiment of the present disclosure. [Figure 8A2] Figure 8A2 collectively illustrates exemplary integrated circuit structures at various stages of processing according to the method of Figure 7, according to one embodiment of the present disclosure. [Figure 8B1] Figure 8B1 collectively illustrates exemplary integrated circuit structures at various stages of processing according to the method of Figure 7, according to one embodiment of the present disclosure. [Figure 8B2]Figure 8B2 collectively illustrates exemplary integrated circuit structures at various stages of processing according to the method of Figure 7, according to one embodiment of the present disclosure. [Figure 8C1] Figure 8C1 collectively illustrates exemplary integrated circuit structures at various stages of processing according to the method of Figure 7, according to one embodiment of the present disclosure. [Figure 8C2] Figure 8C2 collectively illustrates exemplary integrated circuit structures at various stages of processing according to the method of Figure 7, according to one embodiment of the present disclosure. [Figure 8D1] Figure 8D1 collectively illustrates exemplary integrated circuit structures at various stages of processing according to the method of Figure 7, according to one embodiment of the present disclosure. [Figure 8D2] Figure 8D2 collectively illustrates exemplary integrated circuit structures at various stages of processing according to the method of Figure 7, according to one embodiment of the present disclosure. [Figure 8E] Figure 8E collectively illustrates exemplary integrated circuit structures at various stages of processing according to the method of Figure 7, according to one embodiment of the present disclosure.

[0004]

[0011] The figures are illustrative only and depict various embodiments of the present disclosure, and are not necessarily drawn to scale. Numerous variations, configurations, and other embodiments will become apparent from the following detailed description. [Modes for carrying out the invention]

[0005]

[0012] This specification discloses an integrated circuit structure comprising one or more conductive wires extending onto multiple surfaces of a first device, wherein the one or more conductive wires facilitate interconnection between (i) a second device located above the first device and (ii) a third device located below the first device. In one example, each of the first, second, and third devices may be, for example, an integrated circuit die, an integrated circuit package, or a circuit board (e.g., a PCB). In one such example, the first device is a first integrated circuit die, the second device is a second integrated circuit die, and the third device is an integrated circuit package, but other combinations may be used.

[0006]

[0013] For example, the first device has (i) a bottom surface, (ii) an upper surface opposite to the bottom surface, and (iii) a side surface extending between the bottom surface and the upper surface. In some such examples, the conductive wire extends over the bottom surface, side surface, and top surface of the first device, and as a result, the conductive wire has multiple parts, each on a corresponding surface of the first device. For example, the conductive wire has (i) a first part on the top surface, (ii) a second part on the side surface, and (iii) a third part on the bottom surface of the first device. In one such example, at least two adjacent parts of the conductive wire form a conductive monolithic structure, for example, without a seam or interface between at least two adjacent parts. Thus, at least one of (i) the first and second parts of the conductive wire is a monolithic conductive structure such that there is no seam or interface between the first and second parts, and (ii) the second and third parts of the conductive wire is a monolithic conductive structure such that there is no seam or interface between the second and third parts.

[0007]

[0014] In some examples, a second device above a first device is coupled to a first portion of a conductive wire (for example, on the upper surface of the first device) through a first interconnecting component. Similarly, a third device below the first device is coupled to a third portion of a conductive wire (for example, on the lower surface of the first device) through a second interconnecting component. In one such example, each of the first and second interconnecting components is a solder ball or solder bump (or, for example, a gold stud bump, thermosonic bond, anisotropic conductive paste, or another suitable interconnecting component). Thus, conductive wires on multiple surfaces of the first device bond (i) a second device laminated above the first device and (ii) a third device below the first device.

[0008]

[0015] In one embodiment, the conductive wire is formed using a subtractive process. For example, a first conductive material may be deposited on a first surface of a first device, and the first conductive material on the first surface may be patterned (e.g., using a laser beam) to form a first portion of the conductive wire. Alternatively, a second conductive material may be deposited on a second and a third surface of the first device, and the second conductive material on the second and a third surface may be patterned (e.g., using a laser beam) to form a second and a third portion of the conductive wire on the second and a third surface of the first device, respectively. In one example, the conductive wire is a continuous structure extending on the first, second, and third surfaces of an integrated circuit device. Based on this disclosure, numerous variations and embodiments will become apparent.

[0009] General Overview

[0016] As described above, in a stacked device configuration, TSVs can be formed within an intermediate device to interconnect an upper device (e.g., one above the intermediate device) to a lower device (e.g., one below the intermediate device) via TSVs in the intermediate device. However, designing and forming TSVs through integrated circuit devices can be costly and time-consuming. Furthermore, if such devices are configured in a flip-chip mounting configuration, wire bonding may not be usable to interconnect such stacked devices.

[0010]

[0017] Accordingly, techniques for forming one or more conductive wires extending onto multiple surfaces of a first device are described herein, the one or more conductive wires facilitating interconnection between (i) a second device located above the first device and (ii) a third device located below the first device. In one example, each of the first, second, and third devices may be an integrated circuit die, an integrated circuit package, or a circuit board (e.g., a PCB).

[0011]

[0018] For example, the first device has (i) a bottom surface, (ii) an upper surface opposite to the bottom surface, and (iii) a number of sides extending between the bottom and upper surfaces. In one such example, each of the one or more such conductive wires is a continuous conductive structure extending over the upper surface of the first device, the corresponding side of the first device, and the bottom surface of the first device. In an example where the first device has four sides, the conductive wires may be on one, two, three, or all four sides of the first device.

[0012]

[0019] The following description relates to one conductive line on multiple surfaces of a first device, and such description is also applicable to multiple other such conductive lines on the surface of the first device. In some examples, a second device (e.g., above the first device) is coupled to a portion of a conductive line on the top surface of the first device via interconnect components (such as solder bumps or balls, gold stud bumps, thermosonic bonds, anisotropic conductive paste, or other suitable interconnect components). In some such examples, a third device (e.g., below the first device) is coupled to a portion of a conductive line on the bottom surface of the first device via another interconnect component (such as solder bumps or balls, gold stud bumps, thermosonic bonds, anisotropic conductive paste, or other suitable interconnect components). Thus, the second device is coupled to the third device via conductive lines on each of the top, side, and bottom surfaces of the first device. In one example, since the conductive line provides such an interconnect between the second device and the third device, TSVs through the first device are not required.

[0013]

[0020] In one embodiment, the conductive line is formed using a subtractive process. In one example, a first conductive material may be deposited on a first surface of the first device, and the first conductive material on the first surface may be patterned (e.g., using a laser beam or other subtractive formation process) to form a first portion of the conductive line. Also, a second conductive material may be deposited on a second surface and a third surface of the first device, and the second conductive material on the second and third surfaces may be patterned (e.g., using a laser beam or other subtractive formation process) to form a second portion and a third portion of the conductive line on the second surface and the third surface of the first device, respectively. In another example, the conductive material is deposited on the first, second, and third surfaces using the same deposition process and then patterned using the same patterning process.

[0014]

[0021] In one example, the conductive line is a continuous structure that extends over the first surface, the second surface, and the third surface of the integrated circuit device. The conductive line has a plurality of portions, and each portion is on a corresponding surface of the first device. For example, the conductive line has (i) a first portion on the top surface, (ii) a second portion on the side surface, and (iii) a third portion on the bottom surface of the first device.

[0015]

[0022] In some examples, since the conductive line is formed using a subtractive process, two or more adjacent portions of the conductive line may be monolithic, for example, there is no seam or interface between two or more adjacent portions of the conductive line. For example, since the conductive material is deposited on two or more surfaces of the first device by the same deposition process, the corresponding two or more portions of the conductive line cannot have any seam or interface between them. Thus, (i) the first portion and the second portion of the conductive line are a monolithic conductive structure having no seam or interface between the first portion and the second portion, and / or (ii) the second portion and the third portion of the conductive line are a monolithic conductive structure having no seam or interface between the second portion and the third portion.

[0016]

[0023] In one embodiment, within a portion of the conductive line, there may be various segments that extend in corresponding various directions. For example, for a given portion of the conductive line, the first segment is at an angle different from 180 degrees with respect to an adjacent segment (for example, two adjacent segments do not form a straight line and extend in different directions). Thus, the segments of the conductive line are straight portions of the conductive line that have no bends or curves or other direction-changing features therein.

[0017]

[0024] In one embodiment, as will be described in more detail below, the conductive wire is formed using a subtractive process so that the intersection between two adjacent segments is sharp and there is no overhang of segments beyond the intersection (see, for example, Figure 4). In some such examples, such precise intersections are possible because a laser beam is used when patterning the conductive wire from the blanket-deposited conductive material. In contrast, conductive wires formed using an additive process (described later) may have improperly aligned segments and segment overhangs at the intersection.

[0018]

[0025] Furthermore, in the case of conductive wires formed using a subtractive process as described herein, there are no seams or interfaces between adjacent segments of the conductive wire. In contrast, conductive wires formed using an additive process may have seams or interfaces between adjacent segments of the conductive wire.

[0019]

[0026] Furthermore, in the case of additively formed conductive wires, the conductive material at the intersection of the two segments is deposited twice (e.g., deposited as part of the formation of the first segment and again as part of the formation of the second segment). This results in an increase in the thickness of the conductive material at the intersection of the additively formed conductive wires. In contrast, the thickness of conductive wires formed using the subtractive process described herein is substantially uniform (e.g., the conductive material for the entire portion including adjacent segments is blanket-deposited and then patterned using the same deposition process).

[0020]

[0027] According to some embodiments of this disclosure, these various approaches can be used individually or together to form conductive wires using a subtractive process, which facilitates interconnection between stacked devices. Numerous variations and embodiments will become apparent based on this disclosure.

[0021]

[0028] As used herein in the description and claims, the term “about” indicates that the listed values ​​may be changed to some extent, provided that the change does not result in a non-conformity of the process or device. For example, for some elements, the term “about” may refer to a variation of ±0.1%, and for other elements, the term “about” may refer to a variation of ±1%, ±10%, or any point within that range. Also, as used herein, a term defined in the singular is intended to include a term defined in the plural, and vice versa.

[0022]

[0029] Any reference to a numerical range in this specification explicitly includes each number (including fractions and integers) that falls within that range. For example, a reference to the range "at least 50" or "at least about 50" in this specification includes integers such as 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, and 60, and fractions such as 50.1, 50.2, 50.3, 50.4, 50.5, 50.6, 50.7, 50.8, and 50.9. In further examples, references to the range “less than 50” or “about less than 50” in this specification include integers such as 49, 48, 47, 46, 45, 44, 43, 42, 41, 40, and fractions such as 49.9, 49.8, 49.7, 49.6, 49.5, 49.4, 49.3, 49.2, 49.1, 49.0, and so on.

[0023]

[0030] As used herein, the terms “substantially” or “substantial” are equally applicable when used in a negative sense to refer to the complete or near-complete absence of an action, feature, characteristic, state, structure, item, or result. For example, a “substantially” flat surface is either perfectly flat or so nearly flat that it has the same effect as being perfectly flat.

[0024] architecture

[0031] Figure 1 shows a cross-sectional view of an integrated circuit structure 100 according to one embodiment of the present disclosure, comprising: (i) a first device 104; (ii) a second device 108 above the first device 104; (iii) a third device 120 below the first device 104; (iv) a conductive wire 113a extending onto the upper surface 115u, lower surface 115L, and side surface 115s1 of the first device 104; (v) a first interconnection component 112a coupled between the second device 108 and a portion of the conductive wire 113a on the upper surface 115u of the first device 104; and (vi) a second interconnection component 114a coupled between the third device 120 and another portion of the conductive wire 113a on the lower surface 115L of the first device 104.

[0025]

[0032] In one example, structure 100 includes three stacked devices 104, 108, and 120, but structure 100 may include more than three stacked devices, such as four or five stacked devices. In one embodiment, each of devices 104, 108, and 120 may be any suitable integrated circuit device, such as a processor or logic die, a memory die, an integrated circuit package, or a circuit board (e.g., a printed circuit board (PCB)). For example, one or more of devices 104, 108, and 120 may include active devices such as multiple transistors, memory cells, and logic cells, passive devices such as resistors, inductors, and capacitors, and / or one or more other components of a miniature electronic die and package. For example, device 108 is an integrated circuit die or integrated circuit package, device 104 is an integrated circuit die or integrated circuit package, and device 120 is an integrated circuit die, an integrated circuit package, or a circuit board (e.g., a PCB).

[0026]

[0033] In an example where devices 104 and 108 are integrated circuit dies and device 120 is a package carrier substrate, device 104 is coupled to the package carrier substrate 120 in a flip-chip configuration such that, for example, the active bottom surface 115L of device 120 having an interconnection component 116 faces device 104. Devices 104 and 108 form a vertical stack of dies.

[0027]

[0034] Device 104 has six surfaces, including an upper surface 115u, a lower surface 115L, and four side surfaces 115s1, 115s2, 115s3, and 115s4, although only two side surfaces 115s1 and 115s2 are visible in the cross-sectional view of Figure 1. The upper surface 115u of device 104 faces device 108, the lower surface 115L of device 104 is on the opposite side of the upper surface 115u and faces device 120, and each of the side surfaces 115s1, 115s2, 115s3, and 115s4 extends between the upper surface 115u and the lower surface 115L. Note that in one example, the corners of device 104 and / or portions of device 104 between two surfaces may be chamfered. For example, chamfering the corners may improve the reliability in forming the conductive wires described herein.

[0028]

[0035] Similarly, device 108 has six surfaces, including a top surface 117u, a bottom surface 117L, and four specific unlabeled sides, although only two sides are visible in the cross-sectional view of Figure 1. As shown, the bottom surface 117L of device 108 faces device 104, the top surface 117u of device 108 is on the opposite side of the bottom surface 117L, and each of the sides extends between the top surface 117u and the bottom surface 117L.

[0029]

[0036] In one embodiment, the lower surface 115L of device 104 is the active surface of device 104, for example, the surface on which components of device 104 are coupled to an external circuit. For example, a plurality of interconnection components 116 couple device 104 (such as the lower surface 115L of device 104) to device 120. In one example, the interconnection components 116 are conductive balls or bumps such as solder balls or solder bumps (or may comprise, for example, gold stud bumps, thermosonic bonds, anisotropic conductive pastes, or other suitable interconnection components). For example, device 104 is an integrated circuit package or integrated circuit die, and the interconnection components 116 couple device 104 to PCB 120 in a ball grid array (BGA) configuration or another suitable configuration. In one example, each interconnection component 116 is coupled to the lower surface 115L of device 104 via a corresponding contact pad located on the lower surface 115L of device 104. The interconnection components 114a and 114b are also shown to be coupled to the lower surface 115L of the device 104, and these interconnection components 114a and 114b will be described later.

[0030]

[0037] In one embodiment, the structure 100 further comprises conductive wires 113a and 113b (illustrated in Figure 1 using thick gray lines), each of which conductive wires 113a and 113b extends onto the upper surface 115u, lower surface 115L, and side surface 115s1 or 115s2 of the device 104, as illustrated in Figure 1. The device 104 is likely to have three or more such conductive wires 113a and 113b on its surface, but only two such conductive wires 113a and 113b are visible in the cross-sectional view of Figure 1. The conductive wires 113a and 113b may have widths in the range of, for example, 1 to 100 microns, or 1 to 80 microns, or 1 to 50 microns, or 1 to 25 microns, or 1 to 10 microns, or 10 to 100 microns, or 25 to 100 microns.

[0031]

[0038] As shown in the figure, the interconnection component 112a is located between the lower surface 117L of device 108 and a portion of line 113a on the upper surface 115u of device 104, electrically coupling them. For example, the interconnection component 112a is coupled to the lower surface 117L of device 108 via a corresponding conductive contact pad and to the upper surface 115u of device 104 via another corresponding conductive contact pad (e.g., contact pad 219, see Figure 2).

[0032]

[0039] Similarly, another interconnection component 112b lies between the lower surface 117L of device 108 and a portion of line 113b on the upper surface 115u of device 104, electrically coupling them. For example, interconnection component 112b is coupled to the lower surface 117L of device 108 via another corresponding conductive contact pad and to the upper surface 115u of device 104 via another corresponding conductive contact pad. In one example, interconnection components 112a, 112b are conductive balls or bumps such as solder balls or solder bumps (or, for example, gold stud bumps, thermosonic bond, anisotropic conductive paste, or other suitable interconnection components).

[0033]

[0040] As shown in the figure, the interconnection component 114a is located between (i) a portion of line 113a on the lower surface 115L of device 104 and (ii) device 120, electrically coupling them. For example, the interconnection component 114a is coupled to the lower surface 115L of device 104 via a corresponding conductive contact pad (e.g., contact pad 220, see Figure 2) and to the upper surface of device 120 via a corresponding conductive contact pad.

[0034]

[0041] Similarly, another interconnection component 114b is located between (i) a portion of line 113b on the lower surface 115L of device 104 and (ii) device 120, electrically coupling them. For example, interconnection component 114b is coupled to the lower surface 115L of device 104 via a corresponding conductive contact pad and to the upper surface of device 120 via another corresponding conductive contact pad. In one example, interconnection components 114a, 114b are conductive balls or bumps such as solder balls or solder bumps (or, for example, gold stud bumps, thermosonic bond, anisotropic conductive paste, or other suitable interconnection components).

[0035]

[0042] Therefore, in Figure 1, device 108 is electrically coupled to device 120 via interconnection component 112a, conductive wire 113a, and interconnection component 114a. Thus, conductive wire 113a facilitates the electrical coupling of device 108 to device 120. Similarly, conductive wire 113b also facilitates the electrical coupling of device 108 to device 120. Since conductive wires 113a and 113b electrically couple device 108 to device 120, through-silicon vias (TSVs) that penetrate device 104 to couple devices 108 and 120 may not be required, thereby avoiding the cost and complexity associated with forming such TSVs that penetrate device 104.

[0036]

[0043] Figure 2 illustrates in more detail the conductive wire 113a and the first device 104 of Figure 1 according to one embodiment of the present disclosure. For example, the conductive wire 113a has a first portion 204 on the upper surface 115u of the device 104, a second portion 208 on the side surface 115s1 of the device 104, and a third portion 212 on the lower surface 115L of the device 104. In one example, the conductive wire 113a is formed using a subtractive process, as described below. For example, to form a portion of the conductive wire 113a on the surface of the device 104, a conductive material is blanket-deposited on at least a portion of the surface of the device 104. The blanket-deposited conductive material is then patterned (e.g., using a laser beam) to form a portion of the conductive wire 113a on the surface of the device 104. In one embodiment, the conductive material may be deposited simultaneously on one or more surfaces of the device 104 and then patterned.

[0037]

[0044] For example, the conductive material can be deposited on the top surface 115u and side surface 115s1 of the device 104 using the same deposition process (for example, it can be deposited conformally). Thus, a monolithic and continuous layer of conductive material is present on the top surface 115u and side surface 115s1 of the device 104 without any seams or interfaces between the portion of conductive material on the top surface 115u and the other portion of conductive material on the side surface 115s1. Therefore, after patterning, portions 204 and 208 of the conductive wire 113a have no seams or interfaces between them, for example, portions 204 and 208 form a monolithic conductive structure.

[0038]

[0045] In another example, the conductive material can be deposited on the top surface 115u, side surface 115s1, and bottom surface 115L of the device 104 using the same deposition process. Therefore, for the reasons stated above, the conductive wire 113a has no seams or interfaces between portions 204 and 208, nor between portions 208 and 212. Thus, the entire conductive wire 113a becomes a monolithic conductive structure.

[0039]

[0046] In yet another example, the conductive material may be deposited on the side surface 115s1 and the bottom surface 115L of the device 104 using the same deposition process. Thus, for the reasons stated above, the conductive wire 113a has no joints or interfaces between parts 208 and 212, and for example, parts 208 and 212 form a monolithic conductive structure.

[0040]

[0047] As described herein, the conductive wire 113a is formed using a subtractive process, which, as stated above, does not result in a seam or interface between portions 204 and 208 of the conductive wire 113a and / or between portions 208 and 212 of the conductive wire 113a. In contrast, in the case of an additively formed conductive wire (the additive process is also described with respect to Figure 4), as described below with respect to Figure 4, two adjacent portions of the additively formed conductive wire (for example, on two adjacent surfaces of the corresponding device) are deposited using two different deposition processes, so a seam or interface exists between any two adjacent portions.

[0041]

[0048] Figure 2 also illustrates two contact pads 219 and 220 (which are not shown in Figure 1 for clarity as an example). Contact pad 219 is located on portion 204 of the conductive wire 113a and is configured to receive the interconnection component 112a. Contact pad 220 is located on portion 212 of the conductive wire 113a and is configured to receive the interconnection component 114a.

[0042]

[0049] As shown in Figure 2, in one embodiment, the device 104 comprises a layer 224 of dielectric material (illustrated using thick black lines) on at least some portions of various surfaces of the device 104. The layer 224 of dielectric material illustrated in Figure 2 is not shown in Figure 1 for clarity of explanation. In one example, beneath the layer 224 of dielectric material is the body of the device 104, which comprises, for example, bulk silicon or another suitable material, depending on the technology used to form the device 104. If the conductive wire 113 is directly on the semiconductor material body of the device 104 (e.g., a body containing bulk silicon or another semiconductor material), this could cause an electrical short circuit between the conductive wire 113 and the semiconductor material of the body of the device 104. However, the layer 224 of dielectric material prevents or at least reduces the possibility of such an electrical short circuit. In one example, an additional (or alternative) layer of dielectric material 224 may function as a patterning stop layer, such as a laser stop layer, when the conductive material blanket-deposited on the surface of the device 104 is patterned to form conductive wires 113.

[0043]

[0050] Figure 3 shows a plan view or top view of the first device 104 of Figures 1 and 2, having a corresponding portion of the conductive wire 113 on the top surface 115u of the first device 104 according to one embodiment of the present disclosure. In the plan view of Figure 3, all contours of the four sides 115s1, 115s2, 115s3, and 115s4 are visible. In the example in Figure 3, (i) one or more of the first conductive wires 113 extend from the top surface 115u to the side surface 115s1 (such as conductive wire 113a in Figure 1), (ii) one or more of the second conductive wires 113 extend from the top surface 115u to the side surface 115s2 (such as conductive wire 113b in Figure 1), (iii) one or more of the third conductive wires 113 extend from the top surface 115u to the side surface 115s3, and (iv) one or more of the fourth conductive wires 113 extend from the top surface 115u to the side surface 115s4.

[0044]

[0051] Therefore, in the example in Figure 3, conductive wires are formed on all of the sides 115s1, ..., 115s4. However, in another example, there may be conductive wires 113 extending from the top surface 115u to one or more of the sides 115s1, ..., 115s4 of the device 104, but not all of them.

[0045]

[0052] Figure 3 also shows the contour of the interconnect element 112a on the conductive wire 113a (using dotted lines). Other conductive wires may include corresponding interconnect elements, which may be, for example, solder balls or solder bumps (or may comprise gold stud bumps, thermosonic bonds, anisotropic conductive paste, or other suitable interconnect elements).

[0046]

[0053] Figure 4 shows a perspective view of the first device 104 of Figures 1 to 3, having a plurality of conductive wires 113 on one or more surfaces of the first device 104 according to one embodiment of the present disclosure. In the example of Figure 4, a plurality of conductive wires 113 are shown, including the conductive wires 113a described above with respect to Figures 1 to 3.

[0047]

[0054] Figure 4 shows the top surface 115u along with two sides 115s1 and 115s3. Conductive wires 113 on the top surface 115u and side 115s1 are shown. Similarly, conductive wires may exist on the top surface 115u and side 115s3, but such conductive wires are not shown in Figure 4.

[0048]

[0055] The conductive wire 113a labeled in Figure 4 will be described below, but this description may also apply to one or more other conductive wires 113. As can be seen from the figure, the conductive wire 113a has various segments 404a, 404b, 408a, and 408b, and the segments make angles different from 180 degrees with respect to adjacent segments (for example, two adjacent segments do not form a straight line but extend in different directions). Thus, the segments of the conductive wire are straight segments of the conductive wire, without any bends or curves within them.

[0049]

[0056] For example, as explained with respect to Figure 2 and also illustrated in Figure 4, the conductive wire 113a has a first portion 204 on the upper surface 115u of the device 104, a second portion 208 on the side surface 115s1 of the device 104, and a third portion 212 on the lower surface 115L of the device 104 (the third portion 212 is not visible in the perspective view of Figure 4). As illustrated in Figure 4, each such portion may have one or more segments that are at an angle to adjacent segments.

[0050]

[0057] For example, a portion 204 of the conductive wire 113a (e.g., on the upper surface 115u) has a first segment 404a and a second segment 404b, where segments 404a and 404b are at angles different from 180 degrees (for example, in the example in Figure 4, the angle is approximately 90 degrees). Similarly, a portion 208 of the conductive wire 113a (e.g., on the side surface 115s1) has a first segment 408a and a second segment 408b, where segments 408a and 408b are at angles different from 180 degrees (for example, in the example in Figure 4, the angle is obtuse).

[0051]

[0058] The number of segments and the angles of adjacent segments shown in Figure 4 are merely examples; it should be noted that the conductive wire 113a may have more or fewer segments in each section, and adjacent segments may have different angles.

[0052]

[0059] As will be described later, the conductive wire 113a is formed using a subtractive process. For example, to form a portion of the conductive wire 113a, a conductive material is blanket-deposited on the corresponding surface of the die 104, and then the portion of the conductive wire 113a is patterned, for example, using a laser beam. Since the conductive wire 113a is patterned using a laser beam, it is relatively easy to have any number of segments and / or any angle between segments (for example, this can be achieved by moving the laser beam in a specific pattern on the blanket-deposited conductive material). For example, there may be one, two, three, or more segments within a corresponding portion of the conductive wire 113a (e.g., portions 204, 208).

[0053]

[0060] In contrast, conductive wires may be formed using an additive process in which each segment of the conductive wire portion is deposited using a corresponding deposition process and a corresponding mask, and blanket deposition and patterning of the deposited material are not involved. Therefore, in the case of additively formed conductive wires, forming two or more segments for each portion of the conductive wire requires two or more masks correspondingly, making the formation process difficult. Thus, when conductive wires are additively formed, a portion of the conductive wire may have only one corresponding segment, due to the challenge of forming multiple segments for each portion of the conductive wire, for example.

[0054]

[0061] Figure 4 also illustrates a magnified view of a portion 411 of the conductive wire 113a formed using a subtractive process, where portion 411 shows segment 404a joining with segment 404b. As shown, the intersection 428 between segments 404a and 404b is sharp, with no overhang of segments 404a and 404b. Such a precise intersection is possible because a laser beam is used when patterning the conductive wire 113a from the blanket-deposited conductive material.

[0055]

[0062] Figure 4 also illustrates a portion 417 of a conductive wire formed using the additive process described above. For example, forming a multi-segment conductive wire using an additive process is difficult because, as described above, the formation of each segment requires a corresponding mask and a corresponding deposition process. Furthermore, even when forming two segment portions using an additive process, the segments are not perfectly aligned, as shown in the figure, because, for example, it is practically difficult to perfectly align the masks for forming the segments. For example, the additionally formed portion 417 includes segments 424a and 424b, with an intersection 428 between segments 424a and 424b. Since two different masks are used to form the two segments 424a and 424b, the two segments 424a and 424b are most likely not aligned (for example, because it is practically difficult to perfectly align the masks for forming the segments), as shown in Figure 4, with the overhang 432a of segment 424a intersecting the intersection 428 and the overhang 432b of segment 424b intersecting the intersection 428.

[0056]

[0063] Furthermore, in the case of an additively formed conductive wire, since the two segments 424a and 424b are deposited using two different deposition processes, a seam or interface exists between segments 424a and 424b. In contrast, in the case of a conductive wire 113a formed using a subtractive process, since the conductive material deposition process is common to both segments 404a and 404b, there is no seam or interface between segments 404a and 404b.

[0057]

[0064] For similar reasons, since two additionally formed conductive wires (e.g., on two surfaces of the corresponding device) are deposited using two different deposition processes, a seam or interface will exist between any two adjacent parts. In contrast, as described above with respect to Figure 2, there may be no seam or interface between parts 204 and 208 of conductive wire 113a, and / or between parts 208 and 212 of conductive wire 113a.

[0058]

[0065] Furthermore, for additionally formed conductive wires, the conductive material on the intersection 428 of the two segments 424a and 424b is deposited twice (for example, deposited as part of the formation of segment 424a and again as part of the formation of segment 424b). This increases the thickness of the conductive material at the intersection 428. Therefore, for additionally formed conductive wires, the thickness of the conductive wire at the intersection of the two segments is approximately twice the thickness of the conductive wire in the non-intersecting portion.

[0059]

[0066] In contrast, the height or thickness of the conductive wire 113a formed using a subtractive process is substantially uniform (for example, because the conductive material for the entire portion 204 is blanket-deposited and then patterned using the same deposition process). For example, the thickness of portion 204 of the conductive wire 113 (measured in a direction perpendicular to the length and width of the conductive wire 113a, such as perpendicular to the Z-axis in Figure 4) may be T1 at the intersection 418 of the two segments 404a and 404b and T2 at the non-intersecting portion of the two segments. In one example, T1 and T2 are substantially the same. For example, thicknesses T1 and T2 may differ by up to 20% of either thickness T1 and T2, up to 15% of either thickness T1 and T2, up to 10% of either thickness T1 and T2, up to 5% of either thickness T1 and T2, up to 2% of either thickness T1 and T2, or up to 1% of either thickness T1 and T2.

[0060]

[0067] Figure 5 illustrates another perspective view of the first device 104 of Figures 1 to 4, having a plurality of conductive wires 113 on one or more surfaces of the first device 104 according to one embodiment of the present disclosure. For example, all six surfaces of the device 104 are visible in Figure 5. A plurality of exemplary conductive wires 113 are illustrated. The device 104 is illustrated to be transparent for illustrative purposes. Parts of conductive wires that are not visible because they are behind the surfaces of the device 104 are indicated using dotted lines in Figure 5. Some of the conductive wires are illustrated to have segments within a portion of the conductive wire. Note that the location, number, and / or shape of the conductive wires are merely examples, as illustrated in Figure 5. Figure 5 will become clear based on the above description relating to Figures 1 to 4.

[0061]

[0068] In one example, a first conductive wire may need to cross a second conductive wire, for example, to form an interconnection structure with a redistribution layer (RLD), or to facilitate better routing of the conductive wires. In such an example, a dielectric material is deposited between the two conductive wires. For example, when forming a conductive wire (described later), the first conductive material can be deposited and patterned to form the first conductive wire. After this, the second conductive material can be deposited above the first conductive wire and patterned to form the second conductive wire. Thus, the first and second conductive wires may cross each other or may be separated by an intervening layer of dielectric material (for example, to avoid electrical short circuits between the two conductive wires).

[0062]

[0069] Figure 6A shows a magnified view of a portion of the first conductive wire 113 described with respect to Figures 1 to 5 according to one embodiment of the present disclosure; Figure 6B shows a magnified view of a portion of the second conductive wire 613 which may be formed using an additive process; and Figure 6C shows a magnified view of a portion of the third conductive wire 623 which may be formed using a lithography process. Each of Figures 6A to 6C shows a plan view of the wire corresponding to the top of the figure and a cross-sectional view of the wire corresponding to the bottom of the figure. For example, as shown in Figure 6A, the conductive wire 113 formed using a subtractive process is patterned using a laser beam, resulting in sharp or crisp edges as shown in the plan view. Also, as shown in the cross-sectional view, the corners are approximately 90 degrees, resulting in a square or rectangular cross-sectional shape. In contrast, in Figure 6B, for the additively formed conductive wire 613, the conductive material is deposited using one or more masks. As a result, as shown in Figure 6B, a main path of conductive material is formed directly beneath the mask, and several conductive materials are formed on both sides of the main path. Therefore, as shown in Figure 6B, the edges of conductive wire 613 are blurred compared to the edges of conductive wire 113. Also, due to the additional properties of the deposition process using the mask, the cross-sectional view has a bell shape in Figure 6B. The line 623 formed by the lithography process may be sharp (e.g., similar plan views in Figures 6A and 6C). However, the cross-sectional view of line 623 may have a trapezoidal shape, as shown in Figure 6C.

[0063] Formation method

[0070] Figure 7 illustrates a flowchart of a method 700 for forming the conductive wires 113a of the integrated circuit structure 100 of Figures 1 to 5, according to one embodiment of the present disclosure. Figures 8A1, 8A2, 8B1, 8B2, 8C1, 8C2, 8D1, 8D2, and 8E collectively illustrate exemplary integrated circuit structure 100 at various stages of processing according to the method 700 of Figure 7, according to one embodiment of the present disclosure. Figures 7 and 8A1 to 8E are described together.

[0064]

[0071] Figures 8A1, 8B1, 8C1, and 8D1 illustrate cross-sectional views of device 104, similar to the cross-sectional view in Figure 1. Figures 8A2 and 8B2 are bottom views of device 104, for example, viewed along the line A-A' in Figure 8A1. Therefore, Figures 8A2 and 8B2 illustrate the lower surface 115L of device 104.

[0065]

[0072] Figures 8C2 and 8D2 are, for example, top or top views of device 104 as seen along the line B-B' in Figure 8C1. Therefore, Figures 8C2 and 8D2 illustrate the top surface 115u of device 104.

[0066]

[0073] Method 700 describes the formation of one conductive wire 113a, and the process of Method 700 can be applied to form various other conductive wires 113 on the device 104. Referring to Method 700 in Figure 7, for example, depending on the technique used to form the conductive wire 113, processes 704 and 708 may be performed, or alternatively, process 712 may be performed.

[0067]

[0074] In processes 704 and 708, the deposition / patterning of conductive materials on various surfaces of device 104 is carried out using different processes. For example, referring to process 704, a first conductive material is deposited on a first surface of device 104, and the first conductive material on the first surface is patterned to form a first portion of the conductive wire 113a. Subsequently, in 708, a second conductive material is deposited on second and third surfaces of device 104, and the second conductive material on the second and third surfaces is patterned to form a second portion and a third portion of the conductive wire 113a, respectively.

[0068]

[0075] The first surface of process 704 may be any one surface of device 104, and the second and third surfaces of process 708 may be any two remaining surfaces of device 104. For example, the first surface of process 704 may be the bottom surface 115L of device 104, and the second and third surfaces of process 708 may be the side surface 115s1 and the top surface 115u of device 104. In another example, the first surface of process 704 may be the top surface 115u of device 104, and the second and third surfaces of process 708 may be the side surface 115s1 and the bottom surface 115L of device 104.

[0069]

[0076] In one embodiment, the deposition of the first and second conductive materials in processes 704 and 708 may be carried out using any suitable deposition technique (e.g., conformal deposition technique), such as sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), or liquid-phase epitaxy (LPE).

[0070]

[0077] In one embodiment, the patterning of processes 704 and 708 may be performed using a laser beam. For example, laser cutting or shredding can be used to pattern the conductive material and form conductive wires. For example, the laser beam is moved across the corresponding surface using appropriate techniques, for example, by using a galvanometer or a laser beam that is otherwise directed, and the galvanometer (which is an electromechanical instrument) is used to deflect the laser beam by using a mirror so that the laser projection is moved in a specific pre-configured pattern over the conductive material on the corresponding surface of device 104 and selectively removes the first and second conductive materials. The portions of conductive material that are not removed by the laser beam remain on the surface of device 104 and form conductive wires 113.

[0071]

[0078] In one example, the dielectric material layer 224 (see Figure 2) may function as a laser stop layer to prevent, or at least reduce, the opportunity for a laser beam to etch, remove, or otherwise adversely affect or damage the body of the device 104 located beneath the layer 224.

[0072]

[0079] In one example, since the second conductive material is deposited on the second and third surfaces using the same deposition process, there may be no seam or interface between the second and third portions of the conductive wire 113a, and the second and third portions of the conductive wire 113a may be a monolithic conductive structure.

[0073]

[0080] Figures 8A1 to 8D2 illustrate device 104 during processes 704 and 708. In the example of Figures 8A1 to 8D2, the first surface of process 704 is assumed to be the bottom surface 115L of device 104, and the second and third surfaces of process 708 are assumed to be the side surface 115s1 and top surface 115u of device 104.

[0074]

[0081] For example, Figures 8A1 and 8A2 illustrate conformal and blanket deposition of the first conductive material 713 on the lower surface 115L of the device 104. Figures 8B1 and 8B2 illustrate patterning of the first conductive material 713 on the lower surface 115L of the device 104 to form corresponding portions of conductive wires 113 on the lower surface 115L of the device 104.

[0075]

[0082] Figures 8C1 and 8C2 illustrate conformal and blanket deposition of the second conductive material 723 on the top surface 115u and sides 115s1 and 115s2 of device 104. Figures 8D1 and 8D2 illustrate patterning of the second conductive material 723 on the top surface 115u and sides 115s1 and 115s2 of device 104 for forming corresponding portions of conductive wires 113 on the top surface 115u and sides 115s1 and 115s2 of device 104.

[0076]

[0083] As shown in Figure 7, process 712 may be performed instead of processes 704 and 708. In process 712, the conductive material is blanket-deposited on the first, second, and third surfaces of the device 104 (for example, deposited using the same deposition process), and the deposited conductive material on the first, second, and third surfaces is patterned (for example, using the same patterning process) to form the first, second, and third portions of the conductive wire 113a, respectively. Thus, process 712 combines processes 704 and 708.

[0077]

[0084] In one example, the conductive material is deposited on the first, second, and third surfaces using the same deposition process, so there may be no seams or interfaces between the first, second, and third parts of the conductive wire 113a. Therefore, the first, second, and third parts of the conductive wire 113a (for example, the entire conductive wire 113a) can be a monolithic conductive structure.

[0078]

[0085] The deposition of process 712 can be carried out using any suitable deposition technique (e.g., conformal deposition technique), such as sputtering, CVD, PVD, ALD, VPE, MBE, or LPE. In one embodiment, the patterning of process 712 can be carried out using a laser beam, as described above, for example, by laser cutting or fracturing.

[0079]

[0086] Method 700 then proceeds to 708 or 712 through 716, where the first interconnection component 112a is coupled to a portion of the conductive wire 113a on the upper surface 115u of device 104, as shown in Figure 8E, and the second interconnection component 114a is coupled to another portion of the conductive wire 113a on the lower surface 115L of device 104. In one example, another interconnection component 116 may already be present on the lower surface 115L of device 104 and / or may be coupled in process 716, as shown in Figure 8E. Although not shown in Figure 7, devices 108 and 120 may then be coupled to device 104, for example, via interconnection components 112, 114, and 116, as shown in Figure 8E.

[0080]

[0087] It should be noted that the processes in Method 700 are presented in a specific order for the sake of clarity. However, according to some embodiments, one or more of the processes may be performed in a different order, or not at all (and therefore may be optional). Based on this disclosure, numerous variations of Method 700 and the techniques described herein will become apparent.

[0081] Further exemplary embodiments

[0088] The following examples relate to further embodiments, from which numerous substitutions and configurations will become apparent.

[0082]

[0089] Example 1 A microelectronic device structure comprising: a device having (i) a bottom surface, (ii) an upper surface opposite to the bottom surface, and (iii) a side surface extending between the bottom surface and the upper surface; and a conductive wire having (i) a first portion on the upper surface, (ii) a second portion on the side surface, and (iii) a third portion on the bottom surface, wherein the first and second portions of the conductive wire are monolithic conductive structures without a joint or interface between the first and second portions, and / or the second and third portions of the conductive wire are monolithic conductive structures without a joint or interface between the second and third portions.

[0083]

[0090] Example 2 A microelectronic device structure according to Example 1, further comprising a first contact pad on a first portion of a conductive wire, the first contact pad being configured to receive a first interconnection element, and a second contact pad on a third portion of the conductive wire, the second contact pad structure being configured to receive a second interconnection element.

[0084]

[0091] Example 3: The microelectronic device structure according to Example 2, further comprising a first interconnection element and a second interconnection element, wherein the first interconnection element is a solder ball or solder bump, and the second interconnection element is a solder ball or solder bump.

[0085]

[0092] Example 4 A microelectronic device structure according to any one of Examples 1 to 3, wherein the device is a first device, and the integrated circuit structure further comprises a second device above the first device and an interconnection component configured to connect the second device to a first portion of a conductive wire.

[0086]

[0093] Example 5: The microelectronic device structure according to Example 4, wherein the interconnecting component is a first interconnecting component, the integrated circuit structure further comprising a third device below the first device and a second interconnecting component configured to connect a third portion of a conductive wire to the third device.

[0087]

[0094] Example 6: A microelectronic device structure according to any one of Examples 1 to 5, wherein the first, second, and third portions of the conductive wire are part of a monolithic conductive structure with no joints or interfaces between the first, second, and third portions.

[0088]

[0095] Example 7 A microelectronic device structure according to any one of Examples 1 to 6, wherein at least one of the first, second, or third portions of the conductive wire comprises a first segment and a second segment, and the first segment and the second segment intersect at an intersection at an angle different from 180 degrees.

[0089]

[0096] Example 8: The microelectronic device structure according to Example 7, wherein the first thickness of the conductive wire at the intersection and the second thickness of the conductive wire at the non-intersection of the first portion are within 5% of each other.

[0090]

[0097] Example 9 A system comprising: a first device having (i) a bottom surface, (ii) an upper surface opposite to the bottom surface, and (iii) a side surface extending between the bottom surface and the upper surface; a second device above the first device; a third device below the first device; a continuous conductive wire extending over the upper surface, side surface, and bottom surface of the first device, wherein a portion of the conductive wire extending over at least two adjacent surfaces of the first die is monolithic without containing any seams or interfaces; (i) a first interconnection component coupled between the second device and (ii) the portion of the conductive wire on the upper surface of the first device; and (i) a third device and (ii) a second interconnection component coupled between the portion of the conductive wire on the bottom surface of the first device.

[0091]

[0098] Example 10: The system according to Example 9, wherein the first device is a first integrated circuit die or a first integrated circuit package, the second device is a second integrated circuit die or a second integrated circuit package, and the third device is a third integrated circuit die, a third integrated circuit package, or a circuit board.

[0092]

[0099] Example 11: The system according to Example 9 or 10, wherein the first interconnection element is a solder ball or solder bump, and the second interconnection element is a solder ball or solder bump.

[0093]

[0100] Example 12 The system according to any one of Examples 9 to 11, wherein a portion of a conductive wire extending over one of the lower, side, or upper surfaces of the first die comprises a first segment and a second segment, the first segment and the second segment intersect at an intersection at an angle different from 180 degrees, and the first thickness of the conductive wire at the intersection and the second thickness of the conductive wire at the non-intersection of the portion are within 5% of each other.

[0094]

[0101] Example 13 A method comprising depositing a first conductive material on a first surface of an integrated circuit device; patterning the first conductive material on the first surface to form a first portion of a conductive wire; depositing a second conductive material on a second surface and a third surface of the integrated circuit device; and having one of the second or third surfaces substantially perpendicular to the first surface, and patterning the second conductive material on the second and third surfaces to form a second portion and a third portion of a conductive wire on the second surface and the third surface of the integrated circuit device, respectively, wherein the conductive wire is a continuous structure extending over the first surface, the second surface and the third surface of the integrated circuit device.

[0095]

[0102] Example 14 The method of Example 13, further comprising coupling a first interconnection component onto a first portion of a conductive wire located on a first surface, and coupling a second interconnection component onto a third portion of a conductive wire located on a third surface opposite to the first surface.

[0096]

[0103] Example 15 The method of Example 14, wherein the integrated circuit device is a first integrated circuit device, and the method further comprises coupling a second integrated circuit device to a first interconnection component and coupling a third integrated circuit device to a second interconnection component.

[0097]

[0104] Example 16 The method according to Example 14 or 15, wherein the first interconnection component is a solder ball or solder bump, and the second interconnection component is a solder ball or solder bump.

[0098]

[0105] Example 17: The method according to any one of Examples 13 to 16, wherein the first conductive material and the second conductive material are deposited using the same deposition process.

[0099]

[0106] Example 18: The method according to any one of Examples 13 to 17, wherein the first conductive material and the second conductive material are patterned using the same patterning process.

[0100]

[0107] Example 19 The method according to any one of Examples 13 to 18, wherein the second conductive material is deposited after patterning the first conductive material.

[0101]

[0108] Example 20 The method according to any one of Examples 13 to 19, wherein patterning the first conductive material and the second conductive material is performed using a corresponding laser beam.

[0102]

[0109] The foregoing description of exemplary embodiments has been presented for illustrative and explanatory purposes only. It is not intended to be exhaustive or to limit this disclosure to the exact form disclosed. Many modifications and variations are possible based on this disclosure. The scope of this disclosure is intended to be limited not by this detailed description, but rather by the claims appended to this specification. Future applications claiming priority to this application may assert the disclosed subject matter in different ways and may generally include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.

Claims

1. A microelectronic device structure, A device having (i) a lower surface, (ii) an upper surface opposite to the lower surface, and (iii) a side surface extending between the lower surface and the upper surface, (i) a conductive wire having a first portion on the upper surface, (ii) a second portion on the side surface, and (iii) a third portion on the lower surface, Here, The first and second portions of the conductive wire are monolithic conductive structures and / or The second and third portions of the conductive wire are a monolithic conductive structure, forming a microelectronic device structure.

2. A first contact pad is located on the first portion of the conductive wire, and the first contact pad is configured to receive a first interconnection component. The microelectronic device structure according to claim 1, further comprising a second contact pad on the third portion of the conductive wire, wherein the second contact pad is configured to receive a second interconnection component.

3. The microelectronic device structure according to claim 2, further comprising a first interconnection element and a second interconnection element, wherein the first interconnection element is a solder ball or solder bump, and the second interconnection element is a solder ball or solder bump.

4. The aforementioned device is a first device, and in this case, the integrated circuit structure is A second device above the first device, The microelectronic device structure according to claim 1, further comprising an interconnection component configured to couple the second device to the first portion of the conductive wire.

5. The aforementioned interconnection component is a first interconnection component, and in this case, the integrated circuit structure is A third device located below the first device, The microelectronic device structure according to claim 4, further comprising a second interconnection component configured to connect the third portion of the conductive wire to the third device.

6. The microelectronic device structure according to claim 1, wherein the first, second, and third portions of the conductive wire are part of a monolithic conductive structure that does not have joints or interfaces between the first, second, and third portions.

7. The microelectronic device structure according to claim 1, wherein at least one of the first, second, or third portions of the conductive wire comprises a first segment and a second segment, and the first segment and the second segment intersect at an intersection at an angle different from 180 degrees.

8. The microelectronic device structure according to claim 7, wherein the first thickness of the conductive wire at the intersection and the second thickness of the conductive wire at the non-intersection of the first portion are within 5% of each other.

9. It is a system, A first device having (i) a lower surface, (ii) an upper surface opposite to the lower surface, and (iii) a side surface extending between the lower surface and the upper surface, A second device above the first device, A third device located below the first device, A continuous conductive wire extends onto the top surface, side surface, and bottom surface of the first device, and a portion of the conductive wire extending onto at least two adjacent surfaces of the first die is monolithic. (i) the second device and (ii) the portion of the conductive wire on the upper surface of the first device, A system comprising (i) the third device and (ii) a second interconnection component coupled between the portion of the conductive wire on the lower surface of the first device.

10. The first device is a first integrated circuit die or a first integrated circuit package, The second device is a second integrated circuit die or a second integrated circuit package, The system according to claim 9, wherein the third device is a third integrated circuit die, a third integrated circuit package, or a circuit board.

11. The system according to claim 9, wherein the first interconnection element is a solder ball or solder bump, and the second interconnection element is a solder ball or solder bump.

12. The portion of the conductive wire extending onto one of the lower, side, or upper surfaces of the first die comprises a first segment and a second segment, the first segment and the second segment intersect at an angle different from 180 degrees, The system according to claim 9, wherein the first thickness of the conductive wire at the intersection and the second thickness of the conductive wire at the non-intersection of the portion are within 5% of each other.

13. It is a method, Depositing a first conductive material on a first surface of an integrated circuit device, Patterning the first conductive material on the first surface to form a first portion of a conductive wire, A second conductive material is deposited on the second and third surfaces of the integrated circuit device, and one of the second or third surfaces is substantially perpendicular to the first surface. A method comprising patterning the second conductive material on the second surface and the third surface of the integrated circuit device such that the second and third portions of the conductive wire are formed on the second and third surfaces, respectively, wherein the conductive wire is a continuous structure extending on the first surface, the second surface, and the third surface of the integrated circuit device.

14. The first interconnection component is connected to the first portion of the conductive wire on the first surface, The method according to claim 13, further comprising coupling a second interconnection component onto the third portion of the conductive wire located on the third surface opposite to the first surface.

15. The aforementioned integrated circuit device is a first integrated circuit device, and the method described herein is The method according to claim 14, further comprising coupling a second integrated circuit device to the first interconnection component and coupling a third integrated circuit device to the second interconnection component.

16. The method according to claim 14, wherein the first interconnection component is a solder ball or solder bump, and the second interconnection component is a solder ball or solder bump.

17. The method according to claim 13, wherein the first conductive material and the second conductive material are deposited using the same deposition process.

18. The method according to claim 13, wherein the first conductive material and the second conductive material are patterned using the same patterning process.

19. The method according to claim 13, wherein the second conductive material is deposited after patterning the first conductive material.

20. Patterning the first conductive material and the second conductive material is The method according to claim 13, further comprising patterning the first conductive material and the second conductive material using a corresponding laser beam.

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