Prediction of optimal parameters for physical design synthesis

Abstract

Prediction of optimal parameters for physical design synthesis Embodiments of this disclosure provide an improved system and method for predicting optimal design flow parameters for an optimized output target for physical design synthesis of a given IC design. A variational autoencoder (VAE) is trained with a regression network and a dataset containing the synthesis design construction flow from historical IC designs is used to provide a training data representation of the dataset constrained to the latent space of the VAE. The system generates feature vectors based on the training data representation of the dataset and updates the feature vectors with the initial design characteristics of the given IC design. The system iteratively performs an input gradient search of the updated feature vectors to optimize the objective function of the design target to identify locally optimal design parameters. Based on the locally optimal design parameters, the system identifies globally optimal design flow parameters for the optimized design target.

Description

Background Art

[0001] The present invention relates to electronic design automation (EDA) for integrated circuit (IC) design, and more particularly, to predicting optimal design flow parameters for power, congestion, and timing for physical design synthesis of IC design.

[0002] Industrial digital implementation construction flows include thousands of parameters for controlling algorithms that optimize circuits. Generating an optimal set of design parameters based on given design characteristics presents a significant challenge of providing optimal power, performance, and area at the end of the construction flow with a legally placed and routable design. Currently, predicting optimal design flow parameters is generally a nondeterministic polynomial-time (NP) complete problem or a computational problem for which no efficient solution algorithm has been discovered.

[0003] Parameters for use in EDA physical design synthesis of IC design are determined using various techniques and algorithms and often involve trial and error. One technique for determining design flow parameters for physical design synthesis involves running many synthesis construction jobs with different parameter values, collecting metrics on the results of combinations of parameters, and generating parameter recommendations. The resource cost of this technique is extremely high, consuming significant runtime and processing power, requiring the execution of designs on many machines, while this technique is limited by the runtime of the construction flow.

Summary of the Invention

[0004] Embodiments of this disclosure provide a system and method for predicting optimal design flow parameters for optimized output targets for physical design synthesis of integrated circuit (IC) designs. The disclosed system and method enable the prediction of optimal design flow parameters for optimized output targets for physical design synthesis with improved runtime performance. Optimized output targets may include power, congestion, and timing output targets. According to one embodiment, a method is provided comprising the steps of: receiving initial design characteristics, design flow parameters, and a design target from a design build flow for a given integrated circuit (IC) design; receiving a historical dataset including a synthesized design build flow from a historical IC design; training a variational autoencoder (VAE) with a regression network using the historical dataset to provide a training data representation of the dataset constrained to the latent space of the VAE; generating feature vectors based on the training data representation of the dataset and updating the feature vectors with the initial design characteristics; iteratively performing an input gradient search of the updated feature vectors to optimize the objective function of the design target to identify locally optimal design parameters, wherein the training data samples are constrained to the initial design characteristics; and obtaining predictions of globally optimal design flow parameters based on the identified locally optimal design parameters for the optimized design target.

[0005] This method efficiently and effectively obtains predictions of optimal design flow parameters for offline optimized design targets using trained VAEs and regression networks. This method effectively eliminates the need for online execution of multiple synthetic design build flows on many machines to determine design flow parameters, as is done by conventional parameter prediction systems.

[0006] According to one or more preferred embodiments, the present invention effectively and efficiently predicts optimal design flow parameters for optimizing power, congestion, and timing targets for physical design synthesis of IC designs; reducing runtime; and overcoming some of the shortcomings of conventional parameter prediction systems.

[0007] According to one or more preferred embodiments, the present invention performs interpolation training of a VAE with a regression network to smooth the constrained training data points in the latent space and minimize reconstruction errors, thereby enabling more accurate parameter prediction. Preferably, the present invention performs interpolation training of the VAE with the regression network to generate interpolated vectors of the dataset, and combines the interpolated vectors with training vectors to generate an expanded dataset in each epoch.

[0008] According to one or more preferred embodiments, the present invention selects and decodes a random set of samples from a training data representation of a dataset to generate a feature vector containing design properties and design flow parameters. The system updates the generated feature vector by replacing the design properties in the generated feature vector with initial design properties from a design build flow for a given design. Preferably, the present invention iteratively performs an input gradient search of the updated generated feature vector to optimize the objective function of the design target to identify locally optimal design parameters.

[0009] In another embodiment, a system is provided comprising a processor and memory, the memory having a computer program product configured to perform operations for predicting optimal design flow parameters for physical design synthesis of a given integrated circuit (IC) design, the operations comprising: receiving initial design characteristics, design flow parameters, and a design target from a design build flow for the given integrated circuit (IC) design; receiving a historical dataset including a synthesis design build flow from a historical IC design; training a variational autoencoder (VAE) with a regression network using the historical dataset to provide a training data representation of the dataset constrained to the latent space of the VAE; generating feature vectors based on the training data representation of the dataset and updating the feature vectors with the initial design characteristics; iteratively performing an input gradient search of the updated feature vectors to optimize the objective function of the design target to identify locally optimal design parameters, where the training data samples are constrained to the initial design characteristics; and obtaining predictions of globally optimal design flow parameters based on the identified locally optimal design parameters for the optimized design target.

[0010] In another embodiment, a computer program product for performing prediction of optimal design flow parameters for physical design synthesis of a given integrated circuit (IC) design, the computer program product comprising a computer-readable storage medium in which computer-readable program code is embodied, the computer-readable program code comprising: a procedure for receiving initial design characteristics, design flow parameters, and design targets from a design build flow for a given integrated circuit (IC) design; a procedure for receiving a historical dataset including a synthesis design build flow from a historical IC design; and training a variational autoencoder (VAE) together with a regression network using the historical dataset to constrain the dataset to the latent space of the VAE. A computer program product is provided that is executable by one or more computer processors to perform operations including: providing a training data representation of; generating feature vectors based on the training data representation of the dataset and updating the feature vectors with the initial design characteristics; iteratively performing an input gradient search of the updated feature vectors to optimize the objective function of the design target to identify locally optimal design parameters, where the training data samples are constrained by the initial design characteristics; and obtaining predictions of globally optimal design flow parameters based on the identified locally optimal design parameters for the optimized design target.

[0011] Other disclosed embodiments include computer systems and computer program products for predicting optimal design flow parameters for an optimal design target for physical design synthesis of IC designs, which implement the features of the methods disclosed above. [Brief explanation of the drawing]

[0012] Herein, preferred embodiments of the present invention will be described with reference to the following drawings, merely as examples.

[0013] [Figure 1]This is a block diagram of an exemplary computer environment for use in combination with one or more disclosed embodiments for performing prediction of optimal design flow parameters for an optimized output target for physical design synthesis of IC designs.

[0014] [Figure 2] This is a block diagram of an exemplary system for performing prediction of optimal design flow parameters for physical design synthesis of one or more disclosed embodiments.

[0015] [Figure 3] This is a schematic block diagram of an exemplary variational autoencoder (VAE) combined with a regression network model of the system in Figure 2 of one or more disclosed embodiments.

[0016] [Figure 4] This document provides an illustrative flowchart of an exemplary method for performing the prediction of optimal design flow parameters for an optimal design target for physical design synthesis in one or more disclosed embodiments.

[0017] [Figure 5] The images illustrate two dimensions of the latent space for congestion, timing, and power output targets in one or more disclosed embodiments.

[0018] [Figure 6] The dataflow training phase of one or more disclosed embodiments of VAEs and combined regression networks is schematically shown.

[0019] [Figure 7] This schematic illustrates how to generate interpolated vectors for interpolation training of one or more disclosed embodiments of VAEs and combined regression networks.

[0020] [Figure 8]Schematically shows an exemplary interpolation training of a VAE and a combined regression network of one or more disclosed embodiments.

[0021] [Figure 9] Schematically shows an exemplary initialization of an optimization gradient search of one or more disclosed embodiments.

[0022] [Figure 10] Schematically shows an exemplary optimization operation for obtaining a prediction of optimal design flow parameters of one or more disclosed embodiments.

[0023] [Figure 11] Schematically shows an exemplary optimization operation for fine-tuning the optimal design flow parameters of one or more disclosed embodiments.

Mode for Carrying Out the Invention

[0024] Problems with existing parameter prediction systems include the inherent limitations in performing many synthetic construction jobs, collecting metrics on the results of parameter combinations, and generating parameter recommendations, as well as the significantly long time consumed for the runtime of the synthetic construction jobs. Embodiments of the present disclosure provide an effective and efficient technique for performing predictions of optimal design flow parameters for an optimized output target for physical design synthesis of IC designs. The disclosed systems and methods can perform predictions of optimal design flow parameters for an optimized output target, resulting in a significant speedup over conventional parameter identification configurations and reducing the computing resources required.

[0025] In one embodiment, the disclosed system uses an offline machine learning neural network model, which includes a variational autoencoder (VAE) that provides dimensionality reduction in combination with a regression network, to generate predictions of optimal design flow parameters for an optimized output target for physical design synthesis of a given integrated circuit (IC) design. By combining the VAE with the regression network, the system is trained to model the features that influence the regression while simultaneously obtaining the benefits of the VAE, which include the construction of a constrained latent space and the generalization of input features. Since the latent space is centered at the origin, the inventors can use the radius of a point in the latent space to compare with the radius of the inventors' training points in the latent space to determine whether it is within or outside the domain of the inventors' training. Since neural networks cannot extrapolate and can only interpolate where they are trained, if interpolation is attempted in an untrained latent space, it will result in unreliable predictions. When a simple autoencoder is used to reduce dimensionality, it is not easy to determine whether a data point is part of the trained latent space, as data points can be mapped to any location. On the other hand, VAE constrains the latent space, so that all data points map to each other in proximity within the latent space.

[0026] In one embodiment, the system receives a historical dataset, which includes features and metrics from a synthesis design build flow from historical IC designs. Target metrics may include selected design targets used at the end of the design build flow to recognize and optimize targets such as congestion, timing, and power. For example, target labels and metrics may include names and values ​​of targets such as congestion (weighted mean congestion estimate), timing (sum of negative slack between latches), and total power (sum of leakage power and dynamic power). The system uses the historical dataset to train a VAE with a regression network to provide a training data representation of the dataset constrained to the latent space of the VAE.

[0027] In one embodiment, the disclosed system performs interpolation training to smooth the training data points in the latent space and minimize reconstruction errors for the interpolated values, thereby enabling more accurate parameter predictions. The system can interpolate points sampled from a machine-trained latent space representation of the dataset.

[0028] In one embodiment, the system generates a feature vector based on the training data representation of the dataset and updates the feature vector with the initial design characteristics. The system iteratively performs an input gradient search of the updated feature vector to optimize the objective function of the design target to identify locally optimal design parameters, where the updated feature vector is constrained by the initial design characteristics of a given IC design. The prediction of the globally optimal design flow parameters is based on the identified locally optimal design parameters for the optimized design target, such as congestion, timing, and power output targets. The system sorts the locally optimal constrained latent space samples based on their selected contributions to the objective function and selects the optimal latent points of the constrained samples to use for prediction. During optimization, the radius of each point in the latent space is calculated in terms of standard deviation for each dimension. Collapsed dimensions are treated as if they had a standard deviation of 1. A loss function equal to the square of the radius is added, which is called the wander. This encourages the gradient search to stay in the latent space covered by the training data. The system obtains predictions of optimal design flow parameters for optimal power, congestion, and timing targets based on selected optimal latent points. This method effectively performs optimized design flow parameter predictions using offline machine learning and trained latent spaces without involving online execution of multiple synthetic design build flows on many machines, as performed by conventional parameter prediction systems.

[0029] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or to limit the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments described. The terminology used herein has been selected to best describe the principles of the embodiments, practical applications or technical improvements to the art found in the market, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

[0030] The following references are to embodiments presented in this disclosure. However, the scope of this disclosure is not limited to the specific embodiments described. Instead, any combination of the following features and elements, whether related to a different embodiment or not, is intended to carry out and practice the intended embodiments. Furthermore, while embodiments disclosed herein may achieve advantages over other possible solutions or the prior art, whether or not a particular advantage is achieved by a given embodiment does not limit the scope of this disclosure. Therefore, the following aspects, features, embodiments and advantages are merely illustrative and shall not be considered elements or limitations of the appended claims unless expressly stated in the claims. Similarly, references to “the present invention” shall not be construed as generalizations of the subject matter of any invention disclosed herein and shall not be considered elements or limitations of the appended claims unless expressly stated in the claims.

[0031] Various aspects of this disclosure are described by explanatory text, flowcharts, block diagrams of computer systems and / or block diagrams of machine logic included in computer program product (CPP) embodiments. With respect to any flowchart, depending on the technology involved, operations may be performed in a different order than those shown in a given flowchart. For example, again depending on the technology involved, two operations shown in consecutive flowchart blocks may be performed in reverse order, as a single integrated stage, simultaneously, or with at least partial time overlap.

[0032] Computer program product embodiment ("CPP embodiment" or "CPP") is a term used in this disclosure to describe any set of one or more storage media ("mediums") that collectively comprise a set of one or more storage devices that collectively contain machine-readable code corresponding to instructions and / or data for performing computer operations specified in a given CPP claim. A "storage device" is any tangible device capable of holding and storing instructions for use by a computer processor. Computer-readable storage media may be, but are not limited to, electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, mechanical storage media, or any suitable combination of those described above. Some known types of storage devices, including these media, include diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices (such as pits / lands formed on the main surface of a punch card or disk), or any suitable combination of the foregoing. When the term "computer-readable storage medium" is used in this disclosure, it shall not be interpreted as storage in the form of a transient signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides, optical pulses passing through optical fiber cables, electrical signals communicated through wires, and / or other transmission media.As those skilled in the art will understand, data is typically moved at several intermittent points during the normal operation of a storage device, such as during access, defragmentation, or garbage collection; however, data is not transient while it is stored, and therefore, a storage device is not transient.

[0033] Referring to Figure 1, the computing environment 100 includes an example of an environment for executing at least a portion of the computer code involved in executing the method of the present invention, such as the parameter predictive control component 182 in block 180, the feature target metric dataset 184, and the hyperparameters and values ​​186. In addition to block 180, the computing environment 100 includes, for example, a computer 101, a wide area network (WAN) 102, an end user device (EUD) 103, a remote server 104, a public cloud 105, and a private cloud 106. In this embodiment, the computer 101 includes a processor set 110 (including processing circuits 120 and a cache 121), a communication fabric 111, volatile memory 112, persistent storage 113 (including an operating system 122 and block 180 as identified above), a peripheral device set 114 (including a user interface (UI) device set 123, storage 124, and an Internet of Things (IoT) sensor set 125), and a network module 115. The remote server 104 includes the remote database 130. The public cloud 105 includes the gateway 140, the cloud orchestration module 141, the host physical machine set 142, the virtual machine set 143, and the container set 144.

[0034] Computer 101 may take the form of a desktop computer, laptop computer, tablet computer, smartphone, smartwatch or other wearable computer, mainframe computer, quantum computer, or any other form of computer or mobile device currently known or to be developed in the future that is capable of running programs, accessing networks, or querying databases such as remote database 130. As is well understood in the field of computer technology, and depending on the technology, the execution of the computer implementation method may be distributed among multiple computers and / or across multiple locations. On the other hand, in this presentation of the computing environment 100, in order to keep the presentation as concise as possible, the detailed discussion focuses on a single computer, specifically computer 101. Computer 101 is not shown in the cloud in Figure 1, but it may be located in the cloud. On the other hand, computer 101 is not required to be located in the cloud, except to any extent that can be definitively shown.

[0035] The processor set 110 includes one or more computer processors of any type currently known or to be developed in the future. The processing circuitry 120 may be distributed across multiple packages, for example, multiple coordinated integrated circuit chips. The processing circuitry 120 may implement multiple processor threads and / or multiple processor cores. The cache 121 is memory located within the processor chip package and is typically used for data or code that should be available for high-speed access by threads or cores running on the processor set 110. The cache memory is typically organized into multiple levels, depending on its relative proximity to the processing circuitry. Alternatively, some or all of the cache for the processor set may be located "off-chip". In some computing environments, the processor set 110 may function using qubits and be designed to perform quantum computing.

[0036] Computer-readable program instructions typically cause a set of operational steps to be executed by the processor set 110 of computer 101, thereby loading them onto computer 101 to implement a computer implementation method, and thereby the instructions thus executed instantiate the methods specified in the flowcharts and / or descriptions of the computer implementation methods contained herein (collectively referred to as the "Methods of the Invention"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as a cache 121 and other storage media discussed below. The program instructions and associated data are accessed by the processor set 110 to control and direct the execution of the Methods of the Invention. In the computing environment 100, at least some of the instructions for executing the Methods of the Invention may be stored in blocks 180 in persistent storage 113.

[0037] The communication fabric 111 is a signal conduction path that enables various components of the computer 101 to communicate with one another. Typically, this fabric is made up of switches and conductive paths, such as buses, bridges, physical input / output ports, and similar switches and conductive paths. Other types of signal communication paths, such as optical fiber communication paths and / or wireless communication paths, may be used.

[0038] The volatile memory 112 is any type of volatile memory currently known or to be developed in the future. Examples include dynamic type random access memory (RAM) or static type RAM. Typically, the volatile memory 112 is characterized by random access, but this is not required unless explicitly stated. In computer 101, the volatile memory 112 is located in a single package and resides inside computer 101, but alternatively or in addition, the volatile memory may be distributed across multiple packages and / or located externally to computer 101.

[0039] The persistent storage 113 is any form of non-volatile storage for a computer, currently known or to be developed in the future. The non-volatility of this storage means that the stored data is maintained whether or not power is directly supplied to the computer 101 and / or the persistent storage 113. The persistent storage 113 may be read-only memory (ROM), but typically at least a portion of the persistent storage allows for writing, deleting, and rewriting of data. Some well-known forms of persistent storage include magnetic disks and solid-state storage devices. The operating system 122 may take several forms, such as various known proprietary operating systems or open-source portable operating system interface (CSI) type operating systems employing a kernel. The code contained in block 180 typically includes at least a portion of computer code involved in performing the method of the present invention.

[0040] The peripheral device set 114 includes a set of peripheral devices of the computer 101. Data communication connections between the peripheral devices of the computer 101 and other components may be implemented in various ways, such as Bluetooth connections, near-field communication (NFC) connections, connections made by cables (such as universal serial bus (USB) type cables), insert-type connections (e.g., secure digital (SD) cards), connections made via local area communication networks, and even connections made via wide area networks such as the internet. In various embodiments, the UI device set 123 may include components such as a display screen, speaker, microphone, wearable devices (such as goggles and smartwatches), keyboard, mouse, printer, touchpad, game controller, and haptic device. Storage 124 is external storage such as an external hard drive, or insertable storage such as an SD card. Storage 124 may be persistent and / or volatile. In some embodiments, storage 124 may take the form of a quantum computing memory device for storing data in the form of qubits. In embodiments where computer 101 is required to have a large amount of storage (for example, computer 101 locally stores and manages a large database), this storage may be provided by peripheral storage devices designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor set 125 consists of sensors that can be used in Internet of Things applications. For example, one sensor may be a thermometer and another may be a motion detector.

[0041] The network module 115 is a collection of computer software, hardware, and firmware that enables computer 101 to communicate with other computers via the WAN 102. The network module 115 may include hardware such as a modem or Wi-Fi signal transceiver, software for packetizing and / or depacketizing data for transmission over a communication network, and / or web browser software for communicating data over the internet. In some embodiments, the network control and network forwarding functions of the network module 115 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software-defined networking (SDN)), the control and forwarding functions of the network module 115 are performed on physically separate devices, such that the control function manages several different network hardware devices. Computer-readable program instructions for performing the method of the present invention can typically be downloaded from an external computer or external storage device to computer 101 through a network adapter card or network interface included in the network module 115.

[0042] WAN102 is any wide area network (e.g., the Internet) capable of transmitting computer data over non-local distances by any currently known or future-developed technology for transmitting computer data. In some embodiments, WAN102 may be replaced and / or supplemented by a local area network (LAN), such as a Wi-Fi network, designed to transmit data between devices located in a local area. WANs and / or LANs typically include computer hardware such as copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and edge servers.

[0043] The end-user device (EUD) 103 is any computer system used and controlled by an end-user (e.g., a customer of the company operating computer 101) and can take any of the forms discussed above in relation to computer 101. Typically, EUD 103 receives useful and valuable data from the operation of computer 101. For example, in a hypothetical case where computer 101 is designed to provide recommendations to the end-user, these recommendations would typically be communicated from the network module 115 of computer 101 to EUD 103 via WAN 102. In this way, EUD 103 can display or otherwise present the recommendations to the end-user. In some embodiments, EUD 103 may be a client device such as a thin client, heavy client, mainframe computer, or desktop computer.

[0044] The remote server 104 is any computer system that provides at least some data and / or functionality to computer 101. The remote server 104 may be controlled and used by the same entity that operates computer 101. The remote server 104 represents a machine that collects and stores useful and valuable data for use by other computers, such as computer 101. For example, in the hypothetical case where computer 101 is designed and programmed to provide recommendations based on historical data, this historical data may be provided to computer 101 from the remote database 130 of the remote server 104.

[0045] The public cloud 105 is any computer system available for use by multiple entities, providing on-demand availability of computer system resources and / or other computing capabilities, particularly data storage (cloud storage) and computing power, without direct active management by the user. Cloud computing typically leverages resource sharing to achieve coherence and economies of scale. Direct active management of the computing resources of the public cloud 105 is performed by the computer hardware and / or software of the cloud orchestration module 141. The computing resources provided by the public cloud 105 are typically implemented by virtual computing environments running on various computers that make up the computers of the host physical machine set 142, which is the universe of physical computers available in and / or to the public cloud 105. The virtual computing environment (VCE) typically takes the form of virtual machines from the virtual machine set 143 and / or containers from the container set 144. These VCEs may be stored as images and are understood to be transferable either as images or after instantiation of the VCE, among and between various physical machine hosts. The cloud orchestration module 141 manages the transfer and storage of images, deploys new VCE instances, and manages active instances of the VCE deployment. The gateway 140 is a collection of computer software, hardware, and firmware that enables the public cloud 105 to communicate over the WAN 102.

[0046] Here, some further explanation of virtualized computing environments (VCEs) is provided. A VCE can be stored as an "image." A new active instance of a VCE can be instantiated from an image. Two well-known types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature in which the kernel allows for the existence of multiple isolated user-space instances called containers. These isolated user-space instances typically behave as actual computers from the perspective of the programs running in them. Computer programs running on a normal operating system can utilize all of that computer's resources, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, programs running inside a container can only use the contents of the container and the devices allocated to the container; this feature is known as containerization.

[0047] The private cloud 106 is similar to the public cloud 105, except that its computing resources are available only for use by a single enterprise. While the private cloud 106 is shown as communicating with the WAN 102, in other embodiments, the private cloud may be completely isolated from the internet and accessible only via a local / private network. A hybrid cloud is a combination of multiple clouds of different types (e.g., private, community, or public cloud types), often implemented by different vendors. Each of the multiple clouds remains a separate discrete entity, but the larger hybrid cloud architecture is coupled by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability between the multiple configuration clouds. In this embodiment, both the public cloud 105 and the private cloud 106 are part of a larger hybrid cloud.

[0048] Embodiments of this disclosure provide a system and method for performing prediction of design flow parameters for an optimized output target for physical design synthesis of an IC design, avoiding the generally extreme runtime of conventional parameter prediction configurations. In the disclosed embodiments, the system receives initial design characteristics, design flow parameters, and a design target to be optimized for a physical design synthesis build flow for a given IC design. The system uses a machine learning neural network model, including a variational autoencoder (VAE) that provides dimensionality reduction, combined with a regression model, to predict optimal design flow parameters for an optimal design target for a given IC design. The system uses a dataset of design characteristics, design parameters, and target metrics extracted from a database of historical synthesis design build flows to base-train the VAE and the combined regression network together. The VAE and the combined regression network generate predictions of optimal design flow parameters for an optimal design target, such as optimal power, congestion, and timing targets, for a physical design synthesis build flow for a given IC design.

[0049] Figure 2 shows an exemplary system 200 for performing improved parameter prediction in one or more disclosed embodiments. System 200 uses a machine learning neural network model 300, which includes a variational autoencoder (VAE) combined with a regression network model, as shown in Figure 3, to perform improved parameter prediction.

[0050] System 200 can efficiently and effectively predict optimal design flow parameters using offline machine learning in a machine learning neural network model 300, avoiding the online execution of multiple synthetic design build flows on many machines, as is done by conventional parameter prediction systems.

[0051] System 200 includes a controller 202 and a parameter prediction control component 182, together with a processor computer 101, for example in Figure 1, to control the operation of a machine learning neural network model 300 for performing predictions of optimal design flow parameters. In the disclosed embodiments, System 200 includes a feature target metric dataset 184 and hyperparameters and values ​​186, used together with the controller 202 and the processor computer 101 to perform improved predictions of optimal design flow (physical synthesis) parameters for optimized congestion, timing, and power targets of the disclosed embodiments.

[0052] System 200 uses a feature target metric dataset 184, which includes design characteristic features, design parameter features, and target metrics from a history synthesis design build flow file to train a machine learning neural network model 300. System 200 receives initial design characteristics, design flow parameters, and a design target to be optimized for a design build flow for a given IC design. The design target to be optimized includes selected design target outputs such as congestion, timing, and power. In one embodiment, System 200 uses hyperparameters and values ​​186, e.g., weights, for regression, reconstruction, and regularization of the machine learning neural network model 300.

[0053] Referring also to Figure 3, the illustrated exemplary structure of the offline machine learning neural network model 300 includes a variational autoencoder (VAE) 302 that provides dimensionality reduction, combined with a regression network 306 of the disclosed embodiment. The VAE 302 and the combined regression network 306 predict optimal design flow parameters for optimal design targets (e.g., congestion, timing, and power targets) for the synthesis construction of a given integrated circuit of the disclosed embodiment. The exemplary dataflow operation of the VAE 302 with the combined regression network 306 is illustrated and described with respect to Figures 6 to 11.

[0054] In the disclosed embodiments, VAE302 provides dimensionality reduction, constrains the latent space 307, and enables interpolation of sampled points from a machine-trained latent space representation of a feature target metric dataset 184 in the latent space 307. For example, TensorFlow and Keras layers can be used to implement VAE302. TensorFlow is an open-source end-to-end platform for running libraries for multiple machine learning tasks, while Keras is a high-level neural network library that runs on top of TensorFlow. Both provide high-level application programming interfaces (APIs) used to build and train models.

[0055] The VAE 302 of the machine learning neural network model 300 includes a latent space collectively represented by a neural network encoder 304, a neural network decoder 305, and 307. A regression network 306 is used with VAE 302 for training, inference, and optimization operations of the disclosed embodiment. The encoder 304, decoder 305, and latent space 307 of VAE 302 combined with the regression network 306 of the disclosed embodiment generate predictions of optimal design flow parameters for an optimized output target for a synthesis build flow for a given IC design.

[0056] The latent space 307 of VAE302 implements a machine learning-trained latent space representation of the training feature target metric dataset 184, which is input to the encoder 304 of the combined VAE302 and regression network 306 of the disclosed embodiment. The latent space 307 includes, for example, a random sample layer consisting of multiple nodes, for example, 35 nodes. Each node of the 35 exemplary latent space nodes represents one dimension of the latent space 307. The latent space 307 can be sampled using a first diagonal multivariate Gaussian #1 308 or a second diagonal multivariate Gaussian #2 309. The first diagonal multivariate Gaussian #1 308 is used for basic and interpolation training of VAE302 with the combined regression network 306 of the disclosed embodiment. Using the feature target metric dataset 184, the neural network learns the mean Zmean 342 and standard deviation Zstddev 344 corresponding to each point in the latent space 307, which are used by the diagonal multivariate Gaussian #1 308 to generate the sample vector Zsample 345. The second diagonal multivariate Gaussian #2 309 is used for the generation of interpolation vectors for interpolation training and for the initialization of the optimized gradient search in the disclosed embodiment. Using the feature target metric dataset 184, the diagonal multivariate Gaussian #2 309 is fitted to all points in the latent space 307 corresponding to all vectors in the feature target metric dataset 184 and used to generate the sample vector Zrandom 346.

[0057] As shown in the machine learning neural network model 300 in Figure 3, the data input layer X336 of the encoder 304 represents the design characteristics 310 and design flow parameters 312 of the feature target metric dataset 184, and the target output of the regression network 306 includes the target output Y'318. The decoded or reconstructed output X'348 of the decoder 305 includes the reconstructed design characteristics 314 and reconstructed design flow parameters 316 (e.g., names and values). For example, the feature target metric dataset 184 in Figure 2 is obtained from the history synthesis design construction flow file of a history IC design. The target output Y'318 of the regression network 306 includes selected targets such as congestion, timing, and power.

[0058] In one disclosed embodiment of the VAE 302 of System 200, the exemplary neural network encoder 304 includes two fully connected dense layers 320, 322 having a Rectified Linear Unit (ReLU) activation function. The encoder 304 includes multiple nodes on the outer layer 320 (e.g., 256 nodes) and multiple nodes on the inner layer 322 (e.g., 128 nodes). The ReLU activation function in the neural network encoder 304 can define how the weighted sum of the inputs is transformed into the output of the neural network encoder. For example, the ReLU activation function of the encoder 304 could include a piecewise linear function that outputs the input directly if it is positive, or zero otherwise. The exemplary model encoder 304 using the ReLU activation function may be relatively easy to train to achieve the effective performance of the VAE 302.

[0059] In the disclosed embodiments, the exemplary decoder 305 of VAE 302 can be configured as the inverse of encoder 304. As shown, decoder 305 includes, for example, two fully connected layers 324, 326 having a ReLU activation function, a first plurality of nodes (e.g., 128 nodes) on the inner layer 324 and a second plurality of nodes (e.g., 256 nodes) on the outer layer 326, and a sub-multiple output node (e.g., 200 nodes) of the decoded output X'348 of decoder 305 uses linear activation for reconstruction.

[0060] For example, the data input layer X336 of encoder 304 includes 200 nodes, including multiple sub-input nodes, such as 26 nodes for design characteristics 310 and 176 nodes for design flow parameters 312. For example, the decoded output X'348 of decoder 305 includes 200 nodes, including multiple sub-nodes, such as 26 nodes for decoded design characteristics 310 and 176 nodes for decoded design flow parameters 312.

[0061] In the disclosed embodiments, the regression network 306 may include two fully connected layers 330, 332, each having 64 nodes using a Tanh activation function and 3 nodes using linear activation for the target output Y'318. For example, the Tanh activation function is a hyperbolic tangent sigmoid function with a range of -1 to 1, which can model nonlinear boundaries. The Tanh activation function can be applied at different scales without losing its effectiveness. In system 200, the target output Y'318 of the regression network 306 may include congestion (weighted mean congestion estimate), timing (zero-based inter-latch sum of negative slack), and total power (sum of leakage power and dynamic power).

[0062] As shown in Figure 3, multiple configurations of the VAE 302 are provided, including separate configurations of the encoder 304, decoder 305, and regression network 306, depending on the data flow for training, inference, and optimization operations. As shown, the separate paths indicated by dashed lines provide the respective connections from Zmean 342, Zsample 345, or Zrandom 346 to connection points or connection block Z347 in the latent space 307. Block Z347 is not a layer, but rather represents a connection to one of three alternative VAE configurations: Zmean 342 for inference operations, Zsample 345 for training operations, or Zrandom 346 for interpolation training and optimization operations. As shown, the VAE 302 includes one of the alternative connections of Zmean 342, Zsample 345, or Zrandom 346 to the decoder 305 and regression network 306 via the connection block Z347.

[0063] The sample using the first diagonal multivariate Gaussian #1 308 provides Zsample345, which is used during the base training and interpolation training of VAE302, but not during inference or optimization (i.e., the first diagonal multivariate Gaussian #1 is not used during optimization initialization or optimization operation). Zsample345 of the first diagonal multivariate Gaussian #1 308 is centered on each of the Zmeans of the training data, each containing some standard deviation Zstddev344 relative to that Zmean. The output Zrandom346 of the second diagonal multivariate Gaussian #2 309 is used to generate interpolation vectors and for optimization initialization of the optimization operation. The output Zrandom346 of the second diagonal multivariate Gaussian #2 309 is a single distribution with a zero mean and a standard deviation equal to the root mean square of the Zmean342 of the training data.

[0064] The VAE302, combined with the regression network 306, is trained together (e.g., simultaneously) with the feature target metric dataset 184 to constrain the latent space 307 and provide a latent space representation of the dataset. The VAE302 constrains the latent space 307 so that all training data points map to each other in proximity in the latent space 307. During the basic and interpolation training of the VAE302, the first diagonal multivariate Gaussian #1 308 samples the outputs Zmean342 and Zstddev344 of the encoder 304 to provide the output Zsample345.

[0065] During training, the dataflow output Zmean342 represents the mean of the encoded latent space of the sampled points, and Zstddev344 represents the variance or standard deviation of the sampled points. The encoded data Zmean342 and Zstddev344 are applied to the first diagonal multivariate Gaussian #1, which provides the conventional VAE sampling and dataflow output Zsample345 during the base training and interpolation training of VAE302. The data points of the first diagonal multivariate Gaussian #1 308 are applied to the decoder 305 and the regression network 306.

[0066] The schematic illustration of the example training data sample distribution in latent space 307 shown below the first diagonal multivariate Gaussian #1 308 represents the output Zsample345 of the example first diagonal multivariate Gaussian #1 308. The points represent the positions of Zmean342 in latent space 307, and the curve represents the Gaussian distribution around the position of Zmean342 with a standard deviation Zstddev344. Although only four distributions are shown, in reality, distributions exist around all positions of Zmean342. We show only four for clarity. The schematic illustration of the example training data sample distribution in latent space 307 shown above the second diagonal multivariate Gaussian #2 309 represents the output Zrandom346 of the second diagonal multivariate Gaussian #2 309. Both the first and second illustrations include the same training data points representing the encoder output Zmean342. Each training data point represents a synthesis build flow that includes design characteristics 310 and design flow parameters 312 of a specific historical IC design obtained from the feature target metric dataset 184.

[0067] For the first diagonal multivariate Gaussian #1 308, each data training point has a distribution in all dimensions of the latent space 307; however, only the four data training distributions shown are shown in one dimension. In the first diagonal multivariate Gaussian #1 308, each of the four training data distributions is centered on one of four Zmeans, each having a standard deviation Zstddev for each Zmean. The training data sample distribution shown represents the sampling output Zsample345 in the latent space 307 of the first diagonal multivariate Gaussian #1 308.

[0068] For the second diagonal multivariate Gaussian #2 309, only one distribution exists in the latent space 307. The single distribution of output Zrandom346 has multiple dimensions in the latent space 307, although the training distribution shown is shown in one dimension. As shown, the output Zrandom346 of the second diagonal multivariate Gaussian #2 309 is used for generating interpolation vectors for interpolation training and for initializing the optimization gradient search for the optimization operation. The output Zrandom346 is a single distribution with a zero mean and a dimensional standard deviation equal to the root-mean-square (RMS) of the Zmean of the training data.

[0069] In System 200, design characteristics 310 generally include static or unchanging design-specific features. Design characteristics 310 may include the height and width of the design-placeable area; area utilization (utilization rate over the total design-placeable area); number of gates (number of instances (cell utilization rate); number of nets (connected instances); and number of connections between instances (sink pins)). Design characteristics 310 may further include the number of available metal layers for routing; the number of routing blocks in the design; the number of ports (main input / output) in the design; the average 1% placement bin density of the design; the average 1% pin density of the placement pins in the design; and the voltage of the design. Design characteristics 310 may further include the worst slack of paths between latches; the number of faulty timing paths; clock gating switching coefficient (dynamic power); system clock period; latch output switching coefficient (dynamic power); and similar.

[0070] The design flow parameters 312, which represent design flow parameters, may include a set of combinations of parameter names and values. In the disclosed embodiments, the design flow parameters are translated into binary features called runids. Runids are designed to facilitate manual parameter selection, a practice that has been continued to ensure consistency in automated parameter optimization. A runid is a small subset of parameters to which specific values ​​are applied, together defining a useful optimization function. This additional level of abstraction allows the function to be transparent to underlying programming changes. The input to the neural network is set to 1 if the corresponding runid is selected, and 0 otherwise. A runid may represent a technically independent reconstruction with values ​​or ranges of none, down, flow, flatten, crush, destroy, and choice; an additional configuration with values ​​or ranges of ripple, fast, and fastest; and a logic synthesis type parameter such as area effort with values ​​or ranges of 0 to 99. Other runids may represent placement type parameters such as pin expansion coefficients with values ​​or ranges of 0.0 to 2.0, target density with values ​​or ranges of 30 to 80, and true / false timing-driven attractions. Other runids may represent clock tree synthesis, e.g., latch fan-out, latch configuration, and multiplier, each with its own value or range. Other runids can represent spreading type algorithm parameters. Other runids can represent global root spreading iterations with values ​​or ranges of 0, 5, 10, 15, and 20, and pin-aware density placement spreading with values ​​or ranges of 0, 5, 10, 15, and 20. Other runids can represent late-design flow optimization parameters such as coarse selection iterations with values ​​or ranges of 1, 2, 3, and 4, fine selection iterations with values ​​or ranges of 1, 2, 3, and 4, coarse selection spreading with true / false values ​​or ranges, fine selection spreading with true / false values ​​or ranges, and additional detail placement with true / false values ​​or ranges.Other runids can represent power optimization type parameters such as low voltage (Vt) percentages with values ​​or ranges of 0.01, 0.05, 0.10, 0.15, 0.20, 0.25, 0.30, and 0.60, and area-timing margins with values ​​or ranges of 5 and 10.

[0071] System 200 can use Kendall correlation on a feature target metric dataset 184 to isolate critical design flow parameters 312 for which congestion, timing, and power target output Y'318 are optimized. Hyperparameters and values ​​186 provide an Adam optimizer having, for example, regression weights, reconstruction weights, and L2 regularization weights, training data batch size such as 256, 512, or 1024, number of epochs such as 15,000, and stepped learning rates 1e-3 and 1e-4 at 25% and 95% of the epochs.

[0072] Referring to Figure 4, System 200, for example, uses the controller 202 and parameter predictive control component 182 together with the processor computer 101 in Figure 1 to perform the operation of Exemplary Method 400 using the feature target metric dataset 184 and hyperparameters and values ​​186. In Figure 4, the same reference numerals are used for identical or similar components in Figure 3.

[0073] As shown in block 402, system 200 accesses the database of the history synthesis design build flow and receives the feature target metric dataset 184 to train the VAE 302 and the regression network 306 simultaneously. The feature target metric dataset 184 used to train the VAE 302 and the regression network 306 includes the design characteristics 310, the design parameters 312 (i.e., runid) which include a set of combinations of parameter names and values, and the target metric or target output Y'318, as shown in Figure 3. In addition to accessing the database of the history synthesis design build flow to identify datasets, system 200 can also identify and provide other data such as designer build, regression deployment data, and similar. In block 404, system 200 identifies the feature vectors and output target vectors from the datasets which should be used to train the VAE 302 and the regression network 306.

[0074] In block 406, system 200 provides or constructs a machine learning neural network model 300, which includes a VAE 302 that provides dimensionality reduction, combined with a combined regression network 306, in order to obtain predictions of optimal design flow parameters for the disclosed embodiment. Figure 3, as described above, schematically illustrates the structure of the VAE 302 and the combined regression network 306. In block 408, system 200 can perform optional basic training of the VAE 302 together with the regression network 306 using the vectors identified in block 404 to provide a training data representation of the dataset constrained to the latent space 307 of the VAE 302. System 200 can train the VAE 302 together with the regression network 306 using unsupervised machine learning with vectors of training data features and supervised machine learning with vectors of training data output targets to provide a training data representation of the dataset constrained to the latent space 307 of the VAE. In block 408, the basic training may include an exemplary data flow for the basic training operation 600, which is schematically illustrated and described with respect to Figure 6.

[0075] In block 410, system 200 alternatively performs interpolation training of VAE 302 together with regression network 306. Note that the base training in block 408 is optional and not a prerequisite for interpolation training in block 410. In the disclosed embodiments, interpolation training can provide improved results for optimization over base training. In block 410, system 200 can use the vectors identified in block 404 to provide a training data representation of the dataset constrained to the latent space 307 of VAE 302. In block 410, system 200 can generate an expanded dataset at each epoch used for the interpolation training operation by sampling the training data representation of the dataset and generating interpolated vectors by performing operations on the sampled points through decoder 305. In block 410, interpolation training may include the generation of interpolated vectors in a vector generation phase, as schematically shown in Figure 7, used in an interpolation training phase, as schematically shown in Figure 8.

[0076] In block 410, interpolation training provides a form of regularization. The purpose of regularization is to enable encoder 305 to perform generalization, i.e., interpolation. In one embodiment, additional L2 regularization on encoder 304 may be useful.

[0077] In block 412, system 200 accesses initial design characteristics from a design build flow for a given IC design. The design build flow is an early build flow following initial placement and early optimization for a given IC design. The design build flow is performed before the synthesis build flow for a given IC design. The design build flow includes features including design characteristics and design flow parameters to be optimized, and output targets (e.g., congestion, timing, and power) to be optimized at the end of the build flow. The design characteristics from the design build flow for a given IC design are used for optimization to predict the optimal design flow parameters for the disclosed embodiment.

[0078] In block 414, system 200 selects a set of random samples in latent space 307, decodes the random samples, and generates a complete feature vector containing initial design characteristics and design flow parameters. In block 416, system 200 replaces the design characteristics in the generated feature vector with the received initial design characteristics for a given IC design, providing an updated set of feature vectors. Using the updated set of feature vectors, system 200 performs optimization to predict the optimal design flow parameters for an optimized output target for a given IC design. The operation in blocks 414 and 416 is schematically shown in Figure 9.

[0079] In block 418, system 200 optimizes the objective function of the design target to identify locally optimal design parameters by performing an input gradient descent search on an updated set of feature vectors from a training data representation of a dataset constrained by the initial design characteristics. For example, system 200 optimizes the objective function of the output target using relative importance weights, constrained to keeping the optimization within a latent space defined by the training data and enabling reliable predictions of locally optimal design parameters. In the disclosed embodiments, importance weights are assigned to the objective function, including, for example, congestion, timing, and power, and contributions to the variability components and reconstruction errors. During the input gradient descent search, the initial design characteristics remain fixed, constrained to keeping the optimization within a latent space defined by the training data, in order to generate reliably recommended design parameters. The operation in block 418 is schematically shown, for example, in Figure 10. In one embodiment, in block 422, system 200 sorts the locally optimal design parameters based on the objective function for the design target to identify the global optimal of the locally optimal design parameters for the optimized output target. In block 424, system 200 optionally performs threshold quantization of the globally optimal design parameters. Alternatively, in block 426, system 200 optionally performs fine tuning of the globally optimal design parameters. The operation in block 426 is schematically shown, for example, in Figure 11. In block 428, system 200 obtains a prediction of the optimized output target based on the globally optimal design parameters.

[0080] Figure 5 shows illustrative projected latent space sample images 500 for each output target, including congestion 502, timing 504, and power 506, in one or more disclosed embodiments. The illustrative images 500 include two dimensions of the latent space for each output target, while the latent space 307 includes, for example, 35 dimensions. The first images 508, 510, and 512 for congestion 502, timing 504, and power 506, respectively, show projected and rotated images of the latent space, where each dot or data point represents a physical synthesis job of design characteristics and parameters / values ​​from the feature target metric dataset 184. In congestion image 508, the shaded legend on the right represents a scale of approximately -4 to +4 for the rotated projection of the indicated vertical axis Z(1) and horizontal axis Z(0) of the scaled and normalized congestion output values. In the timing image 510, the shaded legend on the right represents a scale of approximately -0.5 to +2.5 for the rotated projection of the vertical axis Z(1) and horizontal axis Z(0) showing the scaled and normalized timing output values. In the power image 510, the shaded legend on the right represents a scale of approximately -3 to +3 for the rotated projection of the vertical axis Z(1) and horizontal axis Z(0) showing the scaled and normalized power output values.

[0081] The second images 514, 516, and 518, respectively, show how the values ​​of output target congestion 502, timing 504, and power 506 change in the latent space plane. Since the principal axes for congestion 502, timing 504, and power 506 are different, each of the images 514, 516, and 518 shows a different plane. The third images 520, 522, and 524, respectively, show the reconstruction error in the axis plane for the indicated vertical axis Z(1) and horizontal axis Z(0). The shaded legend on the right of each represents the upward increasing error, starting at zero (0). The third images 520, 522, and 524 can indicate where valid features are located. Low error values ​​in images 520, 522, and 524 indicate a good reconstruction; high errors indicate that the features mapping to that area of ​​latent space are unreliable for parameter prediction.

[0082] Figure 6 schematically shows an exemplary data flow for a basic training operation 600 of the VAE 302 and the combined regression network 306 of the disclosed embodiment. In one embodiment, the system 200 trains the VAE 302 combined with the regression network 306 to constrain the latent space 307 and provide a latent space representation of the feature target metric dataset 184.

[0083] In the disclosed embodiments, the system 200 identifies vectors of features (Xs) and vectors of output targets (Ys) from a feature target metric dataset 184 to train one or more VAEs 302 and combined regression networks 306 of the disclosed embodiments. For example, the vector of features Xs includes design characteristics 310 and design flow parameters 312. The input layer X 336 of the encoder 304 receives the vector of feature data input 602Xs. The output X' 346 of the decoder 305 provides the decoded or reconstructed vector of features 608X's. The output Y' 318 of the regression network 306 provides the vector of predicted output targets 614Y's. In the disclosed embodiments, system 200 calculates a reconstruction error, which is a measure of the difference between the reconstructed features 608X's and 610Xs, where 610Xs is the same data as the vector of the feature data input 602Xs; and calculates a regression error, which is a measure of the difference between the actual target 612Ys and the predicted output target 614Y's. System 200 uses both forward and backward propagation of the training vector of the feature data input 602Xs to perform basic training of the VAE 302 and the combined regression network 306 to minimize the Kullbeck-Leibler divergence and the mean squared error between the training data points for reconstruction and regression.

[0084] Basic training is performed over multiple epochs. Each epoch represents a flow of the dataset that passes through the machine learning neural network model 300 once, with updates to the neural network weights and biases, although typically the dataset is broken down into batches and updated batch by batch. Basic training involves encoding by encoder 304, which provides Zmean 342 and Zstddev 344 to the first diagonal multivariate Gaussian #1 308, which provides Zsample 345, which is input to decoder 305 and regression network 306. Zsample 345 is decoded by decoder 305, which provides a vector of reconstructed features 608X's. The output Y'318 of regression network 306 provides a vector of predicted output targets 614Y's.

[0085] During training 600, the KL divergence loss term pushes each sampling distribution toward a multivariate Gaussian distribution with zero mean and unit variance. For each dimension of the latent space 307, these distributions toward one of two stable states. The first state disperses the sample mean across the latent space 307 with a small variance toward zero. The sample distributions may overlap during the early epochs of training 600, and this overlap decreases during the later epochs of training.

[0086] The second state is that all sample means can be moved toward zero and all sample variances toward one. When the sample means move toward zero or near zero, the dimension can no longer encode any information about the features, and that dimension of the latent space is said to have collapsed. An interesting behavior of latent space dimension collapse is that if the latent space 307 is defined with more dimensions than the VAE uses to encode features, further dimensions will collapse. The number of collapsed dimensions can be counted, and the latent space 307 can be reduced accordingly. To determine whether a dimension has collapsed, the mean of the variances is compared to the variance of the mean. If the mean of the variances is greater, it can be determined that the dimension has collapsed. To keep the latent space 307 completely from collapse, the effective KL weights can be indirectly tuned, and the reconstruction weights can be adjusted, where the collapse of the latent space is caused, for example, by excessively high KL weights or excessively low reconstruction weights.

[0087] Referring to Figures 7 and 8, Figure 7 schematically shows the operation of one or more disclosed embodiments of the VAE 302 and the combined regression network 306 for generating interpolation vectors in each epoch, and Figure 8 shows those exemplary operations for performing interpolation training in each epoch using the interpolation vectors.

[0088] In Figure 7, the exemplary operation 700 for generating a set of interpolated vectors includes selecting a random set of points in the latent space at every epoch and reconstructing vectors for the random set of points using the decoder 305 of the VAE 302. The output Zrandom 346 of the second diagonal multivariate Gaussian #2 309 is used to generate the interpolated vectors. As shown, the latent space vector Zrandom 346 is applied to the decoder 305 and the regression network 306. The reconstructed output layer 348X' of the decoder 305 provides the generated interpolated vectors 702Xi. The regression target output Y' 318 of the regression network 306 provides the corresponding output target.

[0089] Figure 8 schematically illustrates an exemplary interpolation training operation 800 for interpolation training of VAE 302 and the combined regression network 306 using the interpolation vectors generated in each epoch in Figure 7. In one embodiment, system 200 performs interpolation training to improve the reliability of predictions or recommendations and reduce regression errors for design flow parameters to be optimized. In Figure 8, sampling using the first diagonal multivariate Gaussian #1 308 provides Zsample 345 used for interpolation training of VAE 302 (e.g., the same dataflow path used for basic training in Figure 6).

[0090] In Figure 8, the interpolation training operation 800 begins with the dataset training vector 802Xs and the output target vector 818Ys of the regression network 306. In the interpolation training operation 800, the interpolated vector 803Xi generated by the VAE 302 in each epoch is combined with the training vector 802Xs (e.g., concatenated together), and the interpolated vector 820Yi in each epoch is combined with the output target vector 818Ys. In the disclosed embodiment, the system 200 calculates the reconstruction error based on the difference between the combined training vector 810Xs and the interpolated vector 812Xi and the combined reconstructed vector 804X's and the reconstructed interpolated 806X'i. In the disclosed embodiment, the system 200 calculates the regression error, which is a measure of the difference between the combined actual target vector 818Ys and the interpolated vector 820Yi and the combined predicted output target vector 814Y's and the interpolated vector 816Y'i. The combined training vector 802Xs and interpolated vector 803Xi, along with the regression output target vector 818Ys and interpolated vector 816Yi, generate an augmented dataset at each epoch, as indicated by the combined reconstructed vectors 804X's and 806X'i and the output target vectors 814Y' and 816Y'. The augmented dataset is dynamic and generated by using the trained VAE302 and regression network 306.

[0091] Referring to Figures 9 and 10, the system 200 uses the VAE 302 and the combined regression network 306 for an initialization operation 900 schematically shown in Figure 9 for an optimized input gradient search in the disclosed embodiment and an optimization operation 1000 including an iterative optimized input gradient search in Figure 10.

[0092] In Figure 9, System 200 obtains a set of random samples in latent space 307 from Zrandom346 of the second diagonal multivariate Gaussian #2 309 for an exemplary initialization operation 900. The output Zrandom346 is processed by decoder 305 and regression network 306. The decoded output X'348 contains the decoded design characteristic value Xo902 and the decoded design flow parameter Xo904. The regression network target output Y'318 contains the decoded target Yo906. System 200 obtains input 907 containing the initial design characteristic 908 and the design flow parameter 910 to be optimized, and the decoded design characteristic value Xo902 and the decoded design flow parameter Xo904 for predicting the optimal design flow parameters for the physical design synthesis build flow for a given IC design. System 200 merges the input 907, the initial design characteristics 908, and the decoded design flow parameter Xo904 from decoder 305 for use in the next iteration of the optimization gradient search shown in Figure 10.

[0093] Figure 10 schematically illustrates an exemplary optimization operation 1000 for obtaining predictions of optimal design flow parameters for an optimized output target in one or more disclosed embodiments. In the disclosed embodiments as shown in Figure 10, the optimization is performed using an initial design characteristic 1002 (initial design characteristic 908 in Figure 9) and modified design flow parameters 1024 for multiple iterations of the optimization operation. The system 200 iteratively performs an input gradient search of a set of latent space samples constrained by the initial design characteristic 1002 to optimize the objective function of the design target with relative importance weights to identify locally optimal design parameters for the optimal design target. In the disclosed embodiments, the importance weights are assigned to contributions to the objective function, including, for example, congestion, timing, and power; reconstruction error; and variation components to keep the optimization within the latent space defined by the training data and to enable reliable predictions of locally optimal design parameters.

[0094] In the disclosed embodiment, system 200 receives a data input design characteristic 1002, which includes an initial design characteristic 1002 implemented for physical design flow synthesis of a given IC design, and an optimized design flow parameter 1004 (e.g., the decoded design flow parameter X'344 of decoder 305 in Figure 9 for input Zrandom 346). Encoder 304 encodes the initial design characteristic 1002 and the design flow parameter 1004 and provides the encoder output Zmean 342 to decoder 305 and regression network 306. Output X'348 of decoder 305 provides iterated design characteristic values ​​1006 and iterated design flow parameters 1008 for each iteration of optimization. Target output Y'318 of regression network 306 provides an iterated target 1010. As shown, the initial design characteristic 1002 remains unchanged (modified by zero), and the optimized design flow parameter 1004 is modified by the input gradient 1022. The modified design flow parameters 1024 and the same initial design characteristics 1002 provided by the modification are used for the next iteration of the optimization operation.

[0095] Figure 11 schematically illustrates a fine-tuning operation 1100 of an example of optimal design flow parameters in one or more disclosed embodiments. The input 1102 or fine-tuning includes design characteristics 1104 and design flow parameter values ​​1006 provided from gradient descent optimization. A set of vectors 1110 of multiple single vectors includes design flow parameters 1112, which include design characteristics 1104 that remain unchanged and several unquantized parameter features (e.g., several binary features of the optimal design parameters 1106) that are to be quantized to zero or 1. Each binary parameter feature that will be quantized (e.g., five binary parameter features shown in the step having 0-1) is quantized, with one feature fixed at a time. As shown, the quantized design flow parameters 1114 include the same design characteristics 1104 and binary parameter features 1116 that will be quantized with a second parameter value of 0, for example, that will be fixed. For all binary features, zero or 1 is tried, and the objective function for each of the vectors is calculated for each parameter block or slice. Parameter values ​​are inverted to zero or one to identify the best parameter values ​​(e.g., 0 or 1) based on the objective function. Feature values ​​are quantized until all binary features are quantized to the best parameter values ​​of zero and 1.

[0096] While the foregoing describes embodiments of the present invention, other and further embodiments of the present invention can be devised without departing from the basic scope of the present invention, and the scope of the present invention is determined by the following claims.

Claims

1. The stage of receiving initial design characteristics, design flow parameters, and design targets from a design build flow for a given integrated circuit (IC) design; The stage of receiving a historical dataset, including the historical IC design and synthesis design construction flow; The step of training a variational autoencoder (VAE) with a regression network using the aforementioned historical dataset to provide a training data representation of the dataset constrained to the latent space of the VAE; A step of generating feature vectors based on the training data representation of the dataset and updating the feature vectors with the initial design characteristics; The step of iteratively performing the input gradient search of the updated feature vectors to optimize the objective function of the design target to identify locally optimal design parameters, wherein the training data samples are constrained by the initial design characteristics; and Step 1: Obtain predictions of globally optimal design flow parameters based on the identified locally optimal design parameters for the optimized design target. A method that includes [a certain feature].

2. The method according to claim 1, further comprising the step of decoding a random set of samples from the training data representation of the dataset to generate a feature vector including design characteristics and design flow parameters; the step of updating the feature vector with the initial design characteristics comprising replacing the design characteristics in the generated feature vector with the initial design characteristics to provide the updated feature vector.

3. The method according to claim 1, wherein the step of iteratively performing the input gradient search further comprises the step of calculating the input gradient at each optimization epoch and applying the input gradient to modify the next design flow parameters for the next optimization iteration.

4. The method according to claim 1, wherein the step of obtaining the prediction of globally optimal design flow parameters based on the locally optimal design parameters for the optimized design target further comprises the step of performing quantization of at least one binary parameter element of the globally optimal design flow parameters.

5. The method according to claim 1, further comprising the step of constructing the VAE including an encoder, the latent space, and a decoder; the encoder includes one or more neural network layers having a first plurality of nodes on an inner layer and a second plurality of nodes on an outer layer; the decoder includes one or more neural network layers having the second plurality of nodes on an inner layer of the decoder and the first plurality of nodes on an outer layer of the decoder, and the latent space includes a random sample layer having a plurality of nodes.

6. The method according to claim 1, wherein the step of obtaining the prediction of globally optimal design flow parameters based on the identified locally optimal design parameters for the optimized design target further comprises the step of sorting the locally optimal design parameters based on the objective function to identify the globally optimal design flow parameters.

7. The method according to claim 1, further comprising the step of training the VAE together with the regression network, wherein the step of performing interpolation training of the VAE together with the regression network using the combined interpolated vectors and training vectors to minimize the reconstruction error of the training data representation of the dataset.

8. The method according to claim 1, wherein the step of training the VAE together with the regression network further comprises training the VAE together with the regression network using unsupervised machine learning with vectors of training data features and supervised machine learning with vectors of training data output targets to provide the VAE with a training data representation of the dataset constrained to the latent space.

9. The method according to claim 1, wherein the step of training the VAE together with the regression network further comprises the steps of generating interpolated vectors of the dataset and combining the interpolated vectors with training vectors to generate an expanded dataset in each epoch.

10. The method according to claim 1, wherein the step of iteratively performing the input gradient search further comprises using hyperparameter values ​​including at least one of regression weights, reconstruction weights, the number of epochs for training, or the training batch size.

11. The method according to claim 1, wherein the regression network is connected to a neural network layer of the VAE representing the latent space.

12. Processor; and memory A system comprising, the memory having a computer program product configured to perform an operation for predicting optimal design flow parameters for the physical design synthesis of a given integrated circuit (IC) design, the operation being, Receiving initial design characteristics, design flow parameters, and design targets from the design build flow for the given integrated circuit (IC) design; Receiving a historical dataset including the historical IC design and synthesis design construction flow; Training a variational autoencoder (VAE) with a regression network using the aforementioned historical dataset to provide a training data representation of the dataset constrained to the latent space of the VAE; Generating feature vectors based on the training data representation of the dataset, and updating the feature vectors with the initial design characteristics; The objective function of the design target is optimized to identify locally optimal design parameters by iteratively performing an input gradient search of the updated feature vectors, wherein the training data samples are constrained by the initial design characteristics; and To obtain predictions of globally optimal design flow parameters based on the identified locally optimal design parameters for an optimized design target. A system that includes this.

13. The system according to claim 12, further comprising decoding a random set of samples from the training data representation of the dataset to generate a feature vector including design characteristics and design flow parameters; the step of updating the feature vector with the initial design characteristics comprises replacing the design characteristics in the generated feature vector with the initial design characteristics to provide the updated feature vector.

14. The system according to claim 12, further comprising training the VAE together with the regression network by performing training of the VAE together with the regression network using unsupervised machine learning with vectors of training data features and supervised machine learning with vectors of training data output targets to provide the VAE's training data representation of the dataset constrained to the latent space.

15. The system according to claim 12, wherein iteratively performing the input gradient search further includes calculating the input gradient at each optimization epoch and applying the input gradient to modify the next design flow parameters for the next optimization epoch.

16. The system according to claim 12, wherein obtaining the prediction of the globally optimal design flow parameters further comprises performing quantization of at least one binary parameter element of the globally optimal design flow parameters.

17. A computer program product for performing prediction of optimal design flow parameters for physical design synthesis of a given integrated circuit (IC) design, wherein the computer program product is Computer-readable storage medium in which computer-readable program code is embodied. The computer-readable program code is provided, A procedure for receiving initial design characteristics, design flow parameters, and design targets from a design build flow for a given integrated circuit (IC) design; Procedure for receiving a historical dataset including the synthesis design construction flow from the historical IC design; A procedure for training a variational autoencoder (VAE) with a regression network using the aforementioned historical dataset to provide a training data representation of the dataset constrained to the latent space of the VAE; A procedure for generating feature vectors based on the training data representation of the dataset and updating the feature vectors with the initial design characteristics; A procedure to iteratively perform an input gradient search of the updated feature vectors to optimize the objective function of the design target to identify locally optimal design parameters, wherein the training data samples are constrained to the initial design characteristics; and A procedure for obtaining predictions of globally optimal design flow parameters based on the identified locally optimal design parameters for an optimized design target. A computer program product that is executable by one or more computer processors to perform an operation that includes [a specific action].

18. The computer program product according to claim 17, further comprising the step of sorting the locally optimal design parameters based on the objective function to obtain the prediction of the globally optimal design flow parameters for the given IC design.

19. The computer program product according to claim 17, wherein the procedure for training the VAE together with the regression network further includes the procedure for generating interpolated vectors of the dataset, and the procedure for combining the interpolated vectors with training vectors to generate an expanded dataset at each epoch.

20. The computer program product according to claim 17, wherein the procedure for training the VAE together with the regression network further includes the procedure of training the VAE together with the regression network using unsupervised machine learning using vectors of training data features and supervised machine learning using vectors of training data output targets to provide the training data representation of the dataset of the VAE constrained to the latent space.

21. The computer program product according to claim 16, further comprising the steps of decoding a random set of samples from the training data representation of the dataset to generate a feature vector including design characteristics and design flow parameters; and updating the feature vector with the initial design characteristics, comprising the steps of replacing the design characteristics in the generated feature vector with the initial design characteristics to provide the updated feature vector.

22. A computer program comprising program code means adapted to perform the method described in any one of claims 1 to 11 when the program is executed on a computer.

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