Transistor with bottom dielectric isolation and fully self-aligned direct back contacts

Abstract

The microelectronic device comprises a nanosheet transistor including a first source / drain and a second source / drain. The front contact is connected to the first source / drain, and the back contact is connected to the second source / drain. Multiple isolation layers are located beneath the nanosheet transistor, and the second source / drain extends through the multiple isolation layers and connects to the back contact.

Description

Technical Field

[0001] The present invention generally relates to the field of microelectronics, and more specifically, to the formation of transistors with self-aligned back contacts.

Background Art

[0002] Nanowires are a major device architecture in continuous CMOS scaling. However, nanowire technology has shown problems during scaling down, such as devices interfering with each other as they become smaller and closer together. As the number of devices mounted in a narrow area increases, it becomes difficult to form the necessary contacts and ensure proper alignment of the contacts.

Summary of the Invention

[0003] Additional aspects and / or advantages are described in part in the following description, become apparent in part from the description, or may be learned by practice of the present invention.

[0004] A microelectronic device includes a nanowire transistor including a first source / drain and a second source / drain. A front contact is connected to the first source / drain, and a back contact is connected to the second source / drain. A plurality of isolation layers are disposed under the nanowire transistor, and the second source / drain extends through the plurality of isolation layers to be connected to the back contact.

[0005] A microelectronic device includes a first source / drain and a second source / drain. A front contact is connected to the first source / drain, and a back contact is connected to the second source / drain. A plurality of isolation layers are disposed under the nanowire transistor, and the second source / drain extends through the plurality of isolation layers to be connected to the back contact. The back contact extends through the plurality of isolation layers to be connected to the second source / drain.

[0006] The method comprises the steps of forming a back-side interlayer dielectric layer on a first substrate; forming at least one back-side contact placeholder on the back-side interlayer dielectric layer; and forming a first dielectric layer on the back-side interlayer dielectric layer and on at least one back-side contact placeholder. A plurality of alternating layers, each consisting of a channel layer and a sacrificial layer, are formed on a second substrate. A second dielectric layer is formed on the alternating layers. The second substrate is inverted, and the second dielectric layer is attached to the first dielectric layer; and a nanosheet transistor is formed from the alternating layers. [Brief explanation of the drawing]

[0007] The above and other aspects, features, and advantages of certain exemplary embodiments of the present invention will become more apparent from the following description, which will be read in conjunction with the accompanying drawings.

[0008] [Figure 1] This figure shows a top view of a plurality of nanodevices or transistors according to an embodiment of the present invention.

[0009] [Figure 2] This figure shows a cross-section X1 of substrate A after the formation of a plurality of placeholders and a first dielectric layer according to an embodiment of the present invention.

[0010] [Figure 3] This figure shows a cross-section X2 of substrate A after the formation of multiple placeholders and the first dielectric layer according to an embodiment of the present invention.

[0011] [Figure 4] This figure shows a cross-section X1 of substrate B after the formation of alternating layers according to an embodiment of the present invention.

[0012] [Figure 5] This figure shows a cross-section X2 of substrate B after the formation of alternating layers according to an embodiment of the present invention.

[0013] [Figure 6]The figure shows a cross-section Y of substrate A in the source / drain region after the formation of a plurality of placeholders and a first dielectric layer according to an embodiment of the present invention.

[0014] [Figure 7] The figure shows a cross-section Y of substrate B in the source / drain region after the formation of an alternating layer according to an embodiment of the present invention.

[0015] [Figure 8] The figure shows a cross-section X1 of substrate A after the inversion of substrate B according to an embodiment of the present invention.

[0016] [Figure 9] The figure shows a cross-section X2 of substrate A after the inversion of substrate B according to an embodiment of the present invention.

[0017] [Figure 10] The figure shows a cross-section X1 of substrate B after the inversion of substrate B according to an embodiment of the present invention.

[0018] [Figure 11] The figure shows a cross-section X2 of substrate B after the inversion of substrate B according to an embodiment of the present invention.

[0019] [Figure 12] The figure shows a cross-section Y of substrate A in the source / drain region after the inversion of substrate B according to an embodiment of the present invention.

[0020] [Figure 13] The figure shows a cross-section Y of substrate B in the source / drain region after the inversion of substrate B according to an embodiment of the present invention.

[0021] [Figure 14] The figure shows a cross-section X1 of substrate A after attaching substrate B to substrate A and removing a plurality of layers according to an embodiment of the present invention.

[0022] [Figure 15]This figure shows a cross-section X2 of substrate A after substrate B has been attached to substrate A and multiple layers have been removed, according to an embodiment of the present invention.

[0023] [Figure 16] This figure shows a cross-sectional view Y of substrate A in the source / drain region after substrate B is attached to substrate A and multiple layers have been removed, according to an embodiment of the present invention.

[0024] [Figure 17] This figure shows a cross-section X1 of a nanodevice after the formation of a dummy gate, hard mask, and upper spacer according to an embodiment of the present invention.

[0025] [Figure 18] This figure shows a cross-section X2 of a nanodevice after the formation of a dummy gate, hard mask, and upper spacer according to an embodiment of the present invention.

[0026] [Figure 19] This figure shows a cross-sectional view Y of a nanodevice in the source / drain region after separating the alternating layers into multiple rows, according to an embodiment of the present invention.

[0027] [Figure 20] This figure shows a cross-section X1 of a nanodevice after the alternating layers are separated into multiple rows and internal spacers are formed, according to an embodiment of the present invention.

[0028] [Figure 21] This figure shows a cross-section X2 of a nanodevice after the alternating layers are separated into multiple rows and internal spacers are formed, according to an embodiment of the present invention.

[0029] [Figure 22] This figure shows a cross-sectional view Y of a nanodevice in the source / drain region after removing the alternating layers to form the source / drain region, according to an embodiment of the present invention.

[0030] [Figure 23]This figure shows a cross-section X1 of a nanodevice after etching the first and second dielectric layers to expose the back-side contact placeholder, according to an embodiment of the present invention.

[0031] [Figure 24] This figure shows a cross-section X2 of a nanodevice after etching the first and second dielectric layers to expose the back-side contact placeholder, according to an embodiment of the present invention.

[0032] [Figure 25] This figure shows a cross-sectional view Y of a nanodevice in the source / drain region after etching the first and second dielectric layers to expose the back contact placeholder, according to an embodiment of the present invention.

[0033] [Figure 26] This figure shows a cross-section X1 of a nanodevice after source / drain formation according to an embodiment of the present invention.

[0034] [Figure 27] This figure shows a cross-section X2 of a nanodevice after the formation of the source / drain according to an embodiment of the present invention.

[0035] [Figure 28] This figure shows a cross-sectional view Y of the nanodevice in the source / drain region after the formation of the source / drain according to an embodiment of the present invention.

[0036] [Figure 29] This figure shows a cross-section X1 of a nanodevice after the formation of the front interlayer dielectric layer according to an embodiment of the present invention.

[0037] [Figure 30] This figure shows a cross-section X2 of a nanodevice after the formation of the front interlayer dielectric layer according to an embodiment of the present invention.

[0038] [Figure 31]This figure shows a cross-sectional view Y of a nanodevice in the source / drain region after the formation of the front interlayer dielectric layer according to an embodiment of the present invention.

[0039] [Figure 32] This figure shows a cross-section X1 of a nanodevice after removal of the hard mask, dummy gate, and sacrificial layer, formation of the gate, increase in the height of the front interlayer dielectric layer, and formation of the front contact, according to an embodiment of the present invention.

[0040] [Figure 33] This figure shows a cross-section X2 of a nanodevice after removal of the hard mask, dummy gate, and sacrificial layer, formation of the gate, increase in the height of the front interlayer dielectric layer, and formation of the front contact, according to an embodiment of the present invention.

[0041] [Figure 34] This figure shows a cross-sectional Y of the nanodevice in the source / drain region after removal of the hard mask, dummy gate and sacrificial layer, formation of the gate, increase in the height of the front interlayer dielectric layer, and formation of the front contact, according to an embodiment of the present invention.

[0042] [Figure 35] This figure shows the formation of the wiring process (BEOL) layer and carrier wafer, the inversion of the nanodevice for backside processing, and a cross-section X1 of the nanodevice after removal of the first substrate, according to an embodiment of the present invention.

[0043] [Figure 36] This figure shows the formation of the wiring process (BEOL) layer and carrier wafer, the inversion of the nanodevice for backside processing, and a cross-section X2 of the nanodevice after removal of the first substrate, according to an embodiment of the present invention.

[0044] [Figure 37] This shows a cross-sectional Y of the nanodevice in the source / drain region after the formation of the wiring process (BEOL) layer and carrier wafer, inversion of the nanodevice for backside processing, removal of the first substrate, and formation of the frontside contacts, according to an embodiment of the present invention.

[0045] [Figure 38] This figure shows a cross-section X1 of a nanodevice after the removal of the back contact placeholder and the formation of grooves in the source / drain according to an embodiment of the present invention.

[0046] [Figure 39] This figure shows a cross-section X2 of a nanodevice after the removal of the back contact placeholder and the formation of grooves in the source / drain according to an embodiment of the present invention.

[0047] [Figure 40] This figure shows a cross-sectional view Y of the nanodevice in the source / drain region after the removal of the back contact placeholder and the formation of grooves in the source / drain, according to an embodiment of the present invention.

[0048] [Figure 41] This figure shows a cross-section X1 of a nanodevice after the formation of the back contact and back power distribution network according to an embodiment of the present invention.

[0049] [Figure 42] This figure shows a cross-section X2 of a nanodevice after the formation of the back contact and back power distribution network according to an embodiment of the present invention.

[0050] [Figure 43] This figure shows a cross-sectional view Y of the nanodevice in the source / drain region after the formation of the back contact and back distribution network according to an embodiment of the present invention. [Modes for carrying out the invention]

[0051] The following description, with reference to the accompanying drawings, is provided to aid in a comprehensive understanding of the exemplary embodiments of the invention as defined by the claims and their equivalents. Various specific details are included to aid in that understanding, but these are considered merely illustrative. Therefore, those skilled in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the invention. In addition, for clarity and brevity, descriptions of well-known functions and structures may be omitted.

[0052] The terms and words used in the following description and claims are not limited to their figurative meanings, but are used solely to ensure a clear and consistent understanding of the present invention. Accordingly, it should be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention is provided for illustrative purposes only and is not intended to limit the present invention as defined by the appended claims and their equivalents.

[0053] The singular forms "a," "an," and "the" are understood to refer to multiple objects unless the context makes it clear otherwise. Therefore, for example, a reference to "constituent surfaces" refers to one or more such surfaces unless the context makes it clear otherwise.

[0054] Detailed embodiments of the claimed structure and method are disclosed herein, but it should be understood that the disclosed embodiments are merely illustrative of the claimed structure and method, which may be embodied in various forms. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the exemplary embodiments described herein. Rather, these exemplary embodiments are provided so that this disclosure is thorough and complete and so that the scope of the invention may be fully conveyed to those skilled in the art. Details of well-known features and techniques may be omitted in the description to avoid unnecessarily obscuring these embodiments.

[0055] References in this specification such as “one embodiment,” “an embodiment,” and “an example embodiment” indicate that the embodiments described may include certain features, structures, or characteristics, but not all embodiments may include such features, structures, or characteristics. Furthermore, such phrasing does not necessarily refer to the same embodiment. Moreover, when certain features, structures, or characteristics are described in relation to one embodiment, it is assumed that those skilled in the art will know that this affects such features, structures, or characteristics in relation to other embodiments, whether or not they are explicitly described.

[0056] For the purposes of the following description, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” and “bottom,” and their derivatives, are used in relation to the disclosed structures and methods as oriented in the drawings. The terms “overlying,” “atop,” “on top,” “positioned on,” or “positioned atop” mean that a first element, such as a first structure, is located on a second element, such as a second structure, and an intervening element, such as an interface structure, may be located between the first and second elements. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected at the interface of the two elements without an intermediate conductive, insulating, or semiconductor layer.

[0057] To avoid ambiguity in the presentation of embodiments of the present invention, some processing steps or operations known in the art may be combined for presentation and illustrative purposes in the following detailed description, and in some cases may not be described in detail. In other cases, some processing steps or operations known in the art may not be described at all. It should be understood that the following description focuses rather on the distinctive features or elements of various embodiments of the present invention.

[0058] This specification describes various embodiments of the present invention with reference to the relevant drawings. Alternative embodiments can be devised without departing from the scope of the present invention. The following description and drawings describe various connections and positional relationships between elements (e.g., above, below, adjacent, etc.). These connections and / or positional relationships may be direct or indirect unless otherwise specified, and the present invention is not intended to be limited in this respect. Accordingly, the connection between entities may refer to a direct or indirect connection, and the positional relationship between entities may be a direct or indirect positional relationship. As an example of an indirect positional relationship, when this description refers to forming layer "A" on layer "B", it includes a situation where the intermediate layer (e.g., layer "C") is located between layer "A" and layer "B", unless the relevant properties and functionalities of layer "A" and layer "B" are substantially altered by the intermediate layer.

[0059] The following definitions and abbreviations should be used in the claims and in the interpretation of this specification. When used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains,” or “containing,” or any other variation thereof, are intended to encompass non-exclusive inclusion. For example, a complex, mixture, process, method, article, or apparatus comprising a list of elements is not necessarily limited to those elements alone, and may include other elements not expressly enumerated, or other elements specific to such complex, mixture, process, method, article, or apparatus.

[0060] In addition, the term “exemplary” is used herein to mean “serving as an example, case, or illustration.” Any embodiment or design described herein as “exemplary” should not necessarily be construed as being preferable or advantageous to other embodiments or designs. The terms “at least one” and “one or more” may be understood to include any integer greater than or equal to 1, i.e., 1, 2, 3, 4, etc. The term “a plurality” may be understood to include any integer greater than or equal to 2, i.e., 2, 3, 4, 5, etc. The term “connection” may include both indirect and direct “connections.”

[0061] When used herein, the term “about” modifies the amounts of components, constituents, or reactants of the present invention employed, referring to, for example, variations in quantity that may occur through typical measurement and liquid handling procedures used to make concentrations or solutions. Furthermore, variations may arise from careless errors in measurement procedures, differences in production, source, or purity of components employed to make compositions or to perform methods, and the like. The terms “about” or “substantially” are intended to include the degree of error associated with the measurement of a particular quantity based on the equipment available at the time of filing this application. For example, “about” may include a range of ±8%, 5%, or 2% of a given value. In another embodiment, the term “about” means within 5% of the reported value. In another embodiment, the term “about” means within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported value.

[0062] The various processes used to form microchips that will be packaged into integrated circuits (ICs) are classified into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process of growing, coating, or otherwise transferring material onto a wafer. Available technologies include, among many others, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Removal / etching is any process of removing material from a wafer. Examples include etching (wet or dry), reactive ion etching (RIE), chemical-mechanical planarization (CMP), and similar processes. Semiconductor doping is the modification of electrical properties by doping the source and drain of a transistor, for example, generally by diffusion and / or ion implantation. Following these doping processes, furnace annealing or rapid thermal annealing (RTA) is performed. Annealing serves to activate the injected dopants. Both conductive (e.g., aluminum, copper, etc.) and insulating (e.g., various forms of silicon dioxide, silicon nitride, etc.) films are used to connect and separate electrical components. Selective doping of different regions of the semiconductor substrate makes it possible to change the conductivity of the substrate by applying a voltage.

[0063] Embodiments of the present invention are described in detail here, examples of embodiments of the present invention are shown in the accompanying drawings, and similar reference numerals throughout refer to similar elements. The present invention is toward the formation of nanosheet transistors on self-aligned back contacts. A plurality of first sacrificial components are formed on a first interlayer dielectric layer (back interlayer dielectric layer) placed on a first substrate. The first dielectric layer is formed on the first interlayer dielectric layer and the plurality of first sacrificial components. A plurality of alternating layers (alternating sacrificial and channel layers, e.g., nanosheets) are formed on a second substrate, and a second dielectric layer is formed on the alternating layers. The present invention utilizes two separate starting substrates to form initial components / layers separately on each starting substrate. The second substrate (e.g., a substrate with alternating layers) is inverted, and the second substrate is attached / bonded to the first dielectric layer placed on the first substrate. The first and second dielectric layers may consist of different dielectric materials or the same dielectric material. An adhesive seam is formed, where the two dielectric layers are bonded to each other, and the first and second dielectric layers are composed of the same dielectric material. The present invention has back-side contact placeholders (i.e., a plurality of first sacrificial components) formed independently and separately from the alternating layers forming the nanosheet transistor.

[0064] Figure 1 shows a top view of a plurality of devices, nanosheet transistors, or transistors according to an embodiment of the present invention. Section X1 extends horizontally through one nanodevice, nanostack, or transistor of the device. Section X2 extends horizontally through one nanodevice, nanostack, or transistor of the device, where section X1 is parallel to section X2. Sections X1 and X2 extend perpendicular to the gate direction. Section Y is perpendicular to sections X1 and X2, where section Y passes through source / drain regions spanning multiple nanostacks. Section Y is parallel to the gate direction.

[0065] Referring here to Figures 2, 3, and 6, the structure at an intermediate stage of a method for manufacturing a nanosheet transistor structure on a first substrate (substrate A) according to one embodiment of the present invention is shown. Referring here to Figures 4, 5, and 6, the structure at an intermediate stage of a method for manufacturing a nanosheet transistor structure on a first substrate (substrate B) according to one embodiment of the present invention is shown. Figures 2, 3, and 6 show the processing stage after the formation of a plurality of back-side contact placeholders in the back-side interlayer dielectric layer placed on substrate A. Figures 2, 3, and 6 show the first substrate 105, the back-side interlayer dielectric layer 110, the first back-side contact placeholder 112, the second back-side contact placeholder 114, and the first dielectric layer 115. The first dielectric layer 115 is composed of a first dielectric material.

[0066] Figures 4, 5, and 7 show the processing steps after the formation of multiple alternating layers. Figures 4, 5, and 7 show the second substrate 120, etching stop 125, third substrate 130, multiple alternating sacrificial layers 135 and channel layer 140, and second dielectric layer 145. The second dielectric layer 145 is composed of a second dielectric material, where the first dielectric material and the second dielectric material may be the same or different. For reasons of simplicity, it is assumed that the first dielectric layer 115 and the second dielectric layer 145 are composed of the same dielectric material. However, this is not limited to a limiting view, and those skilled in the art can see that these layers may be composed of different dielectric materials.

[0067] The first substrate 105, the second substrate 120, and the third substrate 130 can be, for example, materials containing silicon (Si), silicon germanium (SiGe), Si:C (carbon-doped silicon), carbon-doped silicon germanium (SiGe:C), III-V compound semiconductors, II-V compound semiconductors, or other similar semiconductors, but are not necessarily limited to these. Furthermore, multi-layer semiconductor materials can be used as the semiconductor materials for the first substrate 105, the second substrate 120, and the third substrate 130. In some embodiments, the first substrate 105, the second substrate 120, and the third substrate 130 contain both semiconductor and dielectric materials. The semiconductor first substrate 105, the second substrate 120, and the third substrate 130 may also include organic semiconductors, or layered semiconductors such as Si / SiGe, silicon-on-insulators, or SiGe-on-insulators. Furthermore, part or all of the first semiconductor substrate 105, the second substrate 120, and the third semiconductor substrate 130 may be composed of amorphous, polycrystalline, or single crystal materials. The first semiconductor substrate 105, the second substrate 120, and the third semiconductor substrate 130 may be doped or undoped, and may contain doped and undoped regions.

[0068] The etching stop 125 may be composed of, for example, epitaxial SiGe or SiO2, or another suitable material. The alternating layers have multiple channel layers 140 (e.g., Si nanosheets) and multiple sacrificial layers 135. The multiple sacrificial layers 135 may be composed of SiGe, where Ge is in the range of 15% to 35%. The multiple channel layers 140 may be composed of, for example, Si.

[0069] Figures 8, 9, 10, 11, 12, and 13 show the processing steps after inverting substrate B so that the second dielectric layer 145 faces / orients the first dielectric layer 115. Figures 14, 15, and 16 show the processing steps after substrate B is attached to substrate A and the removal of multiple layers. After inverting substrate B, substrate B is attached / bonded to substrate A, so that substrates A and B are not referred to as separate substrates.

[0070] The second dielectric layer 145, located on substrate B, is attached / bonded to the first dielectric layer 115, located on substrate A. An adhesive seam 150 is formed between the first dielectric layer 115 and the second dielectric layer 145 if the dielectric layers are composed of the same dielectric material. If the first dielectric layer 115 and the second dielectric layer 145 are composed of different dielectric materials, two separate dielectric layers are formed, and / or an adhesive seam 150 may be further formed. The second substrate 120, etching stop 125, and third substrate 130 are removed. A sacrificial layer 135 needs to be formed on the third substrate 130 to allow the formation of alternating layers. The sacrificial layer 135 is removed, exposing the upper channel layer 140, which is the channel layer 140 formed closest to the removed third substrate 130. At this stage of processing, the first dielectric layer 115, the adhesive seam 150, and the second dielectric layer 145 separate the alternating layers from the back interlayer dielectric layer 110 and the back contact placeholders 112 and 114.

[0071] Figures 17, 18, and 19 show the subsequent processing steps in which the alternating layer separation stage is divided into multiple rows and the formation of dummy gates 155, hard masks 165, and upper spacers 160. Figure 19 shows how the alternating layers are divided into multiple rows. Each row should be aligned / oriented on one of the back contact placeholders 112, 114. Figure 19 shows the alternating rows being misaligned on the back contact placeholders 112, 114. The misalignment means that the alternating rows are not perfectly positioned above the back contact placeholders 112, 114. Figures 17 and 18 show that the dummy gates 155 are formed on the upper channel layer 140 and the hard masks 165 are formed on the dummy gates 155. The hard masks 165 and dummy gates 155 are etched / patterned to form multiple rows. The upper spacers 160 or gate spacers are formed on the respective side walls of the rows of dummy gates 155 and hard masks 165.

[0072] Figures 20, 21, and 22 show the subsequent processing steps of dividing the alternating layers into multiple rows, forming internal spacers 167, and removing portions of the alternating layers to form source / drain regions. The alternating layers are etched to form multiple rows or nanostacks and to form source / drain regions. The sacrificial layer 135 is recessed to form voids / empty spaces around the edges of the channel layer 140. The voids / empty spaces are filled with internal spacers 167. One of the source / drain regions is aligned / positioned above the first back contact placeholder 112, and the other source / drain region is aligned / positioned above the second back contact placeholder 114.

[0073] Figures 23, 24, and 25 show the processing steps after etching the first and second dielectric layers 115, 145 and the adhesive seam 150 to expose the back contact placeholders 112, 114. The second dielectric layer 145, the adhesive seam 150, and the first dielectric layer 115 are etched in the source / drain region to expose the top surfaces of the first and second back contact placeholders 112, 114. In situations where the etching process is not properly aligned, the top surface of the back interlayer dielectric layer 110 is exposed. The back interlayer dielectric layer 110 acts as an etching stop for the etching process to expose the first and second back contact placeholders 112, 114.

[0074] Figures 26, 27, and 28 show the post-formation processing steps for the sources / drains 170, 172, 177, and 179. The first source / drain 172 grows epitaxially on the first back contact placeholder 112, and the second source / drain 170 grows epitaxially in the source / drain region on the second dielectric layer 145. The first source / drain 172 extends downward through the first dielectric layer 115, the second dielectric layer 145, and the adhesive seam 150, which are in contact with the front / top surface of the first back contact placeholder 112. The bottom surface of the first source / drain 172 is positioned lower than the bottom surface of the second source / drain 170. The third source / drain 179 grows epitaxially on the second back contact placeholder 114, and the fourth source / drain 177 grows epitaxially in the source / drain region on the second dielectric layer 145. Figure 27 shows a substrate spacer 175 positioned between the second back contact placeholder 114 and the third source / drain 179. The bottom surface of the third source / drain 179 is positioned lower than the bottom surface of the fourth source / drain 177.

[0075] The first source / drain 172, second source / drain 170, third source / drain 179, and fourth source / drain 177 may be, for example, n-type epitaxy or p-type epitaxy. In the case of n-type epitaxy, an n-type dopant selected from the group of phosphorus (P), arsenic (As), and / or antimony (Sb) may be used. In the case of p-type epitaxy, a p-type dopant selected from the group of boron (B), gallium (Ga), indium (In), and / or thallium (Tl) may be used. Other doping techniques may be used, such as ion implantation, gas-phase doping, plasma doping, plasma immersion ion implantation, cluster doping, implantation doping, liquid-phase doping, solid-phase doping, and / or any suitable combination of these techniques. In some embodiments, the dopant is activated by thermal annealing, such as laser annealing, flash annealing, rapid thermal annealing (RTA), or any suitable combination of these techniques.

[0076] Figures 29, 30, and 31 show the processing steps after the formation of the front interlayer dielectric layer 180. The front interlayer dielectric layer 180 is formed on and around the source / drain 170, 172, 177, and 179. The front interlayer dielectric layer 180 is also formed on the second dielectric layer 145.

[0077] Figures 32, 33, and 34 show the post-processing steps after the removal of the hard mask 165, dummy gate 155, and sacrificial layer 135, the formation of the gate 185, the increase in height of the front interlayer dielectric layer 180, and the formation of the front contacts 182, 184. The hard mask 165 is removed, for example, by chemical mechanical processing (CMP) to expose the dummy gate 155. The dummy gate 155 and sacrificial layer 135 are selectively removed to create empty space / voids for the formation of the gate 185. The gate 185 is formed around the channel layer 140 and extends above the upper channel layer 140, positioned between segments of the upper spacer 160. The gate 185 is made of, for example, HfO2, ZrO2, HfL a O x It may consist of a gate dielectric liner such as a high-k dielectric, a work function layer such as TiN, TiAlC, or TiC, and a conductive metal filler such as W.

[0078] An additional front interlayer dielectric 180 is deposited to extend the layer above the gate 185. Multiple trenches (not shown) are formed in the front interlayer dielectric layer 180. The multiple trenches are filled with conductive metal during the metallization process to form front contacts 182, 184. The front contacts 172, 174 are located above and in contact with the second source / drain 170 and the fourth source / drain 177, respectively.

[0079] Figures 35, 36, and 37 show the processing steps after the formation of the wiring process (BEOL) layer 190 and carrier wafer 195, inversion of the nanodevices for backside processing, and removal of the first substrate 105. The wiring process (BEOL) layer 190 is formed on the front surface of the front interlayer dielectric layer 180 and the front surfaces of the front contacts 182 and 184. The carrier wafer 195 is attached to the BEOL layer 190, and the nanodevices are inverted for backside processing. The first substrate 105 is removed so as to expose the back surface of the back interlayer dielectric layer 110 and the back surfaces of the first and second back contact placeholders 112 and 114.

[0080] Figures 38, 39, and 40 show the processing steps after the removal of the back contact placeholders 112 and 114 and the grooving of the sources / drains 172 and 179. The first and second back contact placeholders 112 and 114 are removed. The removal of the first and second back contact placeholders 112 and 114 may expose the back surface of the first source / drain 172 or the back surface of the substrate spacer 175. Grooving the back surface of the first source / drain 172 creates a depression / crater in the source / drain, thereby increasing the exposed surface area of ​​the first source / drain 172. The depression / crater may extend to a position below, at the same height as, or above the level of the adhesive seam 150. Grooving the third source / drain 179 removes the substrate spacer 175. The first dielectric layer 115, the adhesive seam 150, and the second dielectric layer 145 prevent one of the adjacent gates 185 from being exposed by the grooving process. Removal of the first back contact placeholder 112 and grooving of the first source / drain 172 create the first back contact trench 200. Removal of the second back contact placeholder 114 and grooving of the third source / drain 179 create the second back contact trench 205. The first dielectric layer 115, the adhesive seam 150, and the second dielectric layer 145 act as isolation layers between the first and second back contact trenches 200, 205 and the adjacent gates 185, respectively.

[0081] Figures 41, 42, and 43 show the post-formation processing steps for the backside contacts 210, 215 and the backside power distribution network 229. The first backside contact trench 200 and the second backside contact trench 205 are filled with conductive metal to form the first backside contact 210 and the second backside contact 215. The first backside contact trench 200 and the second backside contact trench 205 may contact the first dielectric layer 115. The first backside contact trench 200 and the second backside contact trench 205 may also contact the adhesive seam 150 and / or the second dielectric layer 145, depending on the penetration depth of the first source / drain 172 and the third source / drain 179. The backside power distribution network (BSPDN) 220 is formed on the backside interlayer dielectric layer 110 and on the first and second backside contacts 210, 215. The second dielectric layer 145, the adhesive seam 150, and the first dielectric layer 115 form multiple isolation layers that separate the nanosheet transistor from the back contacts 210, 215, and BSPDN 220. The first source / drain 172 and the third source / drain 179 extend through the multiple isolation layers to connect with the back contacts 210, 215, respectively. As a result, the second dielectric layer 145, the adhesive seam 150, and the first dielectric layer 115 contact the sidewalls of the first source / drain 172 and the third source / drain 179.

[0082] While the present invention has been shown and described with reference to certain exemplary embodiments, it will be understood by those skilled in the art that various modifications in form and detail may be made without departing from the spirit and scope of the invention as defined by the appended claims and equivalents.

[0083] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to exhaust or limit the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments described. The terms used herein have been selected to best describe the principles of one or more embodiments, practical applications or technical improvements to technologies available on the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A nanosheet transistor including a first source / drain and a second source / drain, The front contact connected to the first source / drain and the back contact connected to the second source / drain, A plurality of isolation layers are arranged beneath the nanosheet transistor, Equipped with, The second source / drain extends through the plurality of separation layers and connects to the back contact, Microelectronic devices.

2. The microelectronic device according to claim 1, wherein one of the plurality of separation layers is in direct contact with the back surface of the first source / drain.

3. The microelectronic device according to any one of the preceding claims, wherein the back surface of the first source / drain and the back surface of the second source / drain are arranged at different heights.

4. The microelectronic device according to any one of the preceding claims, wherein the plurality of isolation layers include at least a first dielectric layer and a second dielectric layer.

5. The microelectronic device according to claim 4, wherein the first dielectric layer and the second dielectric layer are made of the same dielectric material.

6. The microelectronic device according to any one of claims 4 to 5, further comprising an adhesive seam disposed between the first dielectric layer and the second dielectric layer.

7. The first dielectric layer is in contact with the back surface of the first source / drain. The microelectronic device according to any one of claims 4 to 6, wherein the first dielectric layer is in contact with the sidewall of the second source / drain.

8. The microelectronic device according to any one of claims 4 to 7, wherein the back contact is in contact with the second dielectric layer.

9. The microelectronic device according to any one of claims 4 or 6 to 8, wherein the first dielectric layer and the second dielectric layer are composed of different dielectric materials.

10. A nanosheet transistor including a first source / drain and a second source / drain, The front contact connected to the first source / drain and the back contact connected to the second source / drain, A plurality of isolation layers are arranged beneath the nanosheet transistor, Equipped with, The second source / drain extends through the plurality of separation layers and connects to the back contact, The aforementioned back contact extends into the plurality of separation layers and connects to the second source / drain. Microelectronic devices.

11. The microelectronic device according to claim 10, wherein one of the plurality of separation layers is in direct contact with the back surface of the first source / drain.

12. The microelectronic device according to any one of claims 10 to 11, wherein the back surface of the first source / drain and the back surface of the second source / drain are arranged at different heights.

13. The microelectronic device according to any one of claims 10 to 12, wherein the plurality of isolation layers include at least a first dielectric layer and a second dielectric layer.

14. The microelectronic device according to claim 13, wherein the first dielectric layer and the second dielectric layer are made of the same dielectric material.

15. The microelectronic device according to any one of claims 13 to 14, further comprising an adhesive seam disposed between the first dielectric layer and the second dielectric layer.

16. The first dielectric layer is in contact with the back surface of the first source / drain. The microelectronic device according to any one of claims 13 to 15, wherein the first dielectric layer is in contact with the sidewall of the second source / drain.

17. The microelectronic device according to any one of claims 13 to 16, wherein the back contact is in contact with the second dielectric layer.

18. The microelectronic device according to any one of claims 13 or 15 to 17, wherein the first dielectric layer and the second dielectric layer are composed of different dielectric materials.

19. The steps include forming a back-side interlayer dielectric layer on the first substrate, The steps include forming at least one back-side contact placeholder in the back-side interlayer dielectric layer, The steps include forming a first dielectric layer on the back-side interlayer dielectric layer and on the at least one back-side contact placeholder, The steps include forming a plurality of alternating layers, each consisting of a channel layer and a sacrificial layer, on a second substrate, The steps include forming a second dielectric layer on the alternating layers, The steps include inverting the second substrate and attaching the second dielectric layer to the first dielectric layer, The step of forming a nanosheet transistor from the alternating layers, A method for providing this.

20. Step of forming an adhesive seam between the first dielectric layer and the second dielectric layer. The method according to claim 19, further comprising:

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