Semiconductor die containing a group III nitride-based amplifier circuit

Abstract

Several semiconductor dies are described that include a group III nitride-based amplifier circuit. In one example, the semiconductor die includes a first group III nitride-based transistor having a first output contact. The semiconductor die includes a second group III nitride-based transistor having a second output contact. The semiconductor die includes an output combiner inductor on the semiconductor die. The output combiner inductor may be coupled to the first and second output contacts. The output combiner inductor may further be coupled to a high-frequency (RF) output interface to the semiconductor die.

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims the benefit and priority of U.S. Patent Provisional Application No. 63 / 512,417, filed on July 7, 2023, entitled “COMPACT SEMICONDUCTOR DIE WITH GROUP III NITRIDE-BASED AMPLIFIER,” which is incorporated herein by reference in its entirety. [Background technology]

[0002] High-frequency driver amplifiers are used in a wide range of communication systems, radar systems, and associated radio frequency (RF) systems. In some applications, it is desirable that such driver amplifiers have a wide bandwidth and operate with high efficiency, among other operating characteristics of the target. As an exemplary amplifier circuit topology, the Doherty amplifier is often well suited to such applications. The Doherty amplifier can provide increased efficiency while maintaining signal linearity. To achieve higher efficiency at both low and high power levels, the Doherty amplifier may use a combination of two or more amplifiers (e.g., a carrier or base amplifier and one or more peaking amplifiers). Power semiconductor devices for driver amplifiers in Doherty and associated amplifiers may be fabricated from wide-bandgap semiconductor materials. For example, high electron-mobility transistors (HEMTs) may be fabricated from gallium nitride (GaN) or other group III nitride-based materials formed on silicon, silicon carbide or other substrates, for example. [Overview of the project]

[0003] A summary of some aspects of the ideas and embodiments described herein is provided below. These embodiments are representative and not exhaustive. In alternative embodiments, certain features and elements may be added, omitted, and interchangeable. Furthermore, those skilled in the art can modify, extend, and change the exemplary embodiments to include equivalent and related structures without departing from the idea.

[0004] An exemplary semiconductor die includes a first group III nitride-based transistor having a first output contact on a substrate, a second group III nitride-based transistor having a second output contact on a substrate, an output combiner inductor on a substrate coupled to the first and second output contacts, and a high-frequency (RF) output interface coupled to the output combiner inductor.

[0005] Another exemplary semiconductor die includes a first group III nitride-based transistor on a substrate, a second group III nitride-based transistor on a substrate, a first input matching circuit on a substrate and coupled to the gate of the first group III nitride-based transistor, and a second input matching circuit on a substrate and coupled to the gate of the second group III nitride-based transistor.

[0006] An exemplary monolithic microwave integrated circuit (MMIC) includes a first Group III nitride-based transistor on a substrate, a second Group III nitride-based transistor on a substrate, a first input matching circuit on a substrate and coupled to the gate of the first Group III nitride-based transistor, a second input matching circuit on a substrate and coupled to the gate of the second Group III nitride-based transistor, an output combiner inductor on a substrate, and a high-frequency (RF) output interface coupled to the output combiner inductor. The output combiner inductor can be coupled to a first output contact of the first Group III nitride-based transistor and a second output contact of the second Group III nitride-based transistor.

[0007] The aspects of this disclosure can be better understood by referring to the drawings below. Note that the elements in the drawings are not necessarily drawn at a constant scale, but rather are exaggerated to illustrate the principle in an example. Throughout some of the drawings, similar reference numerals indicate similar or corresponding elements that are not necessarily the same. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic block diagram of an exemplary Doherty amplifier. [Figure 2] This figure shows an exemplary semiconductor die layout related to an amplification circuit according to an exemplary embodiment of the present disclosure. [Figure 3] Figure 2 is a schematic diagram of an amplifier circuit related to a semiconductor die, according to an exemplary embodiment of the present disclosure. [Figure 4] This figure shows an exemplary semiconductor die layout related to an amplification circuit according to an exemplary embodiment of the present disclosure. [Figure 5] Figure 4 is a schematic diagram of an amplifier circuit related to a semiconductor die, according to an exemplary embodiment of the present disclosure. [Figure 6]This figure shows an exemplary semiconductor die layout related to an amplification circuit according to an exemplary embodiment of the present disclosure. [Figure 7] Figure 6 is a schematic diagram of an amplifier circuit related to a semiconductor die, according to an exemplary embodiment of the present disclosure. [Figure 8] This figure shows an exemplary semiconductor die layout related to an amplification circuit according to an exemplary embodiment of the present disclosure. [Figure 9] Figure 8 is a schematic diagram of an amplifier circuit related to a semiconductor die, according to an exemplary embodiment of the present disclosure. [Figure 10] This is a cross-sectional view of an exemplary unit cell of a high electron-mobility transistor (HEMT) device according to an exemplary embodiment of the present disclosure. [Modes for carrying out the invention]

[0009] Next, embodiments will be referenced in detail. One or more examples of these embodiments are shown in the figures. Each example is shown to illustrate an embodiment and is not intended to limit the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments without departing from the scope or spirit of the disclosure. For example, features illustrated or described as part of one embodiment can be used together with another embodiment to create further additional embodiments. Thus, aspects of the disclosure are intended to cover such modifications and variations.

[0010] Aspects of a semiconductor die that includes a group-III nitride-based amplifier circuit are described. In some cases, this semiconductor die can be relied upon as a compact high-frequency (RF) amplifier that includes a monolithic microwave integrated circuit (MMIC) amplifier. The inventive concept of the semiconductor die described herein is applicable to a range of different RF amplifiers, such as Doherty amplifiers and other types of RF amplifiers. A typical Doherty amplifier includes a combination of a main or carrier amplifier and one or more peaking amplifiers coupled in parallel, and a range of Doherty-type amplifier circuit topologies are known. In some implementations, the carrier amplifier processes most of the input RF signal power, and the peaking amplifiers selectively amplify the RF signal during high power transmission periods. This configuration enables the Doherty amplifier to achieve signal linearity over a wide range of RF signal powers, which makes the Doherty amplifier a suitable option in various wireless communication systems, such as multiple-input multiple-output (MIMO)-based communication systems.

[0011] In RF amplifier applications, semiconductor devices such as high electron mobility transistors (HEMTs) may be used. Due to a combination of material properties including a high breakdown electric field, a wide bandgap, a large conduction band offset, a high saturated electron drift velocity, and related characteristics, HEMTs fabricated using a group-III nitride-based material system have the potential to generate substantial RF power. Therefore, group-III nitride-based HEMTs are excellent candidates for high-frequency high-power RF applications and low-frequency power switching applications.

[0012] Aspects of the present disclosure are directed to implementing an amplifier circuit, such as a Doherty amplifier circuit, using one or more group-III nitride-based transistors on a compact wide-bandgap semiconductor die. To provide a relatively small increase in semiconductor die size and high performance at a lower cost compared to other approaches, one or more aspects of the amplifier circuit may be implemented as integrated elements (e.g., inductors, capacitors, transmission lines, etc.) within the white space on the semiconductor die or substrate.

[0013] FIG. 1 shows a schematic block diagram of an exemplary Doherty amplifier 50. The Doherty amplifier 50 is shown in the context of describing an embodiment as a representative example. The concepts described herein are applicable to amplifiers of other types and topologies, including both Doherty amplifiers and other amplifiers. The schematic block diagram of the Doherty amplifier 50 is not shown comprehensively, and the Doherty amplifier 50 may include other components not shown. Also, in some cases, the Doherty amplifier 50 may omit one or more of the components shown in FIG. 1.

[0014] The Doherty amplifier 50 includes an RF input power splitter 52. The RF input power splitter 52 can split an RF signal into a first path 54 and a second path 56. The first path 54 may include a carrier amplifier 58. The second path 56 may include a peaking amplifier 60. The carrier amplifier 58 may be operable to process most of the input RF signal power, while the peaking amplifier 60 selectively amplifies the RF signal during high power transmission periods. The outputs of the carrier amplifier 58 and the peaking amplifier 60 may be combined and used to drive a load 62. The load 62 may be implemented or executed as an antenna or other interface of a communication system, such as a MIMO-based communication system. In some examples, a phase shifter 64 (e.g., a 90° phase shifter or a λ / 4 phase shifter) may be implemented on the second path 56 before the peaking amplifier 60. Also, as shown in FIG. 1, a phase shifter 66 (e.g., a 90° phase shifter or a λ / 4 phase shifter) may be implemented on the first path 54 after the carrier amplifier 58.

[0015] In one example, the RF input power divider 52 may be implemented as a lumped Wilkinson power divider circuit. However, the RF input power divider 52 may also be implemented as other types of divider circuits and circuit configurations. In some embodiments, the RF input power divider 52 may provide a substantially equal power divide between the carrier amplifier and the peaking amplifier. However, in other cases, the RF input power divider 52 may provide a different power divide. For example, the power divider of the RF input power divider 52 and the bias of the peaking amplifier 60 may be selected or modified to change the turn-on power of the peaking amplifier and the inflection point ("back-off" power level) of the output power / efficiency curve of the Doherty amplifier 50.

[0016] In some examples, the RF input power divider 52 is not a Wilkinson power divider. Rather, the RF input power divider 52 may simply be a node from which two or more separate paths (e.g., a first path 54 and a second path 56) are divided from a common path. Depending on the desired RF power division between the carrier amplifier 58 and the peaking amplifier 60, the two separate paths may have the same impedance or different impedances.

[0017] The carrier amplifier 58 and the peaking amplifier 60 can each be implemented as one or more power transistor amplifiers or amplification circuits, including a multistage power amplification circuit. According to exemplary embodiments of this disclosure, the carrier amplifier 58 and the peaking amplifier 60 are implemented using Group III nitride-based HEMTs. Exemplary Group III nitride-based HEMTs will be discussed in further detail later with reference to Figure 10.

[0018] Figure 2 shows an exemplary semiconductor die 100. The semiconductor die 100 is shown as a representative example. The features of the semiconductor die 100 are not exhaustively described, and the semiconductor die 100 may include other components or features not shown. Also, in some cases, the semiconductor die 100 may omit one or more components from those shown in Figure 2. The semiconductor die 100 can be used to implement various embodiments of an amplification circuit 102, such as a Doherty amplifier, according to exemplary embodiments of this disclosure. For example, the semiconductor die 100 can be implemented as a single type of MMIC, including a range of active and passive circuit components implemented on a single common substrate. However, it is not necessary in all cases for the semiconductor die 100 to be implemented as an MMIC.

[0019] The semiconductor die 100 includes a substrate 104, such as a monolithic wide-bandgap semiconductor substrate. In some examples, the substrate 104 can be a silicon carbide substrate. However, other suitable substrates, including silicon, sapphire, and other suitable substrates, may be used, without departing from the scope of this disclosure. The substrate 104 may include one or more semiconductor material layers formed as a stack on a base substrate or wafer. The semiconductor material layers may include one or more doped and undoped gallium nitride material layers, such as a gallium nitride material conductive layer for a group III nitride-based transistor. The semiconductor material layers may include one or more heterojunctions for active devices as will be understood in the art. These and other embodiments will be described in further detail later with reference to Figure 10.

[0020] The semiconductor die 100 includes a first group III nitride-based transistor 106 (also referred to as the “first transistor 106”) formed at least partially in, on, and above the substrate 104. The first transistor 106 may include one or more unit cell transistor devices, such as one or more unit cell HEMT devices. Exemplary unit cell HEMT devices will be described further later with reference to Figure 10. The first transistor 106 may be used to implement a main amplifier, carrier amplifier, or associated amplifier according to exemplary embodiments of the present disclosure. Among other features, the first transistor 106 particularly includes an input contact 108 and an output contact 110. The input contact 108 can be implemented as the gate contact of the first transistor 106, or the input contact 108 can be coupled to the gate contact of the first transistor 106. The output contact 110 can be implemented as the drain contact of the first transistor 106, or the output contact 110 can be coupled to the drain contact of the first transistor 106.

[0021] The semiconductor die 100 includes a second group III nitride-based transistor 112 (also referred to as the "second transistor 112") formed at least partially in, on, and above the substrate 104. The second transistor 112 may include one or more unit cell transistor devices, such as one or more unit cell HEMT devices. The second transistor 112 may be used to implement a peaking amplifier or associated amplifier according to exemplary embodiments of the present disclosure. The second transistor 112 may, among other features, include an input contact 114 and an output contact 116. The input contact 114 can be implemented as the gate contact of the second transistor 112, or the input contact 114 can be coupled to the gate contact of the second transistor 112. The output contact 116 can be implemented as the drain contact of the second transistor 112, or the output contact 116 can be coupled to the drain contact of the second transistor 112.

[0022] To implement various embodiments of the amplification circuit 102, the semiconductor die 100 includes lumped elements on the substrate 104. For example, as shown in Figure 2, the semiconductor die 100 includes an output combiner inductor 118. The output combiner inductor 118 may be a lumped element coupled, for example, to the output contacts 110 of the first transistor 106 and the output contacts 116 of the second transistor 112. In some examples, the output combiner inductor 118 is a helical inductor. The output combiner inductor 118 may couple the outputs of the first transistor 106 and the second transistor 112. The output combiner inductor 118 may be configured to perform a phase shift (e.g., a 90° phase shift or a λ / 4 phase shift) of the RF signal from the output contacts 110 of the first transistor 106. The output combiner inductor 118 may be coupled to the RF output interface 120 of the semiconductor die 100. In some cases, the output combiner inductor 118 may provide an RF output impedance of approximately 10 ohms or more relative to the semiconductor die 100 at the RF output interface 120. In other cases, the output combiner inductor 118 may also provide other RF output impedances greater than or less than 10 ohms.

[0023] Furthermore, the semiconductor die 100 may include a first input matching circuit 122 on the substrate 104. The first input matching circuit 122 may be coupled to the input contact 108 of the first transistor 106. The first input matching circuit 122 may be coupled to a first RF input interface 124 on the semiconductor die 100. The first RF input interface 124 can be implemented as a first input contact. The first input matching circuit 122 may include one or more lumped elements (e.g., inductors, capacitors, and other passive components) to provide impedance matching between the first RF input interface 124 and the first transistor 106.

[0024] Furthermore, the semiconductor die 100 may include a second input matching circuit 126 on the substrate 104. The second input matching circuit 126 may be coupled to the input contact 114 of the second transistor 112. The second input matching circuit 126 may also be coupled to a second RF input interface 128 on the semiconductor die 100. The second RF input interface 128 can be implemented as a second input contact. In one example, the second input matching circuit 126 can be coupled to the second RF input interface 128 through a DC blocking capacitor 130 and a phase shifter inductor 132 on the semiconductor die 100. However, this coupling can be performed in other ways. The second input matching circuit 126 may include one or more lumped elements (e.g., a passive inductor and a capacitor) to provide impedance matching between the second RF input interface 128 and the second transistor 112. The DC blocking capacitor 130 may be operable to block the DC component of the RF signal from the second RF input interface 128. The phase shifter inductor 132 may be operable to perform a phase shift (e.g., a 90° phase shift or a λ / 4 phase shift) of the RF signal from the second RF input interface 128. In one example, the RF input impedance of the semiconductor die 100 may be approximately 10Ω or more. However, in other cases, the RF input impedance of the semiconductor die 100 may be greater than or less than 10Ω.

[0025] In the exemplary semiconductor die 100 shown in Figure 2, the RF input power divider for dividing the RF signal is located in an "off-chip" position (e.g., not on the semiconductor die 100). The off-chip RF input power divider (e.g., a Wilkinson input divider) may divide the RF signal into two or more paths. The first path may be coupled to the first RF input interface 124. The second path may be coupled to the second RF input interface 128.

[0026] The semiconductor die 100 may include other interfaces. For example, the semiconductor die 100 may include a first gate interface 134 for the first transistor 106 on the substrate 104. The semiconductor die 100 may also include a second gate interface 136 for the second transistor 112 on the substrate 104.

[0027] The semiconductor die 100 may include a first drain interface 138 (e.g., a first drain bias interface) for the first transistor 106 on the substrate 104. The first drain interface 138 can be implemented as an exemplary interface, specifically as a first drain bias interface for the first transistor 106. The semiconductor die 100 may also include a second drain interface 140 for the second transistor 112 on the substrate 104. The second drain interface 140 can be implemented as an exemplary interface, specifically as a second drain bias interface for the second transistor 112.

[0028] In some examples, the semiconductor die 100 may include a first source interface 142 for a first transistor 106 on the substrate 104. In some examples, the first source interface 142 is coupled to ground or a reference. The semiconductor die 100 may also include a second source interface 144 for a second group III nitride-based transistor 112 on the substrate 104. In some examples, the second source interface 144 is coupled to ground or a reference.

[0029] Figure 3 is a schematic diagram corresponding to the amplification circuit 102 on the semiconductor die 100 in Figure 2. As shown, an "off-chip" RF input power divider 146 (e.g., a Wilkinson input divider) may divide the input RF signal and provide an RF signal to a first RF input interface 124 on the semiconductor die 100 and a second RF signal to a second RF input interface 128 on the semiconductor die 100. The first RF signal may also pass through a first input matching circuit 122 to a first transistor 106, which operates as a main amplifier or carrier amplifier. The second RF signal may also pass through a DC blocking capacitor 130, a phase shifter inductor 132, and a second input matching circuit 126 to a second transistor 112, which operates as a peaking amplifier. The output of the first transistor 106 may pass through the output combiner inductor 118 and combine with the output of the second transistor 112 to provide an RF output to the load via the RF output interface 120. As an example, the load may be one or more antennas for a wireless communication system.

[0030] Refer again to Figure 2. The arrangement of elements on the semiconductor die 100 facilitates the implementation of the amplifier circuit 102 in a relatively compact form. The semiconductor die 100 may include a length L. Length L may be a long dimension related to the surface of the semiconductor die 100. The length L of the semiconductor die 100 may be about 2.8 mm or less, for example, in the range of about 2.3 mm to about 2.8 mm, or for example, about 2.5 mm. The semiconductor die 100 may have a width W. Width W may be a short dimension related to the surface of the semiconductor die 100. The width W of the semiconductor die 100 may be about 1.5 mm or less, for example, in the range of about 1.2 mm to about 1.5 mm, or for example, about 1.4 mm. The semiconductor die 100 may have a surface area (for example, the surface area of ​​the surface including the elements of the amplifier circuit 102). The surface area is about 4.2 mm². 2 It may also be less than or equal to approximately 2.7 mm. 2 ~Approximately 4.2mm 2 It may be within the range of, for example, approximately 3.2 mm2 This is also possible. However, the length L, width W, and surface area dimensions of the semiconductor die 100 may differ from the exemplary dimensions described above, depending on the implementation and design needs of the amplification circuit 102. The substrate 104 may also be defined according to the exemplary length L, width W, and surface area dimensions described above.

[0031] To facilitate implementation, the layout of the circuit elements or components of the amplifier circuit 102 on the semiconductor die 100 can be adjusted. Hereinafter, rectangular regions of the semiconductor die 100 and substrate 104 are referred to. Comparing the positions of each region, the regions define exemplary layout arrangements of the elements of the amplifier circuit 102. Although the regions are described as rectangular, regions of different shapes can also be used to understand the positional relationships. Referring to Figure 2 as an example, the semiconductor die may have a first rectangular region 148, a second rectangular region 150, and a third rectangular region 152. The second rectangular region 150 lies between the first rectangular region 148 and the third rectangular region 152. There is no overlap between the first rectangular region 148, the second rectangular region 150, and the third rectangular region 152. The output combiner inductor 118 is located within the first rectangular region 148. The first transistor 106 and the second transistor 112 are located within the second rectangular region 150. The first input matching circuit 122 and the second input matching circuit 126 are located within the third rectangular region 152.

[0032] In some examples, the first drain interface 138 is located within the first rectangular region 148. The second drain interface 140 is located within the first rectangular region 148. The RF output interface 120 is located within the first rectangular region 148. The output combiner inductor 118 is located within the region between the first drain interface 138 and the second drain interface 140. The RF output interface 120 is located within the region between the output combiner inductor 118 and the second drain interface 140.

[0033] The output combiner inductor 118 may be located near the periphery 154 of the semiconductor die 100. There may be no intervening elements related to the amplification circuit 102 within the region 156 between the output combiner inductor 118 and the periphery 154 of the semiconductor die 100.

[0034] The output combiner inductor 118 is not located within the second rectangular region 150. In some examples, the second rectangular region 150 may include a region 158 defined between the first transistor 106 and the second transistor 112. The output combiner inductor 118 is not located within the region 158 defined between the first transistor 106 and the second transistor 112. In some examples, the first source interface 142 is located within the region 158 defined between the first transistor 106 and the second transistor 112. In some examples, the second source interface 144 is located within the region 158 defined between the first transistor 106 and the second transistor 112.

[0035] In some examples, the first RF input interface 124 is located within the third rectangular region 152. The second RF input interface 128 is located within the third rectangular region 152. The DC blocking capacitor 130 is located within the third rectangular region 152. The phase shifter inductor 132 is located within the third rectangular region 152. The first gate interface 134 is located within the third rectangular region 152. The second gate interface 136 is located within the third rectangular region 152. The first gate interface 134 may be located within the region on the semiconductor die 100 between the first input matching circuit 122 and the periphery of the semiconductor die 100. The second gate interface 136 may be located between the second input matching circuit 126 and the periphery of the semiconductor die 100.

[0036] Figure 4 shows an exemplary semiconductor die 160 that may be used to implement various forms of an amplification circuit 162, such as a Doherty amplifier circuit, according to exemplary embodiments of the present disclosure. In one example, the semiconductor die 160 may relate to an MMIC including a range of active and passive circuit components implemented on a single common substrate. However, the semiconductor die 170 is not limited to being implemented as an MMIC in all cases. The semiconductor die 160 is shown as a representative example. The features of the semiconductor die 160 are not exhaustively described, and the semiconductor die 160 may include other components or features not shown. Also, in some cases, the semiconductor die 160 may omit one or more components from those shown in Figure 4.

[0037] The semiconductor die 160 is similar to the semiconductor die 100 discussed with reference to Figure 2 and includes a substrate 104. The semiconductor die 160 includes a first group III nitride-based transistor 106 and a second group III nitride-based transistor 112. The semiconductor die 160 includes an output combiner inductor 118, an RF output interface 120, a first input matching circuit 122, a second input matching circuit 126, a DC blocking capacitor 130, a first gate interface 134, a second gate interface 136, a first drain interface 138, a second drain interface 140, a first source interface 142, and a second source interface 144 on the substrate 104.

[0038] In comparison with the semiconductor die 100 in Figure 2, the semiconductor die 160 in Figure 4 includes an RF input power divider (e.g., an "on-chip" RF input power divider) on the substrate 104. More specifically, the semiconductor die 160 includes a common RF input interface 164 coupled (e.g., via a DC blocking capacitor 130 and an input combiner inductor 166) to both a first input matching circuit 122 and a second input matching circuit 126.

[0039] In some examples, the RF input power divider on the semiconductor die 160 is not a Wilkinson input divider. Rather, the RF input power divider includes a common RF input interface 164, a first input matching circuit 122, a second input matching circuit 126, and an input combiner inductor 166. The input combiner inductor 166 may be a lumped element on the substrate 104 or may include a helical inductor. The input combiner inductor 166 may be located in the region of the semiconductor die 160 between the second input matching circuit 126 and the DC blocking capacitor 130. The impedances of the first input matching circuit 122, the second input matching circuit 126, the input combiner inductor 166, and other elements (e.g., the DC blocking capacitor 130) coupled to the common RF input interface 164 may provide input RF power division between the first transistor 106 and the second transistor 112. The input combiner inductor 166 may be made to have an RF input impedance of about 10 Ω or more relative to the semiconductor die 160. However, in some cases, the RF input impedance can be greater than or less than 10Ω.

[0040] Figure 5 is a schematic diagram corresponding to the amplifier circuit 162 on the semiconductor die 160 of Figure 4. As shown, the amplifier circuit 162 includes an "on-chip" RF input power divider, which includes a common RF input interface 164, a first input matching circuit 122, a second input matching circuit 126, and an input combiner inductor 166. The on-chip RF input power divider may divide the RF signal into a first RF signal and a second RF signal. The first RF signal may pass through the first input matching circuit 122 to reach the first transistor 106. The second RF signal may pass through the DC blocking capacitor 130, the input combiner inductor 166, and the second input matching circuit 126 to reach the second transistor 112. The output of the first transistor 106 may pass through the output combiner inductor 118 and couple with the output of the second transistor 112 to provide an RF output to the load via the RF output interface 120.

[0041] Figure 6 shows an exemplary semiconductor die 170 that may be used to implement various forms of an amplifier circuit 172, such as a Doherty amplifier circuit, according to exemplary embodiments of the present disclosure. In one example, the semiconductor die 170 may relate to an MMIC including a range of active and passive circuit components implemented on a single common substrate. However, the semiconductor die 170 is not limited to being implemented as an MMIC in all cases. The semiconductor die 170 is shown as a representative example. The features of the semiconductor die 170 are not exhaustively described, and the semiconductor die 170 may include other components or features not shown. Also, in some cases, the semiconductor die 170 may omit one or more components from those shown in Figure 6. The semiconductor die 170 is similar to the semiconductor die 160 discussed with reference to Figure 4 and includes a substrate 104. The semiconductor die 170 includes a first group III nitride-based transistor 106 and a second group III nitride-based transistor 112. The semiconductor die 170 includes a common RF input interface 164, an RF output interface 120, a first input matching circuit 122, a second input matching circuit 126, a DC blocking capacitor 130, an input combiner inductor 166, a first gate interface 134, a second gate interface 136, a first drain interface 138, a second drain interface 140, a first source interface 142, and a second source interface 144 on the substrate 104.

[0042] Compared to the semiconductor die 100 in Figure 4, the semiconductor die 170 in Figure 6 includes an interface for an "off-chip" output combiner inductor. For example, the semiconductor die 170 includes a first output combiner interface 174 and a second output combiner interface 176 on the substrate 104. The first output combiner interface 174 and the second output combiner interface 176 may provide an interface for connecting a larger output combiner inductor located in an off-chip position. This larger output combiner inductor may be suitable for use at lower operating frequencies, for example, in the range of about 1.8 GHz or less, for example, in the range of about 400 MHz to about 1.8 GHz. However, it may also depend on other operating frequencies.

[0043] Figure 7 shows a schematic diagram corresponding to the amplifier circuit 172 on the semiconductor die 170 of Figure 6. As shown, the amplifier circuit 172 includes an "on-chip" RF input power divider, which includes a common RF input interface 164, a first input matching circuit 122, a second input matching circuit 126, and an input combiner inductor 166. The on-chip RF input power divider may divide the RF signal into a first RF signal and a second RF signal. The first RF signal may pass through the first input matching circuit 122 to reach the first transistor 106. The second RF signal may pass through the DC blocking capacitor 130, the input combiner inductor 166, and the second input matching circuit 126 to reach the second transistor 112. The output of the first group III nitride-based transistor 106 may pass through the off-chip output combiner inductor 178 (for example, via the first output combiner interface 174 and the second output combiner interface 176) and couple with the output of the second transistor 112 to provide an RF output to the load via the RF output interface 120.

[0044] Figure 8 shows an exemplary semiconductor die 180 that may be used to implement various forms of an amplification circuit 182, such as a Doherty amplifier circuit, according to exemplary embodiments of the present disclosure. In one example, the semiconductor die 180 may relate to an MMIC including a range of active and passive circuit components implemented on a single common substrate. However, the semiconductor die 180 is not limited to being implemented as an MMIC in all cases. The semiconductor die 180 is shown as a representative example. The features of the semiconductor die 180 are not exhaustively described, and the semiconductor die 180 may include other components or features not shown. Also, in some cases, the semiconductor die 180 may omit one or more components from those shown in Figure 6.

[0045] The semiconductor die 180 is similar to the semiconductor die 100 discussed with reference to Figure 2 and includes a substrate 104. The semiconductor die 170 includes a first group III nitride-based transistor 106 and a second group III nitride-based transistor 112. The semiconductor die 180 includes a first RF input interface 124 and a second RF input interface 128 on the substrate 104 for coupling to an off-chip RF input power divider. The semiconductor die 180 includes an RF output interface 120, a first input matching circuit 122, a second input matching circuit 126, a DC blocking capacitor 130, a phase shifter inductor 132, a first gate interface 134, a second gate interface 136, a first drain interface 138, a second drain interface 140, a first source interface 142, and a second source interface 144 on the substrate 104. The semiconductor die 180 includes an interface for an "off-chip" output combiner inductor. For example, the semiconductor die 180 includes a first output combiner interface 174 and a second output combiner interface 176 on the substrate 104.

[0046] Figure 9 shows a circuit diagram corresponding to the amplification circuit 182 on the semiconductor die 180 in Figure 8. An "off-chip" RF input power divider 146 (e.g., a Wilkinson input divider) may divide the input RF signal and provide an RF signal to a first RF input interface 124 on the semiconductor die 180 and a second RF signal to a second RF input interface 128 on the semiconductor die 180. The first RF signal may pass through a first input matching circuit 122 to reach the first transistor 106. The second RF signal may pass through a DC blocking capacitor 130, a phase shifter inductor 132 and a second input matching circuit 126 to reach the second transistor 112. The output of the first transistor 106 may pass through an off-chip output combiner inductor 178 (e.g., via a first output combiner interface 174 and a second output combiner interface 176) and couple with the output of the second transistor 112 to provide an RF output to the load via an RF output interface 120.

[0047] In another embodiment of the embodiments, Figure 10 shows a cross-sectional view of an exemplary Group III nitride-based unit cell transistor device 200 (also referred to as "HEMT200"), which is an example of a HEMT device. Using HEMT200, at least a portion of, for example, a first Group III nitride-based transistor 106 and / or a second Group III nitride-based transistor 112 can be implemented. However, transistors 106 and 112 can also be implemented and carried out as other types of transistors. The exemplary HEMT200 is provided for illustrative and discussion purposes. Those skilled in the art using the disclosures described herein will understand that other Group III nitride-based transistor devices may be used as the first Group III nitride-based transistor 106 and / or the second Group III nitride-based transistor 112. Figure 10 is an example and is intended to show a structure for identification and illustration purposes and is not intended to show the structure at any physical magnification.

[0048] HEMT200 may include a semiconductor structure 202. The semiconductor structure 202 may be a group III nitride semiconductor structure. The semiconductor structure 202 may be metallic polar. However, embodiments of this disclosure are applicable to semiconductor devices having an N-polar semiconductor structure without departing from the scope of this disclosure.

[0049] As shown, the semiconductor structure 202 is executed at least partially within, on, and above the substrate 104. As described above, the substrate 104 may be a silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, or other suitable substrate. In some embodiments, the substrate 104 may be a semi-insulating SiC substrate, which may be, for example, a 4H polytype silicon carbide. Other candidate SiC polytypes may include 3C, 6H, and 15R polytypes. In some cases, the substrate 104 may be a high-purity semi-insulating (HPSI) substrate. In this specification, the term “semi-insulating” is used descriptively rather than in an absolute sense.

[0050] In some embodiments, the SiC bulk crystal of the substrate 104 is approximately 1 × 10⁶ at room temperature. 5 Resistivity equal to Ω·cm, or approximately 1 × 10⁻⁶ 5 The resistivity may be higher than Ω·cm. Exemplary SiC substrates that may be used in some embodiments and methods for producing such substrates are described, for example, in U.S. Patents Re. 34,861, 4,946,547, 5,200,022, and 6,218,680, the disclosures of which are incorporated herein by reference. While SiC may be used as the substrate material, embodiments of this disclosure may utilize any suitable substrate such as sapphire (Al2O3), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, and indium phosphide (InP).

[0051] The substrate 104 may have a lower surface 104A and an upper surface 104B. In some embodiments, the HEMT200 substrate 104 may be a thinned substrate 104. In some embodiments, the thickness of the substrate 104 (i.e., the thickness measured vertically from the top to the bottom of the page in Figure 10) may be about 100 μm or less, for example about 75 μm or less, for example about 50 μm or less.

[0052] The HEMT200 may include a channel layer 206 on the upper surface 104B of the substrate 104 (or on an optional layer further described herein, such as an optional buffer layer or nucleation layer). The HEMT200 may include a barrier layer 208 on the upper surface of the channel layer 206. In some embodiments, the channel layer 206 and the barrier layer 208 may each be formed by epitaxial growth. Techniques for epitaxial growth of group III nitrides are described, for example, in U.S. Patents 5,210,051, 5,393,993 and 5,523,589, the disclosures of these U.S. patents, which are incorporated herein by reference in their entirety. The channel layer 206 may have a band gap smaller than that of the barrier layer 208. The channel layer 206 may have a greater electron affinity than the barrier layer 208. The channel layer 206 and the barrier layer 208 may comprise a group III nitride-based material or a gallium nitride material.

[0053] In some embodiments, under the condition that the energy of the conduction band edge of the channel layer 206 at the interface between the channel layer 206 and the barrier layer 208 is less than the energy of the conduction band edge of the barrier layer 208, the channel layer 206 is Al x Ga( 1-x)It may be a group-III nitride layer such as N. Here, the aluminum molar fraction x satisfies 0 ≦ x < 1. In some embodiments, the aluminum molar fraction x is approximately 0, indicating that the channel layer 206 is GaN. The channel layer 206 may or may not contain other group-III nitrides such as InGaN or AlInGaN. The channel layer 206 may be undoped (or "unintentionally doped") and may be grown to a thickness in the range of about 0.5 μm to about 5 μm, for example, a thickness of about 2 μm, and may also depend on other thicknesses. The channel layer 206 may be a multilayer structure, for example, a superlattice or combination such as GaN or AlGaN. In some embodiments, the channel layer 206 may be under compressive strain.

[0054] The semiconductor structure 202 may include a barrier layer 208 on the upper surface of the channel layer 206. The barrier layer 208 may have a bandgap different from that of the channel layer 206. At the interface between the channel layer 206 and the barrier layer 208, the energy of the conduction band edge of the barrier layer 208 may be greater than the energy of the conduction band edge of the channel layer 206. The barrier layer 208 may be a group-III nitride layer such as Al x Ga( 1-x )N. Here, x is the aluminum molar fraction of the barrier layer 208. In some embodiments, the aluminum molar fraction x is in the range of about 0.15 to about 0.40, for example, in the range of about 0.20 to about 0.25, for example, about 0.22 (for example, the aluminum molar fraction is in the range of 15% to 40%, for example, in the range of about 20% to about 25%, for example, about 22%), indicating that the barrier layer is an AlGaN layer.

[0055] The barrier layer 208 may contain other Group III elements (e.g., In) that do not depart from the scope of this disclosure. In some examples, the barrier layer 208 may be a multilayer structure. The multilayer structure may contain a number of Group III nitride-based layers having different aluminum mole fractions. The barrier layer 208 may have a thickness in the range of about 10 angstroms to about 300 angstroms, for example, about 120 angstroms to about 170 angstroms, for example, about 150 angstroms, and may depend on other thicknesses. The channel layer 206 and / or the barrier layer 208 may be deposited by, for example, metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor epitaxy (HVPE). A two-dimensional electron gas (2DEG) 210 may be induced in the channel layer 206 at the interface between the channel layer 206 and the barrier layer 208. 2DEG210 is highly conductive, enabling conduction between the source and drain regions of HEMT200.

[0056] For illustrative purposes, HEMT200 is shown having a substrate 104, a channel layer 206, and a barrier layer 208, but HEMT200 may include additional layers / structures / elements. For example, HEMT200 may include a buffer layer and / or nucleation layer between the substrate 104 and the channel layer 206. For example, an AlN buffer layer may be present on the top surface 104B of the substrate 104 to provide a suitable crystal structure transition between the SiC substrate and the channel layer 206. Optional buffer / nucleation / transition layers may be deposited by MOCVD, MBE, and / or HYPE.

[0057] HEMT200 may include a cap layer on the barrier layer 208. HEMT structures including the substrate, channel layer, barrier layer and other layers are discussed, for example, in U.S. Patents 5,192,987, 5,296,395, 6,316,793, 6,548,333, 7,544,963, 7,548,112, 7,592,211, 7,615,774, 7,709,269, 7,709,859 and 10,971,612, the disclosures of these U.S. patents are incorporated herein by reference in their entirety. Furthermore, in addition to and / or instead, strain balancing transition layers, for example, as described in U.S. Patent 7,030,428, are provided, the disclosures of this U.S. patent are incorporated herein by reference.

[0058] The HEMT200 may include a source contact 212 located on the upper surface 208A of the barrier layer 208, or a source contact 212 in other ways that is in contact with the barrier layer 208. The HEMT200 may also include a drain contact 214 located on the upper surface 208A of the barrier layer 208, or a drain contact 214 in other ways that is in contact with the barrier layer 208. The source contact 212 and the drain contact 214 may be spaced apart from each other laterally. In some embodiments, the source contact 212 and the drain contact 214 may include a metal that may form ohmic contact with a group III nitride-based semiconductor material. Suitable metals may include high-melting-point metals such as titanium (Ti), tungsten (W), titanium tungsten (TiW), silicon (Si), titanium tungsten nitride (TiWN), tungsten silicide (WSi), rhenium (Re), niobium (Nb), Ni, gold (Au), aluminum (Al), tantalum (Ta), molybdenum (Mo), NiSix, titanium silicide (TiSi), titanium nitride (TiN), silicon tungsten nitride (WSiN), and platinum (Pt). In some embodiments, the source contact 212 may be an ohmic source contact 212. The drain contact 214 may be an ohmic drain contact 214. Thus, the source contact 212 and / or the drain contact 214 may include an ohmic contact portion that is in direct contact with the barrier layer 208. In some embodiments, the source contact 212 and / or drain contact 214 may include multiple layers for forming an ohmic contact, which may be provided, for example, as described in U.S. Patents 8,563,372 and 9,214,352, the disclosures of which are incorporated herein by reference in their entirety.

[0059] The HEMT200 may include gate contacts 216 located on the upper surface 208A of the barrier layer 208, or gate contacts 216 in other ways that are in contact with the barrier layer 208 (e.g., embedded in the barrier layer 208). The gate contacts 216 may have a gate length LG. As shown in Figure 10, the gate length LG may be the length of the portion of the gate contact 216 that is on the semiconductor structure 202. In some embodiments, the gate length LG may be in the range of about 100 nm to about 400 nm, for example, about 100 nm to about 350 nm. In some embodiments, the gate length LG may be less than or equal to about 100 nm, for example, less than or equal to about 90 nm, for example, less than or equal to about 60 nm. In some embodiments, the gate length LG may be in the range of about 40 nm to about 90 nm.

[0060] The material of the gate contact 216 may be selected based on the composition of the barrier layer 208, and in some embodiments may be a Schottky contact. For example, materials that can form a Schottky contact with group III nitride-based semiconductor materials such as nickel (Ni), platinum (Pt), nickel silicide (NiSix), copper (Cu), palladium (Pd), chromium (Cr), tungsten (W), and / or silicon tungsten nitride (WSiN) may be used.

[0061] The source contact 212 may be coupled to a reference signal, such as a ground voltage or another reference signal. Coupling to the reference signal may be provided by a via 218 extending from the bottom surface 104A of the substrate 104 through the substrate 104 and the channel layer 206 to the top surface 208A of the barrier layer 208. The via 218 may expose the bottom surface of the ohm portion 212A of the source contact 212. A back metal layer 220 may be present on the sidewalls of the bottom surface 104A of the substrate 104 and the via 218. The back metal layer 220 may be in direct contact with the ohm portion 212A of the source contact 212. In some embodiments, the contact area between the back metal layer 220 and the bottom surface of the ohm portion 212A of the source contact 212 may be 50 percent or more of the area of ​​the bottom surface of the ohm portion 212A of the source contact 212. Thus, the back metal layer 220 and the signal coupled to the back metal layer 220 may be electrically connected to the source contact 212.

[0062] In some embodiments, via 218 may have an elliptical or circular cross-section when viewed in a plan view. However, the disclosure is not limited to such cross-sections. As will be understood by those skilled in the art who have used the disclosure described herein, in some embodiments, the cross-section of via 218 may be polygonal or other shapes. In some embodiments, the dimensions of the via (e.g., length and / or width) may be such that the maximum cross-sectional area A1 of via 218 is approximately 1000 μm². 2The dimensions may be as follows. The cross-sectional area A1 may be measured in a direction parallel to the bottom surface 104A of the substrate 104 (e.g., the XY plane in Figure 10). In some embodiments, the maximum cross-sectional area A1 of the via 218 may be the portion of the via 218 adjacent to the bottom surface 104A of the substrate 104 (e.g., the opening of the via 218). For example, in some embodiments, the maximum width (e.g., in the X direction from right to left on the page of Figure 10) may be about 16 μm, and the maximum length (e.g., in the Y direction from top to bottom on the page of Figure 10) may be about 40 μm. However, the disclosure is not limited to these dimensions. In some embodiments, the sidewalls of the via 218 may be inclined and / or tilted with respect to the bottom surface 104A of the substrate 104. In some embodiments, the sidewalls of the via 218 may be substantially perpendicular to the bottom surface 104A of the substrate 104.

[0063] The drain contact 214 may be formed on, within, and / or through the barrier layer 208, and ions can be implanted into the material surrounding the drain contact 214 (for example, through the barrier layer 208 into the channel layer 206) to reduce resistivity and provide improved ohmic contact with the semiconductor material. In yet another embodiment, there is no source via 218, and the source contact 212 is formed on, within, and / or through the barrier layer 208, and ions can be implanted into the material surrounding the source contact 212 to reduce resistivity and provide improved ohmic contact with the semiconductor material.

[0064] The HEMT200 may include a first insulating layer 222. The first insulating layer 222 may be in direct contact with the upper surface of the semiconductor structure 202 (for example, in contact with the upper surface 208A of the barrier layer 208). The HEMT200 may also include a second insulating layer 224. The second insulating layer 224 may be on top of the first insulating layer 222. In some embodiments, it is understood that three or more insulating layers may be included. The first insulating layer 222 and / or the second insulating layer 224 may serve as passivation layers of the HEMT200. The first insulating layer 222 and / or the second insulating layer 224 may be dielectric layers. Different dielectric materials may be used, such as SiN, SiO2, Al2O3, MgOx, MgNx, ZnO, SiNx, SiOx, alloys or layer sequences thereof, or epitaxial materials.

[0065] The source contact 212, drain contact 214, and gate contact 216 may be located within the first insulating layer 222. In some embodiments, at least a portion of the gate contact 216 may be on the first insulating layer 222. In some embodiments, the gate contact 216 may be a T-shaped gate and / or a gamma gate, and the formation of the gate is discussed, for example, in U.S. Patents 8,049,252, 7,045,404, and 8,120,064, the disclosures of these U.S. patents, which are incorporated herein by reference in their entirety. The second insulating layer 224 may be located on the first insulating layer 222, as well as on portions of the source contact 212, drain contact 214, and gate contact 216. The portion protruding from the gate may also be referred to as the field plate integrated with the gate.

[0066] Optionally, depending on the number of insulating layers included in the HEMT200, the field plate 226 may be located on a second insulating layer 224, as shown in Figure 10, or on another insulating layer. At least a portion of the field plate 226 may overlap the gate contact 216 at least partially. At least a portion of the field plate 226 may be located on the portion of the second insulating layer 224 between the gate contact 216 and the drain contact 214. The field plate 226 may reduce the peak electric field of the HEMT200, which may result in an increase in breakdown voltage and a reduction in charge trapping. The reduction in the electric field may also result in other benefits, such as a reduction in leakage current and an increase in reliability. The field plate and techniques for forming the field plate are discussed, for example, in U.S. Patent No. 8,120,064, the disclosure of which is incorporated herein by reference.

[0067] Depending on the number of insulating layers included in the HEMT200, the metal contacts 228 may be located within a second insulating layer 224 as shown in Figure 10, or on another insulating layer. The metal contacts 228 may provide interconnection between the source contacts 212 and other parts of the integrated circuit including the HEMT200. Each of the metal contacts 228 may be in direct contact with the drain contacts 214 and / or the source contacts 212. The metal contacts 228 may include metals or other highly conductive materials, such as copper, cobalt, gold and / or composite metals.

[0068] The HEMT200 may be formed by an active region between the source contact 212 and the drain contact 214, which is under the control of a gate contact 216 between the source contact 212 and the drain contact 214. For illustrative purposes, Figure 10 shows a cross-sectional view of one unit of the HEMT200. The HEMT200 may be formed adjacent to additional HEMT device units, for example, by sharing a source contact 212 with an adjacent HEMT device unit.

[0069] The transistors and other active devices described herein can be formed using Group III nitride-based semiconductor materials, Group III-V semiconductor materials and related semiconductor materials and semiconductor manufacturing processes. Group III elemental materials include scandium (Sc), aluminum (Al), gallium (Ga), and indium (In), while Group V elemental materials include nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb). Therefore, in some examples, the ideas can be applied to Group III nitride (aluminum (Al), gallium (Ga), indium (In), and alloy (AlGaIn) based nitrides), GaAs, InP, InGaP, and AlGaAs devices, which are Group III-V active semiconductor devices. However, the ideas may also be applied to transistors and other active devices formed from other semiconductor materials.

[0070] The embodiments and concepts described herein can be applied to semiconductor die amplifier circuits implemented in, on, and above silicon (e.g., GaN-on-Si), silicon carbide (e.g., GaN-on-silicon carbide (SiC)), gallium arsenide (GaAs), and other types of substrate materials. When used herein, the phrases “gallium nitride material” or “GaN material” refer to gallium nitride and any gallium nitride alloy, for example, in particular aluminum gallium nitride (Al x Ga (1-x) N), indium gallium nitride (In y Ga (1-y) N), aluminum indium gallium nitride (Al x In y Ga (1-x-y) N), gallium nitride arsenide (GaAs a P b N (1-a-b) ), aluminum indium gallium nitride (Al phosphide) x In y Ga (1-x-y) As a P b N (1-a-b)Gallium nitride materials can be n-type doped, p-type doped, or unintentionally doped (UID) materials. Gallium nitride materials can be formed on silicon, silicon carbide, or other types of substrates. The term "gallium nitride" or GaN semiconductor refers directly to gallium nitride and does not include gallium nitride alloys.

[0071] In embodiments containing high concentrations of gallium, the gallium nitride material has a high concentration of gallium and contains little to no aluminum or indium. In high-gallium-concentration embodiments, the sum (x+y) may be less than 0.4 in some cases, less than 0.2 in some cases, less than 0.1 in some cases, or even smaller in other cases. The term "gallium nitride" or "GaN" refers directly to gallium nitride and does not include alloys of gallium nitride (i.e., x=y=a=b=0).

[0072] The transistors described herein can be formed as field-effect transistors (FETs), but the concepts can also be applied to other types of transistors. While there are other types of FET transistors, the transistors described herein can be formed, in particular, as HEMTs, pseudo-image high electron mobility transistors (pHEMTs), modified high electron mobility transistors (mHEMTs), and other types of transistors. FETs may include metal-oxide-semiconductor or metal-insulating semiconductor (MOSFET or MISFET) transistors and metal-semiconductor field-effect transistors (MESFETs). A transistor may include one or more field plates, such as a source-connected field plate, a gate-connected field plate, or both source-connected and gate-connected field plates.

[0073] Given the limitations of semiconductor manufacturing and processing technologies available in this field, the terms “approximately” and “about” reflect a certain inability (or uncertainty) to precisely control the exact dimensions of a feature described herein. Depending on the level of precision achievable using commercially available semiconductor processing tools at that time, the terms “approximately” and “about” may be used to mean within ±20% of the target value for some features, within ±10% of the target value for some features, within ±5% of the target value for some features, and within ±2% of the target value for some features. The terms “approximately” and “about” may include the target value.

[0074] The ideas described herein can be combined in any suitable way in one or more embodiments, and in some cases the features discussed in those embodiments are interchangeable. Although exemplary embodiments are described herein, those skilled in the art will understand that in some cases the technical solutions and ideas can be implemented without any of the specific details of each example. Furthermore, substitute or equivalent steps, components and materials may be used. It should also be understood that some well-known process steps, semiconductor material layers, semiconductor device features and other features are omitted to avoid obscuring the ideas.

[0075] Relative terms such as "above," "below," "above," "below," "top," "bottom," "right," and "left" are sometimes used to describe the relative spatial relationships of structural features, but in the examples, these terms are used only for convenience to indicate direction. Therefore, if a structure is inverted, the "above" component becomes the "bottom" component. When a structure or feature is described as being "above" (or formed on) another structure or feature, that structure may be placed directly on (i.e., in contact with) the other structure without any other structure or feature intervening between it and the other structure. When a structure or feature is described as being "on top of" (or formed on top of) another structure or feature, that structure may be placed on the other structure with or without other structures or features intervening between them. When two components are described as being "joined" to each other, they may be electrically joined to each other with other components electrically joined and interposed between them, or without other components electrically joined and interposed between them. When two components are described as being "directly joined" to each other, they may be electrically joined to each other without other components electrically joining between them.

[0076] As described herein, when we refer to the “thickness” of a substrate or material layer, it is a measurement of the cross-sectional thickness of the substrate or layer, measured from the top surface of the substrate or layer to the bottom surface of the substrate or layer, such as from the top to the bottom of a page. Furthermore, unless otherwise explicitly stated, the “top” or “top surface” of a layer is located near the top of a page, and the “bottom” or “bottom surface” of a layer is located near the bottom of a page.

[0077] Terms such as "a," "an," "the," and "said" are used to indicate the presence of one or more elements and components. The terms "comprise," "include," "have," "contain," and their variations are used because they are open-ended and, unless explicitly stated otherwise, may include or encompass additional elements, components, etc., in addition to the listed elements, components, etc. The terms "first," "second," etc., may be used as identifiers to distinguish individual or separate components from a group of components, rather than as descriptors for several components, unless explicitly stated otherwise.

[0078] While embodiments have been described in detail herein, these descriptions are illustrative. The features of the embodiments described herein are representative, and alternative embodiments may include or omit certain features and elements. Furthermore, those skilled in the art can modify the embodiments described herein without departing from the spirit and scope of the invention as defined in the following claims, and the scope of the invention is given the broadest possible interpretation to include modifications and equivalent structures.

Claims

1. A first group III nitride-based transistor having a first output contact on a substrate, A second group III nitride-based transistor having a second output contact is located on the aforementioned substrate, An output combiner inductor located on the aforementioned substrate, coupled to the first output contact and the second output contact, The high-frequency (RF) output interface coupled to the output combiner inductor and A semiconductor die equipped with the following features.

2. A first RF input interface coupled to the first group III nitride-based transistor, The second RF input interface coupled to the second group III nitride-based transistor and The semiconductor die according to claim 1, further comprising:

3. A first gate interface coupled to the gate of the first group III nitride-based transistor, The second gate interface coupled to the gate of the second group III nitride-based transistor and A semiconductor die according to any one of claims 1 or 2, further comprising:

4. The first drain interface for the first group III nitride-based transistor, The second drain interface for the second group III nitride-based transistor and A semiconductor die according to any one of claims 1 to 3, further comprising:

5. The semiconductor die according to any one of claims 1 to 4, wherein the output combiner inductor is configured to perform a phase shift of the RF signal output by the first group III nitride-based transistor.

6. The semiconductor die according to any one of claims 1 to 5, wherein the output combiner inductor comprises a helical inductor.

7. The semiconductor die according to any one of claims 1 to 6, wherein the output combiner inductor is located within the region of the semiconductor die between the first drain interface and the second drain interface.

8. The semiconductor die according to claim 7, wherein the RF output interface is located within the region of the semiconductor die between the output combiner inductor and the second drain interface.

9. The semiconductor die according to any one of claims 1 to 8, wherein the output combiner inductor is located in a region of the semiconductor die outside the region defined between the first group III nitride-based transistor and the second group III nitride-based transistor.

10. A first input matching circuit, located on the substrate and coupled to the first gate interface of the first group III nitride-based transistor, A second input matching circuit, located on the substrate and coupled to the second gate interface of the second group III nitride-based transistor, A semiconductor die according to any one of claims 1 to 9, further comprising:

11. A first RF input interface coupled to the first input matching circuit, The second RF input interface coupled to the second input matching circuit and The semiconductor die according to claim 10, further comprising:

12. The semiconductor die according to claim 11, further comprising a phase shifter inductor located on the substrate and disposed within a region of the semiconductor die between the second RF input interface and the second input matching circuit.

13. The semiconductor die according to claim 12, wherein the first input matching circuit and the second input matching circuit are coupled to a common RF input interface of the semiconductor die.

14. The semiconductor die according to claim 13, further comprising an input combiner inductor located on the substrate and disposed within the region of the semiconductor die between the common RF input interface and the second input matching circuit.

15. The semiconductor die according to claim 10, further comprising a blocking capacitor located on the substrate and coupled to the second input matching circuit.

16. The output combiner inductor is located within a first region of the semiconductor die, the first group III nitride-based transistor and the second group III nitride-based transistor are located within a second region of the semiconductor die, and the first input matching circuit and the second input matching circuit are located within a third region of the semiconductor die. The second region of the semiconductor die is located between the first region of the semiconductor die and the third region of the semiconductor die. The semiconductor die according to claim 10.

17. The semiconductor die according to any one of claims 1 to 16, wherein the first group III nitride-based transistor comprises a first plurality of transistor unit cells, and the second group III nitride-based transistor comprises a second plurality of transistor cells.

18. A first group III nitride-based transistor on the substrate, A second group III nitride-based transistor is located on the aforementioned substrate, A first input matching circuit, located on the substrate and coupled to the gate of the first group III nitride-based transistor, A second input matching circuit, located on the substrate and coupled to the gate of the second group III nitride-based transistor, A semiconductor die equipped with the following features.

19. The semiconductor die according to claim 18, further comprising a high-frequency (RF) input interface directly coupled to the first input matching circuit.

20. The semiconductor die according to claim 19, wherein the RF input interface is a common RF input interface for the first group III nitride-based transistor and the second group III nitride-based transistor, located on the substrate.

21. The semiconductor die according to claim 20, further comprising an input combiner inductor located on the substrate in the region of the semiconductor die between the common RF input interface and the second input matching circuit.

22. A first high-frequency (RF) input interface directly coupled to the first input matching circuit, A second RF input interface directly coupled to the second input matching circuit and A semiconductor die according to any one of claims 18 to 21, further comprising:

23. The semiconductor die according to any one of claims 18 to 22, further comprising an output combiner inductor located on the substrate and coupled to a first output contact of the first group III nitride-based transistor and a second output contact of the second group III nitride-based transistor, wherein the output combiner inductor is further coupled to an RF output interface to the semiconductor die.

24. The semiconductor die according to claim 23, wherein the output combiner inductor is configured to perform a phase shift of the RF signal output by the first group III nitride-based transistor.

25. The semiconductor die according to claim 23, wherein the output combiner inductor comprises a helical inductor.

26. The semiconductor die according to claim 23, wherein the output combiner inductor is located within the region of the semiconductor die between the first drain interface and the second drain interface.

27. The semiconductor die according to claim 26, wherein the RF output interface is located within the region of the semiconductor die between the output combiner inductor and the second drain interface.

28. The semiconductor die according to claim 23, wherein the output combiner inductor is located in a region of the semiconductor die outside the region defined between the first group III nitride-based transistor and the second group III nitride-based transistor.

29. The output combiner inductor is located within a first region of the semiconductor die, the first group III nitride-based transistor and the second group III nitride-based transistor are located within a second region of the semiconductor die, and the first input matching circuit and the second input matching circuit are located within a third region of the semiconductor die. The second region of the semiconductor die is located between the first region of the semiconductor die and the third region of the semiconductor die. The semiconductor die according to claim 23.

30. The semiconductor die according to any one of claims 18 to 29, wherein the first group III nitride-based transistor comprises a first plurality of transistor unit cells, and the second group III nitride-based transistor comprises a second plurality of transistor cells.

31. Monolithic microwave integrated circuit (MMIC), A first group III nitride-based transistor on the substrate, A second group III nitride-based transistor is located on the aforementioned substrate, A first input matching circuit, located on the substrate and coupled to the gate of the first group III nitride-based transistor, A second input matching circuit, located on the substrate and coupled to the gate of the second group III nitride-based transistor, An output combiner inductor located on the aforementioned substrate, coupled to the first output contact of the first group III nitride-based transistor and the second output contact of the second group III nitride-based transistor, The high-frequency (RF) output interface coupled to the output combiner inductor and Equipped with, The output combiner inductor is arranged within the first region of the MMIC. The first group III nitride-based transistor and the second group III nitride-based transistor are arranged within the second region of the MMIC. The first input matching circuit and the second input matching circuit are arranged within the third region of the MMIC. The second region of the MMIC is positioned between the first region and the third region. MMIC.

32. The MMIC according to claim 31, wherein the output combiner inductor comprises a helical inductor.

33. The MMIC according to any one of claims 31 or 32, wherein the output combiner inductor is located within the region of the MMIC between the first drain interface and the second drain interface.

34. The MMIC according to claim 33, wherein the RF output interface is located within the region of the MMIC between the output combiner inductor and the second drain interface.

35. A first high-frequency (RF) input interface directly coupled to the first input matching circuit, A second RF input interface directly coupled to the second input matching circuit and The MMIC according to any one of claims 31 to 34, further comprising:

36. The MMIC according to claim 35, further comprising a phase shifter inductor on the substrate, disposed within the region of the MMIC between the second RF input interface and the second input matching circuit.

37. The MMIC according to any one of claims 31 to 36, further comprising a common RF input interface for the first group III nitride-based transistor and the second group III nitride-based transistor, located on the substrate.

38. The MMIC according to claim 37, further comprising an input combiner inductor located on the substrate in the region of the MMIC between the common RF input interface and the second input matching circuit.

39. The MMIC according to any one of claims 31 to 38, further comprising a blocking capacitor located on the substrate and coupled to the second input matching circuit.

40. The MMIC according to any one of claims 31 to 39, wherein the first group III nitride-based transistor comprises a first plurality of transistor unit cells, and the second group III nitride-based transistor comprises a second plurality of transistor cells.

41. The semiconductor die according to any one of claims 1 to 30 or the MMIC according to any one of claims 31 to 40, wherein the substrate includes a silicon carbide substrate.

42. A semiconductor die according to any one of claims 1 to 30 or an MMIC according to any one of claims 31 to 40, wherein the first group III nitride-based transistor and the second group III nitride-based transistor include high electron mobility transistors.

43. A semiconductor die according to any one of claims 1 to 30 or an MMIC according to any one of claims 31 to 40, wherein the RF input impedance is approximately 10 ohms or more.

44. A semiconductor die according to any one of claims 1 to 30 or an MMIC according to any one of claims 31 to 40, wherein the RF output impedance is approximately 10 ohms or more.

45. A semiconductor die according to any one of claims 1 to 30 or an MMIC according to any one of claims 31 to 40, configured to perform at least a portion of a Doherty amplifier.

46. The aforementioned substrate is approximately 4.2 mm 2 A semiconductor die according to any one of claims 1 to 30 or an MMIC according to any one of claims 31 to 40 having the following surface area.

47. The aforementioned substrate is approximately 2.7 mm 2 ~4.2 mm 2 A semiconductor die according to any one of claims 1 to 30 or an MMIC according to any one of claims 31 to 40 having a surface area in the range of [specified range].

48. The semiconductor die according to any one of claims 1 to 30 or the MMIC according to any one of claims 31 to 40, wherein the substrate has a length dimension different from the width dimension.

49. The semiconductor die according to any one of claims 1 to 30 or the MMIC according to any one of claims 31 to 40, wherein the substrate has a length dimension of about 2.8 mm or less and a width dimension of about 1.5 mm or less.

50. The semiconductor die according to any one of claims 1 to 30 or the MMIC according to any one of claims 31 to 40, wherein the substrate has a length dimension in the range of about 2.3 mm to about 2.8 mm and a width dimension in the range of about 1.2 mm to about 1.5 mm.

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