Double-sided circuit connection

Abstract

The semiconductor device includes an upper side and a lower side opposite the upper side. A central portion having a semiconductor substrate is located between the upper and lower sides. Components are located in the central portion in contact with the semiconductor substrate. The components include a first electrical connection from the upper side and a second electrical connection from the lower side. (Selected Figure) Figure 1

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices and processing methods, and more specifically to a semiconductor device having front-side and back-side wiring for double-sided connection that contacts a device or device component from both sides.

Background Art

[0002] Integrated circuit devices are constructed by forming diffusion regions in a substrate, and then building wiring connections from the substrate to a back end of line (BEOL) structure. Such devices include a diffusion region (e.g., a source / drain region) on one side of the device formed within the substrate, and a contact is dropped down to connect to the diffusion region. Metal lines connect to the contacts, and other contacts and metal lines are connected in turn to form a metal structure according to the chip design. In the case of a stacked field effect transistor structure in which field effect transistors are stacked on each other, the device is again built from the substrate. Even if the wafer or substrate is flipped to process the opposite side, the contacts are still dropped down toward the substrate.

[0003] In devices using large stacked gate structures, for example in nanosheet stacks, the gate resistance limits the switching capability of transistors controlled by the gate due to the large size of the gate, for example the large distance between the top and bottom of the gate. Since the contact is formed on the top of the large gate structure, gate resistance occurs at the distant lower portion of the gate.

[0004] Asymmetry of metal structures around the substrate can result in parasitic resistance and wiring resistance across the entire chip or device.

[0005] Therefore, there is a need for a more balanced wiring configuration to address gate resistance issues, area constraints, and parasitic losses within integrated circuits. Furthermore, there is a need to form multiple connections to the same component in order to reduce contact resistance and current density through connecting metal structures. [Overview of the project]

[0006] According to one embodiment of the present invention, the semiconductor device includes an upper side and a lower side opposite the upper side. The central portion has a semiconductor substrate located between the upper and lower sides. A component located in the central portion is in contact with the semiconductor substrate. The component includes a first electrical connection from the upper side and a second electrical connection from the lower side. By using the first and second electrical connections to the component, resistance caused by insufficient connection surface area is mitigated. Problems such as gate resistance or contact resistance are significantly reduced as a result of using two-sided connections. Furthermore, the use of another wiring side according to embodiments of the present invention offers many possibilities with respect to circuit layout, saving area space and reducing current density through electrical connections.

[0007] According to another embodiment of the present invention, the semiconductor device includes an upper wiring including metal lines and contacts, and a lower wiring including metal lines and contacts, arranged opposite to the upper wiring. The central portion includes a semiconductor substrate arranged between the upper and lower wirings. Components are formed on the semiconductor substrate and arranged in the central portion. The components include a first electrical connection from the upper wiring and a second electrical connection from the lower wiring. The first and second electrical connections can reduce resistance caused by insufficient connection surface area. The significant reduction in resistance improves device performance. Furthermore, the use of alternative wiring sides according to embodiments of the present invention offers many possibilities with respect to circuit layout, saving area space and reducing current density through electrical connections.

[0008] According to another embodiment of the present invention, the semiconductor device includes upper wiring including metal lines and contacts, and lower wiring including metal lines and contacts, arranged opposite to the upper wiring. The central portion includes a semiconductor substrate positioned between the upper and lower wiring. A first component is formed on the semiconductor substrate and positioned in the central portion. The first component includes a first electrical connection from the upper wiring and a second electrical connection from the lower wiring. A second component is formed on the semiconductor substrate and positioned in the central portion. The second component includes a first electrical connection from the upper wiring and a second electrical connection from the lower wiring. In addition to reducing resistance, the bridge connects the first electrical connection of the first component to the first electrical connection of the second component. By using the bridge to connect subcircuits throughout the device, the upper and lower metal structures can be used in a single circuit spanning the upper, lower, and central regions of the device.

[0009] According to another embodiment of the present invention, the semiconductor device includes an upper wiring including metal lines and contacts, and a lower wiring including metal lines and contacts, arranged opposite to the upper wiring. The central portion includes a semiconductor substrate arranged between the upper and lower wiring. A first circuit is arranged on the upper and lower wiring. The first circuit has a first component including a first electrical connection from the upper wiring and a second electrical connection from the lower wiring. A second circuit is arranged on the upper and lower wiring. The second circuit has a second component including a first electrical connection from the upper wiring and a second electrical connection from the lower wiring. A bridge connects the first circuit to the second circuit to form a single circuit spanning the upper wiring, the lower wiring, and the central portion, where the upper wiring is a mirror image of the lower wiring with respect to the central portion. In addition to reducing resistance, the bridge connects the first electrical connection of the first component to the first electrical connection of the second component. By using bridges to connect subcircuits throughout the device, the upper and lower metal structures can be used in a single circuit spanning the upper, lower, and central regions of the device.

[0010] These and other features and advantages will become apparent from the following detailed description relating to these exemplary embodiments, which should be read in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0011] The following description provides details of preferred embodiments with reference to the drawings below.

[0012] [Figure 1] A schematic cross-sectional view of a semiconductor device according to one embodiment of the present invention, comprising a central portion having a substrate and including an upper metal structure and a lower metal structure, wherein the upper and lower metal structures provide two-sided connections to a component, and the upper and lower metal structures are mirror images of each other in one or more dimensions.

[0013] [Figure 2] A schematic cross-sectional view of a semiconductor device according to one embodiment of the present invention, which has a central portion having a substrate and includes an upper metal structure and a lower metal structure, wherein the upper and lower metal structures provide a two-sided connection and have similar metal densities but are not strictly mirror images of each other.

[0014] [Figure 3] The image shows a top layout diagram of a semiconductor device according to one embodiment of the present invention, in which the semiconductor device includes an upper metal structure and a lower metal structure, the upper and lower metal structures providing a two-sided connection and being mirror images of each other in one or more dimensions.

[0015] [Figure 4] Figure 3 shows three schematic cross-sectional views, cut along cross-sectional lines A, B, and E, illustrating a semiconductor device according to one embodiment of the present invention, wherein the semiconductor device includes an upper metal structure and a lower metal structure, the upper and lower metal structures providing a two-plane connection and being mirror images of each other in one or more dimensions.

[0016] [Figure 5] Fig. 1 is a top layout diagram of a semiconductor device according to an embodiment of the present invention, wherein the semiconductor device includes an upper metal structure and a lower metal structure, the upper and lower metal structures provide double-sided connection, are not mirror images of each other, and include a through contact passing through a semiconductor substrate.

[0017] [Figure 6] Fig. 2 shows three schematic cross-sectional views taken along section lines C, D, and F of Fig. 5, illustrating a semiconductor device according to an embodiment of the present invention, wherein the semiconductor device includes an upper metal structure and a lower metal structure, the upper and lower metal structures provide double-sided connection, are not mirror images of each other, and include a through contact passing through a semiconductor substrate.

[0018] [Figure 7] Fig. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention, the semiconductor device having a central portion with a substrate, and a stacked nanosheet gate structure having double-sided connection that is also connected by a through contact passing through the substrate for reducing gate resistance.

[0019] [Figure 8] Fig. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention, the semiconductor device having a central portion with a substrate, and a stacked nanosheet gate structure and an active region connected across different circuits with double-sided connection.

[0020] [Figure 9] Fig. 5 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention, the semiconductor device having a central portion with a substrate, and a stacked nanosheet gate structure and an active region connected across different circuits by a bridge, and having double-sided connection also connected by a through contact.

[0021] [Figure 10]1 is a schematic cross-sectional view illustrating a semiconductor device having a two-sided connection, which comprises a central portion having a substrate, a nanosheet stacked gate structure and a stacked field-effect transistor connected across different circuits by a bridge, and is also connected by a through contact, according to an embodiment of the present invention. DESCRIPTION OF EMBODIMENTS

[0022] According to embodiments of the present invention, devices and methods including a semiconductor device including front-side and back-side wirings that enable two-sided connection to a single component are described. The two-sided connection may include a connection from an upper wiring circuit and a connection from a lower wiring circuit. The upper and lower wiring circuits are separated by a semiconductor substrate. Connections may be formed between the two sides of the two-sided connection using, for example, through contacts. The two-sided connection may be controlled such that the component is activated from the upper and lower wiring circuits simultaneously. In other embodiments, the upper and lower wiring circuits may be used independently to supply power to the component or derive signals from the component.

[0023] The two-sided connection is formed in a metal layer or structure of the semiconductor device and formed on the component, providing access to the component through both sides of the semiconductor device. The metal layers or structures provide completely isolated connections to the same component. In this way, current density can be reduced by using completely different circuit paths to common components of the semiconductor device, such as gates, source regions, drain regions, and the like.

[0024] In one embodiment, both front-side and back-side connections to the same device element can be used to form an electrical connection between two device elements. In one example, source / drain (S / D) regions may be connected from both the front side and the back side of the device. In another example, a gate region may be connected from both the front side and the back side of the device.

[0025] In useful embodiments, a first wiring connection may be formed to a component (e.g., the top of the S / D), a second wiring connection may be formed to the same component (the bottom of the S / D), and a third wiring connection (e.g., a through-contact formed through a semiconductor substrate) may be formed between the first and second wiring connections. This may include a number of different configurations. For example, the wiring connections may be joined on one side or the other, or the connections may pass through the substrate of a chip on which the component is formed.

[0026] In another embodiment, the component may include a gate, where a first wiring connection may be formed, for example, on the top of the gate, a second wiring connection may be formed on the same component (for example, on the bottom of the gate), and a third wiring connection may be formed between the first and second wiring connections.

[0027] In yet another embodiment, the first wiring connection may be formed to the upper parts of the first and second S / Ds, and the second and third wiring connections may be formed to the lower parts of the first and second S / Ds and to the first wiring, respectively. In one embodiment, the first upper and lower connections may be formed to the first device S / D, and the second upper and lower connections may be formed to the gate of the second device. One or more electrical connections may be formed between the first and second devices.

[0028] Using upper and lower wiring circuits, a more symmetrical power or signal structure can be realized. The upper and lower circuits may include mirror images of each other, or they may include different layouts. Even with different layouts, a more uniform voltage field can be provided across the device using similar metal densities. In either case, the upper and lower circuits provide greater electrical symmetry and parallelism to the device.

[0029] By placing a back metal in parallel with the front metal, circuit performance can be improved by reducing wiring resistance and parasitic resistance. Furthermore, the additional back metal also improves electromigration resistance by reducing the current density through electrical connections. For example, two connections instead of one can reduce the current density by approximately half. This is particularly noticeable in small node devices where the feature size is nanoscale.

[0030] When used in conjunction with a gate structure, the upper and lower wiring improves the electrostatic properties of the device by contacting the gate from both sides, especially in thicker nanosheet (NS) stacks, particularly stacks with three or more sheets. In this way, the voltage drop across the gate structure due to gate resistance is minimized.

[0031] Embodiments of the present invention may be used in any type of semiconductor device or chip. In a particularly useful embodiment, a chip having logic circuits may include dual-sided connections according to embodiments of the present invention. For example, these embodiments may include input / output (IO) circuits, high-performance computing (HPC) circuits, clock buffers, processors, memory devices, or any other integrated circuit chip, or a combination thereof. Circuit performance can be improved for any of these devices by reducing wiring resistance and parasitic resistance by sandwiching the central portion of the device in parallel with upper and lower metals. Furthermore, adding additional metal to the opposite side of the device can be incorporated into any manufacturing process with little or no impact on cost or processing time.

[0032] In useful embodiments, the upper and lower metals are uniformly distributed to distribute the current density. In particularly useful embodiments, the front metal structure is a mirror image of the back metal structure. The mirror image may include one-dimensional, two-dimensional, or three-dimensional symmetry between the upper and lower metal structures with respect to the central plane (or central region) of the device. Thus, intentional efforts are made to form corresponding contacts and metal lines on both sides of the device. This may include the same width, length, and footprint, connection points, distances, etc., for the metal structures on both sides of the device.

[0033] Next, we will refer to the drawings, where similar reference numerals represent the same or similar elements. Referring first to Figure 1, a schematic cross-sectional view of a semiconductor device 100 according to one embodiment of the present invention is shown. The semiconductor device 100 includes a central region 102. The central region 102 may include a front end of line (FEOL) structure and may also include a middle of the line (MOL) structure. The central region 102 may include a substrate 101 in which a semiconductor component 104 is formed in and / or on it.

[0034] The substrate 101 can include any suitable substrate structure, such as a bulk semiconductor or a semiconductor-on-insulator (SOI) substrate, and preferably a single-crystal semiconductor. In one example, the substrate 101 may include a silicon-containing material. Exemplary examples of suitable Si-containing materials for the substrate may include, but are not limited to, Si, SiGe, SiGeC, SiC, and multilayers thereof. Although silicon is the main semiconductor material used in wafer manufacturing, alternative semiconductor materials such as, but are not limited to, germanium, gallium arsenide, gallium nitride, silicon germanium, cadmium telluride, and zinc selenide may be used as additional layers.

[0035] The semiconductor component 104 may include, for example, an active region such as a source / drain region (S / D region), a gate structure, a capacitor plate, a memory element, and the like. Other components may include other electronic and electrical components. As described throughout, contacts connecting to a component provide physical and electrical connections to it. A two-sided connection provides at least two contacts to the component, where each two-sided connection is associated with wiring on the opposite side of the device. The semiconductor component 104 having a two-sided connection is formed on or within the substrate 101 in the central region 102.

[0036] In one embodiment, the central region 102 is sandwiched between the upper 106 and lower 108 of the semiconductor device 100. In this embodiment, the metallic structures of the upper 106 and the lower 108 are mirror images of each other. For example, the metallic lines 114 and contacts 118, 120 of the upper 106 provide symmetry or mirror image with the metallic lines 116 and contacts 122, 124 of the lower 108. The metallic structures of the upper 106 are collectively referred to as upper wiring 110, and the metallic structures of the lower 108 are collectively referred to as lower wiring 112. The symmetry or mirror image provided between the upper wiring 110 and the lower wiring 112 may extend in one or more dimensions. For example, the upper wiring 110 may be symmetrical with the lower wiring 112 in any or all of the x, y, and / or z directions, two of which define the plane of the substrate 101.

[0037] The symmetry between the upper wiring 110 and the lower wiring 112 is provided to reduce asymmetry in the overall electrical characteristics of the semiconductor device 100. For example, the symmetry provides two paths for the flow of circuit current: half of the current flows through the upper wiring 110, while the other half flows through the lower wiring 112. By reducing the amount of current flowing through each wiring, this implementation avoids high currents that could cause electromigration failures.

[0038] Furthermore, parasitic and wiring resistance can be reduced or better controlled by the characteristics of the upper wiring 110 and lower wiring 112. It should be understood that strict symmetry is not required, and that the degree of symmetry can vary depending on the performance objectives of the particular design.

[0039] The central region 102 includes bifacial circuit connections (two-sided connections) from both the upper wiring 110 and the lower wiring 112. Contact 118 connects to component 104 from the upper 106, and contact 122 connects to component 104 from the lower wiring 112. Contacts 118 and 122 may be positioned in the same vertical column relative to each other and contact the component from both sides. The upper wiring 110 and the lower wiring 112 can provide power or signal connections to component 104.

[0040] It should be understood that the upper wiring 110 and the lower wiring 112 may be constructed outward from the central region 102 by constructing one side, then inverting the semiconductor device and constructing the other side. In other embodiments, construction may be unidirectional, from the lower side 108 to the upper side 106, or vice versa. The upper wiring 110 and the lower wiring 112 are in electrical communication with each other. The two-sided connections can work together to simultaneously provide power or signals to a single component from both sides of the device. The two-sided connections can also operate independently of each other, for example, to power a component from one side under a first condition (e.g., activating a first circuit) and to power a component from both sides under a second condition (e.g., activating a second circuit when the component is common to both circuits).

[0041] In some embodiments, it may be useful to have a connection 126 between the upper wiring 110 and the lower wiring 112. The connection 126 may include a through contact passing through the central region 102, for example, to connect to or through the substrate of the semiconductor device 100. The connection 126 may be formed from one side, or from the upper 106 and the lower 108 and converging in the central region 102.

[0042] In one embodiment, an etching mask is formed on either the upper or lower side and etched through the substrate 101 (and any other intervening structures) to open a trench. The hole or trench may then be filled with an optional barrier layer and conductor to form a connection 126. In some embodiments, the connection 126 may include a series of connections or stacked connections. The electrical connections shown in Figure 1 and other figures are illustrative, and it should be understood that other connections, wiring configurations, and connection points are assumed by embodiments of the present invention.

[0043] Referring to Figure 2, a schematic cross-sectional view of a semiconductor device 130 according to one embodiment of the present invention is shown. The semiconductor device 130 includes a central region 102. The central region 102 may include a front-end-of-line (FEOL) structure and may also include a middle-of-line (MOL) structure. The central region 102 may include a substrate 101 in which a semiconductor component 104 is formed in and / or on it.

[0044] The semiconductor component 104 may include, for example, an active region such as a source / drain region (S / D region), a gate structure, a capacitor plate, a memory element, and the like. Other components may include other electronic and electrical components.

[0045] In one embodiment, the central region 102 is sandwiched between the upper 106 and lower 128 of the semiconductor device 130. In this embodiment, the upper 106 and lower 128 do not have a symmetrical structure but provide a similar metallic structure in which the conductive material is evenly distributed between the upper 106 and lower 128 based on the density of the metal or conductor (e.g., conductor mass per unit volume). In one example, the conductor density is maintained within about 10% between the metallic structures of the upper 106 and lower 128.

[0046] In one example, the upper metal lines 114 and contacts 118, 120 of the upper 106 provide approximately the same amount of metal as the lower metal lines 136 and contacts 122, 134 of the lower 138. The upper metal structure of the upper 106 is collectively referred to as the upper wiring 110, and the lower metal structure of the lower 128 is collectively referred to as the lower wiring 132. Higher uniformity of current density across the semiconductor device 100 can help control the effects of electromigration, parasitic resistance, and wiring resistance, depending on the characteristics of the upper wiring 110 and the lower wiring 132.

[0047] The central region 102 includes bifacial circuit connections from both the upper wiring 110 and the lower wiring 132. Contact 118 connects to component 104 from the upper side 106, and contact 122 connects to component 104 from the lower side 128. Contacts 118 and 122 may be positioned in the same vertical column relative to each other and contact the component from both sides. The upper wiring 110 and the lower wiring 132 can provide power or signal connections to component 104.

[0048] It should be understood that the upper wiring 110 and the lower wiring 132 may be constructed outward from the central region 102 by constructing one side, then inverting the semiconductor device and constructing the other side. In other embodiments, construction may be unidirectional, from the lower side 128 to the upper side 106, or vice versa.

[0049] In some embodiments, it may be useful to have a connection 126 between the upper wiring 110 and the lower wiring 132. The connection 126 may include a through contact passing through the central region 102, for example, to connect to or through the substrate of the semiconductor device 130. The connection 126 may be formed from one side, or from the upper 106 and lower 128 and converging in the central region 102. The electrical connections shown in Figure 2 and other figures are illustrative, and it should be understood that other connections, wiring configurations, and connection points are conceivable in embodiments of the present invention.

[0050] Referring to Figures 3 and 4, a top layout diagram 202 and three partial schematic cross-sectional views 230, 232, and 234 of a semiconductor device 200 having two-sided connections according to an embodiment of the present invention are shown. Dielectric materials and layers are omitted to allow the underlying metallic structure to be visible. The top view 202 shows active regions 204 and 206. In one embodiment, active region 204 includes a p-doped region and active region 206 includes an n-doped region. This may be reversed, or all regions may be n-doped or p-doped. Active regions 204 and 206 provide S / D regions and channels between S / D regions for a transistor device such as a field-effect transistor (FET). The channels of the device are located beneath the gate conductor 210. The gate conductor 210 is connected to a metal line 214 through a contact 212. Active regions 204 and 206 are connected by a metal line 208 as appropriate. Contact 212 connects metal line 208 to metal line 214.

[0051] A shallow trench isolation (STI) region 220 is shown in partial cross-sectional views 230, 232, and 234. As shown in the top view 202, Figure 230 is cut through cross-sectional line A, Figure 232 is cut through cross-sectional line E, and Figure 234 is cut through cross-sectional line B. Region 240 shows a mirror-image metallic structure formed to provide a two-plane contact connection. The two-plane connection is formed to and between the active regions 204 and 206 by the upper contact 212 and lower contact 242 of the active regions 204 and 206 in Figure 230. Metal lines 244 and 248 within region 240 correspond to the corresponding metal lines 214 and 208 in a mirror-image relationship. Similarly, contacts 212 and 242 form two-plane connections to the active regions 204 and 206 from both sides.

[0052] The two-sided connection is formed in Figure 232 with respect to and between the gate conductor 210 by the upper contact 212 and the lower contact 242 on the gate conductor 210. The metal lines 244 and 248 within region 240 correspond to the corresponding metal lines 214 and 208 in a mirror image relationship. Similarly, the contacts 212 and 242 form two-sided connections with respect to the gate conductor 210 from both sides.

[0053] The two-sided connection is formed in Figure 234 with respect to and between the gate conductor 210 by the upper contact 212 and the lower contact 242 on the gate conductor 210. The metal line 244 within region 240 corresponds to the corresponding metal line 214 in a mirror image relationship. Similarly, the contacts 212 and 242 form two-sided connections with respect to the gate conductor 210 from both sides.

[0054] The biplane connection on both sides of device 200, which has a mirror image between its upper and lower metal structures, is particularly useful in I / O circuits, clock distribution circuits, high-performance circuitry (HPC), and other circuits that are susceptible to parasitic losses and wiring resistance issues. Thus, the mirror image of the biplane wiring scheme reduces current density by halving the current through each of the biplane connections.

[0055] The two-sided connection on both sides of device 200 can also address problems arising from large gate structures. The gate conductor 210 can be activated simultaneously from, for example, the top and bottom to switch the transistor on and off. In the case of large gates, the resistance of the entire gate structure is high, especially at the furthest points across the gate structure. By providing two connection points on both sides of the gate conductor 210, the gate resistance can be significantly reduced, resulting in better device performance.

[0056] Referring to Figures 5 and 6, a top layout diagram 302 and three partial schematic cross-sectional views 330, 332, and 334 of a semiconductor device 300 having two-sided connections according to an embodiment of the present invention are shown. Dielectric materials and layers are omitted to allow the underlying metallic structure to be visible. Top view 302 shows active regions 304 and 306. In one embodiment, active region 304 includes a p-doped region and active region 306 includes an n-doped region. This may be reversed, or all regions may be n-doped or p-doped. Active regions 304 and 306 provide S / D regions and channels between S / D regions that form a transistor device such as a field-effect transistor (FET). The channels of the device are located beneath the gate conductor 310. The gate conductor 310 is connected to a metal line 314 through a contact 312. Active regions 304 and 306 are connected by a metal line 308 as appropriate. The contact 312 connects the metal line 308 to the metal line 314.

[0057] The STI region 320 is shown in partial cross-sectional views 330, 332, and 334. As shown in the top view 302, Figure 330 is cut through cross-sectional line C, Figure 332 is cut through cross-sectional line F, and Figure 334 is cut through cross-sectional line D. In Figure 330, the two-plane connection is formed to and between the active regions 304 and 306 by the upper contact 312 and the lower contact 342 of the active regions 304 and 306. The metal lines 344 and 348 correspond to the corresponding metal lines 314 and 308 in Figure 330 in a mirror image relationship. Similarly, the contacts 312 and 342 form two-plane connections to the active regions 304 and 306 from positions on both sides.

[0058] In Figure 334, the two-sided connection is formed with respect to and between the gate conductor 310 by the upper contact 312 and the lower contact 342 on the gate conductor 310. The metal line 344 within region 340 corresponds to the corresponding metal line 314 in a mirror image relationship. Similarly, the contacts 312 and 342 form two-sided connections with respect to the gate conductor 310 from both sides.

[0059] The two-sided connection is formed with respect to and between the gate conductor 310 by the upper contact 312 and the lower contact 342 on the gate conductor 310 in Figure 332. The metal lines 344 and 348 do not correspond to the metal lines 314 and 308 in a mirror image relationship. Here, the front metal structure of Figure 302 has been modified to complement the back metal structure 354. In region 352, the front and back metal structures are not symmetrical, but still provide metal balance and two-sided connection on both sides of the central region between the front and back metal structures.

[0060] Through-contacts 350 and 351 are provided to pass through the central region (including the substrate of device 300), forming a connection between the front and back metal structures. In Figure 332, through-contact 350 connects metal line 314 to metal line 344. Through-contact 350 penetrates the substrate and other structures within the central region of the device. In addition to the two-sided connection provided by contacts 312 and 342, through-contact 350 provides an additional conductive path across the central region, reducing the resistance of the connection path between active regions 304 and 306, which are connected as shown in Figure 330. The additional connection of through-contact 350 reduces signal delay and allows for a lower-resistance electrical path overall between electrical nodes.

[0061] A through-contact 351 is also provided to pass through the central region (including the substrate of device 300) and form a connection between its front and back metal structures. In Figure 332, the through-contact 351 connects metal line 314 to metal line 344. The through-contact 351 penetrates the substrate and other structures within the central region of the device. In addition to the two-sided connection provided by contacts 312 and 342, the through-contact 351 provides an additional conductive path connecting the two ends of the gate conductor 310 across the central region. This further reduces gate resistance. The additional connection of the through-contact 351 reduces signal delay and allows for a lower-resistance electrical path overall between electrical nodes. This improves the switching performance of the transistor and reduces signal delay at the gate.

[0062] The biface connections on both sides of device 300 are substantially mirror images between the upper and lower metal structures. Although not perfectly symmetrical, the substantial symmetry still provides improvements for I / O circuits, clock distribution circuits, high-performance circuits (HPCs), and other circuits that are susceptible to parasitic losses and wiring resistance issues, and can also still provide improved electromigration performance by providing multiple conductive paths.

[0063] The two-sided connection on both sides of device 300 can also address problems arising from the large gate structure. The gate conductor 310 can be activated simultaneously from, for example, the top and bottom to switch the transistor on and off. The additional connection provided by the through contact 351 further ensures that resistance is reduced, especially at the furthest points on either side across the gate structure (e.g., gate conductor 310). By providing two connection points on both sides of the gate conductor 310, and a redundant through contact 351 between them, gate resistance can be reduced, resulting in better device performance.

[0064] Referring to Figure 7, a partial schematic cross-sectional view of a semiconductor device 400 having a two-sided connection according to an embodiment of the present invention is shown. Dielectric materials and layers are omitted to allow the underlying metallic structure to be visible. The gate structure 410 includes a nanosheet (NS) structure. The nanosheet includes multiple layers that are utilized, which are prefabricated to reduce manufacturing costs. The nanosheet often includes a number of alternating layers that are processed to form a metallic gate, such as a high dielectric constant metal gate (HKMG) structure. Due to area constraints on the semiconductor chip, the gate structure grows vertically. As the vertical dimension increases, the gate resistance also increases.

[0065] In one embodiment, a two-sided connection is formed to the gate structure 410 by metal lines 414 and 416, and contact 418 associated with the upper 402 metal structure, and contact 420 associated with the lower 404 metal structure, including metal line 422. A through-contact 424 extends across a central region 406, which includes the substrate and other components. The through-contact 424 connects the upper and lower parts of the gate structure 410 by alternating paths. The metal lines 416 and 422 correspond in a mirror image relationship; however, the mirror image is not maintained in the higher metal layer (e.g., metal line 414) in this embodiment. Instead, the metal line 414 and contact 408 are aligned with the through-contact 424 to provide a more direct connection (e.g., metal line 414, contact 408, metal line 416, through-contact 424, metal line 422) between the upper 402 circuit and the lower 404 circuit through the central region 406.

[0066] The through-contact 424 penetrates the substrate and other structures within the central region 406 of the device 400. In addition to the two-sided connection provided by contacts 418 and 420, the through-contact 424 provides an additional conductive path connecting the two ends of the gate structure 410 across the central region 406. This further reduces gate resistance, especially for tall nanosheet gate structures containing many layers. The additional connection of the through-contact 424, with its direct connection to the upper contact 408, can further reduce signal / power delay and allow for lower-resistance electrical paths.

[0067] Referring to Figure 8, a partial schematic cross-sectional view of a semiconductor device 500 having a two-sided connection according to an embodiment of the present invention is shown. Dielectric materials and layers are omitted to allow the underlying metallic structure to be visible. The gate structure 510 may include a nanosheet structure, such as a high dielectric constant metal gate (HKMG) structure. The gate structure 510 is included as part of an electrical circuit 532. The electrical circuit 530 may include any useful circuit, such as a memory circuit or an I / O circuit. In one embodiment, the two-sided connection is formed to the gate structure 510 by contact 508 associated with an upper metallic structure including metal line 516 and contact 508, and by contact 520 associated with a lower metallic structure including metal line 522 and contact 520.

[0068] Furthermore, a two-sided connection is provided across the central region 506. The source / drain region 512 is connected by contacts 508 and 520 on both sides, which are included as part of the electrical circuit 530. The electrical circuit 530 may include any useful circuit, such as a memory circuit or an I / O circuit. Circuits 530 and 532 can be connected or wired to each other using two-sided connections between the components of each circuit. In this way, the two subcircuits 530 and 532 can form a single circuit distributed across the upper wiring, lower wiring, and the central portion of the device 500. In one embodiment, circuits 530 and 532 are connected by two-sided connections (e.g., metal lines 516 and 522) to form a single input / output circuit. As shown in Figure 8, the two-sided connection path connects different devices in different circuits 530 and 532, but each component (e.g., S / D region 512 and gate structure 510) includes an upper connection (contact 508) and a lower connection (contact 520).

[0069] Metal lines 516 and 522 correspond in a mirror image relationship; however, components and circuit elements can be connected using both the upper 502 metal structure and the lower 504 metal structure to form connections to the same component, connections to components in the same circuit, or connections to components in different circuits on the chip. The two-sided connection structure according to the embodiments described herein provides additional connection opportunities and allows for greater flexibility in realizing circuit configurations for performance or functionality. These performance-enhancing features can be realized without incurring additional chip area or processing costs, as the additional metal lines can be integrated into existing process of record (POR) sequences.

[0070] Referring to Figure 9, a partial schematic cross-sectional view of a semiconductor device 600 having a biplane connection with additional through-contact connections according to an embodiment of the present invention is shown. Dielectric materials and layers are omitted to allow the underlying metallic structure to be visible. In the configuration shown in Figure 9, local biplane connections 634 and 635 are formed using through-contacts 628 and 629 and contacts 608 and 620, respectively. The biplane connections are provided across a central region 606 including the semiconductor substrate and other chip components. These local connections are then connected to each other or to other structures using higher-level metallic structures (e.g., bridge 624 and contact 626).

[0071] The source / drain region 612 is connected by contacts 608 and 620 on both sides, which are included as part of the electrical circuit 630. The gate structure 610 is connected by contacts 608 and 620 on both sides, which are included as part of the electrical circuit 632. The electrical circuits 630 and 632 may include any useful circuits, such as memory circuits and I / O circuits. Circuits 630 and 632 can be connected or wired to each other using a bridge 624, which in this case can be positioned on one side of the central region 606 in the upper 602. In other embodiments, the bridge 624 may be formed on the lower 604, and in other embodiments, the bridge 624 can be formed on both the upper 602 and the lower 604, mirrored or not mirrored with respect to the other side.

[0072] In one embodiment, circuits 630 and 632 are connected by a bridge 624 including a metal line and contact 626. Contact 626 is connected to metal line 616, which then connects to contact 608. By being close to the connection points of contacts 628 and 629, contact 626 can achieve performance advantages. In this way, line resistance can be reduced. By connecting circuits 630 and 632, a single input / output circuit can be provided, distributed across device 600 and located on both sides of the central region 606. The two-sided connection structure provides additional connection opportunities and allows for greater flexibility in realizing circuit configurations for performance or functionality.

[0073] Referring to Figure 10, a partial cross-sectional view of a semiconductor device 700 having a biplane connection with additional through-contact connections according to an embodiment of the present invention is shown. Dielectric materials and layers are omitted to allow the underlying metallic structure to be visible. In the configuration shown in Figure 10, local biplane connections 734 and 735 are formed using through-contacts 728 and 729 and contacts 708 and 720, respectively. The biplane connections are provided across a central region 706 including a semiconductor substrate and other chip components. These local connections are then connected to each other or to other structures using higher-level metallic structures (e.g., bridges 724 and contacts 726).

[0074] In one embodiment, the semiconductor device 700 includes a multilayer field-effect transistor (FET) device. The multilayer FET device includes an upper active region 711 (e.g., S / D region) on the upper side 702 and an active region 713 (e.g., S / D region) on the lower side 704. The upper and lower active regions 711 and 713 are stacked and provide an S / D region of an operable FET separated by a distance 712 including a dielectric. The corresponding active regions 711 and 713 can be connected across a central region using through contacts 728. The active regions 711 and 713 can be connected, respectively, by contacts 708 and 720 included as part of an electrical circuit 730. The gate structure 710 is connected by on-side contacts 760 and 720 included as part of an electrical circuit 732, where the gate structure 710 includes an upper portion 703 on the upper side 702 and a lower portion 705 on the lower side 704, which are separated by an intermediate dielectric region 709. Parts 703 and 705 can be connected through the through contact 729. In other embodiments, parts 703 and 705 of the gate structure 710 can be wired independently and function separately from each other.

[0075] The electrical circuits 730 and 732 may include any useful circuits such as memory circuits and I / O circuits. Circuits 730 and 732 can be connected or wired to each other using a bridge 724, which in this case may be located on one side of the central region 706 in the upper 702. In other embodiments, the bridge 724 may be formed in the lower 704, and in other embodiments, the bridge 724 may be formed in both the upper 702 and the lower 704, either mirrored or not mirrored to the other side.

[0076] In one embodiment, circuits 730 and 732 are connected by a bridge 724 including a metal line and contact 726. Contact 726 is connected to the metal line 716, which then connects to contact 708. By being close to the connection points of contacts 728 and 729, contact 726 can achieve performance advantages. In this way, line resistance can be reduced. By connecting circuits 730 and 732, a single input / output circuit can be provided, distributed across device 700 and located on both sides of the central region 706. The two-sided connection structure provides additional connection opportunities and allows for greater flexibility in realizing circuit configurations for performance or functionality.

[0077] Exemplary applications / uses to which the present invention can be applied include, but are not limited to, semiconductor devices. Semiconductor devices may include processors, memory devices, application-specific integrated circuits (ASICs), logic circuits or devices, combinations thereof, and any other circuit devices. In such devices, one or more semiconductor devices may be included in a central processing unit, a graphics processing unit, and / or a controller based on a separate processor or computing element (e.g., logic gates). Semiconductor devices may include one or more onboard memories (e.g., caches, dedicated memory arrays, read-only memory). In some embodiments, semiconductor devices may include one or more memories (e.g., ROMs, RAMs, BASIC input / output systems (BIOS)) that may be onboard or offboard, or that may be dedicated to use by a hardware processor subsystem.

[0078] In some embodiments, the semiconductor device may include and execute one or more software elements. These software elements may include an operating system and / or one or more applications and / or specific code for achieving a specified result. In yet other embodiments, the semiconductor device may include specialized circuits dedicated to performing one or more electronic processing functions to achieve a specified result. Such circuits may include one or more field-programmable gate arrays (FPGAs) and / or programmable logic arrays (PLAs) for programmable applications.

[0079] Aspects of the present invention have been described in terms of a given exemplary architecture; however, it should be understood that other architectures, structures, substrate materials, and process features and steps may vary within the scope of the present invention.

[0080] When an element such as a layer, region, or substrate is described as being "on" or "over" another element, it will also be understood that there may be elements that are directly on or interposed to the other element. In contrast, when an element is described as being "directly on" or "directly over" another element, there is no intervening element. When an element is described as being "connected" or "coupled" to another element, it will also be understood that there may be elements that it obtains by being directly connected or coupled to the other element, or that are intervening to it. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there is no intervening element.

[0081] This embodiment may include a design for an integrated circuit chip, which may be created in a graphical computer programming language and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as a memory access network). If the designer does not manufacture the chip or the photolithography mask used to manufacture the chip, the designer may transmit the resulting design directly or indirectly to such an entity by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted into a suitable format (e.g., GDSII) for manufacturing a photolithography mask, which typically includes multiple copies of the chip design to be formed on a wafer. The photolithography mask is used to define areas of the wafer (or layers thereon, or both) to be etched or otherwise processed.

[0082] Methods as described herein may be used in the manufacture of integrated circuit chips. The resulting integrated circuit chips may be supplied by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packaged form. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leaded wires fixed to a motherboard, or other higher-level carriers) or in a multi-chip package (such as a ceramic carrier with either or both surface-mounted or embedded interconnects). In either case, the chips are then integrated with other chips, discrete circuit elements, or other signal processing devices or combinations thereof as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product may be any product containing integrated circuit chips, ranging from toys and other low-end applications to displays, keyboards or other input devices, and advanced computer products with central processing units.

[0083] It should also be understood that the material compounds are described with respect to the listed elements, for example, SiGe. These compounds may contain different proportions of elements within the compound; for example, SiGe is Si x Ge 1-x This includes, where x is less than or equal to 1, etc. In addition, other elements may be included in the compound and still function according to this principle. Compounds having additional elements are referred to herein as alloys.

[0084] The “one embodiment” or “an embodiment” and any other variations thereof referred to herein mean that the specific features, structures, characteristics, etc. described in relation to the embodiments are included in at least one embodiment. Therefore, the phrases “one embodiment” or “an embodiment” and any other variations appearing in various places throughout this specification do not necessarily all refer to the same embodiment.

[0085] Please understand that the use of any of the following, namely " / ", "and / or", and "at least one of", is intended to encompass the selection of only the first enumerated option (A), or only the second enumerated option (B), or both options (A and B), for example, in the cases of "A / B", "A and / or B", and "at least one of A and B". As a further example, in the cases of "A, B, and / or C", and "at least one of A, B, and C", such phrasing is intended to encompass the selection of only the first enumerated option (A), or only the second enumerated option (B), or only the third enumerated option (C), or only the first and second enumerated options (A and B), or only the first and third enumerated options (A and C), or only the second and third enumerated options (B and C), or all three options (A, B, and C). This can be extended to many of the listed items, as will be readily apparent to those skilled in the art in this and related fields.

[0086] The terms used herein are intended solely to describe specific embodiments and are not intended to be limited to exemplary embodiments. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. When the terms "comprises," "comprising," "includes," or "including," used herein, they identify the presence of a described feature, integer, stage, operation, element, or component, or a combination thereof, but do not exclude the presence or addition of one or more other features, integers, stages, operations, elements, components, or groups thereof, or combinations thereof.

[0087] Spatial relative terms such as “downward,” “below,” “underside,” “up,” “upper side,” “top,” “lower part,” and similar terms may be used herein to facilitate explanation and to describe the relationship of one element or feature to another element or feature as shown in the figure. It will be understood that spatial relative terms are intended to encompass different orientations of the device during use or operation, in addition to the orientation shown in the figure. For example, if the device in the figure is turned over, the element described as “below” or “below” the other element or feature will then be oriented “above” the other element or feature. Thus, the term “below” may encompass both upward and downward orientations. The device may otherwise be oriented (rotated 90 degrees or to other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Furthermore, when a layer is referred to as being “between” two layers, it will also be understood that it may be the sole layer between the two layers, or there may also be one or more intervening layers.

[0088] Terms such as "first," "second," etc., may be used herein to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. Therefore, the first element described below may be referred to as the second element without deviating from the scope of this concept.

[0089] Preferred embodiments of the device and method have been described (these are illustrative and not limiting), but it should be noted that modifications and variations are possible in light of the above teachings by those skilled in the art. Therefore, it should be understood that changes may be made within the specific embodiments disclosed within the scope of the invention and outlined in the appended claims. Thus, aspects of the invention have been described with the details and specificity required by patent law, but what is claimed and desired to be protected by the patent certificate is described in the appended claims.

Claims

1. The upper side, and the lower side opposite to the upper side; A central portion having a semiconductor substrate positioned between the upper and lower parts; and A component disposed on the semiconductor substrate in the central portion, the component having a first electrical connection from the upper side and a second electrical connection from the lower side. Semiconductor devices, including those mentioned above.

2. The semiconductor device according to claim 1, wherein the component has a gate structure, the first electrical connection is connected to the upper portion of the gate structure, and the second electrical connection is connected to the lower portion of the gate structure opposite to the upper portion.

3. The semiconductor device according to claim 1, wherein the upper part has a metallic structure symmetrical to the lower part.

4. The semiconductor device according to claim 1, wherein the first electrical connection is connected to the second electrical connection across the central portion by a through contact.

5. The semiconductor device according to claim 1, wherein the component has an active region, the first electrical connection is connected to the upper portion of the active region, and the second electrical connection is connected to the lower portion of the active region opposite to the upper portion.

6. The semiconductor device according to claim 5, wherein the active region includes the source / drain region of the transistor device.

7. The semiconductor device according to claim 5, wherein the active region includes the source / drain region of a multilayer field-effect transistor device.

8. Upper wiring with metal lines and contacts; Lower wiring having metal lines and contacts, positioned opposite the upper wiring; A central portion having a semiconductor substrate positioned between the upper wiring and the lower wiring; and A component formed on the semiconductor substrate and positioned in the central portion; the component has a first electrical connection from the upper wiring and a second electrical connection from the lower wiring. Semiconductor devices, including those mentioned above.

9. The semiconductor device according to claim 8, wherein the component has a gate structure, the first electrical connection is connected to the upper portion of the gate structure, and the second electrical connection is connected to the lower portion of the gate structure opposite to the upper portion.

10. The semiconductor device according to claim 9, wherein the upper wiring and the lower wiring have a symmetrical metallic structure with respect to each other.

11. The semiconductor device according to claim 8, wherein the first electrical connection is connected to the second electrical connection across the central portion by a through-contact that passes through the semiconductor substrate.

12. The semiconductor device according to claim 8, wherein the component has an active region, the first electrical connection is connected to the upper portion of the active region, and the second electrical connection is connected to the lower portion of the active region opposite to the upper portion.

13. The semiconductor device according to claim 12, wherein the active region includes the source / drain region of the transistor device.

14. The semiconductor device according to claim 12, wherein the active region includes the source / drain region of a multilayer field-effect transistor device.

15. The semiconductor device according to claim 8, wherein the upper wiring is a mirror image of the lower wiring with respect to the central portion.

16. The semiconductor device according to claim 8, wherein the upper wiring is a mirror image of the lower wiring in three dimensions.

17. Upper wiring with metal lines and contacts; Lower wiring having metal lines and contacts, positioned opposite the upper wiring; A central portion having a semiconductor substrate positioned between the upper wiring and the lower wiring; A first component is formed on the semiconductor substrate and positioned in the central portion, the first component having a first electrical connection from the upper wiring and a second electrical connection from the lower wiring; A second component formed on the semiconductor substrate and positioned in the central portion, the second component having a first electrical connection from the upper wiring and a second electrical connection from the lower wiring; and A bridge connecting the first electrical connection of the first component to the first electrical connection of the second component. Semiconductor devices, including those mentioned above.

18. The semiconductor device according to claim 17, wherein the first component has a gate structure, the first electrical connection is connected to the upper portion of the gate structure, and the second electrical connection is connected to the lower portion of the gate structure opposite to the upper portion.

19. The semiconductor device according to claim 17, wherein the first electrical connection is connected to the second electrical connection across the central portion by through contacts passing through the semiconductor substrate.

20. The semiconductor device according to claim 17, wherein the second component has an active region, the first electrical connection is connected to the upper portion of the active region, and the second electrical connection is connected to the lower portion of the active region opposite to the upper portion.

21. The semiconductor device according to claim 17, wherein the upper wiring is a mirror image of the lower wiring with respect to the central portion.

22. Upper wiring with metal lines and contacts; Lower wiring having metal lines and contacts, positioned opposite the upper wiring; A central portion having a semiconductor substrate positioned between the upper wiring and the lower wiring; A first circuit is arranged in the upper and lower wiring, the first circuit having a first component including a first electrical connection from the upper wiring and a second electrical connection from the lower wiring; A second circuit is arranged in the upper wiring and the lower wiring, the second circuit having a second component including a first electrical connection from the upper wiring and a second electrical connection from the lower wiring; and A bridge is formed by connecting the first circuit to the second circuit, forming a single circuit spanning the upper wiring, the lower wiring, and the central portion, where the upper wiring is a mirror image of the lower wiring with respect to the central portion. Semiconductor devices, including those mentioned above.

23. The semiconductor device according to claim 22, wherein the first component includes a gate structure, the first electrical connection of the first component is connected to the upper portion of the gate structure, and the second electrical connection of the first component is connected to the lower portion of the gate structure opposite to the upper portion.

24. The semiconductor device according to claim 22, wherein the first electrical connection is connected to the second electrical connection across the central portion by through contacts passing through the semiconductor substrate.

25. The semiconductor device according to claim 22, wherein the second component has an active region, the first electrical connection of the second component is connected to the upper portion of the active region, and the second electrical connection of the second component is connected to the lower portion of the active region opposite to the upper portion.

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