Display boards and display devices

Abstract

The present invention provides a display board and a display device. The display board includes a base substrate, a plurality of pixel units including a plurality of subpixels distributed in an array along a first direction and a second direction, wherein the plurality of subpixels include a first subpixel and a second subpixel located in two adjacent rows of the same column, a detection transistor for driving the subpixels including a third gate and a third active layer, and a scanning signal line including a body portion extending along the first direction and a plurality of protrusions extending along the second direction. The plurality of protrusions include a first protrusion and a second protrusion, and the orthographic projections of the first protrusion and the second protrusion onto the base substrate at least partially overlap with the third active layer of the detection transistor of the first subpixel and the second subpixel, respectively, with the overlapping portion being the third gate of the detection transistor of the first subpixel and the second subpixel, respectively, and the third gates of the respective detection transistors of the first subpixel and the second subpixel are located on both sides of the body portion of the same scanning signal line in the second direction.

Description

[[Technical Field]]

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. [[Background Art]]

[0002] Organic Light-Emitting Diode (OLED) devices have attracted attention due to their advantages including self-luminescence, rich colors, fast response speed, wide viewing angle, light weight, thin thickness, low power consumption and capability of realizing flexible display, and are currently widely used in devices such as mobile phones, televisions and wearable devices. With the continuous development of display technology, image quality requirements for OLED display panels are also increasing. High pixel density (Pixels Per Inch, PPI) display panels have high image density and better image quality. However, for a display panel, the higher the PPI, the smaller the pixel size and the smaller the wiring space.

[0003] How to rationally layout devices and signal lines in a limited space, while taking into account the pixel aperture ratio, improve the space utilization of display products, increase the aperture ratio, and extend the service life of display panels is one of the important issues for researchers and developers.

[0004] It should be noted that the information disclosed in the above background section is only for enhancing the understanding of the background of the present disclosure, and may include information that does not constitute prior art known to those skilled in the art. [[Summary of Invention]]

[0005] In one embodiment, a display substrate is provided, the display substrate comprising a base substrate and a plurality of pixel units located on the base substrate, wherein at least one pixel unit includes a plurality of subpixels, and at least one subpixel includes a light-emitting element and a pixel driving circuit for driving the light-emitting element, the plurality of subpixels of the plurality of pixel units are distributed in an array on the base substrate along a first direction and a second direction, the plurality of pixel units where the first direction and the second direction intersect, and scanning signal lines located on the base substrate including a main body portion extending in the first direction and a plurality of protrusions extending in the second direction, the pixel driving circuit includes a sensing transistor including a third gate and a third active layer, and the plurality of subpixels of at least one pixel unit include a first subpixel located in the i-th row and j-th column and a second subpixel located in the i+1-th row and j-th column, where i and j are either The third gate is a positive integer greater than or equal to 1, and the plurality of protrusions include a first protrusion and a second protrusion, the orthographic projection of the first protrusion onto the base substrate at least partially overlaps with the third active layer of the detection transistor of the first subpixel, the overlapping portion of the first protrusion and the third active layer of the detection transistor of the first subpixel is the third gate of the detection transistor of the first subpixel, the orthographic projection of the second protrusion onto the base substrate at least partially overlaps with the third active layer of the detection transistor of the second subpixel, the overlapping portion of the second protrusion and the third active layer of the detection transistor of the second subpixel is the third gate of the detection transistor of the second subpixel, and the third gate of the first subpixel and the third gate of the detection transistor of the second subpixel are located on both sides of the same scanning signal line in the second direction.

[0006] According to some exemplary embodiments, a plurality of subpixels of at least one pixel unit further includes a third subpixel located in the i-th row and j+1-th column, and a fourth subpixel located in the i+1-th row and j+1-th column, wherein the plurality of protrusions further include a third protrusion and a fourth protrusion, the orthogonal projection of the third protrusion onto the base substrate at least partially overlaps with the third active layer of the detection transistor of the third subpixel, the overlapping portion of the third protrusion and the third active layer of the detection transistor of the third subpixel is the third gate of the detection transistor of the third subpixel, the orthogonal projection of the fourth protrusion onto the base substrate at least partially overlaps with the third active layer of the detection transistor of the fourth subpixel, the overlapping portion of the fourth protrusion and the third active layer of the detection transistor of the fourth subpixel is the third gate of the detection transistor of the fourth subpixel, and the third gate of the detection transistor of the third subpixel and the third gate of the detection transistor of the fourth subpixel are located on either side of the same scanning signal line body in a second direction.

[0007] According to some exemplary embodiments, the display substrate further includes a detection signal line extending along a second direction, the detection signal line being used to supply a detection signal to the pixel drive circuit, the third gate of the detection transistor of the first subpixel and the third gate of the detection transistor of the third subpixel being located on opposite sides of the same detection signal line in the first direction, and / or the third gate of the detection transistor of the second subpixel and the third gate of the detection transistor of the fourth subpixel being located on opposite sides of the same detection signal line in the first direction.

[0008] According to some exemplary embodiments, the third active layer of the sensing transistor further includes a channel region, a first pole region, and a second pole region, wherein the orthographic projection of the channel region of the third active layer onto the base substrate at least partially overlaps with the orthographic projection of the third gate onto the base substrate, the first pole region and the second pole region are located on either side of the channel region of the third active layer in a first direction, and at least a portion of the third active layer located between the channel region of the sensing transistor of the first subpixel and the channel region of the sensing transistor of the third subpixel is used simultaneously as the first pole region of the sensing transistor of the first subpixel and the second pole region of the sensing transistor of the third subpixel, and / or at least a portion located between the channel region of the sensing transistor of the second subpixel and the channel region of the sensing transistor of the fourth subpixel is used simultaneously as the first pole region of the sensing transistor of the second subpixel and the second pole region of the sensing transistor of the fourth subpixel.

[0009] According to some exemplary embodiments, the third gate of the detection transistor for the first subpixel and the third gate of the detection transistor for the third subpixel are symmetric with respect to a first center line, and the first center line is the detection signal It is a virtual straight line passing through the center of the line and extending along the second direction, and / or the third gate of the detection transistor of the second subpixel and the third gate of the detection transistor of the fourth subpixel are symmetrical with respect to the first center line.

[0010] According to some exemplary embodiments, the third active layer of the first subpixel's sensing transistor and the third active layer of the third subpixel's sensing transistor are connected to each other and extend in a first direction.

[0011] According to some exemplary embodiments, the first protrusion and the second protrusion each protrude in opposite directions in a second direction from the same scanning signal line body, and the first protrusion and the second protrusion are offset by a first predetermined distance in the first direction, and the third protrusion and the fourth protrusion each protrude in opposite directions in a second direction from the same scanning signal line body, and the third protrusion and the fourth protrusion are offset by a second predetermined distance in the first direction.

[0012] According to some exemplary embodiments, the pixel driving circuit further includes a switching transistor, the switching transistor including a second gate and a second active layer, the plurality of protrusions including a fifth protrusion and a sixth protrusion, the orthogonal projection of the fifth protrusion onto the base substrate at least partially overlapping with the second active layer of the first subpixel switching transistor, the overlapping portion of the fifth protrusion and the second active layer of the first subpixel switching transistor being the second gate of the first subpixel, the orthogonal projection of the sixth protrusion onto the base substrate at least partially overlapping with the second active layer of the second subpixel switching transistor, the overlapping portion of the sixth protrusion and the second active layer of the second subpixel switching transistor being the second gate of the second subpixel, and the second gate of the first subpixel switching transistor and the second gate of the second subpixel switching transistor are located on either side of the same scanning signal line body in a second direction.

[0013] According to some exemplary embodiments, the fifth protrusion and the sixth protrusion each protrude in opposite directions in a second direction from the same scanning signal line body, and the fifth protrusion and the sixth protrusion are offset by a third predetermined distance in a first direction.

[0014] According to some exemplary embodiments, any two of the first predetermined distance, the second predetermined distance, and the third predetermined distance are approximately equal.

[0015] According to some exemplary embodiments, the detection signal line includes a line body and a first line projection projecting from the line body toward the first subpixel, the display substrate further includes a first conductive connection, the first conductive connection, the first projection and the third projection are located on the same layer, and the first conductive connection is located between the first projection and the third projection in a first direction, the orthographic projection of the first line projection onto the base substrate at least partially overlaps with the orthographic projection of the first conductive connection onto the base substrate, and the first line projection is electrically connected to the first conductive connection via a first via hole.

[0016] According to some exemplary embodiments, the orthographic projection onto the base substrate of either the first conductive connection or the first via hole at least partially overlaps with the orthographic projection onto the base substrate of the portion of the third active layer that is simultaneously used as the first pole region of the first subpixel's sensing transistor and the second pole region of the third subpixel's sensing transistor.

[0017] According to some exemplary embodiments, the display substrate further comprises a second conductive connection portion, the second conductive connection portion, the first protrusion and the fifth protrusion located on the same layer, and the second conductive connection portion located between the first protrusion and the fifth protrusion in a first direction; the display substrate further comprises a light-shielding portion located on the base substrate, the orthographic projections of the light-shielding portion, the second pole region of the first subpixel detection transistor and the second conductive connection portion onto the base substrate overlap at least partially, and the second pole region of the first subpixel detection transistor is electrically connected to the light-shielding portion via the second conductive connection portion and the second via hole.

[0018] According to some exemplary embodiments, the orthographic projection of the second active layer onto the base substrate at least partially overlaps with the orthographic projection of the light-shielding portion onto the base substrate, the pixel driving circuit further includes a storage capacitor, the storage capacitor includes a first plate and a second plate, at least a portion of the second active layer is used as the first plate, and at least a portion of the light-shielding portion is used as the second plate.

[0019] According to some exemplary embodiments, the detection signal line further includes a first widening portion having a width in a first direction greater than the width of the line body in a first direction, wherein the orthographic projection of the first widening portion onto the base substrate is located in a first direction between the orthographic projection of the first plate of the storage capacitor of the first subpixel onto the base substrate and the orthographic projection of the first plate of the storage capacitor of the third subpixel onto the base substrate, and / or, the detection signal line further includes a second widening portion having a width in a first direction greater than the width of the line body in a first direction, wherein the orthographic projection of the second widening portion onto the base substrate is located in a first direction between the orthographic projection of the first plate of the storage capacitor of the second subpixel onto the base substrate and the orthographic projection of the first plate of the storage capacitor of the fourth subpixel onto the base substrate.

[0020] According to some exemplary embodiments, the orthographic projection of the first widening portion onto the base substrate and the orthographic projection of the first plate of the storage capacitor of the first subpixel onto the base substrate are separated by a first separation distance in a first direction, the orthographic projection of the first widening portion onto the base substrate and the orthographic projection of the first plate of the storage capacitor of the third subpixel onto the base substrate are separated by a second separation distance in a first direction, and the first separation distance and the second separation distance are approximately equal, and / or, the orthographic projection of the second widening portion onto the base substrate and the orthographic projection of the first plate of the storage capacitor of the second subpixel onto the base substrate are separated by a third separation distance in a first direction, the orthographic projection of the second widening portion onto the base substrate and the orthographic projection of the first plate of the storage capacitor of the fourth subpixel onto the base substrate are separated by a fourth separation distance in a first direction, and the third separation distance and the fourth separation distance are approximately equal.

[0021] According to some exemplary embodiments, the display substrate further includes a first conductive connection portion, the first conductive connection portion, the first protrusion portion and the second protrusion portion are located on the same layer, the orthographic projection of the first widening portion onto the base substrate at least partially overlaps with the orthographic projection of the first conductive connection portion onto the base substrate, and the first widening portion is electrically connected to the first conductive connection portion via a first via hole.

[0022] According to some exemplary embodiments, the third active layer further includes an active extension portion extending in a direction parallel to the extending direction of the detection signal line from the portion of the third active layer that is simultaneously used as the first pole region of the detection transistor of the first subpixel and the second pole region of the detection transistor of the third subpixel, wherein the orthographic projection of the active extension portion onto the base substrate at least partially overlaps with the orthographic projection of the detection signal line onto the base substrate, and the active extension portion is electrically connected to the first conductive connection portion.

[0023] According to some exemplary embodiments, the second active layer includes a first portion extending in a first direction, a second portion extending in a second direction, and a third portion used as the first electrode plate, wherein the portion where the first portion and the fifth projection overlap is the channel region of the switching transistor, the second portion connects the first portion and the third portion, and the width of the second portion in the first direction is greater than the width of the first portion in the second direction.

[0024] According to some exemplary embodiments, the pixel driving circuit further includes a driving transistor including a first active layer, the display substrate further includes a fifth conductive connection and a first power signal line for transmitting a first power signal, the fifth conductive connection and the scanning signal line are located on the same layer, the first power signal line and the detection signal line are located on the same layer, one end of the fifth conductive connection is electrically connected to the first active layer via a fifth via hole, the other end of the fifth conductive connection is electrically connected to the first power signal line via a sixth via hole, and two subpixels located in two adjacent rows of pixel units and in the same column share the fifth conductive connection.

[0025] According to some exemplary embodiments, the display substrate includes a semiconductor layer located on the base substrate, a first conductive layer located on the side of the semiconductor layer away from the base substrate, a second conductive layer located on the side of the first conductive layer away from the base substrate, and a light-shielding layer located on the side of the semiconductor layer closer to the base substrate, wherein the light-shielding portion is located on the light-shielding layer, the first active layer, the second active layer and the third active layer are located on the semiconductor layer, the scanning signal line, the first conductive connection portion and the second conductive connection portion are located on the first conductive layer, and the detection signal line and the first power supply signal The line is located in the second conductive layer.

[0026] According to some exemplary embodiments, the display substrate further includes a pixel defining layer located on the side of the second conductive layer away from the base substrate for defining a plurality of pixel apertures, and a reflective electrode layer located on the side of the pixel defining layer away from the base substrate, wherein the pixel defining layer further defines a plurality of slots, each of which is located between any two adjacent pixel apertures, and at least a portion of the reflective electrode layer is located in the plurality of slots.

[0027] According to some exemplary embodiments, the display substrate further comprises a first conductive part located on a side of the light shielding layer closer to the base substrate, and a second conductive part located on the semiconductor layer, an orthographic projection of the first conductive part onto the base substrate at least partially overlaps with an orthographic projection of the pixel opening onto the base substrate, an orthographic projection of the second conductive part onto the base substrate at least partially overlaps with the orthographic projection of the pixel opening onto the base substrate, the first electrode plate further comprises the second conductive part, the second electrode plate further comprises the first conductive part, the first conductive part is electrically connected to the light shielding part, and the first conductive part comprises a transparent conductive material.

[0028] According to some exemplary embodiments, the display substrate further comprises a plurality of data lines located on the second conductive layer, the plurality of data lines comprise a first data line, a second data line, a third data line and a fourth data line, the first data line is electrically connected to a first electrode of a switching transistor of the first sub-pixel, the second data line is electrically connected to a first electrode of a switching transistor of the second sub-pixel, the third data line is electrically connected to a first electrode of a switching transistor of the third sub-pixel, the fourth data line is electrically connected to a first electrode of a switching transistor of the fourth sub-pixel, the first data line and the second data line are located on one side of a pixel driving circuit of the pixel unit in a first direction, the third data line and the fourth data line are located on the other side of the pixel driving circuit of the pixel unit in the first direction, the first data line and the second data line are arranged at an interval in the first direction, the first data line is located on a side of the second data line away from the pixel driving circuit of the pixel unit, and the fourth data line is located on a side of the third data line away from the pixel driving circuit of the pixel unit.

[0029] In another aspect, a display device comprising the display substrate according to any one of the above is provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above-mentioned contents and other purposes, features, and advantages of this disclosure will become clearer by describing embodiments of this disclosure with reference to the drawings below. [Figure 1] Figure 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure. [Figure 2A] Figure 2A is an equivalent circuit diagram of the pixel driving circuits for multiple subpixels of the display board in Figure 1. [Figure 2B] Figure 2B is an equivalent circuit diagram of the pixel driving circuit for a single subpixel of the display board in Figure 1. [Figure 3] Figure 3 is a partial plan view of a display substrate according to some embodiments of the present disclosure, schematically showing the plan view of the pixel driving circuit and the first electrode of the light-emitting element included in the display substrate. [Figure 4A] Figure 4A is a plan view of the light-shielding layer 30, which includes multiple light-shielding portions 31, among the multiple film layers shown in Figure 3. [Figure 4B] Figure 4B is a plan view of the second conductive layer 20, one of the multiple film layers shown in Figure 3. [Figure 4C] Figure 4C is a plan view of the active layer 40, one of the multiple film layers shown in Figure 3. [Figure 4D] Figure 4D is a plan view of the multiple membrane layers shown in Figure 3, and shows multiple GI via holes. [Figure 4E] Figure 4E is a plan view of the first conductive layer 10, one of the multiple film layers shown in Figure 3. [Figure 4F] Figure 4F is a plan view of multiple passivation layer PVX via holes, among the multiple membrane layers shown in Figure 3. [Figure 4G] Figure 4G is a plan view of multiple first electrode via holes of the light-emitting element, among the multiple film layers shown in Figure 3. [Figure 4H] Figure 4H is a plan view of the first electrode of the light-emitting element, among the multiple film layers shown in Figure 3. [Figure 4I] Figure 4I is a plan view of the pixel definition layer, one of the multiple film layers shown in Figure 3. [Figure 4J] Figure 4J is a schematic diagram of the combined film layer of the second conductive layer 20 and the first conductive layer 10, among the multiple film layers shown in Figure 3. [Figure 5] Figure 5 is a magnified view of the area near the dashed rectangular region in Figure 3. [Figure 6A] Figure 6A is a cross-sectional view along dashed line 1 in Figure 5. [Figure 6B] Figure 6B is a cross-sectional view along dashed line 2 in Figure 5, and the orthographic projection of dashed lines 1 and 2 onto the base substrate partially overlaps with the second via hole VH2. [Figure 7] Figure 7 is a schematic plan view of the lamination of the partial light-shielding layer 30 and the active layer 40 according to some exemplary embodiments of the present disclosure. [Figure 8] Figure 8 is a partial plan view of a display board according to another embodiment of the present disclosure, showing the detection signal line widening section. [Figure 9] Figure 9 is a magnified view of a portion of the area near the dashed line frame at the top of Figure 8. [Figure 10] Figure 10 is a schematic partial plan view of a display substrate according to another embodiment of the present disclosure, showing the active extension portion of the third active layer. [Figure 11] Figure 11 is a magnified view of the region near the intermediate scan signal line in Figure 10. [Figure 12] Figure 12 is a schematic partial plan view of a display substrate according to another embodiment of the present disclosure. [Figure 13] Figure 13 is a schematic partial cross-sectional view of a display substrate according to another embodiment of the present disclosure.

[0031] In addition, in the drawings illustrating embodiments of the present invention, the sizes of layers, structures, or regions may have been enlarged or reduced for clarity; that is, these drawings are not drawn to actual scale. [Modes for carrying out the invention]

[0032] To further clarify the purpose, technical proposal and advantages of the embodiments of this disclosure, the technical proposal of the embodiments of this disclosure will be described clearly and completely below with reference to the drawings of the embodiments of this disclosure. Clearly, the embodiments described are some embodiments of this disclosure, not all embodiments. All other embodiments obtained by those skilled in the art without requiring any creative work based on the embodiments of this disclosure are within the scope of protection of this disclosure.

[0033] In addition, the size and relative size of the elements may be enlarged in the drawings for clarity and / or explanatory purposes. Thus, the dimensions of each element and the relative dimensions are not necessarily limited to those shown. In this specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0034] Unless otherwise defined, technical or scientific terms used in this disclosure have their ordinary meanings as understood by those skilled in the art. The terms “First,” “Second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similar terms such as “includes” or “contains” mean that the element or article appearing first encompasses the elements or articles listed later and their equivalents, and do not exclude other elements or articles.

[0035] In this specification, unless otherwise specified, directional terms such as “up,” “down,” “left,” “right,” “inside,” and “outside” are intended to indicate orientations or positional relationships as shown in the drawings and are merely for the purpose of facilitating the disclosure. They do not indicate or imply that the pointed-to devices, elements, or components necessarily have a specific orientation or are configured or operated in a specific orientation. It should be understood that after the absolute position of the object being described changes, the relative positional relationships they represent may also change accordingly. Therefore, these directional terms should not be understood as limiting the disclosure.

[0036] In this specification, "same layer" refers to a layer structure formed by creating a film layer for a specific pattern using the same film deposition process, and then patterning the film layer using the same mask with a single patterning process. Depending on the differences in the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures, and / or parts located in the "same layer" are made of the same material and formed by the same patterning process, and typically have approximately the same thickness.

[0037] Those skilled in the art will understand that, unless otherwise specified, the terms "height" or "thickness" in this specification mean the dimension along the surface of each film layer provided perpendicular to the display substrate, that is, the dimension along the light emission direction of the display substrate, or the dimension along the normal direction of the display device.

[0038] In this specification, the directional expressions “first direction” and “second direction” are used to describe different directions along a pixel unit, such as the vertical and horizontal directions of a pixel unit, or the row and column directions of a sub-pixel array. Such expressions should be understood to be illustrative and not to limit the scope of this disclosure.

[0039] In this specification, the term "transistor" may refer to a transistor, a thin-film transistor, a field-effect transistor, or any other device having the same properties. In the embodiments of this disclosure, to distinguish between the two poles of a transistor other than the control pole, one pole is referred to as the first pole and the other as the second pole. In actual operation, if the transistor is a thin-film transistor or a field-effect transistor, the first pole may be the drain and the second pole may be the source, or the first pole may be the source and the second pole may be the drain.

[0040] Some exemplary embodiments of the present disclosure provide a display substrate, the display substrate comprising a base substrate and a plurality of pixel units located on the base substrate, wherein at least one pixel unit comprises a plurality of subpixels, and at least one subpixel comprises a light-emitting element and a pixel driving circuit for driving the light-emitting element, the plurality of subpixels of the plurality of pixel units are distributed in an array on the base substrate along a first direction and a second direction, the plurality of pixel units where the first direction and the second direction intersect, and scanning signal lines located on the base substrate comprising a body portion extending in the first direction and a plurality of protrusions extending in the second direction, the pixel driving circuit comprising a sensing transistor comprising a third gate and a third active layer, and the plurality of subpixels of at least one pixel unit comprises a first subpixel located in the i-th row and j-th column and a second subpixel located in the i+1-th row and j-th column, where i, j Each of these is a positive integer greater than or equal to 1, and the plurality of protrusions include a first protrusion and a second protrusion, the orthographic projection of the first protrusion onto the base substrate at least partially overlaps with the third active layer of the first subpixel's detection transistor, the overlapping portion of the first protrusion and the third active layer of the first subpixel's detection transistor is the third gate of the first subpixel's detection transistor, the orthographic projection of the second protrusion onto the base substrate at least partially overlaps with the third active layer of the second subpixel's detection transistor, the overlapping portion of the second protrusion and the third active layer of the second subpixel's detection transistor is the third gate of the second subpixel's detection transistor, and the third gate of the first subpixel's detection transistor and the third gate of the second subpixel's detection transistor are located on both sides of the same scanning signal line in the second direction. This method allows for uniform distribution of the subpixel's detection transistors to both the upper and lower sides of the gate line, significantly improving space utilization, increasing the aperture ratio of the display panel, and extending the lifespan of the display panel.

[0041] Figure 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.

[0042] Referring to Figure 1, the display substrate according to the embodiment of the present disclosure may include a base substrate 100, a pixel unit PX provided on the base substrate 100, a drive unit DRU provided on the base substrate 100, and wiring PL that electrically connects the pixel unit PX and the drive unit DRU, the drive unit DRU being used to drive the pixel unit PX.

[0043] The display board may include a display area AA and a non-display area NA. The display area AA may be an area where pixel units PX for displaying images are provided. Each pixel unit PX will be described later. The non-display area NA may be an area where no pixel units PX are provided, i.e., an area where no image is displayed. The non-display area NA is provided with a drive unit DRU for driving the pixel units PX and several wiring PLs connecting the pixel units PX and the drive unit DRU. The non-display area NA corresponds to the frame in the final display device, and the width of the frame can be determined according to the width of the non-display area NA.

[0044] The display area AA may have various shapes. For example, the display area AA can be set to various shapes such as a closed polygon with straight sides (e.g., a rectangle), a circle or ellipse with curved sides, or a semicircle or semiellipse with both straight and curved sides. In the embodiments of this disclosure, the display area AA is set to a single area having the shape of a quadrilateral with straight sides, but this is merely an exemplary embodiment of this disclosure and should be understood as not limiting the disclosure.

[0045] The non-display area NA may be provided on at least one side of the display area AA. In embodiments of the present disclosure, the non-display area NA may surround the outer perimeter of the display area AA. In embodiments of the present disclosure, the non-display area NA may include a lateral portion extending in a first direction X and a vertical portion extending in a second direction Y.

[0046] The pixel unit PX is located in the display area AA. The pixel unit PX is the smallest unit for displaying an image, and multiple units may be provided. For example, the pixel unit PX may include a light-emitting device that emits white light and / or colored light.

[0047] Multiple pixel units PX are provided, with rows and extending in the first direction X. 2 The pixels are arranged in a matrix by columns extending in the direction Y. However, the embodiments of this disclosure do not particularly limit the arrangement of the pixel units PX, and they can be arranged in various ways. For example, the pixel units PX are arranged in the first direction X and 2 The columns may be arranged such that the direction inclined with respect to direction Y becomes the column direction, and the direction intersecting the column direction becomes the row direction.

[0048] A single pixel unit PX may contain multiple subpixels. For example, a single pixel unit PX may contain three subpixels: a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3. Alternatively, a single pixel unit PX may contain four subpixels: a first subpixel SP1, a second subpixel SP2, a third subpixel SP3, and a fourth subpixel. For example, the first subpixel SP1 may be a red subpixel, the second subpixel SP2 a green subpixel, the third subpixel SP3 a blue subpixel, and the fourth subpixel a white subpixel.

[0049] Each subpixel may include a light-emitting element and a pixel driving circuit for driving the light-emitting element. For example, a first subpixel SP1 may include a first light-emitting element located in a first light-emitting region SPA1 and a first pixel driving circuit SPC1 for driving the first light-emitting element, with the first light-emitting element emitting red light; a second subpixel SP2 may include a second light-emitting element located in a second light-emitting region SPA2 and a second pixel driving circuit SPC2 for driving the second light-emitting element, with the second light-emitting element emitting green light; and a third subpixel SP3 may include a third light-emitting element located in a third light-emitting region SPA3 and a third pixel driving circuit SPC3 for driving the third light-emitting element, with the third light-emitting element emitting blue light.

[0050] The light-emitting region of a subpixel may be the region where the subpixel's light-emitting element is located. For example, in an OLED display panel, the light-emitting element of a subpixel may include a stacked first electrode (e.g., anode), a light-emitting material layer, and a second electrode (e.g., cathode). Thus, the light-emitting region of a subpixel may be the region corresponding to the portion of the light-emitting material layer sandwiched between the anode and the cathode.

[0051] Each subpixel further includes a non-emitting region; for example, the pixel driving circuit for a subpixel is located in the non-emitting region of the subpixel. The ratio of the area of ​​the emitting region of each subpixel to the total area of ​​that subpixel (the sum of the areas of the emitting and non-emitting regions) determines the aperture ratio of that subpixel.

[0052] OLED light-emitting devices (e.g., light-emitting layer, EL layer) may have poor consistency during manufacturing. For example, when the EL layer is manufactured using a vapor deposition process, limitations of the vapor deposition process can cause the EL layers of each manufactured subpixel to not match, resulting in uneven luminescence or chromaticity between different subpixels. Furthermore, as usage time increases, the EL layers degrade to varying degrees, which also causes uneven luminescence or chromaticity between different subpixels. In embodiments of this disclosure, the display substrate may further include a photosensitive circuit OSC, which can detect the light actually emitted by the pixel unit. Thus, in embodiments of this disclosure, the display substrate can improve the uniformity of light emission by performing optical compensation for the subpixels within each pixel unit based on the light actually emitted by the pixel unit detected by the photosensitive circuit OSC.

[0053] For example, in some exemplary embodiments of this disclosure, each pixel unit PX has one photosensitive A circuit OSC is provided. photosensitive The OSC circuit detects the light actually emitted by the pixel unit PX in which it is located.

[0054] For example, in the embodiments of this disclosure, at least two pixel units PX may share one photosensitive circuit OSC. Referring to Figure 1, two pixel units PX located in two adjacent rows within the same row of pixel units can share one photosensitive circuit OSC. In this way, it is not necessary to provide one photosensitive circuit for each pixel unit PX, the number of photosensitive circuits can be reduced, and the aperture ratio can be improved. When the display substrate is in the display state, the photosensitive circuit OSC can detect the light actually emitted by the two adjacent pixel units. For example, the photosensitive circuit OSC may include at least a photoelectric conversion element. In this way, the photosensitive circuit OSC may be configured to detect the light actually emitted by the two adjacent pixel units and transmit a detected electrical signal based on the detected light.

[0055] Furthermore, referring to Figure 1, for example, the photosensitive circuit OSC can transmit the detection electrical signal to an external circuit, such as the control IC of the display device. The control IC can control the control signals transmitted to the pixel unit PX based on the detection electrical signal, and can, for example, control the data signals (i.e., data signals) transmitted to the pixel drive circuits of each subpixel. In response to the control of the data signals, each subpixel emits light accordingly.

[0056] In the embodiment shown in Figure 1, subpixels SP1, SP2, and SP3 are arranged side by side, and each subpixel SP1, SP2, and SP3 has its own data line DL.

[0057] Figure 2A is an equivalent circuit diagram of the pixel driving circuits for multiple subpixels of the display board in Figure 1, and Figure 2B is a single subpixel of the display board in Figure 1. Drive This is an equivalent circuit diagram of the circuit. The pixel driving circuit shown in Figure 2B may be any of the pixel driving circuits SPC1, SPC2, or SPC3 described above. Referring to Figures 2A and 2B, the pixel driving circuit may include multiple elements such as a driving transistor T1, a switching transistor T2, a sensing transistor T3, and a storage capacitor Cst. This pixel driving circuit can be called a 3T1C structure.

[0058] Here, the pixel driving circuit included in the display substrate according to the embodiment of this disclosure will be described using the 3T1C structure as an example, but the pixel driving circuit included in the display substrate according to the embodiment of this disclosure is not limited to the 3T1C structure.

[0059] Continuing to refer to Figure 2B, the gate of switching transistor T2 is connected to the scan signal line GL, the first electrode of switching transistor T2 is connected to the data line DL, and the second electrode of switching transistor T2 is connected to the gate of drive transistor T1. For example, both the second electrode of switching transistor T2 and the gate of drive transistor T1 may be electrically connected to node G. Switching transistor T2 controls the writing of the voltage signal from data line DL to the pixel drive circuit.

[0060] Each transistor may include an active layer, a gate, a first electrode (e.g., a source), and a second electrode (e.g., a drain). For example, a driving transistor T1 includes a first gate G1 and a first active layer ACT1, a switching transistor T2 includes a second gate G2 and a second active layer ACT2, and a sensing transistor T3 includes a third gate G3 and a third active layer ACT3. In the embodiments of this disclosure, the active layer of the transistor may be located on a semiconductor layer, and the gate may be located on a different conductive layer.

[0061] In this specification, the first electrode of a transistor may be either the source or the drain of the transistor, and the second electrode of a transistor may be the other of the source or the drain of the transistor.

[0062] The gate of the drive transistor T1 is electrically connected to node G, the first electrode of the drive transistor T1 is connected to a first power supply signal (e.g., a high-voltage level signal VDD), and the second electrode of the drive transistor T1 is connected to the anode of the light-emitting element, thereby generating a drive current based on the voltage signal to drive the light emission of the light-emitting element D1. For example, the light-emitting element D1 may be an organic light-emitting diode (OLED).

[0063] The ends of the storage capacitor Cst are connected to the gate and source of the drive transistor T1, respectively, and store the voltage signal input from the data line. For example, one end of the storage capacitor Cst is electrically connected to node G, and the other end of the storage capacitor Cst is electrically connected to node S. That is, one end of the storage capacitor Cst, the second electrode of the switching transistor T2, and the gate of the drive transistor T1 are all electrically connected to node G, while the other end of the storage capacitor Cst, the second electrode of the drive transistor T1, and the anode of the light-emitting element D1 are all electrically connected to node S.

[0064] The gate of the detection transistor T3 is connected to the scan signal line GL, the first electrode of the detection transistor T3 is connected to the detection signal line SL, and the second electrode of the detection transistor T3 is electrically connected to node S.

[0065] The anode of the light-emitting element D1 is electrically connected to node S, and the cathode of the light-emitting element D1 is electrically connected to the low-voltage level signal VSS. Both the level signal VDD and VSS are DC voltage signals that provide the voltage necessary to drive the light emission of the light-emitting element D1.

[0066] Figure 3 is a partial plan view of a display substrate according to some embodiments of the present disclosure, schematically showing the plan view of the pixel driving circuit and the first electrode of the light-emitting element included in the display substrate. Figures 4A to 4I are plan views of a plurality of film layers shown in Figure 3, respectively. Figure 4A shows a light-shielding layer 30, which includes a plurality of light-shielding portions 31. Figure 4B shows a second conductive layer 20. Figure 4C shows an active layer 40. Figure 4D shows a plurality of GI via holes VHG. Figure 4E shows a first conductive layer 10. Figure 4F shows a plurality of passivation layer PVX via holes VHP. Figure 4G shows a plurality of first electrode via holes VHR of the light-emitting element. Figure 4H shows a first electrode of the light-emitting element. Figure 4I shows a pixel definition layer. Figure 4J shows a schematic diagram of a combined film layer of the second conductive layer 20 and the first conductive layer 10.

[0067] Referring to Figures 1 and 3, the display board includes a base board 100 and a plurality of pixel units located on the base board 100, where at least one pixel unit includes a plurality of subpixels, and each subpixel includes a light-emitting element and a pixel driving circuit for driving the light-emitting element, for example, pixels The drive circuit includes a drive transistor T1, a switching transistor T2, and a detection transistor T3. Multiple subpixels of multiple pixel units are distributed in an array on the base substrate 100 along a first direction D1 and a second direction D2, where the first direction D1 and the second direction D2 intersect. Referring to Figures 3, 4C, and 4E, the display substrate further includes a scanning signal line GL located on the base substrate 100, the scanning signal line including a main body portion 110 extending along the first direction D1 and multiple protrusions extending along the second direction D2. The pixel drive circuit includes a detection transistor T3 including a third gate G3 and a third active layer ACT3. Multiple subpixels of at least one pixel unit include a first subpixel SP1 and a second subpixel SP2, where the first subpixel SP1 is located in the i-th row and j-th column, and the second subpixel SP2 is located in the i+1-th row and j-th column, where i and j are both positive integers of 1 or greater. The multiple protrusions include a first protrusion 111 and a second protrusion 112. The orthographic projection of the first protrusion 111 onto the base substrate 100 at least partially overlaps with the third active layer ACT313 of the detection transistor T31 of the first subpixel SP1, and the overlapping portion of the first protrusion 111 and the third active layer ACT313 of the detection transistor T31 of the first subpixel SP1 is the third gate G31 of the detection transistor T31 of the first subpixel SP1. The orthographic projection of the second protrusion 112 onto the base substrate 100 at least partially overlaps with the third active layer ACT324 of the detection transistor T32 of the second subpixel SP2, and the overlapping portion of the second protrusion 112 and the third active layer ACT324 of the detection transistor T32 of the second subpixel SP2 is the third gate G32 of the detection transistor T32 of the second subpixel SP2. The third gate G31 of the detection transistor T31 of the first subpixel SP1 and the third gate G32 of the detection transistor T32 of the second subpixel SP2 are located on opposite sides of the main body 110 of the same scanning signal line GL in the second direction.

[0068] In some exemplary embodiments of the present disclosure, with continued reference to Figures 3, 4C, and 4E, the plurality of subpixels of at least one pixel unit further include a third subpixel SP3 located in the i-th row and j+1-th column, and a fourth subpixel SP4 located in the i+1-th row and j+1-th column. The plurality of protrusions further include a third protrusion 113 and a fourth protrusion 114, wherein the orthographic projection of the third protrusion 113 onto the base substrate 100 at least partially overlaps with the third active layer ACT313 of the sensing transistor T33 of the third subpixel SP3, and the overlapping portion of the third protrusion 113 and the third active layer ACT313 of the sensing transistor T33 of the third subpixel SP3 is the third gate G33 of the sensing transistor T33 of the third subpixel SP3. The orthographic projection of the fourth protrusion 114 onto the base substrate 100 overlaps at least partially with the third active layer ACT324 of the detection transistor T34 of the fourth subpixel SP4, and the overlapping portion of the fourth protrusion 114 and the third active layer ACT324 of the detection transistor T34 of the fourth subpixel SP4 is the third gate G34 of the detection transistor T34 of the fourth subpixel SP4. The third gate G33 of the detection transistor T33 of the third subpixel SP3 and the third gate G34 of the detection transistor T34 of the fourth subpixel SP4 are located on opposite sides of the main body 110 of the same scanning signal line GL in the second direction.

[0069] By uniformly distributing the sub-pixel detection transistors on both the upper and lower sides of the scanning signal line, space utilization is improved, the aperture ratio is enhanced, and this is advantageous for realizing the design of high PPI display panels.

[0070] In some exemplary embodiments of the present disclosure, referring to Figure 3, the display substrate further includes a detection signal line SL extending along a second direction D2, the detection signal line SL is pixelsA detection signal is supplied to the drive circuit. The third gate G31 of the detection transistor T31 of the first subpixel SP1 and the third gate G33 of the detection transistor T33 of the third subpixel SP3 are located on opposite sides of the same detection signal line SL in the first direction D1, and / or the third gate G32 of the detection transistor T32 of the second subpixel SP2 and the third gate G34 of the detection transistor T34 of the fourth subpixel SP4 are located on opposite sides of the same detection signal line SL in the first direction D1.

[0071] In some exemplary embodiments of the present disclosure, referring to Figures 3 and 4C, the third active layer ACT3 of the sensing transistor T3 further includes a channel region A0, a first pole region A1, and a second pole region A2. The orthographic projection of the channel region A0 of the third active layer ACT3 onto the base substrate 100 at least partially overlaps with the orthographic projection of the third gate G3 onto the base substrate 100, and the first pole region A1 and the second pole region A2 are located on either side of the channel region A0 of the third active layer ACT3 in a first direction D1. The third active layer ACT3 is located in at least a portion of the area between the channel region A013 of the detection transistor T31 of the first subpixel SP1 and the channel region A013 of the detection transistor T33 of the third subpixel SP3, and is used as the first pole region A113 of the detection transistor T31 of the first subpixel SP1 and the second pole region A213 of the detection transistor T34 of the third subpixel SP3, and / or the third active layer ACT3 is located in at least a portion of the area between the channel region A024 of the detection transistor T32 of the second subpixel SP2 and the channel region A024 of the detection transistor T34 of the fourth subpixel SP4, and is used as the first pole region A124 of the detection transistor T32 of the second subpixel SP2 and the second pole region A224 of the detection transistor T34 of the fourth subpixel SP4.

[0072] In some exemplary embodiments of this disclosure, referring to Figure 3, the third gate G31 of the detection transistor T31 of the first subpixel SP1 and the third gate G33 of the detection transistor T33 of the third subpixel SP3 are symmetric with respect to the first center line, and the first center line is the detection line. signalThe first center line M1 is a virtual straight line that passes through the center of line SL and extends along the second direction D2, and / or the third gate G32 of the detection transistor T32 of the second subpixel SP2 and the third gate G34 of the detection transistor T34 of the fourth subpixel SP4 are symmetrical with respect to the first center line M1.

[0073] Detection of detection transistors T3 in multiple subpixels signal By designing it symmetrically with respect to line SL, in the first direction D1 running Inspection signal By reducing the length of the connecting wires, wiring space can be significantly saved, the process failure rate can be reduced, and the display quality of the display panel can be improved.

[0074] In some exemplary embodiments of this disclosure, referring to Figures 3 and 4C, the third active layer ACT313 of the sensing transistor T31 of the first subpixel SP1 and the third active layer ACT313 of the sensing transistor T33 of the third subpixel SP3 are connected to each other and extend along the first direction D1. That is, the sensing transistor T31 of the first subpixel SP1 and the sensing transistor T33 of the third subpixel SP3 can share a source and drain. By designing two sensing transistors of two adjacent subpixels in the same row to share a source and drain, the number of connection holes can be reduced, further saving wiring space, increasing the aperture ratio of the display substrate, and improving the display quality of the display panel.

[0075] In some exemplary embodiments of the present disclosure, referring to Figure 4E, the first projection 111 and the second projection 112 each project in opposite directions in a second direction D2 from the body 110 of the same scanning signal line, and the first projection 111 and the second projection 112 are offset by a first predetermined distance D12 in the first direction D1, and / or the third projection 113 and the fourth projection 114 each project in opposite directions in a second direction D2 from the body 110 of the same scanning signal line, and the third projection 113 and the fourth projection 114 are offset by a second predetermined distance D34 in the first direction D1.

[0076] In some exemplary embodiments of this disclosure, referring to Figures 3, 4C, and 4E, the pixel driving circuit further includes a switching transistor T2 comprising a second gate G2 and a second active layer ACT2, for example, a first sub-pixel SP1 pixels The drive circuit includes a switching transistor T21 which includes a second gate G21 and a second active layer ACT21. The plurality of protrusions include a fifth protrusion 115 and a sixth protrusion 116. The orthographic projection of the fifth protrusion 115 onto the base substrate 100 at least partially overlaps with the second active layer ACT21 of the switching transistor T21 of the first subpixel SP1, and the overlapping portion of the fifth protrusion 115 and the second active layer ACT21 of the switching transistor T21 of the first subpixel SP1 is the second gate G21 of the switching transistor T21 of the first subpixel SP1. The orthographic projection of the sixth protrusion 116 onto the base substrate 100 at least partially overlaps with the second active layer ACT22 of the switching transistor T22 of the second subpixel SP2, and the overlapping portion of the sixth protrusion 116 and the second active layer ACT22 of the switching transistor T22 of the second subpixel SP2 is the second gate G22 of the switching transistor T22 of the second subpixel SP2. The second gate G21 of the switching transistor T21 of the first subpixel SP1 and the second gate G22 of the switching transistor T22 of the second subpixel SP2 are located on opposite sides of the main body 110 of the same scanning signal line GL in the second direction D2.

[0077] Multiple subpixel switching transistors T2 Run Inspection signal By designing the wiring on both the top and bottom sides, wiring space can be significantly reduced, the process failure rate can be lowered, and the display quality of the display panel can be improved.

[0078] In some exemplary embodiments of the present disclosure, referring to Figure 4E, the fifth projection 115 and the sixth projection 116 each project in opposite directions in a second direction D2 from the main body 110 of the same scanning signal line GL, and the fifth projection 115 and the sixth projection 116 are offset by a third predetermined distance D56 in a first direction D1.

[0079] In some exemplary embodiments of the present disclosure, referring again to Figure 4E, any two of the first predetermined distance D12, the second predetermined distance D34, and the third predetermined distance D56 are approximately equal.

[0080] For illustrative purposes, referring to Figure 4J, the display board further includes a first data line DL1, a second data line DL2, a third data line DL3, and a fourth data line DL4, the first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4 located in the second conductive layer 20.

[0081] Referring to Figures 3 and 4J, the first data line DL1 is electrically connected to the switching transistor T21 of the first subpixel SP1 and is used to write a data signal to the first subpixel SP1; the second data line DL2 is electrically connected to the switching transistor T22 of the second subpixel SP2 and is used to write a data signal to the second subpixel SP2; similarly, the third data line DL3 is electrically connected to the switching transistor of the third subpixel SP3 and is used to write a data signal to the third subpixel SP3; and the fourth data line DL4 is... 4 It is electrically connected to the switching transistor of the sub-pixel SP4 and is used to write data signals to the fourth sub-pixel SP4.

[0082] Due to limitations in the spatial layout of the data lines, the first data line DL1 and the second data line DL2 are offset by a fourth predetermined distance D012 in the first direction D1, and the third data line DL3 and the fourth data line DL4 are offset by a fifth predetermined distance D034 in the first direction D1. Note that the offset distance between data lines here may be the minimum distance or the average distance between two adjacent data lines.

[0083] In the embodiments of this disclosure, the first pole (source or drain) of the switching transistor T21 of the first subpixel SP1 is electrically connected to the first data line DL1 via the third conductive connection 123 and the third via hole VH3. Similarly, the first pole (source or drain) of the switching transistor T22 of the second subpixel SP2 is electrically connected to the second data line DL2, the first pole (source or drain) of the switching transistor T23 of the third subpixel SP3 is electrically connected to the third data line DL3, and the first pole (source or drain) of the switching transistor T24 of the fourth subpixel SP4 is electrically connected to the fourth data line DL4. In other words, for the first subpixel SP1 and the third subpixel SP3 located in the same row, the first pole of the switching transistor of the first subpixel SP1 is electrically connected to the first data line DL1 located on the outside, and the first pole of the switching transistor of the third subpixel SP3 is electrically connected to the third data line DL3 located on the inside. For the second subpixel SP2 and the fourth subpixel SP4 located in the same row, the first pole of the switching transistor of the second subpixel SP2 is electrically connected to the second data line DL2 located on the inside, and the first pole of the switching transistor of the fourth subpixel SP4 is electrically connected to the fourth data line DL4 located on the outside.

[0084] To ensure that the distance from the data signal to the drive transistor via the data writing transistor is not too far, for example, to ensure that the distance from the data signal to the drive transistor T11 of the first subpixel SP1 via the switching transistor T21 of the first subpixel SP1 is small, multiple protrusions are designed with an offset, for example, the first protrusion 111 and the second protrusion 112 are offset by a first predetermined distance D12 in the first direction D1, the third protrusion 113 and the fourth protrusion 114 are offset by a second predetermined distance D34 in the first direction D1, and the fifth protrusion 115 and the sixth protrusion 116 are offset by a third predetermined distance D56 in the first direction D1.

[0085] For example, in several embodiments, the first prescribedAny two of the distances D12, the third predetermined distance D56, and the fourth predetermined distance D012 may be approximately equal. For example, in some other embodiments, the third predetermined distance D56 is the first prescribed If the distance D12 is greater than and / or the third predetermined distance D56 is greater than the fourth predetermined distance D012, and / or the fourth predetermined distance D012 is the first prescribed The distance is greater than D12.

[0086] By providing the third gate G3 of the detection transistor T3 and the second gate G2 of the switching transistor T2 for multiple subpixels on both sides of the same scanning signal line body 110, and by regularly offsetting the third gate G3 of the detection transistor T3 and the second gate G2 of the switching transistor T2 for multiple subpixels by a certain distance in the first direction D1, the space on both sides of the scanning signal line body 110 can be fully utilized, reducing the length of the crossover wires for the lateral scanning signal line, further saving wiring space, improving the aperture ratio, and enabling a high PPI design for the display panel. In some exemplary embodiments of this disclosure, referring to Figures 3 and 4B, the detection signal line SL includes a line body 210, a first line projection 211, and a second line projection 212, the first line projection 211 protruding from the line body 210 toward the first subpixel SP1, and the second line projection 212 protruding from the line body 210 toward the fourth subpixel SP4.

[0087] Referring to Figure 4E, the display board further includes a first conductive connection portion 121 and a sixth conductive connection portion 126. The first conductive connection portion 121, the sixth conductive connection portion 126, the first protrusion 111, the second protrusion 112, the third protrusion 113, and the fourth protrusion 114 are located on the same layer. The first conductive connection portion 121 is located between the first protrusion 111 and the third protrusion 113 in the first direction D1, and the sixth conductive connection portion 126 is located between the second protrusion 112 and the fourth protrusion 114 in the first direction D1.

[0088] Referring to Figures 3, 4B, and 4E, the orthographic projection of the first wire projection 211 onto the base substrate 100 at least partially overlaps with the orthographic projection of the first conductive connection portion 121 onto the base substrate 100, and the first wire projection 211 is electrically connected to the first conductive connection portion 121 via the first via hole VH1. The orthographic projection of the second wire projection 212 onto the base substrate 100 at least partially overlaps with the orthographic projection of the sixth conductive connection portion 126 onto the base substrate 100, and the second wire projection 212 is electrically connected to the sixth conductive connection portion 126 via the seventh via hole VH7.

[0089] Referring to Figure 4B, the display board further includes a first conductive relay section 221 and a second conductive relay section 222, the first conductive relay section 221 and the second conductive relay section 222 being located on the same layer as the first wire projection section 211 and the second wire projection section 212. Referring to Figures 3, 4B and 4E, the orthographic projection of the first conductive relay section 221 onto the base substrate 100 at least partially overlaps with the orthographic projection of the second conductive connection section 122 onto the base substrate 100, and the first conductive relay section 221 is electrically connected to the second conductive connection section 122 via a second via hole VH2. The orthographic projection of the second conductive relay section 222 onto the base substrate 100 at least partially overlaps with the orthographic projection of the fourth conductive connection section 124 onto the base substrate 100, and the second conductive relay section 222 is electrically connected to the fourth conductive connection section 124 via an eighth via hole VH8. In some exemplary embodiments of the present disclosure, referring to Figures 3, 4C, and 4E, the orthographic projection onto the base substrate 100 of either the first conductive connection portion 121 or the first via hole VH1 at least partially overlaps with the orthographic projection onto the base substrate 100 of the portion of the third active layer ACT3 that is simultaneously used as the first pole region A113 of the first subpixel SP1's sensing transistor T31 and the second pole region A213 of the third subpixel SP3's sensing transistor T33.

[0090] Figure 5 is a partially enlarged view of the vicinity of the dashed rectangular area in Figure 3. Figure 6A is a cross-sectional view along dashed line 1 in Figure 5, and Figure 6B is a cross-sectional view along dashed line 2 in Figure 5. The orthographic projection of dashed lines 1 and 2 onto the base substrate is as follows: 2It partially overlaps with via hole VH2. Referring to Figures 3, 4C, and 6A, the third active layer ACT313 of the first subpixel SP1 on the display substrate is electrically connected to the first conductive layer 10 via the first via hole VH1 and the second via hole VH2, respectively, forming the source and drain of the sensing transistor T31 of the first subpixel SP1.

[0091] In some exemplary embodiments of the present disclosure, referring to Figure 4E, the display substrate further includes a second conductive connection portion 122, the second conductive connection portion 122, the first projection 111 and the fifth projection 115 are located on the same layer, and the second conductive connection portion 122 is located between the first projection 111 and the fifth projection 115 in a first direction D1.

[0092] Referring to Figures 3, 4A, 4C, and 4E, the display board further includes a light-shielding portion 31 located on the base board 100, and the orthographic projections of any two of the light-shielding portion 31, the second pole region A213 of the detection transistor T31 of the first subpixel SP1, and the second conductive connection portion 122 onto the base board 100 overlap at least partially, and the second pole region A213 of the detection transistor T31 of the first subpixel SP1 is electrically connected to the light-shielding portion 31 via the second conductive connection portion 122 and the second via hole VH2.

[0093] Referring to Figures 3, 4A, 4G, and 4H, the display substrate further includes a first light-emitting electrode 91 and a first light-emitting electrode via hole VHR located on the base substrate 100. Exemplarily, the first light-emitting electrode 91 includes the first light-emitting electrode 913 of the third subpixel SP3, the first light-emitting electrode via hole VHR includes the first light-emitting electrode via hole VHR3 of the third subpixel SP3, and the light-shielding portion 31 includes the light-shielding portion 313 of the third subpixel SP3. The first light-emitting electrode 913 of the third subpixel SP3 is electrically connected to the light-shielding portion 313 of the third subpixel SP3 via the first light-emitting electrode via hole VHR3 of the third subpixel SP3.

[0094] Figure 7 is a schematic plan view of the lamination of the partial light-shielding layer 30 and the active layer 40 according to some exemplary embodiments of the present disclosure.

[0095] In some exemplary embodiments of the present disclosure, referring to Figure 7, the orthographic projection of the second active layer ACT2 onto the base substrate 100 at least partially overlaps with the orthographic projection of the light-shielding portion 31 onto the base substrate. The pixel driving circuit further includes a storage capacitor Cst comprising a first electrode plate S1 and a second electrode plate S2, wherein at least a portion of the second active layer ACT2 is used as the first electrode plate S1 and at least a portion of the light-shielding portion 31 is used as the second electrode plate S2. pixels The design of the drive circuit allows, for example, the detection transistor T3 to be evenly distributed on both the upper and lower sides of the main body 110 of the scanning signal line, making it symmetrical and saving wiring space, which is advantageous for saving a large amount of space for the storage capacitor and for increasing the capacitance value of the storage capacitor.

[0096] Figure 8 is a partial plan view of a display board according to another embodiment of the present disclosure, showing the detection signal line widening section, and Figure 9 is a partial enlarged view of the area near the dashed frame at the top of Figure 8.

[0097] In some other exemplary embodiments of the present disclosure, referring to Figures 8 and 9, the detection signal line SL further includes a first widening portion 213, the width d of the first widening portion 213 in a first direction D1 being greater than the width c of the line body portion 210 in a first direction D1, and the orthographic projection of the first widening portion 213 onto the base substrate is the orthographic projection of the first plate S11 of the storage capacitor of the first subpixel SP1 onto the base substrate and the orthographic projection of the first plate S13 of the storage capacitor of the third subpixel SP3 onto the base substrate in a first direction D1. Located between the shadow and / or, and / or continuing to refer to Figure 8, the detection signal line SL further includes a second widening portion 214, the width e of the second widening portion 214 in a first direction D1 being greater than the width c of the line body portion 210 in a first direction D1, and the orthographic projection of the second widening portion 214 onto the base substrate being located in a first direction between the orthographic projection of the first plate S12 of the storage capacitor of the second subpixel SP2 onto the base substrate and the orthographic projection of the first plate S14 of the storage capacitor of the fourth subpixel SP4 onto the base substrate.

[0098] Continuing to refer to Figures 7, 8, and 9, the orthographic projection of the first widening portion 213 onto the base substrate and the orthographic projection of the first plate S11 of the storage capacitor of the first sub-pixel SP1 onto the base substrate are separated by a first separation distance a in the first direction D1, and the first plate S11 of the storage capacitor of the first sub-pixel SP1 is in the region that overlaps with the light-shielding portion 31 in the second active layer ACT21 of the first sub-pixel SP1. The orthographic projection of the first widening portion 213 onto the base substrate and the orthographic projection of the first plate S13 of the storage capacitor of the third sub-pixel SP3 onto the base substrate are separated by a second separation distance a in the first direction D1, and the first plate S13 of the storage capacitor of the third sub-pixel SP3 is in the region that overlaps with the light-shielding portion 31 in the second active layer ACT23 of the third sub-pixel SP3. In other words, the first separation distance and the second separation distance are approximately equal. And / or, the orthographic projection of the second widening portion 214 onto the base substrate and the orthographic projection of the first electrode plate S12 of the storage capacitor of the second subpixel SP2 onto the base substrate are separated by a third separation distance b in the first direction D1, where the first electrode plate S12 of the storage capacitor of the second subpixel SP2 is the region that overlaps with the light-shielding portion 31 in the second active layer ACT22 of the second subpixel SP2, and the orthographic projection of the second widening portion 214 onto the base substrate and the orthographic projection of the first electrode plate S14 of the storage capacitor of the fourth subpixel SP4 onto the base substrate are separated by a fourth separation distance b in the first direction D1, where the first electrode plate S14 of the storage capacitor of the fourth subpixel SP4 is the region that overlaps with the light-shielding portion 31 in the second active layer ACT24 of the fourth subpixel SP4, meaning that the third separation distance and the fourth separation distance are approximately equal.

[0099] For example, referring to Figures 3 and 4C, the drive transistor T11 of the first subpixel SP1 is electrically connected to the storage capacitor of the first subpixel SP1 via a fourth via hole VH4, and the storage capacitor of the first subpixel SP1 can store the drive voltage and ensure the stability of pixel driving.

[0100] In the exemplary embodiment, the distances a and b may be approximately equal, that is, any two of the first, second, third, and fourth distances are approximately equal.

[0101] In this specification, unless otherwise specified, the expression "approximately equal" may include various cases in which the ratio of the two compared values ​​is in the range of 0.8 to 1.2, for example, when the two compared values ​​are equal and the ratio of the two compared values ​​is 0.8, 0.9, 1.1, 1.2, etc.

[0102] By arranging the detection transistors of multiple subpixels horizontally, they are evenly distributed on both the upper and lower sides of the scanning signal line, and the source and drain of the detection transistors T3 of two subpixels are shared, meaning that the detection transistors T3 of multiple subpixels are symmetrical with respect to the detection signal line SL. At the same time, by adopting a widened design for the detection signal line SL in the aperture region of the two subpixels on the left and right, it is ensured that the distance from the detection signal line SL to the first gate G1 of the drive transistor T1 of each subpixel is the same, and the influence on the potential of the first gate G1 of the drive transistor T1 of each subpixel is the same. On the other hand, adopting a widened design for the detection signal line SL in the aperture region of the two subpixels on the left and right also helps to reduce the resistance of the detection signal line SL, reduce voltage drop, improve brightness uniformity of each subpixel, and improve the display effect of the display panel.

[0103] In some other exemplary embodiments of the present disclosure, referring to Figures 4E and 8, the display substrate further includes a first conductive connection portion 121, the first conductive connection portion 121, the first projection 111 and the second projection 112 located on the same layer. The orthographic projection of the first widening portion 213 onto the base substrate at least partially overlaps the orthographic projection of the first conductive connection portion 121 onto the base substrate, and the first widening portion 213 is electrically connected to the first conductive connection portion via a first via hole VH1.

[0104] Figure 10 is a schematic partial plan view of a display substrate according to some other embodiments of the present disclosure, showing the active extension portion of the third active layer, and Figure 11 is a partially enlarged view of the region near the intermediate scanning signal line in Figure 10.

[0105] In some other exemplary embodiments of the present disclosure, referring to Figures 10 and 11, the third active layer ACT3 further includes an active extended portion ACT301 extending along a direction parallel to the extending direction of the detection signal line SL from the portion of the third active layer ACT3 that is simultaneously used as the first pole region A113 of the detection transistor T31 of the first subpixel SP1 and the second pole region A213 of the detection transistor T33 of the third subpixel SP3. The orthographic projection of the active extended portion ACT301 onto the base substrate at least partially overlaps the orthographic projection of the detection signal line SL onto the base substrate. The active extended portion ACT301 is electrically connected to the first conductive connection portion 121.

[0106] Continuing to refer to Figures 10 and 11, the second active layer ACT2 includes a first portion ACT201 extending along a first direction D1, a second portion ACT202 extending along a second direction D2, and a third portion ACT203 used as the first electrode plate S1. The portion where the first portion ACT201 and the fifth protrusion 115 overlap is the channel region of the switching transistor. The second portion ACT202 connects the first portion ACT201 and the third portion ACT203, and the width f of the second portion ACT202 in the first direction D1 is greater than the width g of the first portion ACT201 in the second direction.

[0107] By arranging the detection transistors of multiple subpixels laterally, they are evenly allocated on both the upper and lower sides of the scan signal line, and the source and drain of the detection transistors T3 of two subpixels are shared, meaning that the detection transistors T3 of multiple subpixels are symmetrical with respect to the detection signal line SL. At the same time, by employing a widening design for the detection signal line SL in the two subpixel aperture regions on the left and right, it is possible to ensure that the distance from the detection signal line SL to the third gate G3 of each subpixel's detection transistor T3 is the same, and the influence on the potential of the third gate G3 of each subpixel's detection transistor T3 is the same. On the other hand, the source-drain common terminal and the detection signal line SL are connected via a first via hole VH1, where the first via hole VH1 is designed on the detection signal line SL, which saves wiring space in the first direction D1 and is advantageous for widening the width of the high-impedance second active layer ACT2, for example, the width of the second part ACT202 of the second active layer ACT2, which is advantageous for the potential input of the scanning signal line and can further improve the aperture ratio. Furthermore, the two-layer design can reduce the resistance of the detection signal line SL, reduce voltage drop, improve the brightness uniformity of each subpixel, and improve the display effect of the display panel.

[0108] Figure 12 is a schematic partial plan view of a display substrate according to another embodiment of the present disclosure.

[0109] In some other exemplary embodiments of the present disclosure, referring to Figures 4E and 12, the pixel driving circuit further includes a driving transistor T1 including a first active layer ACT1, and the display substrate further includes a fifth conductive connection 125 and a first power signal line VDD for transmitting a first power signal, wherein the fifth conductive connection 125 and the scanning signal line GL are located on the same layer, and the first power signal line VDD and the detection signal line SL are located on the same layer. One end of the fifth conductive connection portion 125 is electrically connected to the first active layer ACT1 via the fifth via hole VH5, and the other end of the fifth conductive connection portion is electrically connected to the first power signal line VDD via the sixth via hole VH6. Two subpixels located in two adjacent rows of pixel units and in the same column share the fifth conductive connection portion. For example, the second subpixel SP2 and the fifth subpixel SP5 are two subpixels located in two adjacent rows of pixel units and in the same column, and the second subpixel SP2 and the fifth subpixel SP5 can share the fifth conductive connection portion 125. This design saves wiring space, further improves the aperture ratio, and enhances the display effect of the display panel.

[0110] Figure 13 is a schematic partial cross-sectional view of a display substrate according to another embodiment of the present disclosure.

[0111] Illustratively, referring to Figure 13, the display substrate includes a semiconductor layer 40 located on a base substrate, a first conductive layer 10 located on the side of the semiconductor layer 40 away from the base substrate, a second conductive layer 20 located on the side of the first conductive layer 10 away from the base substrate, and a light-shielding layer 30 located on the side of the semiconductor layer 40 closer to the base substrate. Referring to Figures 4A, 4B, 4C, and 4E, the light-shielding portion 31 is located on the light-shielding layer 30, the first active layer ACT1, the second active layer ACT2, and the third active layer ACT3 are located on the semiconductor layer 40, the scanning signal line GL, the first conductive connection portion 121, and the second conductive connection portion 122 are located on the first conductive layer 10, and the detection signal line SL and the first power supply signal Line VDD is located in the second conductive layer 20.

[0112] Illustratively, continuing with reference to Figure 13, the display substrate further includes a pixel definition layer 50 located on the side of the second conductive layer 20 away from the base substrate for defining a plurality of pixel apertures, and the display substrate further includes a reflective electrode layer 93 located on the side of the pixel definition layer 50 away from the base substrate.

[0113] Referring to Figures 3, 4I, and 13, the pixel definition layer 50 is also used to define a plurality of slots 52, each of which is located between any adjacent pixel apertures. By having at least a portion of the reflective electrode layer 93 located within the plurality of slots 52, crosstalk between adjacent pixels can be avoided, thereby improving the stability of the display panel.

[0114] Exemplary, in some embodiments of the present disclosure, with reference to Figures 7 and 13, the display substrate further includes a first conductive portion 90 located on the side of the light-shielding layer 30 closer to the base substrate, and a second conductive portion 41 located on the semiconductor layer 40, wherein the orthographic projection of the first conductive portion 90 onto the base substrate at least partially overlaps with the orthographic projection of the pixel aperture PO onto the base substrate, and the orthographic projection of the second conductive portion 41 onto the base substrate at least partially overlaps with the orthographic projection of the pixel aperture PO onto the base substrate. The first electrode plate S1 further includes the second conductive portion 41, and the second electrode plate S2 further includes the first conductive portion 90, wherein the first conductive portion 90 is electrically connected to the light-shielding portion 30, and the first conductive portion 90 includes a transparent conductive material, such as ITO, IZO, etc.

[0115] Selectively, embodiments of the present disclosure further provide a display device including the display substrate described above. The display device includes, but is not limited to, any product or component having a display function, such as electronic paper, mobile phones, tablet computers, displays, notebook computers, digital photo frames, and navigators. The display device has the same effects as the display substrate according to the embodiments described above.

[0116] While several embodiments of the overall concept of the present disclosure have been shown and described, those skilled in the art will understand that modifications can be made to these embodiments without departing from the principles and spirit of the overall concept of the present disclosure, and that the scope of the present disclosure is limited by the claims and their equivalents.

Claims

1. A display board, Base board and A plurality of pixel units located on the base substrate, wherein at least one pixel unit includes a plurality of subpixels, and at least one subpixel includes a light-emitting element and a pixel driving circuit for driving the light-emitting element, and the plurality of subpixels of the plurality of pixel units are distributed in an array on the base substrate along a first direction and a second direction, and the plurality of pixel units where the first direction and the second direction intersect, The scanning signal line located on the base substrate includes a main body portion extending in a first direction and a plurality of protrusions extending in a second direction, The pixel driving circuit includes a detection transistor comprising a third gate and a third active layer. Multiple subpixels of at least one pixel unit include a first subpixel located at the i-th row and j-th column, and a second subpixel located at the (i+1)-th row and j-th column, where i and j are both positive integers greater than or equal to 1. The plurality of protrusions include a first protrusion and a second protrusion, the orthographic projection of the first protrusion onto the base substrate at least partially overlaps with the third active layer of the first subpixel's detection transistor, the overlapping portion of the first protrusion and the third active layer of the first subpixel's detection transistor is the third gate of the first subpixel's detection transistor, the orthographic projection of the second protrusion onto the base substrate at least partially overlaps with the third active layer of the second subpixel's detection transistor, the overlapping portion of the second protrusion and the third active layer of the second subpixel's detection transistor is the third gate of the second subpixel's detection transistor, The third gate of the detection transistor for the first subpixel and the third gate of the detection transistor for the second subpixel are located on opposite sides of the main body of the same scanning signal line in the second direction. A display board characterized by the following features.

2. Multiple subpixels of at least one pixel unit further include a third subpixel located in the i-th row and j+1-th column, and a fourth subpixel located in the i+1-th row and j+1-th column, The plurality of protrusions further include a third protrusion and a fourth protrusion, wherein the orthographic projection of the third protrusion onto the base substrate at least partially overlaps with the third active layer of the detection transistor of the third subpixel, and the overlapping portion of the third protrusion and the third active layer of the detection transistor of the third subpixel is the third gate of the detection transistor of the third subpixel; the orthographic projection of the fourth protrusion onto the base substrate at least partially overlaps with the third active layer of the detection transistor of the fourth subpixel, and the overlapping portion of the fourth protrusion and the third active layer of the detection transistor of the fourth subpixel is the third gate of the detection transistor of the fourth subpixel. The third gate of the detection transistor for the third subpixel and the third gate of the detection transistor for the fourth subpixel are located on opposite sides of the main body of the same scanning signal line in the second direction. The display board according to feature 1.

3. The display board further includes detection signal lines extending along a second direction, and these detection signal lines are used to supply detection signals to the pixel driving circuit. The third gate of the detection transistor for the first subpixel and the third gate of the detection transistor for the third subpixel are located on opposite sides of the same detection signal line in the first direction, and / or the third gate of the detection transistor for the second subpixel and the third gate of the detection transistor for the fourth subpixel are located on opposite sides of the same detection signal line in the first direction. The display board according to feature 2.

4. The third active layer of the sensing transistor further includes a channel region, a first pole region, and a second pole region. The orthographic projection of the channel region of the third active layer onto the base substrate at least partially overlaps with the orthographic projection of the third gate onto the base substrate, and the first pole region and the second pole region are located on both sides of the channel region of the third active layer in the first direction, The third active layer is used simultaneously as the first pole region of the first subpixel and the second pole region of the third subpixel, with at least a portion located between the channel region of the first subpixel detection transistor and the channel region of the third subpixel detection transistor, and / or as the first pole region of the second subpixel detection transistor and the second pole region of the fourth subpixel detection transistor, with at least a portion located between the channel region of the second subpixel detection transistor and the channel region of the fourth subpixel detection transistor. The display board according to claim 2 or 3, characterized in that it is a display board according to the feature described above.

5. The third gate of the detection transistor for the first subpixel and the third gate of the detection transistor for the third subpixel are symmetric with respect to a first center line, the first center line is a virtual straight line passing through the center of the detection line and extending along the second direction, and / or The third gate of the detection transistor for the second subpixel and the third gate of the detection transistor for the fourth subpixel are symmetrical with respect to the first center line. A display board according to any one of claims 2 to 4.

6. The third active layer of the detection transistor of the first subpixel and the third active layer of the detection transistor of the third subpixel are connected to each other and extend in the first direction. A display board according to any one of claims 2 to 5.

7. The first protrusion and the second protrusion each protrude in opposite directions in a second direction from the same scanning signal line body, and the first protrusion and the second protrusion are offset by a first predetermined distance in the first direction. The third and fourth protrusions each protrude in opposite directions in a second direction from the same scanning signal line body, and the third and fourth protrusions are offset by a second predetermined distance in a first direction. A display board according to any one of claims 2 to 6.

8. The pixel driving circuit further includes a switching transistor, the switching transistor including a second gate and a second active layer. The plurality of protrusions include a fifth protrusion and a sixth protrusion, the orthogonal projection of the fifth protrusion onto the base substrate at least partially overlaps with the second active layer of the switching transistor of the first subpixel, the overlapping portion of the fifth protrusion and the second active layer of the switching transistor of the first subpixel is the second gate of the switching transistor of the first subpixel, the orthogonal projection of the sixth protrusion onto the base substrate at least partially overlaps with the second active layer of the switching transistor of the second subpixel, the overlapping portion of the sixth protrusion and the second active layer of the switching transistor of the second subpixel is the second gate of the switching transistor of the second subpixel, The second gate of the switching transistor of the first subpixel and the second gate of the switching transistor of the second subpixel are located on opposite sides of the main body of the same scanning signal line in the second direction. A display board according to any one of claims 2 to 7.

9. The fifth and sixth protrusions each protrude in opposite directions in a second direction from the same scanning signal line body, and the fifth and sixth protrusions are offset by a third predetermined distance in a first direction. The display board according to feature 8.

10. Any two of the first predetermined distance, the second predetermined distance, and the third predetermined distance are approximately equal. The display board according to feature 9.

11. The detection signal line includes a line body and a first line projection that protrudes from the line body toward the first subpixel. The display substrate further includes a first conductive connection portion, the first conductive connection portion, the first protrusion, and the third protrusion are located on the same layer, and the first conductive connection portion is located between the first protrusion and the third protrusion in a first direction. The orthographic projection of the first wire projection onto the base substrate at least partially overlaps with the orthographic projection of the first conductive connection portion onto the base substrate, and the first wire projection is electrically connected to the first conductive connection portion via the first via hole. A display board according to any one of claims 2 to 10.

12. The orthographic projection onto the base substrate of either the first conductive connection portion or the first via hole at least partially overlaps with the orthographic projection onto the base substrate of the portion of the third active layer that is simultaneously used as the first pole region of the detection transistor for the first subpixel and the second pole region of the detection transistor for the third subpixel. The display board according to feature 11.

13. The present invention further comprises a second conductive connection portion, wherein the second conductive connection portion, the first protrusion, and the fifth protrusion are located in the same layer, and the second conductive connection portion is located between the first protrusion and the fifth protrusion in the first direction. The display substrate further includes a light-shielding portion located on the base substrate, wherein the orthographic projections onto the base substrate of any two of the following—the light-shielding portion, the second pole region of the detection transistor of the first subpixel, and the second conductive connection portion—at least partially overlap, and the second pole region of the detection transistor of the first subpixel is electrically connected to the light-shielding portion via the second conductive connection portion and the second via hole. The display board according to feature 12.

14. The orthographic projection of the second active layer onto the base substrate overlaps at least partially with the orthographic projection of the light-shielding portion onto the base substrate. The pixel driving circuit further includes a storage capacitor, the storage capacitor includes a first plate and a second plate, at least a portion of the second active layer is used as the first plate, and at least a portion of the light-shielding portion is used as the second plate. The display board according to feature 13.

15. The detection signal line further includes a first widening portion whose width in a first direction is greater than the width of the line body in a first direction, and the orthographic projection of the first widening portion onto the base substrate is located in a first direction between the orthographic projection of the first plate of the storage capacitor of the first subpixel onto the base substrate and the orthographic projection of the first plate of the storage capacitor of the third subpixel onto the base substrate, and / or The detection signal line further includes a second widening portion whose width in the first direction is greater than the width of the line body in the first direction, and the orthographic projection of the second widening portion onto the base substrate is located in the first direction between the orthographic projection of the first plate of the storage capacitor of the second subpixel onto the base substrate and the orthographic projection of the first plate of the storage capacitor of the fourth subpixel onto the base substrate. The display board according to feature 14.

16. The orthographic projection of the first widening portion onto the base substrate and the orthographic projection of the first plate of the storage capacitor of the first subpixel onto the base substrate are separated by a first separation distance in the first direction, and the orthographic projection of the first widening portion onto the base substrate and the orthographic projection of the first plate of the storage capacitor of the third subpixel onto the base substrate are separated by a second separation distance in the first direction, and the first separation distance and the second separation distance are approximately equal, and / or The orthographic projection of the second widening portion onto the base substrate and the orthographic projection of the first electrode plate of the storage capacitor of the second subpixel onto the base substrate are separated by a third separation distance in the first direction, and the orthographic projection of the second widening portion onto the base substrate and the orthographic projection of the first electrode plate of the storage capacitor of the fourth subpixel onto the base substrate are separated by a fourth separation distance in the first direction, and the third separation distance and the fourth separation distance are approximately equal. The display board according to feature 15.

17. The display substrate further includes a first conductive connection portion, and the first conductive connection portion, the first protrusion, and the second protrusion are located on the same layer. The orthographic projection of the first widened portion onto the base substrate at least partially overlaps with the orthographic projection of the first conductive connection portion onto the base substrate, and the first widened portion is electrically connected to the first conductive connection portion via the first via hole. The display board according to claim 15 or 16, characterized by the features described herein.

18. The third active layer further includes an active extension portion that extends in a direction parallel to the direction of extension of the detection signal line from the portion of the third active layer that is simultaneously used as the first pole region of the detection transistor of the first subpixel and the second pole region of the detection transistor of the third subpixel, The orthographic projection of the active extension onto the base substrate overlaps at least partially with the orthographic projection of the detection signal line onto the base substrate, and The active extension portion is electrically connected to the first conductive connection portion. The display board according to feature 17.

19. The second active layer includes a first portion extending in a first direction, a second portion extending in a second direction, and a third portion used as the first electrode plate, wherein the portion where the first portion and the fifth protrusion overlap is the channel region of the switching transistor, and the second portion connects the first portion and the third portion. The width of the second portion in the first direction is greater than the width of the first portion in the second direction. The display board according to feature 18.

20. The pixel driving circuit further includes a driving transistor which includes a first active layer, The display board further includes a fifth conductive connection and a first power signal line for transmitting a first power signal, wherein the fifth conductive connection and the scanning signal line are located on the same layer, and the first power signal line and the detection signal line are located on the same layer. One end of the fifth conductive connection is electrically connected to the first active layer via a fifth via hole, and the other end of the fifth conductive connection is electrically connected to the first power signal line via a sixth via hole. Two subpixels located in adjacent rows of pixel units and in the same column share the fifth conductive connection portion. A display board according to any one of claims 1 to 19.

21. The aforementioned display board is A semiconductor layer located on the base substrate, A first conductive layer located on the side of the semiconductor layer away from the base substrate, A second conductive layer located on the side of the first conductive layer away from the base substrate, The semiconductor layer includes a light-shielding layer located on the side closer to the base substrate, The light-shielding portion is located in the light-shielding layer, the first active layer, the second active layer, and the third active layer are located in the semiconductor layer, the scanning signal line, the first conductive connection portion, and the second conductive connection portion are located in the first conductive layer, and the detection signal line and the first power line are located in the second conductive layer. A display board according to any one of claims 13 to 19.

22. The second conductive layer further includes a pixel definition layer located on the side away from the base substrate for defining a plurality of pixel apertures, and a reflective electrode layer located on the side away from the base substrate of the pixel definition layer, The pixel definition layer further defines a plurality of slots, each of which is located between any two adjacent pixel apertures, and at least a portion of the reflective electrode layer is located in the plurality of slots. The display board according to feature 21.

23. The light-shielding layer further includes a first conductive portion located on the side closer to the base substrate and a second conductive portion located on the semiconductor layer. The orthographic projection of the first conductive portion onto the base substrate at least partially overlaps with the orthographic projection of the pixel aperture onto the base substrate, and the orthographic projection of the second conductive portion onto the base substrate at least partially overlaps with the orthographic projection of the pixel aperture onto the base substrate. The first electrode plate further includes the second conductive portion, the second electrode plate further includes the first conductive portion, the first conductive portion is electrically connected to the light-shielding portion, and the first conductive portion includes a transparent conductive material. The display board according to claim 22.

24. The second conductive layer further includes a plurality of data lines, the plurality of data lines including a first data line, a second data line, a third data line and a fourth data line, wherein the first data line is electrically connected to the first pole of the switching transistor of the first subpixel, the second data line is electrically connected to the first pole of the switching transistor of the second subpixel, the third data line is electrically connected to the first pole of the switching transistor of the third subpixel, and the fourth data line is electrically connected to the first pole of the switching transistor of the fourth subpixel. The first and second data lines are located on one side of the pixel drive circuit of the pixel unit in the first direction, the third and fourth data lines are located on the other side of the pixel drive circuit of the pixel unit in the first direction, the first and second data lines are spaced apart in the first direction, the first data line is located on the side of the second data line away from the pixel drive circuit of the pixel unit, and the fourth data line is located on the side of the third data line away from the pixel drive circuit of the pixel unit. A display board according to any one of claims 8 to 10.

25. A display board according to any one of claims 1 to 24, A display device characterized by the following features.

Images