Method and structure for high-strength asymmetric dielectrics in hybrid coupling

Abstract

A first structure for semiconductor devices having a dielectric film on its upper surface can be used to form a semiconductor device consisting of a hybrid junction structure in which the dielectric surface area and the pitch of the metal studs are reduced. The upper surface of the dielectric film of the first structure can be hybrid-junctioned to a dielectric layer of the second structure. The dielectric film of the first structure and the dielectric layer of the second structure can be made of different dielectrics. In this way, the hybrid junction of the two structures includes a hybrid junction of asymmetric dielectrics.

Description

Technical Field

[0001] Cross-Reference to Related Applications

[0001] This application claims the benefit and priority of U.S. Non-Provisional Application No. 18 / 460,189, entitled "METHODS AND STRUCTURES FOR HIGH STRENGTH ASYMMETRIC DIELECTRIC IN HYBRID BONDING", filed on September 1, 2023, the content of which is incorporated herein by reference in its entirety for all purposes.

[0002] Technical Field

[0002] The present technology relates to semiconductor systems, processes, and apparatuses. Specifically, the present technology relates to processes and semiconductor devices for hybrid bonding. Background Art

[0003]

[0003] Hybrid bonding, which may also be referred to as heterogeneous integration, is a semiconductor manufacturing technique that enables further miniaturization of three-dimensional semiconductor device manufacturing processes associated with advanced node technologies requiring heterogeneous integration. Hybrid bonding requires creating strong bonds between dies, wafers, and / or substrates without the need for adhesives or interconnect materials. However, heterogeneous integration techniques can be limited by pitch scaling. As the desired pitch is reduced, the available dielectric surface area at the contact bonds of hybrid bonding is also reduced. Accordingly, hybrid bonding systems may require that most of the bonding surface between dies is dielectric. As the desired pitch decreases, standard hybrid bonding techniques and systems may fail to adequately provide sufficient bonding strength.

[0004]

[0004] Accordingly, with pitch scaling, there is a need for improved systems and methods that can be used to improve systems for hybrid bonding. The present technology addresses this need and other needs. Summary of the Invention

[0005]

[0005] In some embodiments, the semiconductor device for the hybrid junction may include a first structure comprising: a first metal layer covering a first substrate; a first dielectric layer covering the first metal layer and defining a set of one or more feature portions recessed in the first dielectric layer; a dielectric film covering the first dielectric layer, comprising the first dielectric; and a first copper-containing material deposited inside the set of one or more feature portions; a second metal layer covering a second substrate; and a second metal layer covering the second metal layer. The present invention may include a second dielectric layer defining a second set of one or more feature portions recessed in a dielectric layer, the second dielectric layer being made of a second dielectric material different from that of the first dielectric; and a second structure which may include a second copper-containing material deposited inside the second set of one or more feature portions; the dielectric film of the first structure being hybrid-bonded to the second dielectric layer of the second structure, and the first copper-containing material of the first structure being in contact with the second copper-containing material of the second structure.

[0006]

[0006] In some embodiments, a method for forming a semiconductor device includes forming a first structure, which may include: forming a first metal layer on a first substrate; forming a first dielectric layer on the first metal layer; forming a dielectric film made of a first dielectric on the first dielectric layer; etching trenches in the dielectric film and the first dielectric layer that extend downward from the upper surface of the dielectric film to at least the upper surface of the first metal layer; filling the trenches with a first copper-containing material; and bringing the first structure into contact with a second structure, wherein the second structure covers a second substrate. Bringing a first structure into contact with a second structure, which may include a metal layer; a second dielectric layer covering the second metal layer and defining a second set of one or more feature portions in the second dielectric layer, the second dielectric layer being made of a second dielectric material different from the first dielectric; and a second copper-containing material deposited inside the second set of one or more feature portions; and joining a first structure to a second structure, which may include a dielectric film of the first structure being hybrid-bonded to the second dielectric layer of the second structure, and a first copper-containing material of the first structure in contact with the second copper-containing material of the second structure.

[0007]

[0007] In some embodiments, a method for forming a semiconductor device is to form a first structure, which may include forming a first metal layer on a first substrate; forming a first dielectric layer on the first metal layer; etching trenches in the first dielectric layer that extend downward from the upper surface of the first dielectric layer to at least the upper surface of the first metal layer; filling the trenches with a first copper-containing material; and selectively depositing a dielectric film on the first structure, wherein the dielectric film covers the first dielectric layer but not the first copper-containing material, and the dielectric film is composed of a first dielectric; and forming a second structure on the first structure Contacting the first structure to the second structure, wherein the second structure may include: a second metal layer covering the second substrate; a second dielectric layer covering the second metal layer and defining a second set of one or more feature portions in the second dielectric layer, the second dielectric layer being made of a second dielectric material different from the first dielectric; and a second copper-containing material deposited inside the second set of one or more feature portions; and joining the first structure to the second structure, wherein the dielectric film of the first structure is hybrid-bonded to the second dielectric layer of the second structure, and the first copper-containing material of the first structure is in contact with the second copper-containing material of the second structure.

[0008]

[0008] In any embodiment, all of the following features can be implemented in any combination without limitation. The first dielectric layer may be a second dielectric or may contain a second dielectric. The first dielectric may contain silicon carbonitride and the second dielectric may contain silicon oxide. The first dielectric may contain silicon oxynitride and the second dielectric may contain silicon oxide. The dielectric film may have a thickness of 5 nm. The first copper-containing material may be characterized by a dish shape with a dish depth of about 1 nm or less. A method for forming a semiconductor device may also include contacting the first structure with one or more slurries and one or more platens, the one or more slurries and one or more platens removing a portion of the first copper-containing material and a second portion of the dielectric film. A method for forming a semiconductor device may also include forming a liner in a trench, filling the trench with the first copper-containing material, including covering the liner with the first copper-containing material. A method for forming a semiconductor device may also include contacting a first structure with one or more slurries and one or more platens, the one or more slurries and one or more platens removing a portion of the first copper-containing material and a second portion of the first dielectric layer, and contacting the first structure with one or more slurries causes the first dielectric layer to recede by a distance of about 5 nm or more from the top surface of the first copper-containing material. Etching trenches in the dielectric film and the first dielectric layer may include etching trenches in the dielectric film using chlorine etching. Etching trenches in the dielectric film and the first dielectric layer may also include etching trenches in the dielectric film and the first dielectric layer using multi-material etching, the multi-material etching may include two or more of chlorine etching, fluorine etching, oxygen-plasma etching, and fluorine-oxygen etching.Forming a first metal layer and a first dielectric layer can be carried out in a first chamber, etching trenches into the dielectric film and the first dielectric layer can be carried out in a second chamber, and the first structure can be moved from the first chamber to the second chamber without exposing the first substrate to the external atmosphere. Contacting the first structure with one or more slurries and one or more platens can cause it to recede into the trenches below the upper surface of the dielectric film in the first copper-containing material by a distance of about 1 nm or less. The first dielectric may contain silicon oxide, and the second dielectric may contain silicon oxynitride. The first dielectric may contain silicon oxide, and the second dielectric may contain silicon carbonitride. The first dielectric layer may be a third dielectric or may contain a third dielectric, the third dielectric being a different material from the first and second dielectrics. Depositing a polymer may involve depositing a long-chain polymer by vapor deposition. [Brief explanation of the drawing]

[0009]

[0009] The properties and advantages of various embodiments can be further understood by referring to the remainder of this specification and the drawings, in which the same reference numerals are used throughout multiple drawings to refer to similar components. In some cases, a sublabel is associated with a single reference numeral indicating one of several similar components. Where a reference numeral is used without specifying an existing sublabel, it is intended to refer to all such multiple similar components.

[0010] [Figure 1]

[0010] This is a top view of one embodiment of a processing system comprising a deposition chamber, an etching chamber, a baking chamber, and a curing chamber, which can be included or configured by several embodiments. [Figure 2]

[0011] The steps of a semiconductor processing method according to several embodiments are shown. [Figure 3A-B]

[0012] Figures 3A and 3B are schematic cross-sectional views illustrating some embodiments of structures that include or are treated with material layers. [Figure 3C-D] Figures 3C and 3D are schematic cross-sectional views illustrating some embodiments of structures that include or are treated with material layers. [Figure 4]

[0013] The steps of a semiconductor processing method according to several embodiments are shown. [Figure 5A-B]

[0014] Figures 5A and 5B are schematic cross-sectional views illustrating some embodiments of structures that include or are treated with material layers. [Figure 5C-D] Figures 5C and 5D are schematic cross-sectional views illustrating some embodiments of structures that include or are treated with material layers. [Figure 5E] Figure 5E is an illustrative schematic cross-sectional view of a structure containing or being treated with a material layer, according to several embodiments. [Figure 6]

[0015] The steps of a semiconductor processing method according to several embodiments are shown. [Figure 7]

[0016] Figures 7A to 7E are schematic cross-sectional views illustrating some embodiments of structures that include or are treated with material layers. [Figure 8]

[0017] The steps of a semiconductor processing method according to several embodiments are shown. [Figure 9A-B]

[0018] Figures 9A and 9B are schematic cross-sectional views illustrating some embodiments of structures that include or are processed with material layers. [Figure 9C-E] Figures 9C-9E are schematic cross-sectional views illustrating some embodiments of structures that include or are treated with material layers. [Figure 9F-H] Figures 9F to 9H are schematic cross-sectional views illustrating some embodiments of structures that include or are treated with material layers. [Modes for carrying out the invention]

[0011]

[0019] A first structure for a semiconductor device having a dielectric film on the upper surface of the structure can be used to form a semiconductor device consisting of a hybrid junction structure in which the dielectric surface area and the pitch of the metal studs are reduced. The semiconductor device can be formed by hybrid junctioning the dielectric film of the first structure to the upper dielectric of a second structure, where the dielectric film and the upper dielectric are different dielectrics. In this way, the first structure and the second structure have asymmetric dielectrics on their respective upper surfaces. The hybrid junction between asymmetric dielectrics can have increased junction strength compared to the hybrid junction of symmetric dielectrics.

[0012]

[0020] Conventional hybrid bonding systems can provide sufficient bonding strength to bond two wafers under certain conditions, but conventional systems may have limitations on the pitch, which may be limited to a predetermined minimum size and / or on the wafer surface, which may be limited to a minimum percentage of the dielectric surface area. Therefore, on the wafer, the metal pad is limited to a predetermined percentage of the wafer surface, and consequently, the metal density is limited. For example, the pitch may have a minimum size of 1 micron, and the dielectric bonding surface may be approximately 80% or more of the bonding surface between wafers. This technology overcomes these problems associated with conventional hybrid bonding systems by increasing the bonding strength between the dielectrics of the die. By hybrid bonding asymmetric dielectrics, the increased bonding strength during the hybrid bonding process can enable a reduced pitch and a higher density of metal pads between wafers.

[0013]

[0021] In summary, hybrid bonding is a semiconductor manufacturing technique that combines the advantages of both direct bonding and traditional bonding methods. This enables the integration of dissimilar materials at the molecular level, potentially eliminating the need for metal interconnects and facilitating the development of advanced semiconductor devices with improved performance, functionality, and miniaturization. Hybrid bonding is particularly useful for the fabrication of three-dimensional semiconductor devices.

[0014]

[0022] When a system consisting of two wafers (dies and substrates can also be used) is bonded to each other via hybrid bonding, the top dielectric of the wafer is first processed to form a reactive layer through surface activation. The top dielectrics can then be brought into contact with each other and bonded, for example, by spontaneous hydrophilic oxide-oxide bonding. Once the top dielectrics are bonded, the metal pads of each wafer will be separated by a dishing gap. The system can then be annealed such that the metal pads of each wafer thermally expand and connect to each other, during which the top dielectric remains substantially the same size compared to the metal. When annealing is completed, the wafers are bonded via hybrid bonding.

[0015]

[0023] The remaining disclosure conventionally identifies specific hybrid bonding processes that utilize the disclosed technology, but it will be readily understood that the systems and methods are equally applicable to various other processes that may be performed in the described chamber. Therefore, the present technology should not be considered limited to use only with the described etching or deposition processes. In the present disclosure, one possible system that can be used in the present technology is described before describing systems and methods, or exemplary process sequences according to some embodiments of the present technology. It should be understood that the technology is not limited to the described apparatus, and the described processes may be performed in any number of processing chambers and systems.

[0016]

[0024] FIG. 1 is a top view of one embodiment of a processing system 100 comprising a deposition chamber, an etching chamber, a baking chamber, and a curing chamber that can be included in or configured in accordance with some embodiments of the present technology. In the figure, a pair of front-opening integrated pods 102 supply substrates of various sizes that are received by a robotic arm 104 and positioned in a low-pressure holding area 106, and the substrates are then positioned in one of the substrate processing chambers 108a-f positioned at tandem sections 109a-c. A second robotic arm 110 may be used to transport substrate wafers from the holding area 106 to and from the substrate processing chambers 108a-f. Each of the substrate processing chambers 108a-f can be equipped to perform several substrate processing steps, including cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, annealing, plasma processing, degassing, orientation, and other substrate processes, in addition to the dry etching processes described herein.

[0017]

[0025] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching material films on a substrate or wafer. In one configuration, two pairs of processing chambers, e.g., 108c-d and 108e-f, can be used to deposit material onto the substrate, and a third pair of processing chambers, e.g., 108a-b, can be used to cure, anneal, or process the deposited film. In another configuration, all three pairs of chambers, e.g., 108a-f, may be configured to deposit and cure films onto the substrate. Any one or more of the processes described may be performed in additional chambers separated from the manufacturing system shown in different embodiments. Further configurations of deposition chambers, etching chambers, annealing chambers, and curing chambers for material films will be considered by system 100. In addition, any number of other processing systems may be utilized in this technology, which may incorporate chambers for performing any of the specific steps. In some embodiments, a chamber system that can provide access to multiple processing chambers while maintaining a vacuum environment in various sections such as the holding area and transport area may enable the execution of processes in multiple chambers while maintaining a specific vacuum environment between separate processes.

[0018]

[0026] Structures according to several embodiments of the Art can be generated using System 100, or more specifically, a chamber incorporated into System 100 or another processing system. Figure 2 shows an exemplary step flow diagram of Method 200 for forming a semiconductor device 300 for a hybrid bond that enables pitch reduction and stronger bond strength, according to several embodiments of the Art. Method 200 may be carried out in various processing chambers in which the process can be performed, for example, a chamber incorporated into System 100 as described above. Method 200 may include one or more steps prior to the commencement of Method 200, including front-end processing, deposition, etching, polishing, cleaning, or any other optional steps that may be performed before the described steps. Method 200 may include several optional steps that may or may not be specifically associated with some embodiments of the method according to embodiments of the Art. Method 200 describes the steps schematically shown in Figures 3A-3D, and the description thereof is provided together with the steps of Method 200. Please understand that the figure is only a partial schematic and that the substrate 302 may include any number of additional material and feature portions having various characteristics and configurations as shown.

[0019]

[0027] It should be understood that the specific steps shown in Figure 2 provide a particular method for forming a semiconductor device 300 for a hybrid junction according to various embodiments. Other sequences of steps may also be carried out according to alternative embodiments. For example, in alternative embodiments, the steps described above may be carried out in a different order. Furthermore, the individual steps shown in Figure 2 may include a plurality of substeps that can be carried out in various sequences suitable for the individual step. Furthermore, additional steps may be added or removed depending on the particular application. Many variations, modifications, and alternatives are also included within the scope of this disclosure.

[0020]

[0028] Figures 3A–3D show progressive structures for forming a semiconductor device 300 for a hybrid junction according to several embodiments. The flow chart of method 200 describes the steps schematically shown in Figures 3A–3D, and its description is provided in conjunction with the steps of this method. It should be understood that the figures are only partial schematic diagrams with limited details, and that in some embodiments the substrate may include any number of semiconductor sections having the illustrated configuration as well as other structural configurations that may benefit from any of the embodiments of this art.

[0021]

[0029] In step 202, the method 200 of the flow diagram for forming the first structure 301 may include forming a metal layer 304 on a substrate 302. As shown in Figure 3A, the structure 300 may include a substrate 302. In various embodiments, the substrate 302 may have a substantially flat surface plane or a non-uniform surface. The substrate 302 may be made of materials such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, silicon-on-insulator, carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, or sapphire. The substrate 426 may have various dimensions, such as wafers with a diameter of 200 or 300 mm, and rectangular or square panels. The substrate 302 may be deposited inside the processing area of ​​a semiconductor processing chamber. Although shown as a planar substrate, substrate 302 is included solely to represent the underlying structure, which may include any number of layers or features on a wafer or other substrate, and the structure described later may be formed on top of it.

[0022]

[0030] As shown in Figure 3A, the first structure 301 may include a metal layer 304. The metal layer 304 can include various integrated circuits. For example, the integrated circuit can be formed using techniques such as CMOS, NMOS, or any other suitable integrated circuit technique. Thus, the metal layer 304 can include various layers of metal, oxide, and semiconductor. The metal used in the metal layer can include copper or any other highly conductive metal. Although copper is usually described herein, it should be understood that any number of conductive metal materials may be used in embodiments of this technology, and that this technology should not be limited to any particular conductive metal material.

[0023]

[0031] In some embodiments, the layers described herein (e.g., substrate 302, metal layer 304, and other layers described herein, e.g., barrier film 306, dielectric layer 308, and dielectric film 310) can overlap each other directly, one above the other, such that the first layer covers the second layer. For example, the metal layer 304 can directly cover the substrate 302 without any intervening layers. In some embodiments, the layers described herein can have layers between them. For example, the metal layer 304 can cover an intervening layer covering the substrate 302. Furthermore, when forming the layers, any process for forming or depositing the material can be used. For example, chemical vapor deposition (CVD) can be used in some embodiments, and atomic layer deposition (ALD) can be used in other embodiments. Details relating to specific layers and / or materials are also described herein.

[0024]

[0032] Step 204, the method 200 of the flow diagram for forming the first structure 301, may include forming a dielectric layer 308 on the metal layer 304. As shown in Figure 3A, the dielectric layer 308 may include one or more layers of dielectric material. Exemplary dielectrics may include silicon oxide, tetraethyl orthosilicate (also known as TEOS or TeOs), silicon carbonitride (SiCN), silicon oxynitride (SiON), or any other type of dielectric material. In some embodiments, the dielectric layer 308 may be TEOS. In some embodiments, the dielectric layer 308 may be silicon oxide. In some embodiments, the dielectric layer 308 may be silicon carbonitride (SiCN). In some embodiments, the dielectric layer 308 may be silicon oxynitride (SiON). The dielectric layer 308 may also be called an oxide layer.

[0025]

[0033] In some embodiments, the first structure 301 may include a barrier film 306 between the dielectric layer 308 and the metal layer 304. The barrier film 306 has a low dielectric constant to reduce the dielectric constant of the copper damascene structure, enabling faster and stronger devices to be achieved. Some barrier films may have a dielectric constant of less than 5 or possibly lower. Exemplary barrier films include silicon nitride films and low dielectric constant barrier films such as BLoK (Si-CH compound) or N-BLoK (Si-CHN compound) developed by the applicant. The barrier film 306 may also be called a capping layer for the metal layer 304.

[0026]

[0034] In step 206, the method 200 of the flow diagram for forming the first structure 301 may include forming a dielectric film 310 on a dielectric layer 308. As shown in Figure 3A, the structure 300 may include a dielectric film 310. The dielectric film 310 may be a different dielectric from the dielectric layer 308 below it. In some embodiments, the dielectric film 310 may be a different dielectric from the material of the top layer of the dielectric layer 308. For example, referring to Figure 3A, the dielectric film 310 may be a different dielectric from the dielectric layer 308. In some embodiments, the dielectric layer 308 may be silicon oxide (SiO2) and the dielectric film 310 may be silicon carbonitride (SiCN). In some embodiments, the dielectric layer 308 may be silicon oxide (SiO2) and the dielectric film 310 may be silicon oxynitride (SiON). In some embodiments, the dielectric layer 308 may be silicon carbonitride (SiCN) and the dielectric film 310 may be silicon oxide (SiO2). In some embodiments, the dielectric layer 308 can be silicon oxynitride (SiON), and the dielectric film 310 can be silicon oxide (SiO2). Tetraethyl orthosilicate (TeOs) can also be used in place of silicon oxide (SiO2) in the above combinations. In some embodiments, the dielectric film 310 can be a metal oxide or other type of oxide. For example, the dielectric film 310 can be aluminum oxide (Al2O3), titanium oxide (TiO2), strontium titanate (SrTiO3), zirconium oxide (ZrO2), hafnium oxide (also called hafnium(IV) oxide / HfO2), hafnium silicate (also called hafnium(IV) silicate / HfSiO4), lanthanum oxide (La2O3), yttrium oxide (also called yttrium(III) oxide / Y2O3), and lanthanum aluminate (LaAlO3). In some embodiments, the dielectric film 310, which is a metal oxide or other type of oxide, can be paired with a dielectric layer 308 of silicon oxide, tetraethyl orthosilicate, silicon carbonitride, and / or silicon oxynitride.Metal oxides and other oxides may require special final treatment and / or special etching due to their chemical properties compared to more common materials such as silicon dioxide.

[0027]

[0035] In some embodiments, the formation of the dielectric film 310 can be carried out in a different chamber of the system 100 than the formation of the dielectric layer 308. In some embodiments, the formation of each layer can be carried out in separate chambers. In some embodiments, the formation of the dielectric layer 308, the metal layer 304, and / or the substrate 302 can be carried out in a single chamber.

[0028]

[0036] In some embodiments, forming the dielectric film 310 may involve depositing a dielectric material via atomic layer deposition. Depositing the dielectric material may involve contacting a first structure 301 with a hydrogen-containing precursor. The first structure 301 may be contacted with the hydrogen-containing precursor to hydroxylate the surface of the dielectric layer 308. By hydroxylating the surface of the dielectric layer 308, a surface-activated layer can be formed on the dielectric layer 308 such that hydrogen atoms are formed in positions outside the lattice of the dielectric layer 308. The hydrogen-containing precursor may be contacted with the first structure via any suitable means, such as CVD plasma-enhanced CVD and ALD.

[0029]

[0037] Once the surface of the dielectric layer 308 is activated and a surface activation layer is formed, a precursor can be applied to the first structure 301 to form a dielectric film 310. In some embodiments, the structure 301 can be in contact with one or more precursors. The precursor can be reacted with the surface of the surface activation layer of the dielectric layer 308 to deposit an atomic layer of material, such as a dielectric. Similar to general ALD processes, the first structure 301 can be in contact with a first precursor, then a second precursor (or any number of precursors), and by alternately contacting the first precursor and the second precursor (or any number of precursors), an atomic layer of dielectric material can be deposited to form a dielectric film 310. One or more precursors 718 can be selected to produce a specific dielectric film 310 on the surface of the dielectric layer 308. For example, in an ALD process for depositing aluminum oxide, a trimethylaluminum precursor and water can be used alternately. Any suitable combination of precursors can be used.

[0030]

[0038] In embodiments, following step 206, a determination may be made as to whether the target thickness of the dielectric film 310 has been achieved. If the target thickness of the dielectric film 310 has not been achieved, another ALD cycle may be performed. An exemplary range of target thicknesses for stopping further cycles of forming the dielectric film 710 includes about 10 nm or less. Another exemplary thickness range may include even smaller thicknesses including about 9.5 nm or less, about 9.0 nm or less, about 8.5 nm or less, about 8.0 nm or less, about 7.5 nm or less, about 7.0 nm or less, about 6.5 nm or less, about 6.0 nm or less, about 5.5 nm or less, about 5.0 nm or less, about 4.5 nm or less, about 4.0 nm or less, about 3.5 nm or less, about 3.0 nm or less, about 2.5 nm or less, about 2.0 nm or less, about 1.5 nm or less, about 1.0 nm or less, about 0.5 nm or less, or any percentage of the above numbers.

[0031]

[0039] In step 208, the method 200 of the flow diagram for forming the first structure 301 may include etching feature portions into the dielectric layer 308, the dielectric film 310, and, where applicable, the barrier film 306. The feature portions etched into the dielectric layer 308 and the dielectric film 310 may include trenches, openings, vias, or any other structures useful in semiconductor processing. As shown in Figure 3B, the structure 300 may include trenches 320 in the dielectric film 310 and the dielectric layer 308. In some embodiments, the trenches 320 may extend downward from the upper surface of the dielectric film 310 to at least the upper surface of the metal layer 304. Although only four feature portions are shown in the figure, it should be understood that according to embodiments of the art, the exemplary structure may include any number of feature portions defined along the structure.

[0032]

[0040] The etching solution used to etch the feature portions in the dielectric layer 308, the dielectric film 310, and, where applicable, the barrier film 306, can include various semiconductor etching processes, such as chlorine, fluorine, oxygen plasma, or fluorine-oxygen, which are solutions or plasmas. In some embodiments, the etching solution can be applied at once. In some embodiments, multiple etching solutions can be combined to perform multi-material etching. The etching solution for the dielectric film 310 can be different from the etching solution for the dielectric layer 308 or the barrier film 306. In some embodiments, chlorine etching can be used for the dielectric film 310 made of aluminum oxide as the material. In some embodiments, fluorine etching can be used for the TEOS layer of the dielectric layer 308. In some embodiments, organic matter can be removed using ashing etching such as oxygen plasma. In some embodiments, fluorine-oxygen etching can be used for the BLoK or n-BLoK layer of the barrier film 306. In some embodiments, one or more etchings can be dry reactive ion etchings. In some embodiments, one or more etchings can be wet etchings. Different etching solutions, when used, can have selectivity for different layers such that the etching solution primarily etches the target layer more than other layers exposed to etching. For example, fluorine etching used on the TEOS layer of dielectric layer 308 can selectively etch the TEOS layer more than the dielectric film 310. The etching selectivity can be such that the etching of the target layer can be performed in ratios of about 1.5:1 or higher compared to one or more other layers, and ratios of about 1.6:1 or higher, about 1.7:1 or higher, about 1.8:1 or higher, about 1.9:1 or higher, about 2.0:1 or higher, about 2.1:1 or higher, about 2.2:1 or higher, about 2.3:1 or higher, about 2.4:1 or higher, about 2.5:1 or higher, about 2.6:1 or higher, about 2.7:1 or higher, about 2.8:1 or higher, about 2.9:1 or higher, about 3.0:1 or higher, or even higher.

[0033]

[0041] In step 210, the method 200 in the flow chart for forming the first structure 301 may include filling the feature portion with a metal-containing material. As shown in Figure 3C, the structure 300 may include a metal-containing material 322 within a trench 320. The metal-containing material 322 can be a highly conductive material that can be used as an interconnect between integrated circuits. In some embodiments, the metal in the metal-containing material 322 includes copper, such that the metal-containing material 322 is a copper-containing material. The metal used to fill the feature portion may include copper or any other highly conductive metal. While copper is usually described herein, it should be understood that any number of conductive metal materials can be used in embodiments of this art and that this art should not be limited to any particular conductive metal material.

[0034]

[0042] In some embodiments, the liner is formed within the trench before the trench is filled with the metal-containing material. As shown in Figure 3C, the structure 300 may include a liner 324 within the trench 320 such that the liner is located within the trench 320 between the dielectric layer 308 and the metal-containing material 322. In some embodiments, the structure 300 may include a liner 324 within the trench 320 such that the liner is located within the trench 320 between the barrier film 306 and the metal-containing material 322. In some embodiments, the structure 300 may include a liner 324 within the trench 320 such that the liner is located within the trench 320 between the dielectric film 310 and the metal-containing material 322. In some embodiments, the liner 324 may be tantalum nitride or any other suitable liner material incorporated to limit or prevent the diffusion of metal into the dielectric material.

[0035]

[0043] In some embodiments, after the feature portion is filled with the metal-containing material 322, the first structure 301 can be polished via a chemical mechanical polishing (CMP) process, as described in U.S. Patent Application No. 17 / 411,599 (which is incorporated herein by reference in its entirety), which is further described herein in relation to Figures 6 and 7A-7E. After the first structure 301 has been polished via the CMP process, the upper surface of the metal-containing material 322 can be recessed relative to the upper surface of the dielectric film 310, for example, as shown in Figure 3C. The CMP process may cause the upper surface of the metal-containing material 322 to form a concave or dish shape, which may be characterized by a naidr or dish depth, respectively. Here, the naidr or dish depth is the difference between the lowest point in the metal and the surface of the dielectric material on which the feature portion is formed, or the difference in height between metal edges within the feature portion. If the depth of the recess on the upper surface of the metal-containing material 322, combined with the depth of the lowest point of the recess or dish depth to the upper surface of the dielectric film 310 (this combination is called the combined depth), is too large, the material may not be useful for some end products. For example, copper-copper hybrid junctions are one such application that may be selective to an inaccurate combined depth. In some applications of copper-copper hybrid junctions, if the combined depth is too large, the strength of the copper-copper junction may be insufficient due to limited contact between the mating feature portion and the stud, or a bond may not occur at all. A combined depth of less than 5 nm may be small enough for copper-copper hybrid junctions, for example.

[0036]

[0044] In some embodiments, the liner 324 can be polished via a CMP process so that the upper surface of the liner 324 is aligned with the upper surface of the dielectric layer 308. In some embodiments, the liner 324 can be polished via a CMP process so that the upper surface of the liner 324 is aligned with the upper surface of the metal-containing material 322, as shown in Figure 3C. In some embodiments, the liner 324 can be polished via a CMP process so that the upper surface of the liner 324 recedes relative to the upper surface of the dielectric layer 308 and protrudes relative to the upper surface of the metal-containing material 322.

[0037]

[0045] In step 212, method 200 in the flow diagram may include forming a semiconductor device by hybrid bonding a first structure having a dielectric film with a second structure not having a dielectric film. In some embodiments, method 200 in the flow diagram may include bonding the first structure 301 to the second structure 331 via a hybrid bond, as shown in Figure 3D. In some embodiments, the second structure 331 is similar to the first structure 301 in the layout, layers, and materials used. The second structure 331 may include a second metal layer 334 covering the second substrate 332. The second metal layer 334 may be similar to the metal layer 304, such that all descriptions of the metal layer 304 also apply to the second metal layer 334. The second substrate 332 may be similar to the substrate 302, such that all descriptions of the substrate 302 also apply to the second substrate 332. The second structure 331 may also include a second dielectric layer 338 covering the second metal layer 334 and defining a second set of one or more feature portions in the second dielectric layer 338. The second dielectric layer 338 of the second structure 331 may be similar to the dielectric layer 308 of the first structure 301, such that all descriptions of the dielectric layer 308 also apply to the second dielectric layer 338. In some embodiments, the second structure 331 may include a second barrier film 336 between the second dielectric layer 338 and the second metal layer 334. The second barrier film 336 may be similar to the barrier film 306, such that all descriptions of the barrier film 306 also apply to the second barrier film 336. The second structure 331 may include a second metal-containing material 354 deposited inside the second set of one or more feature portions. The second metal-containing material 354 may be similar to the metal-containing material 322, such that all the descriptions of the metal-containing material 322 also apply to the second metal-containing material 354. In some embodiments, the material used for the metal-containing material 322 is the same material used for the second metal-containing material 354.In some embodiments, the second structure 331 may include the second liner 354 within a second set of one or more feature portions such that the second liner 354 is located between the second set of one or more feature portions of the second dielectric layer 338 and the second metal-containing material 354. The second liner 354 may be similar to liner 324 such that all descriptions of liner 324 also apply to the second liner 354. In some embodiments, the first structure 301 can be considered to be hybrid-bonded to the second structure 331. In some embodiments, the metal-containing material 322 can be considered to be hybrid-bonded to the second metal-containing material 354.

[0038]

[0046] The second structure 331 does not contain a dielectric film. Therefore, when the first structure 301 and the second structure 331 are hybrid-bonded to each other, the upper surface of the dielectric film 310 of the first structure is hybrid-bonded to the upper surface of the second dielectric layer 338 of the second structure 331. In some embodiments, the dielectric film 310 and the second dielectric layer 338 are not made of the same material. For example, the dielectric film 310 may be silicon oxynitride, and the second dielectric layer 338 may be silicon oxide. Therefore, since the dielectric film 310 and the second dielectric layer 338 are not equivalent or the same dielectric material, the hybrid bonding of the first structure 301 and the second structure 331 can be considered a hybrid bonding of asymmetric dielectrics. In some embodiments, the second dielectric layer 338 of the second structure 331 may be made of the same material as the dielectric layer 308 of the first structure 301. For example, both the second dielectric layer 338 and the dielectric layer 308 may be silicon oxide, and the dielectric film 310 may be silicon oxynitride. In another embodiment, both the second dielectric layer 338 and the dielectric layer 308 can be silicon carbonitride, and the dielectric film 310 can be tetraethyl orthosilicate. In some embodiments, the second dielectric layer 338 of the second structure 331 can be made of a different material from the dielectric layer 308 of the first structure 301.

[0039]

[0047] In some embodiments, bonding the first structure 301 to the second structure 331 may involve using a surface activation process on the first structure 301 and / or the second structure 331. The surface activation process may involve contacting the first structure 301 and / or the second structure 331 with a hydrogen-containing precursor. The surface activation process can activate the upper surface of the dielectric film 310 of the first structure 301 and / or the upper surface of the second dielectric layer 338 of the second structure 331 such that one or both surfaces are hydroxylated and have dangling hydroxyl groups. In some embodiments, water is then applied to the upper surface of the dielectric film 310 of the first structure 301 and / or the second dielectric layer 338 of the second structure 331.

[0040]

[0048] Next, the upper surface of the dielectric film 310 of the first structure 301 and the upper surface of the second dielectric layer 338 of the second structure 331 can be aligned and brought into contact. When the upper surface of the dielectric film 310 comes into contact with the upper surface of the second dielectric layer 338, spontaneous bonding occurs mainly via van der Waas junctions, creating an initial bond between the upper surface of the dielectric film 310 and the upper surface of the second dielectric layer 338. As a result, the first structure 301 and the second structure 331 are bonded to each other by bringing the upper surface of the dielectric film 310 into contact with the upper surface of the second dielectric layer. The initial bond between the first structure 301 and the second structure 331 does not have to be a final bond, but it can be used to keep the first structure 301 and the second structure 331 aligned when performing additional processing to finalize the hybrid bond.

[0041]

[0049] The joint structure of the first structure 301 and the second structure 331 can then be annealed. During the annealing process, the dielectric film 310 and the second dielectric layer 338 may further form a covalent bond, increasing the bonding strength between the dielectric film 310 and the second dielectric layer 338. In some embodiments, water and / or dangling hydroxyl groups assist in the formation of a covalent bond between the dielectric film 310 and the second dielectric layer 338. Since the dielectric material of the dielectric film 310 and the dielectric material of the second dielectric layer 338 are different, the covalent bond between the upper surface of the dielectric film 310 and the upper surface of the second dielectric layer 338 is extremely strong. The strength of the covalent bond allows the surface area ratio of the dielectric film 310 and the second dielectric layer 338 to be lower than that of traditional hybrid bonding techniques. Since the dielectric film 310 and the second dielectric layer 338 are made of different materials, the bonding strength between the dielectric film 310 and the second dielectric layer 338 can be about 15-75% stronger than the bonding strength between conventional dielectric layers that are hybrid-bonded to each other. For example, the bonding strength between the silicon oxynitride dielectric film 310 and the tetraethyl orthosilicate second dielectric layer 338 can be about 40-55% stronger than the bonding strength between conventional dielectric layers (e.g., silicon oxide) that are hybrid-bonded to each other. In another embodiment, the bonding strength between the silicon carbonitride dielectric film 310 and the tetraethyl orthosilicate second dielectric layer 338 can be about 60-75% stronger than the bonding strength between conventional dielectric layers (e.g., silicon oxide) that are hybrid-bonded to each other.

[0042]

[0050] Furthermore, annealing of the bond structure can cause the metal-containing material 322 to be extruded toward the second metal-containing material 354. As previously mentioned, the combined depth of the metal-containing material 322 (and the extended second metal-containing material 354) is important for bonding the metal-containing materials. When the combined depth is less than 5 nm, subsequent annealing to bond the metal-containing material 322 and the second metal-containing material 354 may be effective because the metal-containing material 322 and the second metal-containing material 354 can be sufficiently close to each other to bond during the annealing step of the hybrid bond. During the annealing step, the metal-containing materials can be extruded toward each other from the two structures, come into contact with each other, and bond. At low annealing temperatures according to some embodiments of this technology, if dishing is not sufficiently reduced, the amount of expansion may be insufficient to allow sufficient bonding between the copper. By performing a polishing step according to this technology, dishing can be reduced, thereby improving the bonding performance between substrates at low annealing temperatures.

[0043]

[0051] Once the annealing process is complete, the first structure 301 and the second structure 331 are hybrid-junctioned to form a single semiconductor device or a single structure. The use of hybrid junctions enables the fabrication of composite semiconductor devices from multiple structures and the formation of interconnections between the structures.

[0044]

[0052] Figure 4 shows another flowchart of an exemplary step of Method 400 for forming a semiconductor device 500 for a hybrid bond that enables pitch reduction and stronger bond strength, according to several embodiments of the present technology. Method 400 may be carried out in various processing chambers in which the process can be performed, for example, a chamber incorporated into the System 100 described above. Method 400 may include one or more steps prior to the commencement of Method 400, including front-end processing, deposition, etching, polishing, cleaning, or any other optional steps that may be performed prior to the described steps. Method 400 may include several optional steps that may or may not be specifically associated with some embodiments of the method according to embodiments of the present technology. Method 400 describes the steps schematically shown in Figures 5A-5E, and the description thereof is given together with the steps of Method 400. It should be understood that the figures are only partial schematics and the substrate 502 may include any number of additional material and feature portions having various properties and embodiments as shown.

[0045]

[0053] It should be understood that the specific steps shown in Figure 4 provide a particular method for forming a semiconductor device 500 for a hybrid junction according to various embodiments. Other sequences of steps may also be carried out according to alternative embodiments. For example, alternative embodiments may carry out the steps described above in a different order. Furthermore, the individual steps shown in Figure 4 may include a plurality of substeps that can be carried out in various sequences suitable for the individual step. Furthermore, additional steps may be added or removed depending on the particular application. Many variations, modifications, and alternatives are also included within the scope of this disclosure.

[0046]

[0054] Figures 5A–5E show progressive structures for forming a semiconductor device 500 for a hybrid junction according to several embodiments. The flow diagram of Method 400 describes the steps schematically shown in Figures 5A–5E, and its description is provided in conjunction with the steps of this method. It should be understood that the figures are only partial schematic diagrams with limited details, and in some embodiments the substrate may include any number of semiconductor sections having the illustrated configuration as well as other structural configurations that may benefit from any of the embodiments of this art.

[0047]

[0055] In step 402, the method 400 of the flow diagram for forming the first structure 501 may include forming a metal layer 504 on a substrate 502. As shown in Figure 5A, the structure 500 may include a substrate 502. In various embodiments, the substrate 502 may have a substantially flat surface plane or a non-uniform surface. The substrate 502 may be made of materials such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon-on-insulator, carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, or sapphire. The substrate 426 may have various dimensions, such as wafers with a diameter of 400 or 500 mm, and rectangular or square panels. The substrate 502 may be deposited inside the processing area of ​​a semiconductor processing chamber. Although shown as a planar substrate, substrate 502 is included solely to represent the underlying structure, which may include any number of layers or features on a wafer or other substrate, and the structure described later may be formed on top of it.

[0048]

[0056] As shown in Figure 5A, the first structure 501 may include a metal layer 504. The metal layer 504 can include various integrated circuits. For example, the integrated circuit can be formed using techniques such as CMOS, NMOS, or any other suitable integrated circuit technique. Thus, the metal layer 504 can include various layers of metal, oxide, and semiconductor. The metal used in the metal layer can include copper or any other highly conductive metal. Although copper is usually described herein, it should be understood that any number of conductive metal materials can be used in embodiments of this technique, and that this technique should not be limited to any particular conductive metal material.

[0049]

[0057] In some embodiments, the layers described herein (e.g., substrate 502, metal layer 504, and other layers described herein, e.g., barrier film 506, dielectric layer 508, and dielectric film 510) can overlap each other directly, one above the other, such that the first layer covers the second layer. For example, the metal layer 504 can directly cover the substrate 502 without any intervening layers. In some embodiments, the layers described herein can have layers between them. For example, the metal layer 504 can cover an intervening layer covering the substrate 502. Furthermore, when forming the layers, any process for forming or depositing the material can be used. For example, chemical vapor deposition can be used in some embodiments, and atomic layer deposition can be used in other embodiments. Details relating to specific layers and / or materials are also described herein.

[0050]

[0058] Step 404, the method 400 of the flow diagram for forming the first structure 501, may include forming a dielectric layer 508 on the metal layer 504. As shown in Figure 5A, the dielectric layer 508 may include one or more layers of dielectric material. Exemplary dielectrics may include silicon oxide, tetraethyl orthosilicate, silicon carbonitride (SiCN), silicon oxynitride (SiON), or any other type of dielectric material. In some embodiments, the dielectric layer 508 may be TEOS. In some embodiments, the dielectric layer 508 may be silicon oxide. In some embodiments, the dielectric layer 508 may be silicon carbonitride (SiCN). In some embodiments, the dielectric layer 508 may be silicon oxynitride (SiON).

[0051]

[0059] In some embodiments, the first structure 501 may include a barrier film 506 between the dielectric layer 508 and the metal layer 504. The barrier film 506 has a low dielectric constant to reduce the dielectric constant of the copper damascene structure, enabling faster and stronger devices to be achieved. Some barrier films may have a dielectric constant of less than 5 or possibly lower. Exemplary barrier films include low dielectric constant barrier films and silicon nitride films such as BLoK (Si-CH compound) or N-BLoK (Si-CHN compound) developed by the applicant. The barrier film 506 may also be called a capping layer for the metal layer 504.

[0052]

[0060] In step 406, the method 400 of the flow diagram for forming the first structure 501 may include etching the feature portions of the dielectric layer 508 and the barrier film 506. In some embodiments, one or more features may be etched into the dielectric layer 508. The feature portions etched into the dielectric layer 508 may include trenches, openings or vias, or any other structures useful in semiconductor processing. As shown in Figure 5B, the structure 500 may include a trench 520 within the dielectric layer 508. In some embodiments, the trench 520 may extend downward from the upper surface of the dielectric layer 508 to at least the upper surface of the metal layer 504. Although only four feature portions are shown in the figure, it should be understood that according to embodiments of the art, the exemplary structure may include any number of feature portions defined along the structure. The etching solution used to etch the feature portions into the dielectric layer 508 may include various semiconductor processing etchings, such as fluorine, oxygen plasma, or fluorine-oxygen, which are solutions or plasmas. In some embodiments, the etching solution may be applied in a single application. In some examples, multiple etching solutions can be combined to perform multi-material etching.

[0053]

[0061] In step 408, the method 400 of the flow diagram for forming the first structure 501 may include filling the feature portion with a metal-containing material. As shown in Figure 5C, the structure 500 may include a metal-containing material 522 within a trench 520. The metal-containing material 522 can be a highly conductive material that can be used as an interconnect between integrated circuits. In some embodiments, the metal in the metal-containing material 522 includes copper, such that the metal-containing material 522 is a copper-containing material. The metal used to fill the feature portion may include copper or any other highly conductive metal. While copper is usually described herein, it should be understood that any number of conductive metal materials can be used in embodiments of the Art, and the Art should not be limited to any particular conductive metal material.

[0054]

[0062] In some embodiments, the liner is formed within the trench before the trench is filled with the metal-containing material. As shown in Figure 5C, the structure 500 may include a liner 524 within the trench 520 such that the liner is located within the trench 520 between the dielectric layer 508 and the metal-containing material 522. In some embodiments, the structure 500 may include a liner 524 within the trench 520 such that the liner is located within the trench 520 between the barrier film 506 and the metal-containing material 522. In some embodiments, the liner 524 may be tantalum nitride or any other suitable liner material incorporated to limit or prevent the diffusion of metal into the dielectric material.

[0055]

[0063] In some embodiments, after the feature portion is filled with the metal-containing material 522, the first structure 501 can be polished via a chemical mechanical polishing (CMP) process, which is further described herein in relation to Figures 6 and 57-57 and described in U.S. Patent Application No. 17 / 411,599. In some embodiments, the upper surface of the metal-containing material 522 can protrude from the upper surface of the dielectric layer 508, for example, as shown in Figure 5C. The CMP process creates a concave or dish shape on the upper surface of the metal-containing material 522, which may feature a recessed lowest point or dish depth, respectively, where the depth is the difference between the lowest point in the metal and the edge height of the metal within the feature portion.

[0056]

[0064] In some embodiments, the liner 524 can be polished via a CMP process so that the upper surface of the liner 524 is aligned with the upper surface of the dielectric layer 508. In some embodiments, the liner 524 can be polished via a CMP process so that the upper surface of the liner 524 is aligned with the upper surface of the metal-containing material 522, as shown in Figure 5C. In some embodiments, the liner 524 can be polished via a CMP process so that the upper surface of the liner 524 recedes relative to the upper surface of the metal-containing material 522 and protrudes relative to the upper surface of the dielectric layer 508.

[0057]

[0065] In step 410, the method 400 of the flow diagram for forming the first structure 501 may include selectively depositing a dielectric film. As shown in Figure 5D, the structure 500 may include a dielectric film 510. The dielectric film 510 may be a different dielectric than the dielectric layer 508 below it. In some embodiments, the dielectric film 510 may be a different dielectric than the material of the uppermost layer of the dielectric layer 508. For example, referring to Figure 5A, the dielectric film 510 may be a different dielectric than the dielectric layer 508. In some embodiments, the dielectric layer 508 may be silicon oxide (SiO2) and the dielectric film 510 may be silicon carbonitride (SiCN). In some embodiments, the dielectric layer 508 may be silicon oxide (SiO2) and the dielectric film 510 may be silicon oxynitride (SiON). In some embodiments, the dielectric layer 508 may be silicon carbonitride (SiCN) and the dielectric film 510 may be silicon oxide (SiO2). In some embodiments, the dielectric layer 508 can be silicon oxynitride (SiON), and the dielectric film 510 can be silicon oxide (SiO2). Tetraethyl orthosilicate (TEOS) can also be used in place of silicon oxide (SiO2) in the above combinations. In some embodiments, the dielectric film 510 can be a metal oxide or other type of oxide. For example, the dielectric film 510 can be aluminum oxide (Al2O3), titanium oxide (TiO2), strontium titanate (SrTiO3), zirconium oxide (ZrO2), hafnium oxide (also called hafnium(IV) oxide / HfO2), hafnium silicate (also called hafnium(IV) silicate / HfSiO4), lanthanum oxide (La2O3), yttrium oxide (also called yttrium(III) oxide / Y2O3), and lanthanum aluminate (LaAlO3). In some embodiments, the dielectric film 510, which is a metal oxide or other type of oxide, can be paired with a dielectric layer 508 of silicon oxide, tetraethyl orthosilicate, silicon carbonitride, and / or silicon oxynitride.Metal oxides and other oxides may require special final treatment and / or special etching due to their chemical properties compared to more common materials such as silicon dioxide.

[0058]

[0066] In some embodiments, selective deposition of the dielectric film 510 involves a selective atomic layer deposition (ALD) process, as described further herein in relation to Figures 8 and 9A-9H. When the dielectric film 510 is selectively deposited, it covers the dielectric layer 508 but not the metal-containing material 522. After the dielectric film 510 is selectively deposited, the upper surface of the metal-containing material 522 can be recessed relative to the upper surface of the dielectric film 510, for example, as shown in Figure 5D.

[0059]

[0067] As previously explained, the CMP process forms a concave or dish-shaped surface on the upper surface of the metal-containing material 522, which may feature a recess depth or dish depth. If the recess depth of the upper surface of the dielectric film 510 combined with the recess depth of the upper surface of the metal-containing material 522 (this combination is called the combined depth) is too large, the material may not be useful for some end products. For example, copper-copper hybrid junctions are one such application that may be selective to an inaccurate combined depth. In some applications of copper-copper hybrid junctions, if the combined depth is too large, the strength of the copper-copper junction may be insufficient due to limited contact between the stud and the mating feature portion, or a bond may not occur at all. A combined depth of less than 5 nm may be sufficiently small for copper-copper hybrid junctions, for example. Therefore, the selective deposition of the dielectric film 510 needs to be accurate enough to ensure that the combined depth is within an appropriate range, as will be further described herein in relation to Figures 8 and 9A-9H.

[0060]

[0068] In step 412, method 400 in the flow diagram may include forming a semiconductor device by hybrid bonding a first structure having a dielectric film with a second structure not having a dielectric film. In some embodiments, method 400 in the flow diagram may include bonding the first structure 501 to the second structure 531 via a hybrid bond, as shown in Figure 5E. In some embodiments, the second structure 531 is similar to the first structure 501 in the layout, layers, and materials used. The second structure 531 may include a second metal layer 534 covering the second substrate 532. The second metal layer 534 may be similar to the metal layer 504, such that all descriptions of the metal layer 504 also apply to the second metal layer 534. The second substrate 532 may be similar to the substrate 502, such that all descriptions of the substrate 502 also apply to the second substrate 532. The second structure 531 may also include a second dielectric layer 538 covering the second metal layer 534 and defining a second set of one or more feature portions in the second dielectric layer 338. The second dielectric layer 538 of the second structure 531 may be similar to the dielectric layer 508 of the first structure 501, such that all descriptions of the dielectric layer 508 also apply to the second dielectric layer 538. In some embodiments, the second structure 531 may include a second barrier film 536 between the second dielectric layer 538 and the second metal layer 534. The second barrier film 536 may be similar to the barrier film 506, such that all descriptions of the barrier film 506 also apply to the second barrier film 536. The second structure 531 may include a second metal-containing material 554 deposited inside the second set of one or more feature portions. The second metal-containing material 554 may be similar to the metal-containing material 522, such that all the descriptions of the metal-containing material 522 also apply to the second metal-containing material 554. In some embodiments, the material used for the metal-containing material 522 is the same material used for the second metal-containing material 554.In some embodiments, the second structure 531 may include the second liner 554 in a second set of one or more feature portions such that the second liner 554 is located between the second set of one or more feature portions of the dielectric layer 538 and the second metal-containing material 554. The second liner 554 may be similar to liner 524 such that all descriptions of liner 524 also apply to the second liner 554. In some embodiments, the first structure 501 can be considered to be hybrid-bonded to the second structure 531. In some embodiments, the metal-containing material 522 can be considered to be hybrid-bonded to the second metal-containing material 554.

[0061]

[0069] The second structure 531 does not contain a dielectric film. Therefore, when the first structure 501 and the second structure 531 are hybrid-bonded to each other, the upper surface of the dielectric film 510 of the first structure is hybrid-bonded to the upper surface of the second dielectric layer 538 of the second structure 531. In some embodiments, the dielectric film 510 and the second dielectric layer 538 are not made of the same material. For example, the dielectric film 510 may be silicon oxynitride and the second dielectric layer 538 may be silicon oxide. Therefore, since the dielectric film 510 and the second dielectric layer 538 are not equivalent or the same dielectric material, the hybrid bonding of the first structure 501 and the second structure 531 can be considered a hybrid bonding of asymmetric dielectrics. In some embodiments, the second dielectric layer 538 of the second structure 531 may be made of the same material as the dielectric layer 508 of the first structure 501. For example, both the second dielectric layer 538 and the dielectric layer 508 may be silicon oxide, and the dielectric film 510 may be silicon oxynitride. In another embodiment, both the second dielectric layer 538 and the dielectric layer 508 can be silicon carbonitride, and the dielectric film 510 can be tetraethyl orthosilicate. In some embodiments, the second dielectric layer 538 of the second structure 531 can be made of a different material from the dielectric layer 508 of the first structure 501.

[0062]

[0070] In some embodiments, bonding the first structure 501 to the second structure 531 may involve using a surface activation process on the first structure 501 and / or the second structure 531. The surface activation process may involve contacting the first structure 501 and / or the second structure 531 with a hydrogen-containing precursor. The surface activation process can activate the upper surface of the dielectric film 510 of the first structure 501 and / or the upper surface of the second dielectric layer 538 of the second structure 531 such that one or both surfaces are hydroxylated and have dangling hydroxyl groups. In some embodiments, water is then applied to the upper surface of the dielectric film 510 of the first structure 501 and / or the upper surface of the second dielectric layer 538 of the second structure 531.

[0063]

[0071] Next, the upper surface of the dielectric film 510 of the first structure 501 and the upper surface of the second dielectric layer 538 of the second structure 531 can be aligned and brought into contact. When the upper surface of the dielectric film 510 comes into contact with the upper surface of the second dielectric layer 438, spontaneous bonding occurs mainly via van der Waas junctions, creating an initial bond between the upper surface of the dielectric film 510 and the upper surface of the second dielectric layer 538. As a result, the first structure 501 and the second structure 531 are bonded to each other through the contact between the upper surface of the dielectric film 510 and the upper surface of the second dielectric layer 538. The initial bond between the first structure 501 and the second structure 531 does not have to be the final bond, but it can be used to keep the first structure 501 and the second structure 531 aligned when performing additional processing to finalize the hybrid bond.

[0064]

[0072] The joint structure of the first structure 501 and the second structure 531 can then be annealed. During the annealing process, the dielectric film 510 and the second dielectric layer 538 may further form a covalent bond, increasing the bonding strength between the dielectric film 510 and the second dielectric layer 538. In some embodiments, water and / or dangling hydroxyl groups assist in the formation of a covalent bond between the dielectric film 510 and the second dielectric layer 538. Since the dielectric material of the dielectric film 510 and the dielectric material of the second dielectric layer 538 are different, the covalent bond between the upper surface of the dielectric film 510 and the upper surface of the second dielectric layer 538 is extremely strong. The strength of the covalent bond allows the surface area ratio of the dielectric film 510 and the second dielectric layer 538 to be lower than that of traditional hybrid bonding techniques. Since the dielectric film 510 and the second dielectric layer 538 are made of different materials, the bonding strength between the dielectric film 510 and the second dielectric layer 538 can be stronger than the bonding strength between conventional dielectric layers that are hybrid-bonded to each other. For example, the bonding strength between the silicon oxynitride dielectric film 310 and the tetraethyl orthosilicate second dielectric layer 338 can be about 40-55% stronger than the bonding strength between conventional dielectric layers (e.g., silicon oxide) that are hybrid-bonded to each other. In another embodiment, the bonding strength between the silicon carbonitride dielectric film 310 and the tetraethyl orthosilicate second dielectric layer 338 can be about 60-75% stronger than the bonding strength between conventional dielectric layers (e.g., silicon oxide) that are hybrid-bonded to each other.

[0065]

[0073] Furthermore, annealing of the bond structure can cause the metal-containing material 522 to be extruded toward the second metal-containing material 554. As previously mentioned, the combined depth of the metal-containing material 522 (and the extended second metal-containing material 554) is important for bonding the metal-containing materials. When the combined depth is less than 5 nm, subsequent annealing to bond the metal-containing material 522 and the second metal-containing material 554 may be effective because the metal-containing material 522 and the second metal-containing material 554 can be sufficiently close to each other to bond during the annealing step of the hybrid bond. During the annealing step, the metal-containing materials can be extruded toward each other from the two structures, come into contact with each other, and bond. At low annealing temperatures according to some embodiments of this technology, if dishing is not sufficiently reduced, the amount of expansion may be insufficient to allow sufficient bonding between the copper and copper. By performing a polishing step according to this technology, dishing can be reduced, thereby improving the bonding performance between substrates at low annealing temperatures.

[0066]

[0074] Once the annealing process is complete, the first structure 501 and the second structure 531 are hybrid-junctioned to form a single semiconductor device or a single structure. The use of hybrid junctions enables the fabrication of composite semiconductor devices from multiple structures and the formation of interconnections between the structures.

[0067]

[0075] Figure 6 shows an exemplary step flow diagram in a chemical mechanical polishing (CMP) method 600 according to several embodiments of the present technology. Method 600 may be carried out in various processing chambers including a polishing system, as well as in any other chamber, such as a chamber incorporated into the system 100 described above. Method 600 may include one or more steps prior to the commencement of Method 600, including front-end processing, deposition, etching, polishing, cleaning, or any other steps that may be carried out before the described steps. Method 600 may include several optional steps, which may or may not be specifically associated with some embodiments of the method according to embodiments of the present technology. Method 600 describes the steps schematically shown in Figures 7A-7E, and the description thereof is given together with the steps of Method 600. It should be understood that the figures are only partial schematics, and the substrate 705 may include any number of additional material and feature portions having various properties and embodiments as shown. Different CMP processes can be described using Method 600, Figures 6 and 7A-7E. For example, Method 600, Figures 6 and 7A-7E can be used to illustrate the CMP process in relation to Figures 2 and 3A-3D. In another embodiment, Method 600, Figures 6 and 7A-7E can be used to illustrate the CMP process in relation to Figures 4 and 5A-5E.

[0068]

[0076] It should be understood that the specific steps shown in Figure 6 provide a particular chemical mechanical polishing method according to various embodiments. Other sequences of steps may be carried out according to alternative embodiments. For example, alternative embodiments may carry out the steps described above in a different order. Furthermore, the individual steps shown in Figure 6 may include multiple substeps that can be carried out in various sequences suitable for the individual steps. Furthermore, additional steps may be added or removed depending on the particular application. Many variations, modifications, and alternatives are also included within the scope of this disclosure.

[0069]

[0077] Herein, the CMP process relating to methods, processes, and techniques is described in relation to Figures 2 and 3A-3D. Method 600 may or may not include optional steps for forming a semiconductor structure toward a particular polishing step, e.g., one or more semiconductor processing steps for forming one or more layers of material on a substrate and clamping the substrate to a carrier head of a polishing system. It should be understood that Method 600 can be carried out on any number of semiconductor structures or substrates 705 (e.g., substrate 302, metal layer 304, and / or dielectric layer 308 in Figure 3A), as shown in Figure 7A, including exemplary structures 700 (e.g., first structure 301 in Figure 3A) upon which a dielectric layer 710 (e.g., dielectric layer 308 and dielectric film 310 in Figure 3A), a liner 715 (e.g., liner 324 in Figure 3C), and a copper-containing layer 720 (e.g., metal-containing layer 322 in Figure 3C) may be formed. In the following description, the dielectric layer 710 is usually described, but it should be understood that the following description can be applied to any dielectric of the barrier film 306, dielectric layer 308, and / or dielectric film 310 described in relation to Figure 3A, so as not to limit the art to any specific dielectric material on which a feature portion may be formed. In some embodiments, the dielectric layer 710 included in the CMP process described herein relates to the polishing of the dielectric film 310 of structure 301 in Figure 3D. In some embodiments, the dielectric layer 710 included in the CMP process described herein may also relate to the polishing of the dielectric layer 308 of structure 301 in Figure 3D. In some embodiments, the dielectric layer 710 included in the CMP process described herein relates to the polishing of the second dielectric layer 338 of the second structure 331 in Figure 3D. In the following description, the copper-containing layer is usually described, but it should be understood that any number of metal-containing materials may be used in embodiments of the art, and the art is not limited to any specific metal-containing material on which a feature portion may be formed. As shown in Figure 7A and described in relation to Figure 3B, the dielectric layer 710 may be processed to form one or more recesses or features, such as trenches, holes or vias, or any other structure useful in semiconductor processing.The substrate 705 may be a base wafer or substrate 705 made from any number of materials, such as silicon or silicon-containing materials, or other substrate materials. For example, in some embodiments, the substrate may be processed to include one or more materials or structures, such as a dielectric layer 710, a liner 715, and a copper-containing layer 720, for semiconductor processing. Although only two feature portions are shown in the figure, according to embodiments of the art, the exemplary structure may include any number of feature portions defined along the structure.

[0070]

[0078] In some embodiments, method 600 may include, in an optional step 602, providing a substrate 705, for example, the substrate 705 shown in Figure 7A, to the polishing assembly. The substrate 705 may include a dielectric layer 710 defining one or more feature portions recessed from the surface of the dielectric layer 710, a liner 715 extending across the dielectric layer 710 (e.g., the barrier film, dielectric layer 308, and / or dielectric film 310 in Figures 3A-3B) and into the interior of one or more feature portions, and a copper-containing layer 720 deposited on the liner 715 and extending into the interior of one or more feature portions. In some embodiments, the liner 715 may be tantalum nitride, or any other suitable liner material incorporated to limit or prevent the diffusion of metal into the dielectric film, dielectric layer, or other dielectric material. As previously stated, the dielectric layer 710, the liner 715, and the copper-containing layer 720 may be formed by any number of processing techniques that can be performed to form the substrate and manufacture the described structure.

[0071]

[0079] As will be described in more detail below, during polishing in Method 600, the overall removal rate of metal, e.g., copper-containing layer 720, may be greater than the removal rate of dielectric material, e.g., dielectric layer 710 (e.g., dielectric film 310 in Figures 3A-3B), when a metal-selective slurry is used. In addition, the dielectric-selective slurry can still remove a certain amount of metal when exposed to the polishing pad and slurry. Furthermore, the removal rate in the copper-containing layer 720 may increase towards the center of the copper in one or more feature portions, because this copper may be a softer bulk material. This greater removal rate may cause concave or dished shapes to form in the copper during polishing. As previously described, excessive dishing may be considered a defect in the polishing process for copper-copper hybrid bonding applications. The concave or dished shape may be characterized by a recess bottom point or dish depth, respectively, which is the difference between the bottom point in the metal and the surface of the dielectric material in which the feature portion is formed, or the difference in edge height of the metal within the feature portion. If the recess depth or dish depth is too large, the material may not be useful for some final products. For example, copper-copper hybrid junctions are one such application that may be selective for inaccurate recess depths or dish depths. In some applications of copper-copper hybrid junctions, if the recess depth or dish depth is too large, the strength of the copper-copper junction may be insufficient or no junction may occur at all due to limited contact with the stud from the mating feature portion. In these applications, the substrate 705 having the copper-containing layer 720 may be in contact with the secondary substrate for mating during the back-end obline process and before the annealing process. The dielectric material of each substrate 705, e.g., the dielectric layer 710, may be in contact with the dielectric material of the other substrate so that the two separate substrates are joined to form a single structure. During the annealing process, the dielectric materials may form an oxide-oxide covalent junction. The copper-containing layer 720 of the mating substrate may also be extruded and come into contact with the copper-containing layer 720 of the substrate 705.If the lowest point of the recess or the dish depth is too large, the copper-containing layer 720 may be excessively recessed to connect with the copper studs and other copper-containing layers during the annealing process.

[0072]

[0080] After providing the substrate 705 to the polishing assembly, the substrate 705 can be brought into contact with the first slurry in step 604. When used throughout this disclosure, contacting the substrate 705 with the slurry can be a chemical step that polishes the substrate 705, so contact can be used interchangeably with polishing. In some embodiments, in step 604, method 600 may include bringing the substrate 705 into contact with the first slurry and a first platen. In some embodiments, bringing the substrate 705 into contact with the first slurry and the first platen can remove a first portion of the copper-containing layer 720. Step 604 can remove the first portion of the copper-containing layer 720 so that the copper-containing layer 720 recedes below the liner 715. The liner can completely isolate the copper regions throughout the substrate 705 and ensure that the metal does not connect the discrete copper regions throughout the substrate. Removing the first portion of the copper-containing layer 720 can isolate individual copper plugs within the copper-containing layer 720. A copper plug may refer to a portion of the copper-containing layer 720 extending into one or more feature portions. The first slurry may be selective for copper, and even if the copper-containing layer 720 is removed, a large portion of the liner 715 may not be removed. Therefore, step 604 may remove the copper-containing layer 720 such that the liner 715 can be at least partially exposed, and the copper-containing layer 720 recedes to expose the liner 715 across the entire surface of the substrate and / or in one or more feature portions of the dielectric layer 710, as shown in Figure 7B.

[0073]

[0081] In step 606, the substrate 705 may be brought into contact with the second slurry. In some embodiments, in step 606, method 600 may include bringing the substrate 705 into contact with the second platen in addition to the second slurry. In some embodiments, the second slurry and the second platen may remove at least a portion of the liner 715 and / or a first portion of the dielectric layer 710. The second slurry may be selective in removing the liner 715 and may not remove most of the copper-containing layer 720. The second slurry can be selective for oxide and nitride materials and can remove the liner and / or oxide material in ratios of about 1.5:1 or greater with respect to copper, and may be about 1.6:1 or greater, about 1.7:1 or greater, about 1.8:1 or greater, about 1.9:1 or greater, about 2.0:1 or greater, about 2.1:1 or greater, about 2.2:1 or greater, about 2.3:1 or greater, about 2.4:1 or greater, about 2.5:1 or greater, about 2.6:1 or greater, about 2.7:1 or greater, about 2.8:1 or greater, about 2.9:1 or greater, about 3.0:1 or greater, or even greater. The second slurry can remove portions of the liner 715 that may be exposed after step 604. That is, portions of the liner 715 between the dielectric layer 710 and the first portion of the copper-containing layer 720, for example, portions of the copper-containing layer 720 that are removed in step 604, can be removed in step 606. As the portion of the liner 715 is removed, the copper-containing layer 720 may protrude above the dielectric layer 710 based on the selectivity of the removal, as shown in Figure 7C.

[0074]

[0082] After contacting the substrate 705 with the second slurry, the substrate 705 can be contacted with the third slurry in step 608. In some embodiments, in step 608, method 600 may include contacting the substrate 705 with a third platen in addition to the third slurry. In some embodiments, the third slurry and the third platen may remove at least a second portion of the copper-containing layer 720. The third slurry may be selective in removing the copper-containing layer 720 and may not remove most of the dielectric layer 710. In some embodiments, the third slurry may remove a second portion of the copper-containing layer 720 that may be exposed after steps 604 and 606. That is, the copper-containing layer 720 protruding above the dielectric layer 710 may be removed in step 608 such that the copper-containing layer 720 is recessed into the dielectric layer 710, as shown in Figure 7D. Step 608 may be carried out at a higher pressure than in step 604 or step 606. Such higher pressure allows for faster removal of softer bulk copper in the center of one or more feature portions of the substrate 705. This faster removal results in dishing in the copper-containing layer 720, as shown in the figure. In some embodiments, the third slurry may be the same as the first slurry. Additionally or alternatively, the third platen may be the same as the first platen.

[0075]

[0083] While the substrate 705 is in contact with the third slurry, the copper-containing material 720 can be intentionally recessed into the dielectric layer 710. Intentional recessing, or dishing, allows the copper-containing material 720 to be below the appropriate level for the copper-copper hybrid junction, which is preferable as it allows for a longer duration of step 610, thereby providing greater control over the duration of step 610. For example, if the copper-containing material 720 is only slightly recessed into the dielectric layer 710, the duration of step 610 may be too short, unintentionally leading to excessive dishing of the copper-containing material 720, which can result in uniformity issues or excessive etching of the material. If the copper-containing material 720 is excessively recessed into the dielectric layer 710, step 610 may take longer and the process may be slower, but this may allow for more precise control of the final recess depth or dishing depth.

[0076]

[0084] After step 608, the copper-containing layer 720 may be characterized by a concave shape within one or more features of the dielectric layer 710. The copper-containing layer 720 may additionally or alternatively be characterized by a dish shape having a dish depth. The lowest point of the concave shape after step 608, or the dish depth of the dish shape, within the surface of the dielectric layer 710, may be about 5 nm or more, about 6 nm or more, about 7 nm or more, about 8 nm or more, about 9 nm or more, about 10 nm or more, about 6 nm or more, about 11 nm or more, about 12 nm or more, about 13 nm or more, about 14 nm or more, about 15 nm or more, or even greater.

[0077]

[0085] A recess depth or dish depth exceeding 5 nm may be too large for, for example, copper-copper hybrid junctions. When the recess depth or dish depth is approximately 5 nm or greater, subsequent annealing to join the separated copper elements may not be effective because the copper is too far apart from each other. During annealing, the separated copper elements may be pushed toward each other, but if the recess depth or dish depth is too large, the copper elements will not join together. If the recess depth or dish depth is too small, and the copper protrudes from one or both sides of the substrate 705, the dielectric material of the substrate 705 will not be able to join together sufficiently. Furthermore, the temperature during annealing can be limited by other components on the substrate 705, such as gallium nitride, which may have a temperature limit of approximately 400°C. This temperature limit can prevent annealing from being performed at temperatures much higher than approximately 400°C. By performing the bonding at a lower temperature, the amount of thermal expansion can also be reduced, thereby further limiting the expansion of the copper and the bonding between copper materials. Therefore, additional processing may be required to fine-tune the lowest point of the recess or the dish depth of the copper-containing layer 720 so that a copper-copper junction can be formed when connecting the separated copper elements of the two substrates 705.

[0078]

[0086] In step 610, the substrate 705 may be in contact with the fourth slurry. In some embodiments, in step 610, method 600 may include bringing the substrate 705 into contact with the fourth platen in addition to the fourth slurry. In some embodiments, the fourth slurry and the fourth platen may remove at least a second portion of the dielectric layer 710. In some embodiments, the fourth slurry may be selective in removing the dielectric layer 710 and may not remove most of the copper-containing layer 720. Bringing the substrate 705 into contact with the fourth slurry and the fourth platen may further remove a third portion of the copper-containing layer 720. In step 610, the copper-containing material 720 may be recessed so that the fourth slurry and the fourth platen do not immediately remove the copper-containing material 720. Instead, the fourth slurry and the fourth platen may remove only the dielectric layer 710 until the dielectric layer 710 is removed to a level close to the copper-containing material 720. Once the dielectric layer 710 has been removed to a level close to that of the copper-containing material 720, the fourth slurry and the fourth platen can also remove the copper-containing material 720. The fourth slurry and the fourth platen can begin removing the copper-containing material 720 when the height of the dielectric layer 710 is less than about 2 nm of the copper-containing material 720, for example, less than about 1 nm. After step 608, the fourth slurry can remove any dielectric layer 710 that may extend above the copper-containing layer 720. That is, the dielectric layer 710 above the copper-containing layer 720 may be removed during step 610 such that the recess of the copper-containing layer 720 in the dielectric layer 710 is smaller than that in step 608, as shown in Figure 7E. In some embodiments, the fourth slurry may be the same as the second slurry. Additionally or alternatively, the fourth platen may be the same as the second platen.

[0079]

[0087] By bringing the substrate 705 into contact with the fourth slurry, in some embodiments, the fourth platen can persist for a period of about 10 seconds or more. When this period is about 10 seconds or more, processing can be performed to fine-tune the removal of a desired amount of dielectric layer 710 so that the bottom of the concave recess or dish depth of the remaining copper-containing layer 720 can be precise. A precise bottom of the concave recess or dish depth may be necessary for further processing and application of the semiconductor substrate, as will be further described below.

[0080]

[0088] In some embodiments, method 600 may include diluting the second slurry to form a fourth slurry. Diluting the second slurry to form a fourth slurry allows control over the rate at which the dielectric layer 710 is removed when the substrate 705 comes into contact with the fourth slurry. The fourth slurry may be diluted before step 610, or alternatively on the platen during step 610. The fourth slurry may be characterized by having a slurry concentration of about 50% or less of the second slurry, and may be characterized by a slurry concentration of about 47% or less of the second slurry, about 45% or less of the second slurry, about 43% or less of the second slurry, about 40% or less of the second slurry, about 37% or less of the second slurry, about 35% or less of the second slurry, about 33% or less of the second slurry, or even lower. Similar to the removal selectivity between the dielectric layer 710 and copper described above, the fourth slurry being a dilution of the second slurry allows the fourth slurry to remove the dielectric layer 710 and the copper-containing layer 720 at a speed such that the lowest point of the concave recess or the dish depth of the dish shape of the copper-containing layer 720 is sufficiently precise for the subsequent copper-copper hybrid junction.

[0081]

[0089] Diluting the fourth slurry can reduce the removal selectivity between the dielectric layer 710 and copper. Diluting the fourth slurry can reduce the removal selectivity between the dielectric layer 710 and copper to about 2:1 or less, and can further reduce the removal selectivity between the dielectric layer 710 and copper to about 1.9:1 or less, about 1.8:1 or less, about 1.7:1 or less, about 1.6:1 or less, about 1.5:1 or less, about 1.4:1 or less, about 1.3:1 or less, about 1.2:1 or less, about 1.1:1 or less, about 1.1:1 or less, or even lower. With a removal selectivity between the dielectric layer 710 and copper of about 2:1 or less, the fourth slurry can remove the dielectric layer 710 and the copper-containing layer 720 at a sufficiently low speed so that the removal process can reduce copper dishing by slowly removing oxides and edge metal materials. As shown in Figure 6, the higher the degree of dilution of the fourth slurry, the lower the removal selectivity may be. The removal selectivity between the dielectric layer 710 and the copper is approximately 2:1 or less, allowing the fourth slurry to remove the dielectric layer 710 and the copper-containing layer 720 at a speed such that the lowest point of the concave recess or the dish depth of the dish shape of the copper-containing layer 720 can be sufficiently accurate for the subsequent copper-copper hybrid junction.

[0082]

[0090] As shown in Figure 6, contacting the substrate 705 with the fourth slurry during step 610 allows the dielectric layer 710 to be etched or removed at an etching rate of approximately 15 nm per minute or less. This etching rate allows the fourth slurry to remove the dielectric layer 710 at a speed low enough to control the bottom recess or dish depth of the final copper-containing layer 720, so that the structure can be used in various applications, such as copper-copper hybrid junctions. By reducing the removal rate of the dielectric layer 710, the removal rate of the copper-containing layer 720 can also be reduced. Reducing the removal rate of the copper-containing layer 720 can help reduce the bottom recess or dish depth of the copper-containing layer 720, so that the material can be used in copper-copper hybrid junctions. The etching rate can be approximately 15 nm or less per minute, approximately 14 nm or less per minute, approximately 13 nm or less per minute, approximately 12 nm or less per minute, approximately 11 nm or less per minute, approximately 10 nm or less per minute, approximately 9 nm or less per minute, approximately 8 nm or less per minute, approximately 7 nm or less per minute, approximately 6 nm or less per minute, approximately 5 nm or less per minute, approximately 4 nm or less per minute, approximately 3 nm or less per minute, approximately 2 nm or less per minute, approximately 1 nm or less per minute, or even lower. Again, the etching rate of the silicon dioxide 710 in the embodiments of this disclosure allows for fine-tuning of the removal of the silicon dioxide 710, and the lowest point of the recess or dish depth of the copper-containing layer 720 can be controlled as desired depending on the end application of the structure. By reducing the etching rate of the dielectric layer 710, the etching rate of the copper-containing layer 720 can also be reduced. By etching the copper-containing layer 720 at a lower speed, the lowest point of the recess or the dish depth can be reduced, thereby enabling the fabrication of a substrate 705 ideal for the copper-copper hybrid junction described herein.

[0083]

[0091] In this case as well, after step 610, the copper-containing layer 720 may be characterized by a concave or dish shape within one or more feature portions of the dielectric layer 710. The lowest point of the concave recess or the dish depth of the dish shape after step 610 can be about 5 nm or less within the surface of the dielectric layer 710, and may be about 4 nm or less, about 3 nm or less, about 2 nm or less, about 1 nm or less, about 0.5 nm or less, or even smaller.

[0084]

[0092] A recess depth of less than 5 nm or a dish depth can be sufficiently small for, for example, copper-copper hybrid bonding. When the recess depth or dish depth is less than 5 nm, subsequent annealing for bonding the separated copper elements can be effective because the copper can come close enough to bond to each other during the annealing step. During the annealing step, the copper elements are pushed out from the separated substrates toward each other, coming into contact with each other and bonding. At low annealing temperatures according to some embodiments of this technique, if dishing is not sufficiently reduced, the amount of expansion may be insufficient to allow sufficient bonding between the copper. By performing a polishing step according to this technique, dishing can be reduced, thereby improving the bonding performance between substrates at low annealing temperatures.

[0085]

[0093] Notably, the above description of the CMP process relates to both the first structure 301 and the second structure 331 in Figure 3D. However, since the top layer material of each structure may differ (for example, the dielectric film 310 may be a different dielectric than the second dielectric layer 338), the specifications of the CMP process for each structure may differ.

[0086]

[0094] As described above, the CMP process described above relates to the methods, processes, and techniques shown in Figures 2 and 3A-3D.

[0087]

[0095] Here, the CMP process related to the method, process, and technique is described in relation to Figures 4 and 5A-5E. Figure 6 shows an exemplary step flow chart in the chemical mechanical polishing method 600 according to several embodiments of the present art. Method 600 may be carried out in various processing chambers including polishing systems, as well as in any other chamber, such as a chamber incorporated into the system 100 described above. Method 600 may include one or more steps prior to the commencement of Method 600, including front-end processing, deposition, etching, polishing, cleaning, or any other steps that may be carried out before the steps described. Method 600 may include several optional steps, which may or may not be specifically associated with some embodiments of the method according to embodiments of the present art. Method 600 describes the steps schematically shown in Figures 7A-7E, and the description thereof is given together with the steps of Method 600. It should be understood that the figures are only partial schematics, and the substrate 705 may include any number of additional material and feature portions having various properties and embodiments as shown.

[0088]

[0096] It should be understood that the specific steps shown in Figure 6 provide a particular chemical mechanical polishing method according to various embodiments. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments may perform the steps described above in a different order. Furthermore, the individual steps shown in Figure 6 may include multiple substeps that can be performed in various sequences suitable for the individual steps. In addition, additional steps may be added or removed depending on the particular application. Many variations, modifications, and alternatives are also included within the scope of this disclosure.

[0089]

[0097] Method 600 may include, but is not limited to, optional steps for forming a semiconductor structure for a particular polishing step, such as one or more semiconductor processing steps for forming one or more layers of material on a substrate and clamping the substrate to a carrier head of a polishing system. It should be understood that Method 600 can be carried out on any number of semiconductor structures or substrates 705 (e.g., substrate 502, metal layer 504, and / or dielectric layer 508 in Figure 5A) as shown in Figure 7A, including exemplary structure 700 (e.g., first structure 501 in Figure 5A) on which a dielectric layer 710 (e.g., dielectric layer 508 in Figure 5A), a liner 715 (e.g., liner 524 in Figure 5C), and a copper-containing layer 720 (e.g., metal-containing layer 522 in Figure 5C) may be formed. While the following description typically refers to the dielectric layer 710, it should be understood that any number of dielectric materials may be used in embodiments of the Art, and the Art is not limited to any particular dielectric material on which a feature portion may be formed. In some embodiments, the dielectric layer 710 included in the CMP process described herein relates to the polishing of the dielectric layer 508 of the structure 501 in Figure 5E. In some embodiments, the dielectric layer 710 included in the CMP process described herein may also relate to the polishing of the second dielectric layer 538 of the second structure 531 in Figure 5E. While the following description usually describes copper-containing layers, it should be understood that any number of metal-containing materials may be used in embodiments of the Art, and the Art is not limited to any particular metal-containing material on which features can be formed. As shown in Figure 7A, the dielectric layer 710 may be processed to form one or more recesses or features, such as trenches, holes or vias, or any other structures useful in semiconductor processing. The substrate 705 may be a base wafer or substrate 705 made from any number of materials, such as silicon or silicon-containing materials, or other substrate materials. For example, in some embodiments, the substrate may be processed to include one or more materials or structures, such as the dielectric layer 710, the liner 715, and the copper-containing layer 720, for semiconductor processing. Although only two feature portions are shown in the figure, according to embodiments of this technology, the exemplary structure may include any number of feature portions defined along the structure.

[0090]

[0098] In some embodiments, method 600 may include, in an optional step 602, providing a substrate 705, for example, the substrate 705 shown in Figure 7A, to the polishing assembly. The substrate 705 may include a dielectric layer 710 defining one or more feature portions recessed from the surface of the dielectric layer 710, a liner 715 extending across the dielectric layer 710 and into the interior of one or more feature portions, and a copper-containing layer 720 deposited on the liner 715 and extending into the interior of one or more feature portions. In some embodiments, the liner 715 may be tantalum nitride, or any other suitable liner material incorporated to limit or prevent the diffusion of metal into the dielectric material. As previously stated, the dielectric layer 710, the liner 715, and the copper-containing layer 720 may be formed by any number of processing techniques that can be performed to form the substrate and manufacture the described structure.

[0091]

[0099] As will be described in more detail below, the removal rate in the copper-containing layer 720 may increase towards the center of the copper in one or more feature portions because this copper may be a softer bulk material. This increased removal rate may result in the formation of concave or dished shapes in the copper during polishing. As previously explained, excessive dishing can be considered a defect in the polishing process for copper-copper hybrid joint applications. Concave or dished shapes may be characterized by a recess depth or dish depth, or a difference in the metal edge height within the feature portion, respectively. If the recess depth or dish depth is too large, the material may not be useful for some end products. For example, copper-copper hybrid joints are one such application where inaccurate recess depths or dish depths can be selective. In some applications of copper-copper hybrid joints, excessive recess depths or dish depths may result in insufficient strength of the copper-copper joint, or even no joint at all, due to limited contact between the stud and the mating feature portion. In these applications, the substrate 705 having the copper-containing layer 720 may be in contact with the secondary substrate for mating during the back-end obline process, prior to the annealing step. The dielectric material of each substrate 705, for example, the dielectric film 510 in Figure 5D, may be in contact with the dielectric material of the other substrate (for example, the second dielectric film 540 in Figure 5E) so that the two separate substrates are joined to form a single structure. During the annealing step, the dielectric materials may form oxide-oxide covalent junctions. The copper-containing layer 720 of the mating substrate may also be extruded and in contact with the copper-containing layer 720 of the substrate 705. If the recess depth or dish depth is too large, the copper-containing layer 720 may be excessively recessed to connect with the copper studs and other copper-containing layers during the annealing step.

[0092]

[0100] After providing the substrate 705 to the polishing assembly, the substrate 705 can be brought into contact with the first slurry in step 604. When used throughout this disclosure, contacting the substrate 705 with the slurry can be a chemical step that polishes the substrate 705, so contact can be used interchangeably with polishing. In some embodiments, in step 604, method 600 may include bringing the substrate 705 into contact with the first slurry and a first platen. In some embodiments, bringing the substrate 705 into contact with the first slurry and the first platen can remove a first portion of the copper-containing layer 720. Step 604 can remove the first portion of the copper-containing layer 720 so that the copper-containing layer 720 recedes below the liner 715. The liner can completely isolate the copper regions throughout the substrate 705 and ensure that the metal does not connect the discrete copper regions throughout the substrate. Removing the first portion of the copper-containing layer 720 can isolate individual copper plugs within the copper-containing layer 720. A copper plug may refer to a portion of the copper-containing layer 720 extending into one or more feature portions. The first slurry may be selective for copper, and even if the copper-containing layer 720 is removed, a large portion of the liner 715 may not be removed. Therefore, step 604 may remove the copper-containing layer 720 such that the liner 715 can be at least partially exposed, and the copper-containing layer 720 recedes to expose the liner 715 across the entire surface of the substrate and / or in one or more feature portions of the dielectric layer 710, as shown in Figure 7B.

[0093]

[0101] In step 606, the substrate 705 can be brought into contact with the second slurry. In some embodiments, in step 606, method 600 may include bringing the substrate 705 into contact with a second platen in addition to the second slurry. In some embodiments, the second slurry and the second platen may remove at least a portion of the liner 715 and / or a first portion of the dielectric layer 710. The second slurry may be selective in removing the liner 715 and / or the dielectric layer 710, and may not remove most of the copper-containing layer 720. The second slurry can be selective for oxide and nitride materials and can remove the liner and / or oxide material in ratios of about 1.5:1 or greater with respect to copper, and may be about 1.6:1 or greater, about 1.7:1 or greater, about 1.8:1 or greater, about 1.9:1 or greater, about 2.0:1 or greater, about 2.1:1 or greater, about 2.2:1 or greater, about 2.3:1 or greater, about 2.4:1 or greater, about 2.5:1 or greater, about 2.6:1 or greater, about 2.7:1 or greater, about 2.8:1 or greater, about 2.9:1 or greater, about 3.0:1 or greater, or even greater. The second slurry can remove portions of the liner 715 that may be exposed after step 604. That is, portions of the liner 715 between the dielectric layer 710 and the first portion of the copper-containing layer 720, for example, portions of the copper-containing layer 720 removed in step 604, can be removed in step 606. As the portion of the liner 715 is removed, the copper-containing layer 720 may protrude above the dielectric layer 710, based on the selectivity of the removal, as shown in Figure 7C.

[0094]

[0102] After the substrate 705 has come into contact with the second slurry, the substrate 705 may be brought into contact with the third slurry in step 608. In some embodiments, in step 608, method 600 may include bringing the substrate 705 into contact with a third platen in addition to the third slurry. The third slurry and the third platen may, in some embodiments, remove at least a second portion of the copper-containing layer 720. The third slurry may be selective in removing the copper-containing layer 720 and may not remove most of the dielectric layer 710. In some embodiments, the third slurry may remove a second portion of the copper-containing layer 720 that may be exposed after steps 604 and 606. That is, the copper-containing layer 720 protruding above the dielectric layer 710 may be removed in step 608 such that the copper-containing layer 720 is recessed into the dielectric layer 710, as shown in Figure 7D. In some embodiments, the third slurry may not remove the second portion of the copper-containing layer 720 that protrudes above the dielectric layer 710, so that the copper-containing layer 720 can protrude as shown in Figure 5C. Step 608 may be carried out at a higher pressure than in step 604 or step 606. Such higher pressure allows for faster removal of softer bulk copper in the center of one or more feature portions of the substrate 705. Such faster removal results in dishing of the copper-containing layer 720 as shown. In some embodiments, the third slurry may be the same as the first slurry. Additionally or alternatively, the third platen may be the same as the first platen.

[0095]

[0103] While the substrate 705 is in contact with the third slurry, the copper-containing material 720 can be intentionally recessed into the dielectric layer 710. Intentional recessing, or dishing, allows the copper-containing material 720 to be below the appropriate level for the copper-copper hybrid junction, which is preferable as it allows for a longer duration of step 610, thereby providing greater control over the duration of step 610. For example, if the copper-containing material 720 is only slightly recessed into the dielectric layer 710, the duration of step 610 may be too short, unintentionally leading to excessive dishing of the copper-containing material 720, which can result in uniformity issues or excessive etching of the material. If the copper-containing material 720 is excessively recessed into the dielectric layer 710, step 610 may take longer and the process may be slower, but this may allow for more precise control of the final recess depth or dishing depth.

[0096]

[0104] After step 608, the copper-containing layer 720 may be characterized by a concave shape within one or more features of the dielectric layer 710. The copper-containing layer 720 may additionally or alternatively be characterized by a dish shape having a dish depth. The lowest point of the concave shape after step 608, or the dish depth of the dish shape, within the surface of the dielectric layer 710, may be about 5 nm or more, about 6 nm or more, about 7 nm or more, about 8 nm or more, about 9 nm or more, about 10 nm or more, about 6 nm or more, about 11 nm or more, about 12 nm or more, about 13 nm or more, about 14 nm or more, about 15 nm or more, or even greater.

[0097]

[0105] A recess depth or dish depth exceeding 5 nm may be too large for, for example, copper-copper hybrid junctions. When the recess depth or dish depth is approximately 5 nm or greater, subsequent annealing to join the separated copper elements may not be effective because the copper is too far apart from each other. During annealing, the separated copper elements may be pushed toward each other, but if the recess depth or dish depth is too large, the copper elements will not join together. If the recess depth or dish depth is too small, and the copper protrudes from one or both sides of the substrate 705, the dielectric material of the substrate 705 will not be able to join together sufficiently. Furthermore, the temperature during annealing can be limited by other components on the substrate 705, such as gallium nitride, which may have a temperature limit of approximately 400°C. This temperature limit can prevent annealing from being performed at temperatures much higher than approximately 400°C. By performing the bonding at a lower temperature, the amount of thermal expansion can also be reduced, thereby further limiting the expansion of the copper and the bonding between copper materials. Therefore, additional processing may be required to fine-tune the lowest point of the recess or the dish depth of the copper-containing layer 720 so that a copper-copper junction can be formed when connecting the separated copper elements of the two substrates 705.

[0098]

[0106] Alternatively, after step 608, the copper-containing layer 720 may be characterized by a concave shape and may protrude from one or more feature portions of the dielectric layer 710, as shown in Figure 5C. The copper-containing layer 720 may additionally or alternatively be characterized by a dish shape having a dish depth. The lowest point of the concave recess after step 608, or the dish depth of the dish shape, above the upper surface of the dielectric layer 710, can be about 10.0 nm or less, about 9.5 nm or less, about 9.0 nm or less, about 8.5 nm or less, about 8.0 nm or less, about 7.5 nm or less, about 7.0 nm or less, about 6.5 nm or less, about 6.0 nm or less, about 5.5 nm or less, about 5.0 nm or less, about 4.5 nm or less, about 4.0 nm or less, about 3.5 nm or less, about 3.0 nm or less, about 2.5 nm or less, about 2.0 nm or less, about 1.5 nm or less, about 1.0 nm or less, about 0.5 nm or less, or even smaller. In some embodiments, the upper surface of the copper-containing layer 720 after step 608 may be about 10.0 nm or less above the upper surface of the dielectric layer 710, about 9.5 nm or less, about 9.0 nm or less, about 8.5 nm or less, about 8.0 nm or less, about 7.5 nm or less, about 7.0 nm or less, about 6.5 nm or less, about 6.0 nm or less, about 5.5 nm or less, about 5.0 nm or less, about 4.5 nm or less, about 4.0 nm or less, about 3.5 nm or less, about 3.0 nm or less, about 2.5 nm or less, about 2.0 nm or less, about 1.5 nm or less, about 1.0 nm or less, about 0.5 nm or less, or even smaller. In some embodiments, the upper surface of the dielectric layer 710 after step 608 may be 10.0 nm or less below the upper surface of the copper-containing layer 720, approximately 9.5 nm or less, approximately 9.0 nm or less, approximately 8.5 nm or less, approximately 8.0 nm or less, approximately 7.5 nm or less, approximately 7.0 nm or less, approximately 6.5 nm or less, approximately 6.0 nm or less, approximately 5.5 nm or less, approximately 5.0 nm or less, approximately 4.5 nm or less, approximately 4.0 nm or less, approximately 3.5 nm or less, approximately 3.0 nm or less, approximately 2.5 nm or less, approximately 2.0 nm or less, approximately 1.5 nm or less, approximately 1.0 nm or less, approximately 0.5 nm or less, or even smaller.In some embodiments, the upper surface of the dielectric layer 710 after step 608 can be about 10.0 nm or less below the lowest point of the concave recess of the copper-containing layer 720 or below the dish depth of the dish shape, and may be about 9.5 nm or less, about 9.0 nm or less, about 8.5 nm or less, about 8.0 nm or less, about 7.5 nm or less, about 7.0 nm or less, about 6.5 nm or less, about 6.0 nm or less, about 5.5 nm or less, about 5.0 nm or less, about 4.5 nm or less, about 4.0 nm or less, about 3.5 nm or less, about 3.0 nm or less, about 2.5 nm or less, about 2.0 nm or less, about 1.5 nm or less, about 1.0 nm or less, about 0.5 nm or less, or even smaller.

[0099]

[0107] In step 610, the substrate 705 can be brought into contact with the fourth slurry. In some embodiments, in step 610, method 600 may include bringing the substrate 705 into contact with the fourth platen in addition to the fourth slurry. The fourth slurry and the fourth platen can remove at least a second portion of the dielectric layer 710 in some embodiments. In some embodiments, the fourth slurry can be selective in removing the dielectric layer 710 and may not remove most of the copper-containing layer 720. Bringing the substrate 705 into contact with the fourth slurry and the fourth platen may further remove a third portion of the copper-containing layer 720. In step 610, the copper-containing material 720 can be recessed so that the fourth slurry and the fourth platen do not immediately remove the copper-containing material 720. Instead, the fourth slurry and the fourth platen can remove only the dielectric layer 710 until the dielectric layer 710 is removed to a level close to the copper-containing material 720. Once the dielectric layer 710 has been removed to a level close to that of the copper-containing material 720, the fourth slurry and the fourth platen can also remove the copper-containing material 720. The fourth slurry and the fourth platen can begin removing the copper-containing material 720 when the height of the dielectric layer 710 is less than about 2 nm of the copper-containing material 720, for example, less than about 1 nm. After step 608, the fourth slurry can remove any dielectric layer 710 that may extend above the copper-containing layer 720. That is, the dielectric layer 710 above the copper-containing layer 720 may be removed during step 610 such that the recess of the copper-containing layer 720 in the dielectric layer 710 is smaller than that in step 608, as shown in Figure 7E. In some embodiments, the fourth slurry may be the same as the second slurry. Additionally or alternatively, the fourth platen may be the same as the second platen.

[0100]

[0108] In some embodiments, the fourth slurry can be selective for removing the liner 715 and / or dielectric layer 710, while not removing most of the copper-containing layer 720. The fourth slurry can be selective for oxide and nitride materials, and can remove the liner and / or oxide materials in ratios of about 1.5:1 or greater, about 1.6:1 or greater, about 1.7:1 or greater, about 1.8:1 or greater, about 1.9:1 or greater, about 2.0:1 or greater, about 2.1:1 or greater, about 2.2:1 or greater, about 2.3:1 or greater, about 2.4:1 or greater, about 2.5:1 or greater, about 2.6:1 or greater, about 2.7:1 or greater, about 2.8:1 or greater, about 2.9:1 or greater, about 3.0:1 or greater, or even greater, compared to copper.

[0101]

[0109] Therefore, after step 610, the dielectric layer 710 above the copper-containing layer 720 and the dielectric layer 710 near the level of the copper-containing layer may be removed during step 610 so that the copper-containing layer 720 can protrude from the dielectric layer 710, as shown in Figure 5C. The copper-containing layer 720 may be characterized by a concave shape. The copper-containing layer 720 may be additionally or alternatively characterized by a dish shape having a dish depth. The lowest point of the concave recess after step 608, or the dish depth of the dish shape, above the upper surface of the dielectric layer 710, can be about 10.0 nm or less, about 9.5 nm or less, about 9.0 nm or less, about 8.5 nm or less, about 8.0 nm or less, about 7.5 nm or less, about 7.0 nm or less, about 6.5 nm or less, about 6.0 nm or less, about 5.5 nm or less, about 5.0 nm or less, about 4.5 nm or less, about 4.0 nm or less, about 3.5 nm or less, about 3.0 nm or less, about 2.5 nm or less, about 2.0 nm or less, about 1.5 nm or less, about 1.0 nm or less, about 0.5 nm or less, or even smaller. In some embodiments, the upper surface of the copper-containing layer 720 after step 608 may be about 10.0 nm or less above the upper surface of the dielectric layer 710, about 9.5 nm or less, about 9.0 nm or less, about 8.5 nm or less, about 8.0 nm or less, about 7.5 nm or less, about 7.0 nm or less, about 6.5 nm or less, about 6.0 nm or less, about 5.5 nm or less, about 5.0 nm or less, about 4.5 nm or less, about 4.0 nm or less, about 3.5 nm or less, about 3.0 nm or less, about 2.5 nm or less, about 2.0 nm or less, about 1.5 nm or less, about 1.0 nm or less, about 0.5 nm or less, or even smaller. In some embodiments, the upper surface of the dielectric layer 710 after step 608 may be 10.0 nm or less below the upper surface of the copper-containing layer 720, approximately 9.5 nm or less, approximately 9.0 nm or less, approximately 8.5 nm or less, approximately 8.0 nm or less, approximately 7.5 nm or less, approximately 7.0 nm or less, approximately 6.5 nm or less, approximately 6.0 nm or less, approximately 5.5 nm or less, approximately 5.0 nm or less, approximately 4.5 nm or less, approximately 4.0 nm or less, approximately 3.5 nm or less, approximately 3.0 nm or less, approximately 2.5 nm or less, approximately 2.0 nm or less, approximately 1.5 nm or less, approximately 1.0 nm or less, approximately 0.5 nm or less, or even smaller.In some embodiments, the upper surface of the dielectric layer 710 after step 608 can be about 10.0 nm or less below the lowest point of the concave recess of the copper-containing layer 720 or below the dish depth of the dish shape, and may be about 9.5 nm or less, about 9.0 nm or less, about 8.5 nm or less, about 8.0 nm or less, about 7.5 nm or less, about 7.0 nm or less, about 6.5 nm or less, about 6.0 nm or less, about 5.5 nm or less, about 5.0 nm or less, about 4.5 nm or less, about 4.0 nm or less, about 3.5 nm or less, about 3.0 nm or less, about 2.5 nm or less, about 2.0 nm or less, about 1.5 nm or less, about 1.0 nm or less, about 0.5 nm or less, or even smaller.

[0102]

[0110] By bringing the substrate 705 into contact with the fourth slurry, in some embodiments, the fourth platen can persist for a period of about 10 seconds or more. When this period is about 10 seconds or more, processing can be performed to fine-tune the removal of a desired amount of dielectric layer 710 so that the remaining recess depth of the concave shape of the copper-containing layer 720 or the dish depth of the dish shape can be precise. A precise recess depth or dish depth may be necessary for further processing and application of the semiconductor substrate, as will be further described below.

[0103]

[0111] In some embodiments, method 600 may dilute the second slurry to form a fourth slurry. Diluting the second slurry to form a fourth slurry allows control over the rate at which the dielectric layer 710 is removed when the substrate 705 comes into contact with the fourth slurry. The fourth slurry may be diluted before step 610, or alternatively, on the platen during step 610. The fourth slurry may be characterized by having a slurry concentration of about 50% or less of the second slurry, or a slurry concentration of about 47% or less of the second slurry, about 45% or less of the second slurry, about 43% or less of the second slurry, about 40% or less of the second slurry, about 37% or less of the second slurry, about 35% or less of the second slurry, about 33% or less of the second slurry, or even lower. Similar to the removal selectivity between the dielectric layer 710 and copper described above, the fourth slurry being a dilution of the second slurry allows the fourth slurry to remove the dielectric layer 710 and the copper-containing layer 720 at a speed such that the lowest point of the concave recess or the dish depth of the dish shape of the copper-containing layer 720 is sufficiently precise for the subsequent copper-copper hybrid junction.

[0104]

[0112] Diluting the fourth slurry can reduce the removal selectivity between the dielectric layer 710 and copper. Diluting the fourth slurry can reduce the removal selectivity between the dielectric layer 710 and copper to about 2:1 or less, and can be reduced to about 1.9:1 or less, about 1.8:1 or less, about 1.7:1 or less, about 1.6:1 or less, about 1.5:1 or less, about 1.4:1 or less, about 1.3:1 or less, about 1.2:1 or less, about 1.1:1 or less, about 1.1:1 or less, or even lower. With a removal selectivity between the dielectric layer 710 and copper of about 2:1 or less, the fourth slurry removes the dielectric layer 710 and the copper-containing layer 720 at a speed low enough that the removal process can reduce copper dishing by slowly removing oxides and edge metal materials. As shown in Figure 6, the higher the degree of dilution of the fourth slurry, the lower the removal selectivity may be. The removal selectivity between the dielectric layer 710 and the copper is approximately 2:1 or less, allowing the fourth slurry to remove the dielectric layer 710 and the copper-containing layer 720 at a speed such that the lowest point of the concave recess or the dish depth of the dish shape of the copper-containing layer 720 can be sufficiently accurate for the subsequent copper-copper hybrid junction.

[0105]

[0113] As shown in Figure 6, contacting the substrate 705 with the fourth slurry during step 610 allows etching or removal of the dielectric layer 710 at an etching rate of approximately 15 nm per minute or less. Such an etching rate allows the fourth slurry to remove the dielectric layer 710 at a speed low enough to control the recess depth or dish depth of the final copper-containing layer 720, enabling the structure to be used in various applications, such as copper-copper hybrid junctions. By reducing the removal rate of the dielectric layer 710, the removal rate of the copper-containing layer 720 can also be reduced. Reducing the removal rate of the copper-containing layer 720 can help reduce the recess depth or dish depth of the copper-containing layer 720, enabling the material to be used in copper-copper hybrid junctions. The etching rate can be approximately 15 nm or less per minute, approximately 14 nm or less per minute, approximately 13 nm or less per minute, approximately 12 nm or less per minute, approximately 11 nm or less per minute, approximately 10 nm or less per minute, approximately 9 nm or less per minute, approximately 8 nm or less per minute, approximately 7 nm or less per minute, approximately 6 nm or less per minute, approximately 5 nm or less per minute, approximately 4 nm or less per minute, approximately 3 nm or less per minute, approximately 2 nm or less per minute, approximately 1 nm or less per minute, or even lower. Again, the etching rate of the silicon dioxide 710 in the embodiments of this disclosure allows for fine-tuning of the removal of the silicon dioxide 710, and the lowest point of the recess or dish depth of the copper-containing layer 720 can be controlled as desired depending on the end application of the structure. By reducing the etching rate of the dielectric layer 710, the etching rate of the copper-containing layer 720 can also be reduced. By etching the copper-containing layer 720 at a lower speed, the lowest point of the recess or the dish depth can be reduced, thereby enabling the fabrication of a substrate 505 ideal for the copper-copper hybrid junction described herein.

[0106]

[0114] Figure 8 shows an exemplary step flow diagram in a selective atomic layer deposition (ALD) process 800 according to several embodiments of the present technology. Method 800 may be carried out in various processing chambers, including polishing systems, as well as in any other chamber, such as a chamber incorporated into the system 100 described above. Method 800 may include one or more steps prior to the commencement of Method 800, including front-end processing, deposition, etching, polishing, cleaning, or any other steps that may be carried out prior to the described steps. Method 800 may include several optional steps, which may or may not be specifically associated with some embodiments of the method according to embodiments of the present technology. Method 800 describes the steps schematically shown in Figures 9A-9H, and the description is provided in conjunction with the steps of Method 800. It should be understood that the figures are only partial schematics, and the substrate 902 may include any number of additional material and feature portions having various properties and characteristics as shown.

[0107]

[0115] It should be understood that the specific steps shown in Figure 8 provide specific methods of selective ALD according to various embodiments. Other sequences of steps may be performed according to alternative embodiments. For example, alternative embodiments may perform the steps described above in a different order. Furthermore, the individual steps shown in Figure 8 may include multiple substeps that can be performed in various sequences suitable for the individual steps. Furthermore, additional steps may be added or removed depending on the particular application. Many variations, modifications, and alternatives are also included within the scope of this disclosure.

[0108]

[0116] In step 802, method 800 in the flow chart may include depositing a polymer on the first structure to form a polymer layer on the metal-containing material. In some embodiments, the polymer layer is a single layer. As shown in Figure 9A, the first structure 901 is similar to the first structure 501 shown in Figure 5C. The first structure 901 may include a metal layer 904 (e.g., the metal layer 504 in Figure 5A) covering the substrate 902 (e.g., the substrate 502 in Figure 5A). The first structure 901 may also include a dielectric layer 908 (e.g., the dielectric layer 508 described in relation to Figures 5A-5E) covering the metal layer 904 and defining one or more sets of feature portions in the dielectric layer 908. In some embodiments, the first structure 901 may include a barrier film 906 between the dielectric layer 908 and the metal layer 904, as described in relation to Figures 5A-5E. One or more sets of feature portions may be defined by the barrier film 906. As described in relation to Figures 5A-5E, the dielectric layer 908 may include multiple layers. The first structure 901 may include a metal-containing material 922 (e.g., metal-containing material 522 in Figure 5C) deposited inside one or more sets of feature portions. In some embodiments, the first structure 901 may include a liner 924 (e.g., liner 524 in Figure 5C) in one or more sets of feature portions such that the liner 924 is located between one or more sets of feature portions of the dielectric layer 908 and the metal-containing material 904. Depositing the polymer 926 on the first structure 901 can be achieved through any deposition method, such as vapor deposition or ALD. In some embodiments, the polymer 926 is a long-chain polymer. In some embodiments, the polymer 926 is hydrophobic. Once the polymer 926 is deposited on the first structure 901, a polymer layer 928 is formed along the upper surface of the metal-containing material 922, as shown in Figure 9B. In some embodiments, the polymer 926 burns off (e.g., is removed) from the metal-containing material 922 at temperatures above approximately 200°C. In some embodiments, the polymer 926 burns off from the metal-containing material 922 at temperatures above approximately 250°C. In some embodiments, the polymer 926 is deposited on the first structure 901 at temperatures below approximately 200°C.In some embodiments, the polymer 926 is deposited on the first structure 901 at a temperature of about 250°C or less. The exemplary temperatures of the substrate, processing chamber, and / or precursor during the deposition of the polymer 926 described herein may be about 245°C or less, about 240°C or less, about 235°C or less, about 230°C or less, about 225°C or less, about 220°C or less, about 215°C or less, about 210°C or less, about 205°C or less, about 200°C or less, or even lower. In some embodiments, the exemplary temperature can be in the range of 200°C to 250°C. By maintaining the temperature below the threshold, the polymer 926 can be deposited on the metal-containing material 922 without burning.

[0109]

[0117] In step 804, method 800 in the flow chart may include contacting the first structure with a hydrogen-containing precursor. As shown in Figure 9C, the first structure 901 can be contacted with the hydrogen-containing precursor 912 to hydroxylate the surface of the dielectric layer 908. As shown in Figure 9D, by hydroxylating the surface of the dielectric layer 908, a surface activation layer 914 can be formed on the dielectric layer 908 such that hydrogen atoms 914 are formed at positions outside the lattice of the dielectric layer 908, as shown at the atomic level of 916 in Figure 9E. On the other hand, the polymer layer 928 can be formed from a hydrophobic polymer 926. Therefore, the polymer layer 928 is not hydroxylated and does not form a surface activation layer. Similarly, the polymer layer 928 prevents the metal-containing material 922 from being hydroxylated and forming a surface activation layer. The hydrogen-containing precursor 912 can be contacted with the first structure via any suitable means, such as CVD plasma-enhanced CVD and ALD.

[0110]

[0118] In step 806, method 800 in the flow chart may include depositing a dielectric material via atomic layer deposition to form a dielectric film 910 on the dielectric layer 908. Since the deposition of the dielectric material is unlikely to extend to depositing the dielectric material on the polymer layer, depositing the dielectric material via atomic layer deposition to form a dielectric film 910 on the dielectric layer 908 can also be described as selectively depositing the dielectric material via atomic layer deposition to form a dielectric film 910 on the dielectric layer 908. As shown in Figure 9F, structure 901 can be in contact with one or more precursors 918. The precursors 918 can react with the surface of the surface activation layer 914 of the dielectric layer to deposit atomic layers of material, such as a dielectric. Since the polymer layer 928 is not hydroxylated and does not have a surface activation layer, the precursors 918 are unlikely to react with the surface of the polymer layer 928, and therefore the precursors are unlikely to deposit atomic layers of material on the polymer layer 928. Similarly, the polymer layer 928 prevents the precursor 918 from coming into contact with the metal-containing material 922, and since the metal-containing material 922 is not hydroxylated and does not have a surface activation layer, the precursor 918 is unlikely to react with the metal-containing material 922. As shown in Figure 9G, similar to a typical ALD process, the first structure 901 can be brought into contact with a first precursor, and then a second precursor (or any number of precursors), and by alternately bringing the first precursor and the second precursor (or any number of precursors) into contact, atomic layers of dielectric material are deposited to form a dielectric film 910. One or more precursors 918 can be selected to produce a particular dielectric film 910 on the surface of the dielectric layer 908. For example, in an ALD process for depositing aluminum oxide, a trimethylaluminum precursor and water can be used alternately. Any suitable combination of precursors can be used. By depositing the dielectric material as described herein, the upper surface of the metal-containing material 922 can be recessed compared to the uppermost layer of the dielectric film 910.

[0111]

[0119] In embodiments, following step 806, a determination may be made as to whether the target thickness of the dielectric film 910 has been achieved. If the target thickness of the dielectric film 910 has not been achieved, another ALD cycle may be performed. An exemplary range of target thicknesses for stopping further cycles of forming the dielectric film 910 includes about 10 nm or less. Another exemplary thickness range may include even smaller thicknesses including about 9.5 nm or less, about 9.0 nm or less, about 8.5 nm or less, about 8.0 nm or less, about 7.5 nm or less, about 7.0 nm or less, about 6.5 nm or less, about 6.0 nm or less, about 5.5 nm or less, about 5.0 nm or less, about 4.5 nm or less, about 4.0 nm or less, about 3.5 nm or less, about 3.0 nm or less, about 2.5 nm or less, about 2.0 nm or less, about 1.5 nm or less, about 1.0 nm or less, about 0.5 nm or less, or any percentage of the above numbers.

[0112]

[0120] As mentioned above, a recess depth of less than 5 nm or a dish depth of less than 5 nm can be sufficiently small for, for example, copper-copper hybrid bonding. When the recess depth or dish depth is less than 5 nm, subsequent annealing for bonding the separated copper elements can be effective because the copper can come close enough to bond to each other during the annealing step. During the annealing step, the copper elements are pushed out from the separated substrates toward each other, come into contact with each other, and can be bonded. At low annealing temperatures according to some embodiments of this technology, if dishing is not sufficiently reduced, the amount of expansion may be insufficient to allow sufficient bonding between the copper. By performing a polishing step according to this technology, dishing can be reduced, thereby improving the bonding performance between substrates at low annealing temperatures.

[0113]

[0121] After step 806, the metal-containing material 922 can be recessed into the dielectric film 910, as shown in Figures 5D and 9H. The metal-containing material 922 may be characterized by a concave shape. The metal-containing material 922 may additionally or alternatively be characterized by a dish shape with a dish depth. The lowest point of the concave shape recess after step 806, or the dish depth of the dish shape, below the upper surface of the dielectric film 910, can be about 2.0 nm or less, about 1.9 nm or less, about 1.8 nm or less, about 1.7 nm or less, about 1.6 nm or less, about 1.5 nm or less, about 1.4 nm or less, about 1.3 nm or less, about 1.2 nm or less, about 1.1 nm or less, about 1.0 nm or less, about 0.9 nm or less, about 0.8 nm or less, about 0.7 nm or less, about 0.6 nm or less, about 0.5 nm or less, or even smaller. In some embodiments, the upper surface of the metal-containing material 922 after step 806 can be about 2.0 nm or less below the upper surface 910 of the dielectric film, and may be about 1.9 nm or less, about 1.8 nm or less, about 1.7 nm or less, about 1.6 nm or less, about 1.5 nm or less, about 1.4 nm or less, about 1.3 nm or less, about 1.2 nm or less, about 1.1 nm or less, about 1.0 nm or less, about 0.9 nm or less, about 0.8 nm or less, about 0.7 nm or less, about 0.6 nm or less, about 0.5 nm or less, or even smaller. In some embodiments, the upper surface 910 of the dielectric film after step 806 can be about 2.0 nm or less above the upper surface of the metal-containing material 922, and may be about 1.9 nm or less, about 1.8 nm or less, about 1.7 nm or less, about 1.6 nm or less, about 1.5 nm or less, about 1.4 nm or less, about 1.3 nm or less, about 1.2 nm or less, about 1.1 nm or less, about 1.0 nm or less, about 0.9 nm or less, about 0.8 nm or less, about 0.7 nm or less, about 0.6 nm or less, about 0.5 nm or less, or even smaller.In some embodiments, the upper surface 910 of the dielectric film after step 806 can be about 2.0 nm or less above the lowest point of the concave recess of the metal-containing material 922 or the depth of the dish-shaped surface, and may be about 1.9 nm or less, about 1.8 nm or less, about 1.7 nm or less, about 1.6 nm or less, about 1.5 nm or less, about 1.4 nm or less, about 1.3 nm or less, about 1.2 nm or less, about 1.1 nm or less, about 1.0 nm or less, about 0.9 nm or less, about 0.8 nm or less, about 0.7 nm or less, about 0.6 nm or less, about 0.5 nm or less, or even smaller.

[0114]

[0122] In some embodiments, steps 804 and 806 are carried out at a temperature of about 200°C or less. In some embodiments, steps 804 and 806 are carried out at a temperature of about 250°C or less. In these embodiments, carrying out the process at a temperature below the temperature at which the polymer layer 928 burns off (e.g., 200°C or 250°C) suppresses or prevents the burning off of the polymer layer 928 so that the precursor does not interact with the metal-containing material 922, or so that the interaction between the precursor and the metal-containing material 922 is minimized.

[0115]

[0123] In step 808, method 800 in the flow chart may include removing the polymer layer. As shown in Figure 9H, the polymer layer 928 can be removed from the first structure 901. In some embodiments, the polymer layer 928 is removed by burning it off. For example, the chamber temperature can be raised to a temperature that burns the polymer 912 of the polymer layer 928.

[0116]

[0124] In some embodiments, the polymer layer 928 may burn off at temperatures of about 250°C or higher. In some embodiments, the polymer layer 928 may burn off at temperatures of about 300°C or higher. The exemplary temperatures of the substrate, processing chamber, and / or precursor during the burning off of the polymer layer 928 described herein may be about 250°C or higher, about 255°C or higher, about 260°C or higher, about 265°C or higher, about 270°C or higher, about 275°C or higher, about 280°C or higher, about 285°C or higher, about 290°C or higher, about 295°C or higher, or about 300°C or higher. In some embodiments, the exemplary temperatures may be in the range of 250°C to 300°C.

[0117]

[0125] In some embodiments, different steps (e.g., steps 202, 204, 206, 208, 210, 212, 402, 404, 406, 408, 410, 412, 602, 604, 606, 608, 610, 802, 804, 806, 808) and parts of different steps can be performed in different chambers of system 100. When moving the substrate from the first chamber to the second chamber, the substrate is moved without being exposed to the external atmosphere. For example, step 206 for forming a dielectric film on a dielectric layer can be performed in a different chamber than steps 202 and 204 for forming the substrate, metal layer, and dielectric layer. The use of different chambers may relate to different conditions required for different steps. For example, the chambers for etching the dielectric layer and dielectric film may require special settings due to the special properties of the dielectric material used in the dielectric film. Similarly, the CMP processes described in relation to steps 602, 604, 606, 608, and 610 can be carried out in different chambers than those used in steps 202, 204, and 206. In another embodiment, step 410 for selectively depositing a dielectric film can be carried out in different chambers than those used in steps 402 and 404 for forming the substrate, metal layer, and dielectric layer. The use of different chambers may be related to different conditions required for different processes. For example, a chamber for selectively depositing a dielectric film may require special settings due to the specific properties of the dielectric material used for the dielectric film, in contrast to the materials related to the deposition of the metal layer and / or dielectric layer. Similarly, the CMP processes described in relation to steps 602, 604, 606, 608, and 610 can be carried out in different chambers than those used in steps 402, 404, and 406.

[0118]

[0126] As used herein, the terms “about,” “generally,” or “substantially” should be interpreted as being within the range that a person skilled in the art would anticipate from the perspective of this specification.

[0119]

[0127] In the preceding section, for the sake of clarity, several specific details were provided to provide a complete understanding of various embodiments. However, it will become clear that some embodiments can be carried out without some of these specific details. In other cases, well-known structures and devices are shown in the form of block diagrams.

[0120]

[0128] The preceding descriptions provide only illustrative embodiments and are not intended to limit the scope, use, or configuration of this disclosure. Rather, the preceding descriptions of various embodiments provide disclosures that enable implementation of at least one embodiment. It should be understood that various modifications can be made to the function and configuration of the elements without departing from the concept and scope of some of the embodiments set forth in the claims.

[0121]

[0129] The preceding description provides specific details to give a complete understanding of the embodiments. However, it should be understood that the embodiments can be implemented without these specific details. For example, circuits, systems, networks, processes, and other components are shown as components in the form of block diagrams so as not to obscure the embodiments with unnecessary details. In other cases, well-known circuits, processes, algorithms, structures, and techniques are shown without unnecessary details to avoid obscuring the embodiments.

[0122]

[0130] Furthermore, individual embodiments were described as processes shown as flow charts, flow diagrams, data flow diagrams, structural diagrams, or block diagrams. While flow charts described processes as a series of processes, many of these processes can be performed in parallel or simultaneously. In addition, the order of the processes can be rearranged. A process terminates when its process is completed, but it may have additional steps not included in the diagram. A process can correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination can correspond to the function returning to a calling function or the main function.

[0123]

[0131] The term “computer-readable medium” includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying one or more instructions and / or data. A code segment or machine-executable instruction may represent any combination of a procedure, function, subprogram, program, routine, subroutine, module, software package, class, or instruction, data structure, or program segment. A code segment may be linked to another code segment or hard wafer circuit by passing and / or receiving information, data, factors, parameters, or memory content. Information, factors, parameters, data, etc., may be passed, transferred, or transmitted via any suitable means, including memory sharing, message passing, token passing, network transmission, etc.

[0124]

[0132] Furthermore, embodiments may be implemented in hardware, software, firmware, middleware, microcode, hardware description language, or any combination thereof. When implemented in software, firmware, middleware, or microcode, program code or code segments for performing the required tasks may be stored in a machine-readable medium. One or more processors may perform the required tasks.

[0125]

[0133] While the features described in the aforementioned specification are presented with reference to specific embodiments, it should be noted that not all embodiments are limited thereto. Various features and aspects of several embodiments may be used individually or in combination. Furthermore, embodiments may be used in any number of environments and applications beyond those described herein without departing from the broader ideas and scope of this specification. Therefore, this specification and the drawings are illustrative and not limiting.

[0126]

[0134] In addition, for illustrative purposes, the method has been described in a specific order. It should be understood that in alternative embodiments, the method may be performed in a different order than described. Furthermore, it should be understood that the method described above may be implemented by hardware components, or embedded in a sequence of machine-executable instructions that can be used to cause a machine, such as a general-purpose or application-specific processor or logic circuit, to implement the method. These machine-executable instructions may be stored on one or more machine-readable media, such as a CD-ROM or other type of optical disk, a floppy diskette, ROM, RAM, EPROM, EEPROM, magnetic or optical card, flash memory, or other type of machine-readable media suitable for storing electronic instructions. Alternatively, the method may be implemented by a combination of hardware and a soft wafer.

Claims

1. A semiconductor device for hybrid bonding, The first structure, A first metal layer covering the first substrate, A first dielectric layer covering the first metal layer and defining a set of one or more recessed feature portions, A dielectric film made of the first dielectric, which covers the first dielectric layer, and The first copper-containing material deposited inside the set of one or more feature portions A first structure including, The second structure is, A second metal layer covering the second substrate, A second dielectric layer covering the second metal layer and defining a second set of one or more recessed feature portions, the second dielectric layer being made of a second dielectric material different from the first dielectric, and The second copper-containing material deposited inside the second set of one or more feature portions A second structure including Equipped with, A semiconductor device in which the dielectric film of the first structure is hybrid-bonded to the second dielectric layer of the second structure, and the first copper-containing material of the first structure is in contact with the second copper-containing material of the second structure.

2. The semiconductor device according to claim 1, wherein the first dielectric layer is composed of the second dielectric.

3. The semiconductor device according to claim 1, wherein the first dielectric comprises silicon carbonitride and the second dielectric comprises silicon oxide.

4. The semiconductor device according to claim 1, wherein the first dielectric comprises silicon oxynitride and the second dielectric comprises silicon oxide.

5. The semiconductor device according to claim 1, wherein the dielectric film has a thickness of 5 nm.

6. The semiconductor device according to claim 1, wherein the first copper-containing material is characterized by a dish shape with a dish depth of about 1 nm or less.

7. A method for forming a semiconductor device, To form the first structure, Forming a first metal layer on a first substrate, Forming a first dielectric layer on the first metal layer, A dielectric film composed of the first dielectric is formed on the first dielectric layer. Etching trenches into the dielectric film and the first dielectric layer, extending downward from the upper surface of the dielectric film to at least the upper surface of the first metal layer, and The trench is filled with the first copper-containing material. Forming a first structure including, The first structure is brought into contact with the second structure, wherein the second structure is A second metal layer covering the second substrate, A second dielectric layer covering the second metal layer and defining a second set of one or more feature portions, the second dielectric layer being made of a second dielectric material different from the first dielectric, and The second copper-containing material deposited inside the second set of one or more feature portions Including bringing the first structure into contact with the second structure, The first structure is joined to the second structure, wherein the dielectric film of the first structure is hybrid-bonded to the second dielectric layer of the second structure, and the first copper-containing material of the first structure is in contact with the second copper-containing material of the second structure. A method that includes this.

8. The method according to claim 7, wherein etching the trenches in the dielectric film and the first dielectric layer includes etching the trenches in the dielectric film using chlorine-based etching.

9. The method according to claim 7, wherein etching the trenches in the dielectric film and the first dielectric layer includes etching the trenches in the dielectric film and the first dielectric layer using multi-material etching, and the multi-material etching includes two or more of chlorine-based etching, fluorine-based etching, oxygen-plasma etching, and fluorine-oxygen-based etching.

10. The method according to claim 7, wherein forming the first metal layer and forming the first dielectric layer is carried out in a first chamber, etching the trenches in the dielectric film and the first dielectric layer is carried out in a second chamber, and the first structure is moved from the first chamber to the second chamber without exposing the first substrate to the external atmosphere.

11. The method according to claim 7, further comprising bringing the first structure into contact with one or more slurries and one or more platens, wherein the one or more slurries and the one or more platens remove a portion of the first copper-containing material and a second portion of the dielectric film.

12. The method according to claim 11, wherein bringing the first structure into contact with the one or more slurries and the one or more platens causes the first copper-containing material to recede by a distance of about 1 nm or less inside the trench below the upper surface of the dielectric film.

13. The method according to claim 7, further comprising forming a liner in the trench, wherein filling the trench with the first copper-containing material comprises covering the liner with the first copper-containing material.

14. A method for forming a semiconductor device, To form the first structure, Forming a first metal layer on a first substrate, Forming a first dielectric layer on the first metal layer, Etching trenches into the first dielectric layer, extending downward from the upper surface of the first dielectric layer to at least the upper surface of the first metal layer, Filling the trench with the first copper-containing material, The method involves selectively depositing a dielectric film on the first structure, wherein the dielectric film covers the first dielectric layer but does not cover the first copper-containing material, and the dielectric film is composed of a first dielectric. Forming a first structure including, The first structure is brought into contact with the second structure, wherein the second structure is A second metal layer covering the second substrate, A second dielectric layer covering the second metal layer and defining a second set of one or more feature portions, the second dielectric layer being made of a second dielectric material different from the first dielectric, and The second copper-containing material deposited inside the second set of one or more feature portions Including bringing the first structure into contact with the second structure, The first structure is joined to the second structure, wherein the dielectric film of the first structure is hybrid-bonded to the second dielectric layer of the second structure, and the first copper-containing material of the first structure is in contact with the second copper-containing material of the second structure. A method that includes this.

15. The method according to claim 14, wherein the first dielectric comprises silicon oxide and the second dielectric comprises silicon oxynitride.

16. The method according to claim 14, wherein the first dielectric comprises silicon oxide and the second dielectric comprises silicon carbonitride.

17. The method according to claim 14, further comprising bringing the first structure into contact with one or more slurries and one or more platens, wherein the one or more slurries and the one or more platens remove a portion of the first copper-containing material and a second portion of the first dielectric layer, and bringing the first structure into contact with the one or more slurries causes the first dielectric layer to recede by a distance of about 5 nm or more from the upper surface of the first copper-containing material.

18. The method according to claim 14, wherein the first dielectric layer is composed of a third dielectric, and the third dielectric is made of a material different from the first dielectric and the second dielectric.

19. Selectively depositing the dielectric film on the first structure is Depositing a polymer on the first structure, wherein the polymer forms a single layer on the first copper-containing material, and the polymer does not form the single layer on the first dielectric layer. A method for depositing a dielectric material on the first structure via atomic layer deposition, wherein the dielectric material forms a dielectric film on the first dielectric layer, and the dielectric film is not formed on the first copper-containing material, and Remove the aforementioned single layer. The method according to claim 14, including the method described in claim 14.

20. The method according to claim 19, wherein the deposition of the polymer includes deposition of a long-chain polymer by vapor deposition.

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