Title of the invention: Method for manufacturing semiconductor material arm arrays and batch manufacturing method for semiconductor material arm array interface layers

Abstract

The present invention relates to a method for manufacturing a semiconductor material arm array and a batch manufacturing method for an interface layer of a semiconductor material arm array, the manufacturing method of the semiconductor material arm array includes placing a semiconductor block material on the surface of an extrusion die, putting the semiconductor block material and the extrusion die into a pressure-resistant sleeve, plastically deforming the semiconductor block material by extrusion to fill cavities arranged in an array on the surface of the extrusion die, and obtaining the semiconductor material arm array after demolding.

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor material arm array and a batch fabrication method for an interface layer of a semiconductor material arm array, which belongs to the field of semiconductor materials and devices. [Background technology]

[0002] Although small semiconductor devices are expected to be widely applied in many fields (for example, the realization of accurate temperature control by active cooling in the microzone of micro thermoelectric devices, and the field of self-powered wearable devices), as semiconductor devices become finer, the manufacture of high-density and high-integration n-type and p-type semiconductor material arms and their arrays, which are the core functional components, faces many difficulties. On the other hand, as devices become finer, the size of the semiconductor material arms is significantly reduced, and their efficient manufacture is a major challenge. Conventionally, semiconductor material arms are obtained by cutting a semiconductor material block. When the size of the material arms is reduced to the submillimeter level, the cutting yield is significantly reduced, but the cutting work amount and line loss are significantly increased, and the difficulty and cost of manufacturing are also significantly increased. For brittle thermoelectric semiconductor materials, when the size of the material arms is smaller than 0.3 mm, the cutting process cannot basically be carried out. On the other hand, as devices become finer, it is difficult to efficiently complete the arrangement of material arm arrays using conventional processes. Taking the micro thermoelectric device as an example, currently, it is common to pick up single n-type and p-type thermoelectric material arms obtained by cutting and move them to a pre-installed mold to realize array arrangement. As the size of the thermoelectric arm is reduced from the conventional several mm to 0.3 mm to 0.1 mm or less, it is difficult and costly to pick up and move hundreds to thousands of thermoelectric arms using the conventional method. At the same time, as the spacing between adjacent thermoelectric arms in the array is greatly reduced, the inherent gap between the thermoelectric arm and the pre-installed mold significantly affects the array arrangement accuracy, making it difficult to effectively control the device quality.

[0003] And in the manufacturing process of normal mm-level or cm-level semiconductor material arm arrays, the existing technology also has many shortcomings. Meanwhile, in the existing technology, the semiconductor material arm is manufactured based on the cutting method, but the cutting speed of one machine is slow and the productivity is low, so large-scale production requires the purchase of many cutting machines and corresponding labor, which increases the equipment cost and labor cost. In addition, the cutting process also causes a large amount of material loss and environmental pollution. Meanwhile, in the existing technology, the semiconductor material arm is mainly picked up and moved one by one manually by a positioning frame plate to realize the array arrangement, so it is difficult to significantly improve the productivity and effectively control the quality of the product.

[0004] As a result, the manufacture of semiconductor material arm arrays based on existing technology is an inefficient, environmentally-intensive, and labor-intensive process. Existing technology has many challenges when manufacturing regular-sized semiconductor material arm arrays, and even more challenges when manufacturing micro-sized semiconductor material arm arrays. Therefore, developing a new manufacturing method for semiconductor material arm arrays to realize high-quality, low-cost, and mass production is of great value to promoting the development of regular-sized semiconductor devices and promoting the development of miniaturization of devices.

[0005] In addition, in semiconductor devices, the functional elements of n-type and p-type semiconductor materials must be connected to the circuit in some way to ensure the normal operation of the device. Take a thermoelectric device as an example, its core functional element is a thermoelectric arm, which is generally a columnar n-type or p-type semiconductor material. The n-type and p-type thermoelectric arms are arranged in an alternating manner and connected to the metal current-conducting layers of the upper and lower circuit boards, forming an overall electrical series connection and thermal parallel connection. Generally, the connection between the semiconductor material arm and the circuit is realized by welding. In order to obtain the required interfacial bonding strength and contact performance, the semiconductor material arm must first be metallized, that is, an interface layer must be fabricated on the upper and lower end surfaces of the arm, and the interface layer and the circuit must be connected by solder. Thus, the fabrication of the semiconductor material arm interface layer is an important step in the device fabrication process. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2002-158379 A [Patent Document 2] China Patent Application Publication No. 112602203 [Patent Document 3] China Patent Application Publication No. 112602204 [Patent Document 4] China Patent Publication No. 103413888 Summary of the Invention [Problem to be solved by the invention]

[0007] Conventionally, semiconductor material arms are generally manufactured based on a cutting process, while the arrangement of material arm arrays is realized by a pick-up and moving process. Taking a thermoelectric device as an example, the adverse effects of the above process on the manufacturing of semiconductor material arm interface layers are explained. In the field of thermoelectric devices, the size of the material arms currently widely used is at the submillimeter to centimeter level, and there are mainly two methods for manufacturing the material arm interface layer. One is a method in which the interface layer is deposited on the entire material mass and then cut to obtain a material arm with an interface layer, and the other is a method in which the material mass is cut to obtain a semiconductor material arm and the interface layer is batch deposited. The former may cause damage and contamination to the interface layer during cutting, and the latter is not suitable for batch manufacturing because it is necessary to fix the material arm with a clamp, and it is difficult to prevent the metallization of the side of the material arm when depositing the interface layer. In recent years, micro-thermoelectric devices have become a research hotspot because of the expected wide application in the fields of precise temperature control in micro zones and self-powered wearable devices. As the size of the material arm is reduced, the damage to the interface layer in the cutting process becomes more prominent. At the same time, the number of material arms in the micro thermoelectric device is hundreds to thousands, and the size is at the micron level. Considering the difficulty and cost of operation, the conventional process is not suitable for batch manufacturing of the material arm interface layer.

[0008] In response to the above problems, the present invention provides a batch fabrication method for a semiconductor material leg array and a semiconductor material leg array interface layer.

[0009] In a first aspect, the present invention provides a method for manufacturing a semiconductor material arm array, characterized in that a semiconductor block material is placed on a surface of an extrusion die, the semiconductor block material and the extrusion die are placed in a pressure-resistant sleeve, the semiconductor block material is plastically deformed along the pressure direction by extrusion to fill cavities arranged in an array on the surface of the extrusion die, and after demolding, the semiconductor material arm array is obtained.

[0010] Preferably, the extrusion die includes a rigid base and cavities arranged in an array in the rigid base, the rigid base being a metal base (eg, a steel base) or a ceramic base.

[0011] Preferably, the shape of the projection of the cavity on a plane parallel to the surface of the rigid base is a circle, a rectangle, a triangle, a trapezoid, or a sector, and the shape of the projection in a direction perpendicular to the surface of the rigid base is a rectangle or a trapezoid.

[0012] Preferably, when the shape of the projection of the cavity in a direction perpendicular to the surface of the hard base is a trapezoid, the base angle of the trapezoid is >90° and ≦135°, preferably 92° to 100°. In this range, the corresponding thermoelectric arm is slightly tapered, which is advantageous for demolding, while the taper of the thermoelectric arm is not large, so that the difference in size of the thermoelectric arm at different points in the height direction of the thermoelectric arm is small, which avoids the complication of the thermoelectric device configuration and performance design.

[0013] Preferably, the size of the projection of the cavity on a plane parallel to the surface of the hard base is from 1 μm to 20 mm, more preferably from 1 μm to 3000 μm, and even more preferably from 30 μm to 500 μm.

[0014] Preferably, the shortest distance between the centers of adjacent cavities is from 3 μm to 20 mm, more preferably from 50 to 800 μm.

[0015] Preferably, the depth of the cavity is from 1 μm to 50 mm, more preferably from 10 μm to 3 mm.

[0016] Preferably, the relative deviation between the diameters of the semiconductor block material and the extrusion die and the inner diameter of the pressure sleeve is ≦5%. Preferably, the absolute deviation between the diameters of the semiconductor block material and the extrusion die and the inner diameter of the pressure sleeve is ≦0.2mm. During the extrusion process, plastic deformation of the material occurs in the pressure sleeve, and the diameters of the block material and the extrusion die correspond to the inner diameter of the pressure sleeve (relative deviation ≦5% and absolute deviation ≦0.2mm), ensuring that deformation of the block material occurs mainly in the pressure direction during the extrusion process.

[0017] In the present invention, based on the plasticity of bulk semiconductor material, the semiconductor material arms and their arrays are integrally molded by an extrusion process, thereby realizing high quality, low cost, and mass production of semiconductor material arm arrays.

[0018] Preferably, the semiconductor bulk material is a semiconductor material having inherent plasticity, a composite material having plasticity made of a semiconductor material having inherent plasticity and a material having inherent non-plasticity, or a mud-like mixture made based on a semiconductor material having inherent non-plasticity. Also, preferably, the composition of the semiconductor bulk material is a Ag-based semiconductor material (Ag2S x M 1-x , M element is Se or Te, 0≦x≦1), Cu-based semiconductor material (Cu 2-y Ag y Se 1-z M z , 0≦y≦1, 0≦z≦1, M element is S or Te), a Bi-Te based semiconductor material, and a mud-like mixture containing a Bi-Te based semiconductor material as a main component.

[0019] Preferably, the extrusion temperature is 5 to 500°C, more preferably 30 to 250°C, and is equal to or higher than the softening temperature of the semiconductor bulk material. The extrusion pressure is 1 MPa to 10 GPa, preferably 100 MPa to 1 GPa. The pressure holding time of the extrusion is 1 to 100 minutes, preferably 10 to 40 minutes. The demolding temperature is higher than the softening temperature of the semiconductor bulk material, preferably 10 to 170°C. Among them, the semiconductor bulk material is subjected to an extrusion process, and the extrusion temperature is continuously increased from room temperature until the semiconductor bulk material is plastically deformed without bursting, and the temperature is defined as the softening temperature of the semiconductor material. By setting an appropriate extrusion temperature and pressure as required, not only is the semiconductor material reliably extruded, but also costs (energy consumption and die wear) are reduced.

[0020] In a second aspect, the present invention provides a semiconductor material arm array manufactured by the above manufacturing method, comprising a semiconductor material arm and an array integrally molded with the semiconductor material arm, wherein the size, arrangement and pattern design of the semiconductor material arm array correspond to the cavity in the extrusion die respectively.

[0021] In a third aspect, the present invention provides a method for producing ... composition comprising the steps of: (1) selecting an organic binder as an inlay material, injecting it into the semiconductor material arm array produced by the above-mentioned extrusion method to realize a mosaic of the entire organic binder, and after the inlay material is hardened, achieving flattening of the end surface of the semiconductor material arm array by physical processing or / and chemical processing, thereby obtaining a semiconductor material arm array containing the inlay material; (2) depositing an interface layer on a surface of the semiconductor material arm array including the inlay material, and then removing the inlay material and the interface layer attached to the surface of the inlay material, thereby achieving batch fabrication of the semiconductor material arm array interface layer; The present invention provides a batch fabrication method for a semiconductor material arm array interface layer, comprising:

[0022] For semiconductor materials having a certain degree of plasticity, the present inventor has developed a technique for manufacturing semiconductor material arms and their arrays by an extrusion molding process (extrusion method). Specifically, n-type and p-type materials are extruded through a die with a cavity array, respectively, and then demolded, and n-type and p-type semiconductor material arm arrays connected to a base material are obtained. Compared with the existing cutting process, the difficulty and cost of manufacturing semiconductor material arms and their arrays by an extrusion molding process are greatly reduced, and since the material arms and their arrays are integrally molded, there is no need for complicated movement and arrangement of the material arms. This process not only allows the existing normal-sized semiconductor arms and their arrays to be manufactured, but is also particularly suitable for manufacturing hundreds or thousands of micro-type semiconductor material arms and their arrays, each having a size of hundreds to tens of microns. However, in order to realize the batch manufacturing of the semiconductor material arm array interface layer, the following problems need to be solved. (1) The end faces of the semiconductor material arms need to meet certain flatness and appearance requirements to ensure reliable bonding between the end faces and the interface layer. (2) The uniformity of the height of the semiconductor material arm needs to meet specific requirements, so as to ensure the parallelism of the upper and lower substrates of the device and avoid interface soldering in the process of integrating the device. (3) The interface layer should be limited to the end surface of the semiconductor material arm array and does not affect its side surface. In addition, the present invention creatively performs overall mosaic (the inlay material is organic binder), end surface treatment, metallization deposition (interface layer deposition) and mosaic removal on the semiconductor material arm array, so that the required flatness and appearance form of the material arm end surface are obtained, the required uniformity of the height of the material arm is obtained, and the interface layer is located only on the material arm end surface and does not affect its side surface. This method is easy to operate, has low cost, and is suitable for batch manufacturing of the interface layer of the semiconductor material arm array.

[0023] Preferably, the inlay material is selected from one of photoresist (e.g., SU-8, AZ5214, UVN, etc.), PDMS, ABglue, cold-hot inlay material (e.g., phenolic resins of brands such as Epple, Sanling Jinsang, and Ka-ke), and ethyl cyanoacrylate.

[0024] Preferably, the physical and / or chemical treatment is at least one of mechanical polishing, chemical polishing, etching and chemical etching.

[0025] Preferably, after the end surface of the semiconductor material arm array is planarized and before the interface layer is deposited, the appearance morphology of the end surface of the semiconductor material arm array is adjusted, and more preferably, the appearance morphology of the end surface is adjusted by using sandblasting, chemical corrosion or chemical etching to increase the end surface roughness.

[0026] Preferably, the interface layer is selected from at least one of Cu, Ni, Al, In, Te, Sb, Bi, Ge, Pb, Ga, Zn, Cd, Pd, Pt, V, Ta, Hf, Fe, Co, Mn, Ru, Rh, Ir, Mo, Nb, W, Ti, Cr, Zr, Sn, Ag, Au, Pt, TiN, doped ZrO2, ThO2, LaCrO2, LaNiO2, LaMnO3(sr), CoCrO4, LaCoO3(sr), InO2 / SnO2, SiC, MoSi2, the number of layers of the interface layer is ≧1, and the thickness of the interface layer is 10 nm to 20 μm, more preferably 1 to 10 μm.

[0027] Preferably, the inlay material and the interface layer adhering to the inlay material are removed by at least one of heating, light irradiation, chemical dissolution, and ultrasonic treatment. Effect of the Invention

[0028] In the present invention, the plasticity of the semiconductor material is fully utilized, and the thermoelectric arm of the same material is formed by extrusion, and the size of the semiconductor material arm is determined by the size of the cavity in the extrusion die. Therefore, a) compared with various cutting processes, the limitation on the material arm size due to the mechanical properties of the semiconductor material is broken through, and the material arm size can be easily reduced to 0.3 mm to 0.1 mm or less. b) compared with various deposition processes, this method can efficiently manufacture semiconductor material arms with heights of microns to millimeters at low cost, and the aspect ratio of the material arm can be adjusted in a large range, which is favorable for optimizing the performance of semiconductor devices.

[0029] In the present invention, the array of homogeneous semiconductor material arms is not arranged by sequentially picking up independent material arms and moving them one by one, but is integrally formed by extrusion. Therefore, a) the array forming process is greatly simplified, and low-cost mass production can be realized. b) The quality control of the array is very convenient (different arrays extruded by the same die have exactly the same shape and arrangement of their material arms). c) It breaks through the limitations of the positioning accuracy of the semiconductor material arms in the array in the conventional manufacturing method, and is favorable for further miniaturization of the corresponding devices.

[0030] Compared with the conventional method, the present invention has less material loss during the fabrication process of the array, and this advantage is even more obvious as the array size is reduced. This is because the material loss caused by the fabrication method of the present invention is caused by the need to remove the base material connected to the array, and is independent of the height and cross-sectional size of the semiconductor material arm, making it easy to control. The material loss caused by the conventional cutting method is related to the height and cross-sectional area of ​​the semiconductor material arm. As the material arm size is reduced, the rate of material loss necessarily increases at an accelerating rate.

[0031] The extrusion molding technique of the material arm array of the present invention is widely applicable. In terms of material, the method can be used to manufacture a corresponding semiconductor material arm array for materials that have inherent plasticity under specific conditions or that exhibit plasticity through a specific process. In terms of size, if an extrusion die of a corresponding size can be manufactured, the size of the semiconductor material arm can be realized from microscopic (μm level) to macroscopic (mm level to cm level).

[0032] By performing global mosaic on the semiconductor material arm array, the present invention can effectively strengthen a single material arm and avoid mechanical damage during subsequent processing (eg, polishing, sandblasting).

[0033] By selecting an appropriate inlay material, the present invention makes it possible to easily remove the inlay material and the interface layer adhering to the inlay material after forming an interface layer on the end surface of the semiconductor material arm, leaving only the interface layer on the end surface of the semiconductor material arm.

[0034] The method is low cost, easy to operate, and suitable for mass production because it does not require fabricating a mask that precisely matches the semiconductor material arm array, and does not require photolithography processes and related precision equipment. [Brief description of the drawings]

[0035] [Figure 1] FIG. 2 is a plan view schematic diagram of the semiconductor material arm array according to Example 1 (similar to the plan view schematic diagrams of the semiconductor material arm array according to Examples 2 and 4 to 7). [Figure 2a] The extrusion die used in Example 1 (the extrusion dies used in the other examples are similar in appearance to that shown in FIG. 2a). [Figure 2b] The extrusion die used in Examples 4-5 (the extrusion dies used in the other Examples have an appearance similar to that shown in FIG. 2a). [Diagram 3] 1 shows the pressure-resistant sleeve and pressure head used in Examples 1 to 4 and 6 to 7. [Figure 4a] 1 is a semiconductor material arm array obtained by the manufacturing method of the present invention according to Example 1. [Figure 4b] 11 is a semiconductor material arm array obtained by the manufacturing method of the present invention according to Example 2. [Figure 4c] 11 is a semiconductor material arm array obtained by the manufacturing method of the present invention according to Example 6. [Figure 5a] 1 is an extrusion die used in Example 3. [Figure 5b] 2 is a semiconductor material arm array obtained by the manufacturing method of the present invention. [Figure 6a] The extrusion die and its accessories used in Example 4 (circular on the outside, square on the inside). [Figure 6b] 2 is a semiconductor material arm array obtained by the manufacturing method of the present invention. [Figure 7a] 1 shows an extrusion die and a semiconductor block material thereon before extrusion in Example 5. [Figure 7b] 11 shows a semiconductor material extruded without using a pressure-resistant sleeve and an extrusion die in Example 5. [Figure 7c] 13 is a semiconductor material arm array obtained after demolding in Example 5. [Figure 8a] 13 is a cavity array of an extrusion die before extrusion in Example 7. [Figure 8b] 13 is an extrusion die cavity array in Example 7 in which a large number of semiconductor material arms remain broken due to the demolding temperature being too low after extrusion. [Figure 9] 1 is an Ag2S material arm array obtained by superheated extrusion in Example 8. [Figure 10] 13 is a material arm array sample subjected to overall mosaic in Example 8. [Figure 11] This is a material arm array sample in Example 8 in which the end surfaces were flattened by performing overall mosaic. As can be seen from the drawing, the material arms are embedded in the inlay material, and only the flattened top end surfaces are exposed. [Figure 12] This is a material arm array in which the Cu interface layer in Example 8 has been deposited and the inlay material and the Cu interface layer adhering to the inlay material have been removed. As can be seen from the drawing, the Cu interface layer only covers the upper end surface of the material arm and does not affect the side surface of the material arm. [Figure 13] 13 is a Cu2Se material arm array obtained by superheated extrusion in Example 9. [Figure 14] In Example 9, the material arm array sample was subjected to overall mosaic by UVN, followed by end face planarization, sandblasting, metallization and mosaic removal. As can be seen from the figure, the metal interface layer only covers the top end surface of the material arm and does not affect the side surface of the material arm. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] The present invention will now be further described with reference to the following examples, which are intended to illustrate, but not to limit, the present invention.

[0037] The manufacturing process of the semiconductor material arm array in the present invention mainly includes the steps of designing and manufacturing an extrusion die, and molding the n(p) type semiconductor material arm array integrally through the extrusion process and demolding it. This method allows the semiconductor material arm and its array to be integrally molded, realizing high quality, low cost and mass production of the semiconductor material arm array.

[0038] Select an appropriate material to manufacture the extrusion die. The material of the extrusion die must have sufficient pressure resistance so that it will not be deformed during repeated heating and cooling and extrusion processes and affect the accuracy of the array. According to the parameters of the extrusion process of different semiconductor materials, the corresponding die material can be steel materials such as hard alloy steel, high speed steel, mold steel, stainless steel, etc., metal materials such as W, Mo, Nb, Ti, etc., ceramic materials such as ZrO2, Al2O3, AlN, Si3N4, etc., or inorganic or organic materials with the required pressure resistance and processing performance. In a preferred embodiment, the die material is mold steel. The extrusion die further includes a pressure head, etc.

[0039] According to the parameters of the semiconductor material arms and arrays, a corresponding cavity array is processed on the surface of the mold material. Specifically, according to the parameters of the semiconductor material arm array, such as the shape, interval and arrangement of the material arms, a corresponding cavity array is manufactured on the surface of the mold material by using techniques such as mechanical drilling, laser drilling or etching drilling. The horizontal projection of the cavity of the mold may be circular, rectangular, triangular, trapezoidal, sectoral or other irregular shapes, and the vertical projection of the cavity may be rectangular, trapezoidal or other irregular shapes. In order to facilitate demolding, the inner wall of the cavity is as smooth as possible, and the projection of the cavity on a plane perpendicular to the mold surface may be rectangular or trapezoidal, and its base angle may be 90°-135°, preferably 92°-100°. The size of the projection of the cavity on a plane parallel to the surface of the hard base may be 1 μm to 20 mm, preferably 1 μm to 3000 μm, more preferably 20 to 500 μm, even more preferably 30 μm to 200 μm, and most preferably 50 μm to 200 μm. The shortest distance between the centers of adjacent cavities may be 3 μm to 20 mm, preferably 50 to 800 μm. The depth of the cavity may be 1 μm to 50 mm, preferably 10 μm to 3 mm. In a preferred embodiment, laser drilling is used to fabricate the cavity array, the diameter of the bottom of the cavity is about 70 μm, the depth of the cavity is about 200 μm, and the base angle of the trapezoid of the projection is about 92°. In another preferred embodiment, the cavity array is fabricated using mechanical drilling, the diameter of the bottom of the cavity is about 200 μm, the depth of the cavity is about 400 μm or 500 μm, the base angle of the projection trapezoid is about 92°, and the shortest distance between the centers of adjacent cavities is about 707 μm. In another preferred embodiment, the cavity array is fabricated using mechanical drilling, the diameter of the bottom of the cavity is about 150 μm, the depth of the cavity is about 300 μm, and the base angle of the projection trapezoid is about 100°.In another preferred embodiment, mechanical drilling is used to fabricate a cavity array, the cavity diameter is about 200 μm, the cavity depth is about 600 μm, and the projection of the cavity onto a plane perpendicular to the surface of the mold is rectangular.

[0040] The n(p)-type semiconductor mass material is placed in the cavity array of the extrusion die, and then the semiconductor mass material and the extrusion die are placed in a pressure sleeve with an inner diameter equal to or slightly larger than that of the extrusion die (the relative deviation in size is ≦5% and the absolute deviation is ≦0.2mm), and the material is plastically deformed by extrusion. In the extrusion process, the pressure sleeve suppresses the lateral deformation of the semiconductor material and deforms the material (mainly) in the pressure direction to fill all the cavities. By setting the appropriate extrusion temperature, pressure and dwell time according to the properties of the specific semiconductor material, it is possible not only to ensure that the material is extruded (fills the cavities), but also to reduce costs (energy consumption and die wear) and minimize the impact of extrusion on the material performance.

[0041] In an alternative embodiment, the semiconductor bulk material is a Ag-based semiconductor material, Ag2S. x M 1-x The M element may be Se or Te, x may be 0≦x≦1, and the extrusion temperature may be 5 to 170°C, the extrusion pressure may be 100MPa to 1GPa, and the holding time may be 10 to 60 minutes. In a preferred embodiment, the extrusion temperature of the Ag2S material is 20°C, the pressure may be 1.5GPa, and the holding time may be 10 minutes. In another preferred embodiment, the extrusion temperature of the Ag2S material is 80°C, the pressure may be 500MPa, and the holding time may be 40 minutes. In another preferred embodiment, the extrusion temperature of the Ag2S material is 140°C, the pressure may be 200MPa, and the holding time may be 60 minutes.

[0042] In an alternative embodiment, the semiconductor bulk material is a Cu-based semiconductor material (Cu 2-y Ag y Se 1-z M z, 0≦y≦1, 0≦z≦1, M element may be S or Te), and the extrusion temperature may be 180-300°C, the extrusion pressure may be 300MPa-1.5GPa, and the pressure holding time may be 10-60 minutes. In a preferred embodiment, the extrusion temperature of the Cu2Se material is 250°C, the pressure is 1GPa, and the pressure holding time is 40 minutes.

[0043] After the extrusion is completed, the semiconductor material arms are separated from the extrusion die by demolding to obtain a semiconductor material arm array that is composed of n(p)-type semiconductor material arms similar to the cavity shape and the arrangement of the material arms matches the die cavity array. For different semiconductor bulk materials, it is necessary to set an appropriate demolding temperature in this process according to the properties of the semiconductor bulk material. Preferably, the demolding temperature should be slightly higher than the material softening temperature, usually 10-50°C higher. If the temperature is too low, the thermoelectric arms become brittle and easily break due to tension during the demolding process, and the broken thermoelectric arms remain in the extrusion die cavity, making the die unusable and making it impossible to obtain a complete thermoelectric arm array. If the temperature is too high, the material is too soft and easily deformed and even broken due to tension. After demolding, a semiconductor material arm array connected to the base material is obtained, and the shape and array arrangement of the material arms completely match the die cavity array.

[0044] In an alternative embodiment, the semiconductor bulk material is a Ag-based semiconductor material, Ag2S. x M 1-x The M element is Se or Te, x is 0≦x≦1, and after completion of extrusion, the demolding temperature is 10 to 80°C, preferably 20 to 40°C.

[0045] In an alternative embodiment, the semiconductor bulk material is a Cu-based semiconductor material (Cu 2-y Ag y Se 1-z M z , 0≦y≦1, 0≦z≦1, M element may be S or Te), and after completion of extrusion, the demolding temperature may be 130-220°C, preferably 150-170°C.

[0046] Appropriate processing of the end faces of the semiconductor material arms in the array facilitates subsequent end face metallization and integration of semiconductor devices.

[0047] In the present invention, the resulting semiconductor material arms are connected to the base material, the shape of the semiconductor material arms is similar to the cavity of the mold, and the arrangement of the material arm array matches the arrangement of the mold cavity array.

[0048] In the present disclosure, the batch manufacturing process of the interface layer on the end face of the semiconductor material arm mainly includes the steps of overall mosaic of the material arm array, planarization of the material arm end face, appearance morphology processing of the end face, interface layer manufacturing on the end face, and mosaic removal, so that the interface layer can be manufactured on the end face of the material arm without affecting the side face of the material arm.

[0049] In the present disclosure, the high quality, low cost and mass production of the interface layer of the semiconductor material arm array can be realized, which can strongly support the integrated manufacturing of semiconductor thermoelectric devices. The batch manufacturing process of the interface layer of the semiconductor material arm end surface is exemplified below.

[0050] The semiconductor material arm array is manufactured by the above-mentioned extrusion molding. The manufacturing process of the semiconductor material arm array mainly includes the steps of designing and manufacturing an extrusion die, and integrally molding an n(p) type semiconductor material arm array by an extrusion process and demolding it. This method allows the semiconductor material arm and its array to be integrally molded, and realizes high quality, low cost and mass production of the semiconductor material arm array.

[0051] Inlay material is added between the semiconductor material arm array obtained by extrusion molding, so that the array and the inlay material are integrally formed. The array is strengthened by mosaic, so that the semiconductor material arm is prevented from being mechanically damaged in the subsequent processing. The above-mentioned inlay material can be various photoresists (such as SU-8, AZ5214, UVN, etc.), PDMS, AB adhesive, cold-hot inlay materials (such as phenolic resins of brands such as epple, Sanling Jinso, and Huake) and organic binders such as ethyl cyanoacrylate.

[0052] By suitable end surface treatment, the height of the material arm can be precisely adjusted, the required end surface appearance can be obtained, and the reliable bonding between the material arm and the interface layer can be realized. After the inlay material is hardened, the end surface of the semiconductor material arm can be suitable treated by methods such as mechanical grinding, chemical polishing, chemical etching or chemical etching to obtain a flat end surface with a required size and perpendicular to the height direction of the material arm, and the height of each material arm can reach a required uniformity. Preferably, the flat end surface can be further treated, such as sandblasting, chemical etching or chemical etching, as required, to obtain a required surface appearance and improve the bonding between the interface layer and the end surface.

[0053] An interface layer is manufactured on the surface of the mosaic sample of the semiconductor material arm array that has undergone the above-mentioned processing. The manufacturing method includes physical vapor deposition, screen printing, electroplating, and chemical plating. The interface layer may be one or more of metals such as Cu, Ni, Al, In, Te, Sb, Bi, Ge, Pb, Ga, Zn, Cd, Pd, Pt, V, Ta, Hf, Fe, Co, Mn, Ru, Rh, Ir, Mo, Nb, W, Ti, Cr, Zr, Sn, Ag, Au, and Pt, and may be conductive ceramics such as TiN, doped ZrO2, ThO2, LaCrO2, LaNiO2, LaMnO3(sr), CoCrO4, LaCoO3(sr), InO2 / SnO2, SiC, and MoSi2, and the interface layer may be a single layer structure or a multi-layer structure. The thickness of the interface layer may be 10 nm to 20 μm, and preferably 1 to 10 μm.

[0054] By removing the inlay material and the interface layer attached to the inlay material by heating, light irradiation, chemical dissolution, ultrasonic treatment or a combination thereof, etc., a semiconductor material arm array is obtained in which the interface layer is attached only to the end surface of the material arm and the height uniformity of the material arm satisfies the requirements. Because the thickness of the interface layer is thin, when the inlay material is removed, the interface layer collapses and is removed together with the inlay material.

[0055] In alternative embodiments, different removal methods can be used for different inlay materials. For example, for ethyl cyanoacrylate, some AB adhesives and cold-hot inlay materials, it can be removed by acetone. For various photoresists, it can be removed by corresponding developers. For PDMS, it can be removed by dichloromethane.

[0056] The array of semiconductor material arms with the interface layer deposited thereon can be bonded to corresponding circuitry by an appropriate process.

[0057] The present invention will be described in detail below with further examples. The following examples are for further illustrating the present invention, and are not intended to limit the scope of the present invention. Any non-essential improvements and adjustments made by those skilled in the art based on the above content of the present invention are all within the scope of protection of the present invention. The specific process parameters in the following examples are merely examples of suitable ranges, that is, those skilled in the art can select within the suitable ranges through the description in this specification, and are not limited to the specific values ​​exemplified.

[0058] Example 1 A cavity array was fabricated on the surface of mold steel (HRC=60) by a mechanical drilling process, as shown in Figures 1 and 2a. The diameter of the bottom of the cavity was about 200 μm, the depth of the cavity was about 500 μm, and the projection of the cavity on a plane perpendicular to the mold surface was a trapezoid, with its base angle being about 92°.

[0059] The Ag2S material was processed into a block with a diameter of 9.90 mm and a thickness of 1 mm, which was placed on top of the extrusion die cavity array, and the material and the extrusion die were sequentially placed in a pressure-resistant sleeve with an inner diameter of 10 mm. At room temperature of 20°C, the pressure was increased to 1.5 GPa at a pressure increase rate of 0.2 GPa / s, and the pressure was held for 10 min before being released. The mold was removed at 20°C to obtain an Ag2S thermoelectric arm array (shown in Figure 4a) connected to the base material.

[0060] Example 2 A micro-cavity array was fabricated on the surface of mold steel (HRC=50) by a mechanical drilling process, as shown in Fig. 1. The diameter of the bottom of the cavity was about 150 μm, the depth of the cavity was about 300 μm, and the projection of the cavity in the plane perpendicular to the mold surface was a trapezoid, with a base angle of about 100°.

[0061] The Ag2S material was processed into a lump with a diameter of 9.90 mm and a thickness of 1 mm, which was placed in an extrusion die cavity array, and the material and extrusion die were sequentially placed in a pressure-resistant sleeve with an inner diameter of 10 mm. The material and die were heated to 80°C at a heating rate of 10°C / min, kept at that temperature for 5 min, and the pressure was increased to 500 MPa at a pressure increase rate of 0.2 GPa / s. After keeping the pressure for 40 min, the pressure was released, and the mold was demolded at 20°C to obtain an Ag2S thermoelectric arm array (shown in Figure 4b) connected to the base material.

[0062] Example 3 (70 μm) By the laser drilling process, a micro-cavity array was fabricated on the surface of the mold steel (HRC=50) as shown in Fig. 5a. The diameter of the bottom of the cavity was about 70 μm, the depth of the cavity was about 200 μm, and the projection of the cavity in the plane perpendicular to the mold surface was a trapezoid with a base angle of about 92°.

[0063] The Ag2S material was processed into a block with a diameter of 9.9 mm and a thickness of 1 mm, placed in an extrusion die cavity array, and placed in a pressure-resistant sleeve with an inner diameter of 10 mm. At room temperature of 20°C, it was heated to 140°C at a heating rate of 20°C / min, kept at that temperature for 10 min, pressurized to 0.2 GPa at a pressure increase rate of 0.1 GPa / s, and kept at that pressure for 60 min before releasing the pressure. The Ag2S thermoelectric arm array (shown in Figure 5b) connected to the base material was obtained by demolding at 20°C.

[0064] Example 4 (Rectangle) A micro-cavity array was fabricated on the surface of mold steel (HRC=50) by a mechanical drilling process, as shown in Fig. 1. The cavity diameter was about 220 μm, the cavity depth was about 600 μm, and the projection of the cavity in the plane perpendicular to the mold surface was rectangular.

[0065] The Ag2S material was processed into a lump with a diameter of 9.9 mm and a thickness of 1 mm, which was placed in the extrusion die cavity array and the surrounding extrusion accessories (as shown in Figure 6a), and then sequentially placed in a pressure-resistant sleeve with an inner diameter of 10 mm. The material and die were heated to 80°C at a heating rate of 10°C / min, kept at that temperature for 5 min, and pressurized to 500 MPa at a pressure increase rate of 0.2 GPa / s. After keeping the pressure for 40 min, the pressure was released, and the mold was demolded at 20°C to obtain an Ag2S thermoelectric arm array (shown in Figure 6b) connected to the base material.

[0066] Example 5 (without pressure sleeve, array deformation) The Ag2S material was processed into a mass with a diameter of 9.9 mm and a thickness of 1 mm, and placed in the extrusion die cavity array of Example 4, as shown in FIG. 7a, without using a pressure sleeve. The material and die were heated to 80°C at a heating rate of 10°C / min, kept at 4 min, and pressurized to 500 MPa at a pressure increase rate of 0.2 GPa / s, and the pressure was released after 40 min of pressure retention. As shown in FIG. 7b, the material mass was obviously deformed laterally. Although the Ag2S thermoelectric arm array connected to the base material was obtained by demolding at 20°C, the thermoelectric arms in the array were severely deformed, as shown in FIG. 7c.

[0067] Example 6 (CuSe) The Cu2Se material was processed into a lump with a diameter of 9.9 mm and a thickness of 1 mm, and placed in the extrusion die cavity array of Example 1, and then sequentially placed in a pressure-resistant sleeve with an inner diameter of 10 mm. At 250°C, a pressure of 1 GPa was applied at a pressure increase rate of 0.2 GPa / s, and the pressure was held for 40 min, after which the pressure was released, and the Cu2S thermoelectric arm array (shown in FIG. 4c) connected to the base material was obtained by demolding at 160°C.

[0068] Example 7 (CuSe rupture) The Cu2S material was processed into a block with a diameter of 9.9 mm and a thickness of 1 mm, and placed in the extrusion die cavity array of Example 1, which was then sequentially placed in a pressure-resistant sleeve with an inner diameter of 10 mm. The pressure was increased to 1 GPa at a pressure increase rate of 0.2 GPa / s at 250°C, and the pressure was released after 40 min of pressure retention, and the mold was demolded at 120°C. During the demolding process, the roots of the thermoelectric arms were broken, and many thermoelectric arms remained in the extrusion die cavity, as shown in Figure 8b. The fabrication of the array failed, and the extrusion die became unusable.

[0069] Example 8 As shown in FIG. 9, an Ag2S material arm array was obtained by hot extrusion, the bottom of the material arm was connected to the Ag2S material base, and the thickness of the material base was uniform. The manufacturing process of the Ag2S material arm array includes the following steps. A required cavity array was manufactured on the surface of the mold steel (HRC=60) by a mechanical drilling process. The diameter of the bottom of the cavity was about 200 μm, the depth of the cavity was about 500 μm, and the projection of the cavity on a plane perpendicular to the surface of the mold was a trapezoid, and its base angle was about 92°. The Ag2S material was processed into a block with a diameter of 9.9 mm and a thickness of 1 mm, which was placed in the extrusion mold cavity array, and the material and the extrusion mold were sequentially placed in a pressure-resistant sleeve with an inner diameter of 10 mm. The pressure was increased to 1.5 GPa at a pressure increase rate of 0.2 GPa / s at room temperature of 20°C, and the pressure was released after 10 min of pressure retention, and finally demolded at 20°C.

[0070] Figure 10 shows the result of dripping ethyl cyanoacrylate into the gaps of the semiconductor material arm array, filling the gaps of the material arms, and leaving it at room temperature (5℃ to 35℃) for 12 hours until it hardens. The mosaic sample was fixed to the grinding machine sample stage, and its surface was polished with an alumina grindstone until the end faces of the material arms were exposed. It was then polished downward to remove the uneven areas at the tops of the material arms, resulting in a material arm mosaic array (shown in Figure 11) with consistent end face shapes and sizes, and the height of each material arm was uniform.

[0071] The surface of the above sample was sandblasted (Al2O3 particles, particle size 220 mesh, sandblasting pressure 0.05-0.2 MPa), and the sandblasted surface was ultrasonically cleaned with alcohol. After drying, Cu was deposited on the surface by magnetron sputtering (sputtering power 200 W, temperature 100°C, pressure 0.5 Pa, sputtering time 2 h), resulting in a Cu interface layer with a thickness of approximately 5 μm.

[0072] The sample with the sputtered Cu layer was immersed in acetone, the inlay material was ultrasonically dissolved, and the Cu layer attached to the inlay material was removed, resulting in an Ag2S material arm array (shown in FIG. 12) in which the height, end face shape, and size of the material arm met the requirements and the Cu layer was attached only to the end face of the material arm. FIGS. 9 to 12 are photographs of the products obtained at each step of manufacturing a Cu interface on the Ag2S material arm array in Example 8.

[0073] Example 9 As shown in FIG. 13, a Cu2Se material arm array was obtained by hot extrusion. The bottom of the material arm was connected to the Cu2Se material base, and the thickness of the material base was uniform. The manufacturing process of the Cu2Se material arm array includes the following steps. The required cavity array was manufactured on the surface of the mold steel (HRC=60) by a mechanical drilling process. The diameter of the bottom of the cavity was about 200 μm, the depth of the hole was about 500 μm, and the projection of the cavity on a plane perpendicular to the surface of the mold was a trapezoid, and its base angle was about 92°. The Cu2Se material was processed into a block with a diameter of 9.9 mm and a thickness of 1 mm, which was placed in the extrusion mold cavity array, and the material and the extrusion mold were sequentially placed in a pressure-resistant sleeve with an inner diameter of 10 mm. The pressure was increased to 1 GPa at a pressure increase rate of 0.2 GPa / s at 250°C, and the pressure was released after 40 min of pressure retention, and finally demolded at 160°C.

[0074] A drop of UVN photoresist was added to the gaps between the semiconductor material arm arrays, and the gaps were left at 95°C until they hardened. Another drop of photoresist was added, and the gaps were left at 95°C until they hardened. This was repeated so that the tops of the Cu2Se material arms could be covered even after the photoresist had hardened.

[0075] The mosaic sample was fixed to the sample stage of the grinding machine, and its surface was polished with an alumina grindstone until the end faces of the material arms were exposed. It was then polished downward to remove the uneven areas on the tops of the material arms, resulting in a mosaic array of material arms with consistent end face shapes and sizes. The height of each material arm was also uniform.

[0076] The surface of the above sample was sandblasted (Al2O3 particles, particle size 220 mesh, sandblasting pressure 0.05-0.2 MPa), and the sandblasted surface was ultrasonically cleaned with alcohol. After drying, W (sputtering power 100 w, temperature 100 °C, pressure 0.5 Pa, sputtering time 30 min) and Cu (sputtering power 200 w, temperature 100 °C, pressure 0.5 Pa, sputtering time 30 min) were sequentially deposited on the surface by magnetron sputtering.

[0077] The sample with the sputtered W / Cu layer was immersed in a UVN developer to ultrasonically dissolve the hardened photoresist and remove the interface layer adhering to the inlay material. A Cu2Se material arm array (shown in FIG. 14) was obtained in which the height, end face shape and size of the material arm met the requirements and the W / Cu layer was attached only on the end face of the material arm. FIGS. 13 to 14 are photographs of the products obtained at each step of manufacturing the Cu interface layer on the Cu2Se material arm array in Example 9.

Claims

1. 1. A method for manufacturing a semiconductor material arm array, comprising the steps of: placing a semiconductor block material on a surface of an extrusion die, placing the semiconductor block material and the extrusion die in a pressure-resistant sleeve, plastically deforming the semiconductor block material by extrusion to fill cavities arranged in an array on the surface of the extrusion die, and obtaining a semiconductor material arm array after demolding, The extrusion temperature is 5 to 500° C. and is equal to or higher than the softening temperature of the semiconductor bulk material; The extrusion pressure is 1 MPa to 10 GPa; The pressure retention time of the extrusion is 1 to 100 minutes, The demolding temperature is 10 to 170° C., which is higher than the softening temperature of the semiconductor bulk material.

2. The extrusion die includes a hard base, which may be a metal base or a ceramic base, and cavities arranged in an array in the hard base; The shape of the cavity projected on a plane parallel to the surface of the rigid base is a circle, a rectangle, a triangle, a trapezoid, or a sector, and the shape of the cavity projected in a direction perpendicular to the surface of the rigid base is a rectangle or a trapezoid; The manufacturing method according to claim 1 , wherein when the shape of the projection of the cavity in a direction perpendicular to the surface of the hard base is a trapezoid, a base angle of the trapezoid is >90° and ≦135°.

3. The manufacturing method according to claim 2, wherein the size of the projection of the cavity on a plane parallel to the surface of the hard base is 1 μm to 20 mm.

4. The method according to claim 1, characterized in that the shortest distance between the centers of adjacent cavities is between 3 μm and 20 mm.

5. 2. The method according to claim 1, wherein the depth of the cavity is between 1 μm and 50 mm.

6. the relative deviation between the diameters of the semiconductor block material and the extrusion die and the inner diameter size of the pressure-resistant sleeve is ≦5%; 2. The method according to claim 1, wherein the absolute deviation between the diameters of the semiconductor block material and the extrusion die and the inner diameter of the pressure sleeve is ≦0.2 mm.

7. The composition of the semiconductor bulk material is Ag-based semiconductor material (Ag 2 S x M 1-x , M element is Se or Te, 0≦x≦1), Cu-based semiconductor material (Cu 2-y Ag y Se 1-z M z 2. The method according to claim 1, wherein the element M is selected from the group consisting of Bi-Te based semiconductor materials, 0≦y≦1, 0≦z≦1, and M element is S or Te.

8. Step (1) of selecting an organic binder as an inlay material, injecting it into the semiconductor material arm array manufactured by the manufacturing method of claim 1 to realize a mosaic of the entire organic binder, and after the inlay material is hardened, achieving flattening of the end surface of the semiconductor material arm array by physical or / and chemical treatment, to obtain a semiconductor material arm array containing an inlay material; (2) depositing an interface layer on the surface of the semiconductor material arm array including the inlay material, and then removing the inlay material and the interface layer attached to the surface of the inlay material, thereby achieving batch production of the semiconductor material arm array interface layer; 1. A batch fabrication method for a semiconductor material arm array interface layer, comprising:

9. The inlay material is one of photoresist, PDMS, AB adhesive, cold-hot inlay material, and ethyl cyanoacrylate; The physical and / or chemical treatment is at least one of mechanical polishing, chemical polishing, chemical etching, and chemical corrosion; The batch manufacturing method for a semiconductor material arm array interface layer as described in claim 8, characterized in that after the end surface of the semiconductor material arm array is planarized and before the interface layer is deposited, the appearance morphology of the end surface of the semiconductor material arm array is adjusted, and the appearance morphology of the end surface is adjusted by using sandblasting, chemical corrosion or chemical etching to increase the end surface roughness.

10. The interface layer includes Cu, Ni, Al, In, Te, Sb, Bi, Ge, Pb, Ga, Zn, Cd, Pd, Pt, V, Ta, Hf, Fe, Co, Mn, Ru, Rh, Ir, Mo, Nb, W, Ti, Cr, Zr, Sn, Ag, Au, Pt, TiN, ThO. 2 , LaCrO 2 , LaNiO 2 , LaMnO 3 (sr), CoCrO 4 , LaCoO 3 (sr), InO 2 / SnO 2 , SiC, MoSi 2 wherein the number of layers of the interface layer is ≧1, and the thickness of the interface layer is 10 nm to 20 μm; The batch manufacturing method for a semiconductor material arm array interface layer according to claim 8, characterized in that the inlay material and the interface layer adhering to the inlay material are removed by at least one of heating, light irradiation, chemical dissolution, and ultrasonic treatment.

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