Silicon carbide semiconductor device

Abstract

This semiconductor device comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes: a drift region of a first conductive type; a body region that is provided on the drift region and is of a second conductive type different from the first conductive type; a source region that is provided on the body region so as to be spaced apart from the drift region, and is of the first conductive type; and a contact region that is provided on the body region and is of the second conductive type. The first main surface is provided with a gate trench defined by a side surface, which passes through the source region and the body region and extends to the drift region, and a bottom surface, which is connected to the side surface, and extending in a first direction parallel to the first main surface. A source electrode connected to the source region and the contact region is further provided. When viewed in a plan view from a direction perpendicular to the first main surface, the gate trench is surrounded by the source region, and the source region has a portion sandwiched between the gate trench and the contact region which are adjacent to each other in a second direction perpendicular to the first direction.

Description

[Technical Field]

[0001] The present disclosure relates to silicon carbide semiconductor devices.

[0002] This application claims priority to Japanese Application No. 2020-210100, filed on December 18, 2020, and incorporates by reference all of the contents of said Japanese application. [Background technology]

[0003] As one silicon carbide semiconductor device, a trench-gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has been disclosed in which contact regions connected to a body region are arranged discontinuously along a gate trench inside a contact hole formed in an interlayer insulating film (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2012-23291 Summary of the Invention

[0005] a source region having the first conductivity type and provided on the body region so as to be spaced from the drift region; and a contact region having the second conductivity type and provided on the body region; a gate trench provided in the first main surface; the gate trench extending in a first direction parallel to the first main surface; the gate trench having a side surface penetrating the source region and the body region to reach the drift region and a bottom surface continuous with the side surface; and a source electrode connected to the source region and the contact region; and when viewed in a plan view from a direction perpendicular to the first main surface, the gate trench is surrounded by the source region, and the source region has a portion sandwiched between the gate trench and the contact region adjacent to each other in a second direction perpendicular to the first direction. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing the configuration of an interlayer insulating film and a first main surface of a silicon carbide semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a diagram showing a configuration of a first main surface of the silicon carbide semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a cross-sectional view (part 1) showing the configuration of a silicon carbide semiconductor device according to an embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 2) showing the configuration of the silicon carbide semiconductor device according to the embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 3) showing the configuration of the silicon carbide semiconductor device according to the embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 4) showing the configuration of the silicon carbide semiconductor device according to the embodiment. [Figure 7] FIG. 7 is a fifth cross-sectional view illustrating the configuration of the silicon carbide semiconductor device according to the embodiment. [Figure 8]FIG. 8 is a cross-sectional view (part 1) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 2) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 3) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 4) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 12] FIG. 12 is a fifth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 13] FIG. 13 is a cross-sectional view (part 6) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 14] FIG. 14 is a cross-sectional view (part 7) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 15] FIG. 15 is a cross-sectional view (part 8) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 16] FIG. 16 is a ninth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 17] FIG. 17 is a cross-sectional view (part 10) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 18] FIG. 18 is a cross-sectional view (part 11) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 19] FIG. 19 is a twelfth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 20] FIG. 20 is a thirteenth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 21] FIG. 21 is a fourteenth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 22] FIG. 22 is a cross-sectional view (part 15) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 23] FIG. 23 is a sixteenth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 24] FIG. 24 is a cross-sectional view (part 17) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 25] FIG. 25 is a cross-sectional view (part 18) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 26] FIG. 26 is a 19th cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 27] FIG. 27 is a twentieth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 28] FIG. 28 is a 21st cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 29] FIG. 29 is a diagram showing an example of a path of a short-circuit current. [Figure 30] FIG. 30 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to a modification of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] [Problem to be solved by this disclosure] Conventional MOSFETs with discontinuous contact regions do not provide sufficient short-circuit resistance.

[0008] An object of the present disclosure is to provide a silicon carbide semiconductor device that can improve short-circuit resistance.

[0009] [Effects of this disclosure] According to the present disclosure, it is possible to improve short circuit resistance.

[0010] The embodiments for carrying out the invention are described below.

[0011] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, identical or corresponding elements will be given the same symbols, and the same description will not be repeated. In the crystallographic descriptions in this specification, individual directions are represented by [], collective directions by <>, individual planes by (), and collective planes by {}. Furthermore, negative indices in crystallography are usually represented by placing a "-" (bar) above the number, but in this specification, a negative sign is placed before the number.

[0012] [1] a source region having the first conductivity type and provided on the body region so as to be spaced from the drift region; and a contact region having the second conductivity type and provided on the body region; a gate trench provided in the first main surface; the gate trench extending in a first direction parallel to the first main surface; the gate trench having a side surface penetrating the source region and the body region to reach the drift region and a bottom surface continuous with the side surface; and a source electrode connected to the source region and the contact region;

[0013] When the silicon carbide semiconductor device is short-circuited, part of the short-circuit current bypasses the gate trench in plan view, reaches the portion (narrowed portion) sandwiched between the gate trench and the contact region in the second direction of the source region, and flows along the side of the gate trench toward the drift region. When the short-circuit current flows, heat is generated on the second main surface side of the gate trench, and this heat raises the temperature near the first main surface. As a result, the electrical resistance, particularly in the narrowed portion, increases, making it more difficult for the short-circuit current to flow, thereby improving the short-circuit resistance.

[0014] [2] In [1], the source region may have a portion sandwiched between the gate trenches adjacent to each other in the second direction, and in a cross section perpendicular to the first direction, the length in the second direction of the portion of the source region sandwiched between the gate trench and the contact region may be shorter than the length in the second direction of the portion sandwiched between the adjacent gate trenches. In this case, the narrowed portion makes it easier to improve short-circuit resistance.

[0015] [3] In [1] or [2], the contact region may be provided on only one side of the gate trench in the second direction, which makes it easier to ensure an on-current flowing through a portion of the source region that contacts the source electrode and improve short-circuit resistance by a narrowed portion.

[0016] [4] In any of [1] to [3], the silicon carbide substrate may include an electric field relaxation region having the second conductivity type, extending in the first direction, and provided between the bottom surface of the gate trench and the second main surface; and a connection region having the second conductivity type and electrically connecting the contact region and the electric field relaxation region, wherein, when viewed in a plan view from a direction perpendicular to the first main surface, the gate trench and the electric field relaxation region are on an imaginary line extending in the first direction, and the connection region may be in contact with the electric field relaxation region on the imaginary line. In this case, carriers can be supplied from the source electrode to the electric field relaxation region, thereby reducing feedback capacitance. The reduced feedback capacitance reduces switching loss and improves switching speed.

[0017] [5] In the device of [4], the electric field relaxation region may be spaced apart from the bottom surface of the gate trench, whereby the on-resistance is reduced and on-current is more likely to flow.

[0018] [6] In [4] or [5], a lower end of the gate trench may be located inside the electric field relaxation region when viewed in a plan view perpendicular to the first main surface, which facilitates relaxation of electric field concentration at the lower end of the gate trench.

[0019] [7] In [6], an upper end of the gate trench may be located inside the electric field relaxation region when viewed in a plan view perpendicular to the first main surface, which makes it easier to relax the electric field concentration at the lower end of the gate trench.

[0020] [8] In any of [4] to [7], the gate trenches may be provided in a plurality at regular intervals so as to overlap with the imaginary line, and the connection region may be provided between the gate trenches adjacent to each other in the first direction when viewed in a plan view from a direction perpendicular to the first main surface. In this case, carriers can be easily supplied from the source electrode to the electric field relaxation region, and switching loss can be reduced by reducing feedback capacitance, thereby improving switching speed.

[0021] [9] In [8], the distance between the gate trenches adjacent to each other in the first direction may be 0.20 to 0.40 times the dimension of the gate trench in the first direction, which makes it easy to ensure both an on-state current and an improvement in short-circuit resistance.

[0022]

[10] In any of [1] to [9], the side surface of the gate trench may include a {0-33-8} plane, which allows good mobility to be obtained on the side surface of the gate trench and reduces channel resistance.

[0023] [Embodiments of the present disclosure] An embodiment of the present disclosure relates to a so-called vertical MOSFET (silicon carbide semiconductor device). FIG. 1 is a diagram showing a configuration of an interlayer insulating film and a first main surface of a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a diagram showing a configuration of a first main surface of a silicon carbide semiconductor device according to an embodiment. FIGS. 3 to 7 are cross-sectional views showing a configuration of a silicon carbide semiconductor device according to an embodiment. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIGS. 1 and 2. FIG. 4 corresponds to a cross-sectional view taken along line IV-IV in FIGS. 1 and 2. FIG. 5 corresponds to a cross-sectional view taken along line VV in FIGS. 1 and 2. FIG. 6 corresponds to a cross-sectional view taken along line VI-VI in FIGS. 1 and 2. FIG. 7 corresponds to a cross-sectional view taken along line VII-VII in FIGS. 1 and 2.

[0024] 1 to 7 , a MOSFET 100 according to this embodiment mainly includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, a barrier metal film 84, and a passivation film 85. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has n-type (first conductivity type).

[0025] The first main surface 1 is a {0001} plane or a plane inclined at an off angle of 8° or less in the off direction. Preferably, the first main surface 1 is a (000-1) plane or a plane inclined at an off angle of 8° or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1° or more, or 2° or more. The off angle may be 6° or less, or 4° or less.

[0026] The silicon carbide epitaxial layer 40 mainly includes a drift region 11, a body region 12, a source region 13, an electric field reduction region 16, a connection region 17, and a contact region .

[0027] Drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. Drift region 11 mainly includes, for example, a third region 11C, a fourth region 11D, and a fifth region 11E.

[0028] The body region 12 is provided on the drift region 11. The body region 12 contains p-type impurities such as aluminum (Al) and has a p-type (second conductivity type) conductivity. The effective concentration of the p-type impurities in the body region 12 is 5×10 17 cm -3 That's all. The short channel effect (punch-through) can occur when a depletion layer spreads from the pn junction region into the channel region, causing the entire channel region to become a depletion layer. By increasing the effective concentration of p-type impurities in the body region 12, the spread of the depletion layer formed in the channel region can be reduced. The thickness of the body region 12 may be less than 0.7 μm, for example. The effective concentration of p-type impurities in the body region 12 may be, for example, 1×10 18 cm -3 That's about it.

[0029] The source region 13 is provided on the body region 12 so as to be separated from the drift region 11 by the body region 12. The source region 13 contains n-type impurities such as nitrogen or phosphorus, and has n-type conductivity. The source region 13 constitutes the first main surface 1. The source region 13 mainly includes, for example, a first region 13A and a second region 13B. The effective concentration of the n-type impurity in the source region 13 may be higher than the effective concentration of the p-type impurity in the body region 12. The effective concentration of the n-type impurity in the source region 13 is, for example, 1×10 19 cm -3 That's about it.

[0030] The contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 18 constitutes the first main surface 1. The effective concentration of the p-type impurities in the contact region 18 is higher than the effective concentration of the p-type impurities in the body region 12 and the effective concentration of the p-type impurities in the connection region 17, for example. The contact region 18 penetrates the source region 13 and contacts the body region 12. The effective concentration of the p-type impurities in the contact region 18 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0031] The first main surface 1 is provided with a gate trench 5 defined by a side surface 3 and a bottom surface 4. The side surface 3 extends through the source region 13 and the body region 12 to reach the drift region 11. The bottom surface 4 is continuous with the side surface 3. The bottom surface 4 is located in the drift region 11. The bottom surface 4 is, for example, a plane parallel to the second main surface 2. The angle θ1 of the side surface 3 with respect to a plane including the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. The side surface 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility.

[0032] As shown in particular in FIGS. 1 and 2, when viewed in a plan view from a direction perpendicular to the first main surface 1, the gate trench 5 overlaps with an imaginary line L1 extending in a first direction parallel to the first main surface 1. When viewed in a plan view from a direction perpendicular to the first main surface 1, the gate trench 5 is on the imaginary line L1. A plurality of gate trenches 5 are provided at regular intervals on the imaginary line L1. Furthermore, when viewed in a plan view from a direction perpendicular to the first main surface 1, a plurality of gate trenches 5 are also provided at regular intervals in a second direction perpendicular to the first direction. The plurality of gate trenches 5 may be provided, for example, in an array.

[0033] The electric field relaxation region 16 contains p-type impurities such as Al and has p-type conductivity. The electric field relaxation region 16 is located between the bottom surface 4 of the gate trench 5 and the second main surface 2. That is, the electric field relaxation region 16 is spaced apart from the bottom surface 4 of the gate trench 5. Like the gate trench 5, the electric field relaxation region 16 overlaps with the imaginary line L1 when viewed in a plan view from a direction perpendicular to the first main surface 1. When viewed in a plan view from a direction perpendicular to the first main surface 1, the electric field relaxation region 16 is located on the imaginary line L1. On the imaginary line L1, the electric field relaxation region 16 may be provided in common to a plurality of gate trenches 5. Furthermore, when viewed in a plan view from a direction perpendicular to the first main surface 1, a plurality of electric field relaxation regions 16 are provided at regular intervals in the second direction. A plurality of electric field relaxation regions 16 may be provided in a striped pattern. The effective concentration of the p-type impurity in the electric field relaxation region 16 is, for example, 5×10 17 cm -3 5x10 or more 18 cm -3 The following is the result.

[0034] The fifth region 11E of the drift region 11 is located closer to the second main surface 2 than the electric field relaxation region 16. The fifth region 11E is in contact with the electric field relaxation region 16. The fifth region 11E is located closer to the first main surface 1 than the silicon carbide single crystal substrate 50. The fifth region 11E may be sandwiched between the electric field relaxation region 16 and the silicon carbide single crystal substrate 50. The fifth region 11E may be continuous with the silicon carbide single crystal substrate 50. The effective concentration of n-type impurities in the fifth region 11E is, for example, 5×10 15 cm -3 5x10 or more 16 cm -3 The following is the result.

[0035] The fourth region 11D is closer to the first major surface 1 than the fifth region 11E. The fourth region 11D is continuous with the fifth region 11E. The fourth region 11D is in contact with the electric field relaxation region 16 in a direction parallel to the second major surface 2. The fourth region 11D and the electric field relaxation region 16 may be located on the same plane parallel to the second major surface 2. The effective concentration of n-type impurities in the fourth region 11D may be higher than the effective concentration of n-type impurities in the fifth region 11E. The effective concentration of n-type impurities in the fourth region 11D is, for example, 5×10 16 cm-3 5x10 or more 17 cm -3 The following is the result.

[0036] The third region 11C is located closer to the second major surface 2 than the body region 12 and closer to the first major surface 1 than the electric field relaxation region 16 and the fourth region 11D. The third region 11C is continuous with the fourth region 11D. The third region 11C is sandwiched between the body region 12 and the electric field relaxation region 16 and the fourth region 11D. The third region 11C is in contact with each of the body region 12, the electric field relaxation region 16, and the fourth region 11D. The upper end surface of the third region 11C includes, for example, the bottom surface 4 of the gate trench 5. The effective concentration of n-type impurities in the third region 11C may be lower than the effective concentration of n-type impurities in the fourth region 11D. The effective concentration of n-type impurities in the third region 11C is, for example, 5×10 15 cm -3 5x10 or more 16 cm -3 The following is the result.

[0037] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the electric field reduction region 16 at the bottom surface 4. The gate insulating film 81 contacts each of the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 may also contact the source region 13 at the first main surface 1.

[0038] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5. A portion of the gate electrode 82 may be disposed on the first main surface 1.

[0039] The interlayer insulating film 83 is provided in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 from the source electrode 60. A part of the interlayer insulating film 83 may be provided inside the gate trench 5.

[0040] The interlayer insulating film 83, like the gate trench 5 and the electric field reduction region 16, overlaps with the imaginary line L1 when viewed in a plan view from a direction perpendicular to the first main surface 1. On the imaginary line L1, the interlayer insulating film 83 may be provided commonly to a plurality of gate trenches 5. When viewed in a plan view from a direction perpendicular to the first main surface 1, contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals in the second direction. When viewed in a plan view from a direction perpendicular to the first main surface 1, the contact holes 90 are provided so that the gate trench 5 is located between adjacent contact holes 90 in the second direction. The contact holes 90 extend in the first direction. The source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81 through the contact holes 90.

[0041] As shown in particular in FIGS. 1 and 2 , the first region 13A of the source region 13 extends in the first direction and, like the electric field reduction region 16 and the gate trench 5, overlaps with the imaginary line L1 when viewed in a plane perpendicular to the first major surface 1. When viewed in a plane perpendicular to the first major surface 1, the first region 13A is located on the imaginary line L1. On the imaginary line L1, the first region 13A may be common to multiple gate trenches 5. Furthermore, when viewed in a plane perpendicular to the first major surface 1, multiple first regions 13A may be provided at regular intervals in the second direction. The multiple first regions 13A may be provided in a striped pattern. When viewed in a plane perpendicular to the first major surface 1, the first region 13A contacts the entire periphery of the multiple gate trenches 5 aligned on the imaginary line L1 and surrounds these gate trenches 5. The first region 13A is connected to the contact region 18 in the second direction.

[0042] The second region 13B extends in the first direction. When viewed in a plan view from a direction perpendicular to the first main surface 1, the second region 13B is provided between two imaginary straight lines L1 adjacent to each other in the second direction. The second region 13B may be provided on only one side of each gate trench 5 in the second direction. The second region 13B may be provided for each pair of two gate trenches 5 adjacent to each other in the second direction. A plurality of second regions 13B may be provided in a striped pattern. The second region 13B may be continuous with two first regions 13A adjacent to each other in the second direction and sandwiched between these two first regions 13A in the second direction.

[0043] The contact region 18 extends in the first direction. When viewed in a plan view from a direction perpendicular to the first main surface 1, the contact region 18 is provided between two imaginary straight lines L1 adjacent to each other in the second direction, exclusive of the second region 13B. The contact region 18 may be provided on only one side of each gate trench 5 in the second direction. The contact region 18 may be provided for each pair of two gate trenches 5 adjacent to each other in the second direction. A plurality of contact regions 18 may be provided in a stripe pattern. The contact region 18 may be continuous with two first regions 13A adjacent to each other in the second direction, and may be sandwiched between these two first regions 13A in the second direction.

[0044] 1 and 2, the contact region 18 and the second region 13B are exposed from the interlayer insulating film 83 through the contact holes 90. A part of the first region 13A may be exposed from the interlayer insulating film 83.

[0045] The connection region 17 contains p-type impurities such as Al and has p-type conductivity. The connection region 17 electrically connects the contact region 18 and the electric field relaxation region 16. The connection region 17 is in contact with the electric field relaxation region 16 on the imaginary line L1. When viewed in a plan view from a direction perpendicular to the first main surface 1, the connection region 17 is provided between adjacent gate trenches 5 in the first direction. The connection region 17 is in contact with the body region 12 or the contact region 18. The connection region 17 may be in contact with both the body region 12 and the contact region 18. In the direction perpendicular to the second main surface 2, the connection region 17 may be between the electric field relaxation region 16 and the contact region 18. The connection region 17 is located closer to the second main surface 2 than the contact region 18. The connection region 17 is located closer to the first main surface 1 than the electric field relaxation region 16. When the connection region 17 is located between the contact region 18 and the electric field relaxation region 16 in the direction perpendicular to the second main surface 2 and is in contact with both the contact region 18 and the electric field relaxation region 16, the series resistance between the contact region 18 and the electric field relaxation region 16 is reduced. The connection region 17 may extend in the second direction. The effective concentration of the p-type impurity in the connection region 17 may be approximately the same as the effective concentration of the p-type impurity in the electric field relaxation region 16. The effective concentration of the p-type impurity in the connection region 17 may be, for example, 5×10 17 cm -3 5x10 or more 18 cm -3 The following is the result.

[0046] If we assume that multiple gate trenches 5 aligned in the first direction are one gate trench assembly, the gate trench assembly can be considered to be divided into multiple gate trenches 5 by the source region 13, part of the body region 12, and the connection region 17.

[0047] The barrier metal film 84 covers the upper surface and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is in contact with both the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, titanium nitride (TiN).

[0048] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 includes a contact electrode 61 and a source wiring 62. The contact electrode 61 is in contact with the second region 13B of the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 may also be in contact with a part of the first region 13A. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing, for example, titanium (Ti), Al, and Si. The contact electrode 61 forms an ohmic junction with the source region 13 and the contact region 18. The source wiring 62 covers the upper surface and side surfaces of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with each of the barrier metal film 84 and the contact electrode 61. The source wiring 62 is made of a material containing, for example, Al.

[0049] The passivation film 85 covers the upper surface of the source wiring 62. The passivation film 85 is in contact with the source wiring 62. The passivation film 85 is made of a material containing, for example, polyimide.

[0050] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing NiSi, for example. The drain electrode 70 may also be made of a material containing Ti, Al, and Si. The drain electrode 70 is in ohmic contact with the silicon carbide single crystal substrate 50.

[0051] A buffer layer containing n-type impurities such as nitrogen and having n-type conductivity may be provided between silicon carbide single crystal substrate 50 and fifth region 11E. The effective concentration of the n-type impurity in the buffer layer may be higher than the effective concentration of the n-type impurity in fifth region 11E.

[0052] The effective concentration of impurities in each of the impurity regions can be measured, for example, by using a scanning capacitance microscope (SCM) or secondary ion mass spectrometry (SIMS).

[0053] Next, a method for manufacturing the MOSFET 100 according to the embodiment will be described. FIGS. 8 to 28 are cross-sectional views showing a method for manufacturing the MOSFET 100 according to the embodiment. FIGS. 8 to 11 show changes common to the cross section shown in FIG. 3 and the cross section shown in FIG. 4. FIGS. 12, 14, 17, 19, 21, 23, 25, and 27 show changes in the cross section shown in FIG. 4. FIGS. 13, 15, 16, 18, 20, 22, 24, 26, and 28 show changes in the cross section shown in FIG. 3.

[0054] First, as shown in FIG. 8 , a step of preparing a silicon carbide single crystal substrate 50 is performed. For example, a silicon carbide ingot (not shown) manufactured by sublimation is sliced ​​to prepare the silicon carbide single crystal substrate 50. A buffer layer (not shown) may be formed on the silicon carbide single crystal substrate 50. The buffer layer may be formed by a chemical vapor deposition (CVD) method using, for example, a mixed gas of silane (SiH) and propane (C3H8) as a source gas and, for example, hydrogen (H2) as a carrier gas. During epitaxial growth of the buffer layer, an n-type impurity such as nitrogen may be introduced into the buffer layer.

[0055] Next, as also shown in FIG. 8 , a step of forming first epitaxial layer 21 is performed. For example, first epitaxial layer 21 is formed on silicon carbide single crystal substrate 50 by a CVD method using a mixed gas of silane and propane as a source gas and hydrogen as a carrier gas. During epitaxial growth, n-type impurities such as nitrogen are introduced into first epitaxial layer 21. First epitaxial layer 21 has n-type conductivity. The effective concentration of the n-type impurity in first epitaxial layer 21 may be lower than the effective concentration of the n-type impurity in the buffer layer.

[0056] 9, a step of forming the electric field relaxation region 16 is performed. For example, a mask layer (not shown) having an opening is formed on the region where the electric field relaxation region 16 is to be formed. Next, p-type impurity ions capable of imparting p-type conductivity, such as aluminum ions, are implanted into the first epitaxial layer 21. As a result, the electric field relaxation region 16 is formed.

[0057] 10 , a step of forming fourth region 11D is performed. For example, a mask layer (not shown) having openings is formed in the region where fourth region 11D is to be formed, that is, on the side of electric field relaxation region 16 in the direction parallel to second main surface 2. Next, n-type impurity ions capable of imparting n-type conductivity, such as nitrogen, are implanted into first epitaxial layer 21. This forms fourth region 11D. A portion of first epitaxial layer 21 closer to silicon carbide single crystal substrate 50 than electric field relaxation region 16 and a portion closer to silicon carbide single crystal substrate 50 than fourth region 11D constitute fifth region 11E. The effective concentration of n-type impurities in fourth region 11D is higher than the effective concentration of n-type impurities in fifth region 11E.

[0058] Next, as shown in FIG. 11 , a step of forming a second epitaxial layer 22 is performed. For example, the second epitaxial layer 22 is formed on the first epitaxial layer 21 by a CVD method using a mixed gas of silane and propane as a source gas and hydrogen as a carrier gas. During epitaxial growth, n-type impurities such as nitrogen are introduced into the second epitaxial layer 22. The second epitaxial layer 22 has n-type conductivity. The thickness of the second epitaxial layer 22 is, for example, 0.8 μm or more and 1.2 μm or less. For example, the effective concentration of the n-type impurity in the second epitaxial layer 22 is set lower than the effective concentration of the n-type impurity in the fourth region 11D.

[0059] 12 and 13, a step of forming the connection region 17 is performed. For example, a mask layer (not shown) having an opening on the region where the connection region 17 is to be formed is formed. Next, p-type impurity ions capable of imparting p-type conductivity, such as aluminum ions, are implanted into the entire surface of the second epitaxial layer 22. This forms the connection region 17.

[0060] 12 and 13, a step of forming the body region 12 is performed. P-type impurity ions capable of imparting p-type conductivity, such as aluminum ions, are implanted into the entire surface of the second epitaxial layer 22. As a result, the body region 12 is formed.

[0061] 12 and 13, a step of forming the source region 13 is then performed. For example, n-type impurity ions such as phosphorus that can impart n-type conductivity are implanted into the entire surface of the second epitaxial layer 22. As a result, the source region 13 is formed.

[0062] 14 and 15, a step of forming the contact region 18 is performed. For example, a mask layer (not shown) having an opening on the region where the contact region 18 is to be formed is formed. Next, p-type impurity ions capable of imparting p-type conductivity, such as aluminum ions, are implanted into the entire surface of the second epitaxial layer 22. This forms the contact region 18.

[0063] Next, activation annealing is performed to activate the impurity ions implanted into the silicon carbide substrate 10. The temperature of the activation annealing is preferably 1500°C or higher and 1900°C or lower, for example, about 1700°C. The time of the activation annealing is, for example, about 30 minutes. The atmosphere for the activation annealing is preferably an inert gas atmosphere, for example, an Ar atmosphere.

[0064] Next, as shown in FIG. 16 , a step of forming a gate trench 5 is performed. For example, a mask layer (not shown) having an opening at a position where the gate trench 5 is to be formed is formed on the first main surface 1 including the source region 13 and the contact region 18. Using the mask layer, a portion of the source region 13, a portion of the body region 12, and a portion of the drift region 11 are removed by etching. Examples of the etching method include reactive ion etching, particularly inductively coupled plasma reactive ion etching. Specifically, examples of the etching method include inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF) or a mixed gas of SF and oxygen (O) as a reactive gas. By etching, a recess (not shown) having a side portion substantially perpendicular to the first main surface 1 and a bottom portion that is continuous with the side portion and substantially parallel to the first main surface 1 is formed in the region where the gate trench 5 is to be formed.

[0065] Next, thermal etching is performed on the recesses. Thermal etching can be performed, for example, by heating the mask layer formed on the first main surface 1 in an atmosphere containing a reactive gas having at least one type of halogen atom. The at least one type of halogen atom includes at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere includes, for example, chlorine (Cl2), boron trichloride (BCl3), SF6, or carbon tetrafluoride (CF4). For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as the reactive gas, and setting the heat treatment temperature to, for example, 800°C or higher and 900°C or lower. The reactive gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. Examples of the carrier gas that can be used include nitrogen gas, argon gas, and helium gas.

[0066] By the thermal etching, a gate trench 5 is formed in the first main surface 1 of the silicon carbide substrate 10. The gate trench 5 is defined by a side surface 3 and a bottom surface 4. The side surface 3 is formed by the source region 13, the body region 12, and the drift region 11. The bottom surface 4 is formed by the drift region 11. An angle θ1 between the side surface 3 and a plane including the bottom surface 4 is, for example, not less than 45° and not more than 65°. Next, the mask layer is removed from the first main surface 1.

[0067] Next, as shown in FIGS. 17 and 18 , a step of forming a gate insulating film 81 is performed. For example, by thermally oxidizing the silicon carbide substrate 10, the gate insulating film 81 is formed in contact with the source region 13, the body region 12, the drift region 11, the electric field relaxation region 16, and the contact region 18. Specifically, the silicon carbide substrate 10 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300° C. or higher and 1400° C. or lower. This forms the gate insulating film 81 in contact with the first main surface 1, the side surface 3, and the bottom surface 4. Note that, when the gate insulating film 81 is formed by thermal oxidation, strictly speaking, a portion of the silicon carbide substrate 10 is incorporated into the gate insulating film 81. For this reason, in the subsequent processing, it is assumed that the first main surface 1, the side surface 3, and the bottom surface 4 have moved slightly to the interface between the gate insulating film 81 and the silicon carbide substrate 10 after thermal oxidation.

[0068] Next, the silicon carbide substrate 10 may be subjected to a heat treatment (NO annealing) in a nitric oxide (NO) gas atmosphere. In the NO annealing, the silicon carbide substrate 10 is maintained, for example, under conditions of 1100°C or higher and 1400°C or lower for about one hour. This introduces nitrogen atoms into the interface region between the gate insulating film 81 and the body region 12. As a result, the formation of interface states in the interface region is suppressed, thereby improving channel mobility.

[0069] 19 and 20, a step of forming a gate electrode 82 is performed. The gate electrode 82 is formed on the gate insulating film 81. The gate electrode 82 is formed by, for example, a low pressure chemical vapor deposition (LP-CVD) method. The gate electrode 82 is formed so as to face each of the source region 13, the body region 12, and the drift region 11.

[0070] 21 and 22, a step of forming an interlayer insulating film 83 is performed. Specifically, the interlayer insulating film 83 is formed so as to cover the gate electrode 82 and to be in contact with the gate insulating film 81. The interlayer insulating film 83 is formed by, for example, a CVD method. The interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. A part of the interlayer insulating film 83 may be formed inside the gate trench 5.

[0071] Next, as shown in FIGS. 23 and 24 , steps of forming a barrier metal film 84, a contact electrode 61, and a drain electrode 70 are performed. For example, etching is performed to form a contact hole 90 in the interlayer insulating film 83 and the gate insulating film 81, thereby exposing the second region 13B of the source region 13 and the contact region 18 through the contact hole 90 from the interlayer insulating film 83 and the gate insulating film 81. A portion of the first region 13A may also be exposed through the interlayer insulating film 83 and the gate insulating film 81. Next, a barrier metal film 84 is formed to cover the upper surface and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, TiN. The barrier metal film 84 is formed by, for example, sputtering and reactive ion etching (RIE). Next, a metal film (not shown) for the contact electrode 61 is formed on the first main surface 1, contacting the portions of the source region 13 and the contact region 18 exposed through the contact hole 90. The metal film for the contact electrode 61 is formed by, for example, a sputtering method. The metal film for the contact electrode 61 is made of, for example, a material containing Ni. Next, a metal film (not shown) for the drain electrode 70 is formed, which contacts the silicon carbide single crystal substrate 50 on the second main surface 2. The metal film for the drain electrode 70 is formed by, for example, a sputtering method. The metal film for the drain electrode 70 is made of, for example, a material containing Ni.

[0072] Next, alloying annealing is performed. The metal film for the contact electrode 61 and the metal film for the drain electrode 70 are maintained at a temperature of, for example, 900°C or higher and 1100°C or lower for about 5 minutes. As a result, at least a portion of the metal film for the contact electrode 61 and at least a portion of the metal film for the drain electrode 70 reacts with silicon contained in the silicon carbide substrate 10 and becomes silicide. This forms the contact electrode 61 that forms an ohmic junction with the source region 13 and the contact region 18, and the drain electrode 70 that forms an ohmic junction with the silicon carbide single crystal substrate 50. The contact electrode 61 may be made of a material containing Ti, Al, and Si. The drain electrode 70 may be made of a material containing Ti, Al, and Si.

[0073] 25 and 26, a step of forming a source wiring 62 is performed. Specifically, the source wiring 62 is formed to cover the contact electrode 61 and the barrier metal film 84. The source wiring 62 is formed by film formation using a sputtering method and RIE, for example. The source wiring 62 is made of a material containing aluminum, for example. In this way, the source electrode 60 having the contact electrode 61 and the source wiring 62 is formed.

[0074] Next, as shown in FIGS. 27 and 28, a step of forming a passivation film 85 is performed. Specifically, the passivation film 85 is formed to cover the source wiring 62. The passivation film 85 is made of a material containing, for example, polyimide. The passivation film 85 is formed by, for example, a coating method. The passivation film 85 may also be formed by a plasma CVD method.

[0075] In this way, the MOSFET 100 according to the embodiment is completed.

[0076] Next, the effects of the MOSFET according to this embodiment will be described. Fig. 29 is a diagram showing an example of a path of a short-circuit current.

[0077] In the MOSFET 100 according to this embodiment, when a short circuit occurs, as shown in FIG. 29 , part of the short-circuit current 9 flows from the second region 13B of the source region 13 toward the first region 13A and bypasses the periphery of the gate trench 5. The short-circuit current 9 then reaches the portion (narrowed portion) sandwiched between the gate trench 5 and the contact region 18 in the second direction of the first region 13A and flows along the side surface 3 of the gate trench 5 toward the drift region 11. When the short-circuit current 9 flows, heat is generated on the second main surface 2 side of the gate trench 5, and this heat increases the temperature in the vicinity of the first main surface 1. As a result, the electrical resistance increases, particularly in the narrowed portion, making it more difficult for the short-circuit current 9 to flow, thereby improving the short-circuit resistance.

[0078] In this embodiment, the contact region 18 and the electric field relaxation region 16 are electrically connected by the connection region 17. The contact region 18 is electrically connected to the source electrode 60. Therefore, the electric field relaxation region 16 is electrically connected to the source electrode 60. This allows carriers to be supplied from the source electrode 60 to the electric field relaxation region 16, thereby reducing feedback capacitance. Reducing the feedback capacitance reduces switching loss and improves switching speed.

[0079] Furthermore, since the connection region 17 is provided between the gate trenches 5 adjacent to each other in the first direction when viewed in a plan view perpendicular to the first main surface 1, carriers can be easily supplied from the source electrode to the electric field relaxation region. Therefore, the reduction in feedback capacitance can further reduce switching loss and improve switching speed.

[0080] By providing the contact region 18 on only one side of the gate trench 5 in the second direction, it is easy to achieve both ensuring the on-current flowing through the portion of the source region 13 that contacts the source electrode 60 and improving the short-circuit resistance due to the narrowed portion.

[0081] Since the electric field relaxation region 16 is located away from the bottom surface 4 of the gate trench 5, an on-current can easily flow between the source electrode 60 and the drain electrode 70.

[0082] When viewed in a plan view from a direction perpendicular to the first main surface 1, the lower end of the gate trench 5 is preferably located inside the electric field relaxation region 16. This is because it is easier to alleviate electric field concentration at the lower end of the gate trench 5. When viewed in a plan view from a direction perpendicular to the first main surface 1, it is more preferable that the upper end of the gate trench 5 is located inside the electric field relaxation region 16. This is because it is easier to alleviate electric field concentration at the lower end of the gate trench 5.

[0083] The distance W1 between adjacent gate trenches 5 in the first direction is preferably 0.20 to 0.40 times the dimension W2 of the gate trench 5 in the first direction. If the distance W1 is less than 0.20 times the dimension W2, it may be difficult for current to bypass the periphery of the gate trench 5 in the event of a short circuit, making it difficult to improve short-circuit resistance. On the other hand, if the distance W1 is more than 0.40 times the dimension W2, there may be a shortage of channels, resulting in high on-resistance. The distance W1 is more preferably 0.22 to 0.38 times the dimension W2, and even more preferably 0.25 to 0.35 times the dimension W2.

[0084] [Variations] Next, a modified example of the embodiment will be described. The modified example differs from the embodiment mainly in the shape of the gate trench. Fig. 30 is a cross-sectional view showing the configuration of a MOSFET (silicon carbide semiconductor device) according to the modified example of the embodiment. Fig. 30 shows a cross section similar to the cross section taken along line III-III in Figs. 1 and 2.

[0085] 30, in a MOSFET 110 according to the modification, the gate trench 5 is a vertical trench. That is, the angle θ1 of the side surface 3 with respect to a plane including the bottom surface 4 may be 90°. The other configurations are the same as those of the embodiment.

[0086] Even with such a modification, the same effects as those of the embodiment can be obtained.

[0087] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0088] 1 First main surface 2 Second main surface 3. Aspects 4 Bottom 5 Gate trench 9 Short-circuit current 10 Silicon carbide substrate 11 Drift Region 11C Third area 11D 4th area 11E 5th area 12 Body Region 13 Source Region 13A 1st area 13B 2nd area 16 Electric field relaxation region 17 Connection Area 18 Contact Area 21 First epitaxial layer 22 Second epitaxial layer 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 70 drain electrode 81 Gate insulating film 82 gate electrode 83 Interlayer insulating film 84 Barrier metal film 85 Passivation Film 90 Contact Holes 100 MOSFET 110 MOSFET L1 Virtual line

Claims

1. a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface; The silicon carbide substrate is a drift region having a first conductivity type; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; a source region having the first conductivity type and provided on the body region so as to be separated from the drift region; a contact region provided on the body region and having the second conductivity type; and a gate trench is provided in the first main surface, the gate trench being defined by a side surface that penetrates the source region and the body region to reach the drift region and a bottom surface that is continuous with the side surface, and extending in a first direction parallel to the first main surface; a source electrode connected to the source region and the contact region; When viewed in a plan view from a direction perpendicular to the first main surface, the gate trench is surrounded by the source region; the source region has a portion sandwiched between the gate trench and the contact region adjacent to each other in a second direction perpendicular to the first direction, the source region has a portion sandwiched between the gate trenches adjacent to each other in the second direction, In a cross section perpendicular to the first direction, a portion of the source region sandwiched between the gate trench and the contact region having a length in the second direction that is shorter than a portion of the source region sandwiched between adjacent gate trenches;

2. The silicon carbide substrate is an electric field relaxation region that is provided between the bottom surface of the gate trench and the second main surface, extends in the first direction, and has the second conductivity type; a connection region that electrically connects the contact region and the electric field reduction region and has the second conductivity type; and When viewed in a plan view from a direction perpendicular to the first main surface, the gate trench and the electric field relief region are located on a virtual line extending in the first direction, The silicon carbide semiconductor device according to claim 1 , wherein the connection region is in contact with the electric field relaxation region on the imaginary straight line.

3. A silicon carbide substrate having a first main surface and a second main surface opposite the first main surface, The silicon carbide substrate is a drift region having a first conductivity type; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; a source region having the first conductivity type and provided on the body region so as to be separated from the drift region; a contact region provided on the body region and having the second conductivity type; and a gate trench is provided in the first main surface, the gate trench being defined by a side surface that penetrates the source region and the body region to reach the drift region and a bottom surface that is continuous with the side surface, and extending in a first direction parallel to the first main surface; a source electrode connected to the source region and the contact region; When viewed in a plan view from a direction perpendicular to the first main surface, the gate trench is surrounded by the source region; the source region has a portion sandwiched between the gate trench and the contact region adjacent to each other in a second direction perpendicular to the first direction, The silicon carbide substrate is an electric field relaxation region that is provided between the bottom surface of the gate trench and the second main surface, extends in the first direction, and has the second conductivity type; a connection region that electrically connects the contact region and the electric field reduction region and has the second conductivity type; and When viewed in a plan view from a direction perpendicular to the first main surface, the gate trench and the electric field relief region are located on a virtual line extending in the first direction, The connection region is in contact with the electric field relaxation region on the imaginary straight line.

4. The silicon carbide semiconductor device according to claim 2 , wherein the electric field relaxation region is spaced apart from the bottom surface of the gate trench.

5. When viewed in a plan view from a direction perpendicular to the first main surface, The silicon carbide semiconductor device according to claim 2 , wherein a lower end of the gate trench is located inside the electric field relaxation region.

6. When viewed in a plan view from a direction perpendicular to the first main surface, The silicon carbide semiconductor device according to claim 5 , wherein an upper end of the gate trench is located inside the electric field relaxation region.

7. a plurality of the gate trenches are provided at regular intervals so as to overlap with the virtual straight line; 7. The silicon carbide semiconductor device according to claim 2, wherein the connection region is provided between the gate trenches adjacent to each other in the first direction when viewed in a plan view from a direction perpendicular to the first main surface.

8. 8 . The silicon carbide semiconductor device according to claim 7 , wherein a distance between the gate trenches adjacent to each other in the first direction is not less than 0.20 times and not more than 0.40 times a dimension of the gate trench in the first direction.

9. The silicon carbide semiconductor device according to claim 1 , wherein the contact region is provided on only one side of the gate trench in the second direction.

10. 10. The silicon carbide semiconductor device according to claim 1, wherein the side surface of the gate trench includes a {0-33-8} plane.

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