Semiconductor equipment

Abstract

To provide a semiconductor device which can prevent the occurrence of a problem such as an increase in leakage current and a reduction in voltage-withstanding even when the reverse bias is applied for a long period of time to a space between a drain and a source under a high-temperature environment.SOLUTION: A semiconductor device comprises: a first conductive type semiconductor layer 20; an active electrode layer 30 which is formed on one side of the semiconductor layer 20 in an active region; a plurality of voltage-withstanding buried layers 25 which are formed on the semiconductor layer 20 in a voltage-withstanding region surrounding the active region and are made of a second conductive type semiconductor material; and an interlayer insulating layer 40 which is formed on one side of the voltage-withstanding buried layers 25 and in which conductive films 11, 12 extending in the in-plane direction are buried. The conductive films 11, 12 have the first conductive film 11, and the second conductive film 12 provided on a side closer to one side than the first conductive film 11.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device having a voltage-resistant region surrounding an active region. [Background technology]

[0002] Conventional semiconductor devices with a superjunction structure have been known. In semiconductor devices with a superjunction structure, multiple (e.g., dozens) guard rings are provided in the breakdown region surrounding the active region. Therefore, under reverse bias, the depletion layer extends from the active region to the outermost periphery of the breakdown region, thereby increasing the breakdown voltage of the semiconductor device.

[0003] Patent Document 1 proposes a semiconductor device having such a superjunction structure that prevents leakage current from increasing and breakdown voltage from decreasing, especially when reverse bias is applied for a long period of time in a high-temperature environment. Patent Document 1 proposes a semiconductor device having a superjunction structure, comprising a semiconductor layer of a first conductivity type, a plurality of columnar embedded layers made of a semiconductor material of a second conductivity type formed on the surface of the semiconductor layer in the active region, an active electrode layer formed on the surface of the semiconductor layer in the active region, a plurality of annular columnar embedded layers made of a semiconductor material of a second conductivity type formed on the surface of the semiconductor layer in the breakdown voltage region surrounding the active region, and an insulating layer formed on the surface of the semiconductor layer in the breakdown voltage region and the peripheral region surrounding the breakdown voltage region, further comprising a second annular columnar embedded layer made of a semiconductor material of a second conductivity type formed on the surface of the semiconductor layer in the peripheral region, and an annular conductive layer formed on the insulating layer in the peripheral region.

[0004] However, when reverse bias is applied for a long period of time in a high-temperature environment, mobile ions in the package resin can move through the passivation film and interlayer insulating film, and even to the top of the superjunction structure, affecting the elongation of the depletion layer. This can lead to problems such as an increase in leakage current and a decrease in breakdown voltage due to a disruption in the electric field strength distribution on the surface. [Prior art documents]

Patent Document

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] The present invention provides a semiconductor device that can prevent problems such as an increase in leakage current and a decrease in breakdown voltage even when a reverse bias is applied for a long time in a high-temperature environment.

Means for Solving the Problems

[0007] The semiconductor device according to the present invention includes a semiconductor layer of a first conductivity type, an active electrode layer formed on one side of the semiconductor layer in the active region, a plurality of breakdown voltage embedded layers formed in the semiconductor layer in the breakdown voltage region surrounding the active region and made of a semiconductor material of a second conductivity type, an insulating film formed on one side of the breakdown voltage embedded layer and having a conductive film embedded therein and extending in the in-plane direction, and the conductive film may have a first conductive film and a second conductive film provided on one side of the first conductive film.

[0008] In the semiconductor device according to the present invention, the first conductive film has a plurality of first conductive separation films spaced apart from each other, and the second conductive film may have a plurality of second conductive separation films spaced apart from each other.

[0009] In the semiconductor device according to the present invention, the second conductive separation film is provided at a location overlapping the breakdown voltage embedded layer in a plan view, and the first conductive separation film may be provided between the second conductive separation films in a plan view.

[0010] In the semiconductor device according to the present invention, a second conductive isolation film is provided corresponding to each of the plurality of breakdown voltage embedded layers, the first conductive isolation film may be provided between each of the second conductive isolation films in a plan view.

[0011] The semiconductor device according to the present invention includes a peripheral electrode layer formed on one side of the semiconductor layer in the breakdown voltage region, In a longitudinal cross-section, the number of the breakdown voltage embedded layers provided between the active electrode layer and the peripheral electrode layer and the number of the second conductive isolation films may be the same.

[0012] The semiconductor device according to the present invention includes a peripheral electrode layer formed on one side of the semiconductor layer in the breakdown voltage region, In a plan view, an outer end portion of the outermost second conductive isolation film and the peripheral electrode layer may overlap.

[0013] In the semiconductor device according to the present invention, In a plan view, an inner end portion of the innermost second conductive isolation film and the active electrode layer may overlap.

Advantages of the Invention

[0014] By adopting an insulating film formed on one side of the breakdown voltage embedded layer as in the present invention, in which a conductive film extending in the in-plane direction is embedded, and the insulating film has a first conductive film and a second conductive film provided on one side of the first conductive film, even when a reverse bias is applied for a long time in a high-temperature environment, it is possible to prevent the problem that an increase in leakage current and a decrease in breakdown voltage occur.

Brief Description of the Drawings

[0015] [Figure 1] A longitudinal cross-sectional view of a semiconductor device according to a first embodiment of the present invention. [Figure 2]A longitudinal cross-sectional view showing the in-plane overlap of the pressure-resistant embedding layer, the first conductive separation film, and the second conductive separation film in a semiconductor device according to the first embodiment of the present invention. [Figure 3] A longitudinal cross-sectional view showing the in-plane overlap between the peripheral electrode layer and the second conductive separation film in a semiconductor device according to the first embodiment of the present invention. [Figure 4] A longitudinal cross-sectional view showing the in-plane overlap between the active electrode layer and the second conductive separation film in a semiconductor device according to the first embodiment of the present invention. [Figure 5] A schematic longitudinal cross-sectional view showing how mobile ions are trapped by a pseudo-capacitor in a semiconductor device according to the first embodiment of the present invention. [Figure 6A] A graph showing the surface electric field strength during HTRB testing when neither the first nor the second conductive film is applied. [Figure 6B] A graph showing the surface electric field strength during HTRB testing when the first and second conductive films are applied. [Figure 7A] A schematic plan view showing a first conductive film arranged in an annular shape in a plan view in a first embodiment of the present invention. [Figure 7B] A schematic plan view showing a second conductive film arranged in an annular shape in a plan view in the first embodiment of the present invention. [Figure 8] A longitudinal cross-sectional view of a semiconductor device according to a modified example of the first embodiment of the present invention. [Figure 9] A longitudinal cross-sectional view of a semiconductor device in a second embodiment of the present invention, wherein the second conductive film extends longer in the second direction than the first conductive film. [Figure 10] A longitudinal cross-sectional view of a semiconductor device in a second embodiment of the present invention, in which the first conductive film and the second conductive film extend in a second direction with approximately the same length. [Figure 11] A longitudinal cross-sectional view of a semiconductor device according to a third embodiment of the present invention. [Figure 12] A longitudinal cross-sectional view showing an embodiment in which multiple conductive separation films, each consisting of a single conductive film, are provided in an interlayer insulating layer. [Modes for carrying out the invention]

[0016] First Embodiment "composition" In this embodiment, "one side" refers to the upper side of Figure 1, and "the other side" refers to the lower side of Figure 1. The vertical direction in Figure 1 is called the "first direction," the horizontal direction is called the "second direction," and the front-to-back direction of the paper is called the "third direction." The in-plane direction including the second and third directions is called the "in-plane direction." The view from one side of the first direction is called a plan view. In this embodiment, the second direction refers to the direction perpendicular to the direction in which the pressure-resistant embedded layer 25, which consists of a guard ring described later, extends.

[0017] The semiconductor device according to this embodiment may be a Schottky barrier diode having a superjunction structure. However, it is not limited to this, and may also be a pn diode, MOSFET, thyristor, IGBT, etc.

[0018] As shown in Figure 1, the semiconductor device includes a first conductivity type semiconductor layer 20, an active electrode layer 30 formed on one side of the semiconductor layer 20 in the active region, a plurality of withstand voltage embedding layers 25 formed on the semiconductor layer 20 in the withstand voltage region surrounding the active region and made of a second conductivity type semiconductor material, and an interlayer insulating layer 40 formed on one side of the withstand voltage embedding layer 25, in which conductive films 11 and 12 extending in the in-plane direction are embedded. The conductive films 11 and 12 include a first conductive film 11 and a second conductive film 12 provided on one side of the first conductive film 11 (the front side of the semiconductor device). The conductive films 11 and 12 may be made of, for example, polysilicon. The withstand voltage region may be provided surrounding a part or all of the active region. A peripheral region may be provided surrounding a part or all of the withstand voltage region. In this embodiment, n-type is used as the first conductivity type and p-type as the second conductivity type for explanation purposes, but it is not limited to this, and p-type may be used as the first conductivity type and n-type as the second conductivity type. The active region refers to the other side (lower side) of the region where the active electrode layer 30 is in contact with the semiconductor layer 20, and refers to the region where current flows from the back surface to the front surface when it is in the ON state. In the embodiment shown in Figure 1, the peripheral region refers to the other side (lower side) of the region where the peripheral electrode layer 60 is in contact with the semiconductor layer 20.

[0019] On the back side (downward side) of the n-type semiconductor layer 20, there is an n-type semiconductor layer with a higher impurity concentration than the semiconductor layer 20. + A semiconductor substrate 21 of type n may be provided. The n-type semiconductor layer 20 is n + It may also be formed by epitaxial growth on a semiconductor substrate 21 of a specific type.

[0020] n in the active region - Multiple columnar embedded layers 125 made of p-type silicon may be provided in the front surface region of the type semiconductor layer 20. - The active electrode layer 30 provided on the front surface of the semiconductor layer 20 may be a Schottky barrier metal layer as the source electrode layer. n in the breakdown voltage region surrounding the active region -The breakdown voltage embedded layer 25 provided in the front surface region of the n-type semiconductor layer 20 may be a plurality of guard rings (annular embedded layers) made of p-type silicon. n + A drain electrode layer 90 may be provided on the back surface of the n-type semiconductor substrate 21. The columnar embedded layer 125 may have a p-type high-concentration ohmic diffusion region (not shown) on the front surface side. The breakdown voltage embedded layer 25 may have a p-type high-concentration diffusion region (not shown) on the front surface side.

[0021] In the active region, n - On the front surface region of the n-type semiconductor layer 20, a p-type body region 161 and an n + type source region 165 and a p + type contact region 167 may be provided. Also, on the front surface of the n-type semiconductor layer 20 in the active region, a gate insulating layer 172, a gate electrode layer 170 provided on the front surface side of the gate insulating layer 172, and an interlayer insulating film 174 provided between the gate electrode layer 170 and the active electrode layer 30 which is the source electrode layer may be provided (see also FIG. 4). In the present embodiment, the mode in which the active electrode layer 30 which is the source electrode layer, the drain electrode layer 90, and the gate electrode layer 170 are provided is used for explanation, but it is not limited thereto, and a semiconductor device having an anode and a cathode may be used. -

[0022] A peripheral electrode layer 60 having an annular shape in plan view may be provided on one side of the interlayer insulating layer 40 in the peripheral region. The peripheral electrode layer 60 may be connected to an n-type high-concentration diffusion region (n - diffusion region) 65 formed in the front surface region of the n-type semiconductor layer 20. The impurity concentration of the n-type high-concentration diffusion region 65 is, for example, 1 × 10 ++ cm 19 ~5 × 10 -3 cm 20 -3 is.

[0023] n + The semiconductor substrate is composed of an n-type semiconductor substrate 21 and an n - type semiconductor layer 20. n - ​The thickness of the semiconductor layer 20 is, for example, 6 μm to 70 μm, n - The impurity concentration of the semiconductor layer 20 is, for example, 5 × 10⁻⁶. 13 cm -3 ~5×10 16 cm -3 n + The impurity concentration of the semiconductor substrate 21 is, for example, 1 × 10⁻⁶. 19 cm -3 ~5×10 20 cm -3 That is the case.

[0024] The columnar embedded layer 125 is n - The p-type semiconductor material (second conductivity type semiconductor material) may be formed by epitaxial growth inside the first trench 116 formed in the active region of the type semiconductor layer 20. The number of columnar embedded layers 125 can be appropriately set according to the purpose of use and structure. The impurity concentration of the p-type semiconductor material is, for example, 5 × 10⁻⁶. 13 cm -3 ~5×10 16 cm -3 That is the case.

[0025] The depth of the columnar embedded layer 125 is, for example, 5 μm to 50 μm, and the width of the columnar embedded layer 125 is, for example, 0.5 μm to 5 μm. The columnar embedded layer 125 may be formed parallel to each other at a first interval. The first interval is, for example, 1 μm to 15 μm.

[0026] The pressure-resistant embedding layer 25 is n - The p-type semiconductor material (second conductivity type semiconductor material) may be formed by epitaxial growth inside a second trench formed in the breakdown region of the type semiconductor layer 20. The number of breakdown embedding layers 25 is, for example, 5 to 50, but can be set appropriately according to the purpose of use and structure. The impurity concentration of the p-type semiconductor material is, for example, 2 × 10⁻⁶ 14 cm -3 ~5×10 16 cm -3 That is the case.

[0027] The depth of the pressure-resistant embedding layer 25 is, for example, 5 μm to 50 μm, and the width of the pressure-resistant embedding layer 25 is, for example, 0.5 μm to 5 μm. The pressure-resistant embedding layers 25 are formed parallel to each other at a second interval. The second interval is, for example, 1 μm to 15 μm.

[0028] The interlayer insulating layer 40 may be made of a silicon oxide film. The active electrode layer 30 is n - The semiconductor layer 20 may form a Schottky junction, and the columnar embedded layer 125 may form an ohmic junction. The active electrode layer 30 is made of a metal (e.g., aluminum), and its thickness is, for example, 5 μm. The peripheral electrode layer 60 is made of a metal (e.g., aluminum), and its thickness is, for example, 5 μm. The drain electrode layer 90 may be formed by depositing a metal electrode material (e.g., a multilayer metal film such as Ti-Ni-Au) onto the back surface of the semiconductor substrate. The total thickness of the multilayer metal film that makes up the drain electrode layer 90 is, for example, 0.5 μm. The peripheral electrode layer 60 is electrically connected to the drain electrode layer 90, and the peripheral electrode layer 60 and the drain electrode layer 90 may be at the same potential.

[0029] The first conductive film 11 may have a plurality of first conductive separation films 1 spaced apart from each other in the in-plane direction. Similarly, the second conductive film 12 may have a plurality of second conductive separation films 2 spaced apart from each other in the in-plane direction.

[0030] On the front side of the pressure-resistant embedding layer 25, a second conductive separation film 2 may be provided on a straight line extending from the pressure-resistant embedding layer 25 in the thickness direction of the semiconductor device (on a straight line extending parallel to the first direction) (see "A" in Figure 2). In this case, the second conductive separation film 2 will be provided in a location that overlaps with the pressure-resistant embedding layer 25 in a plan view. On the back side between the in-plane directions of the second conductive separation film 2, a first conductive separation film 1 may be provided on a straight line extending from that space (between the in-plane directions of the second conductive separation film 2) in the thickness direction of the semiconductor device (on a straight line extending parallel to the first direction) (see "B" in Figure 2). In this case, the first conductive separation film 1 will be provided between the second conductive separation films 2 in a plan view (see Figures 7A and 7B).

[0031] A second conductive separation film 2 may be provided corresponding to each of the multiple withstand-temperature embedded layers 25. In this case, the second conductive separation film 2 will be provided on a straight line extending from each of the multiple withstand-temperature embedded layers 25 toward the front surface in the thickness direction of the semiconductor device (a straight line extending parallel to the first direction). If one second conductive separation film 2 is provided on a straight line extending from each of the multiple withstand-temperature embedded layers 25 toward the front surface in the thickness direction of the semiconductor device (a straight line extending parallel to the first direction), the number of withstand-temperature embedded layers 25 and the number of second conductive separation films 2 will be the same. In this case, there may be no second conductive separation film 2 corresponding to the withstand-temperature embedded layer 25 located on the other side (back side, lower side in Figure 1) of the active electrode layer 30 and completely covered by the active electrode layer 30 in a plan view, and the number of withstand-temperature embedded layers 25 and the number of second conductive separation films 2 provided between the active electrode layer 30 and the peripheral electrode layer 60 in the in-plane direction may be the same (see Figure 1).

[0032] If the pressure-resistant embedding layer 25 is annular in plan view, the second conductive film 12 will also be annular in plan view, corresponding to the pressure-resistant embedding layer 25 (see Figure 7B). In this case, the annular first conductive film 11 will be provided between the second conductive separation films 2 in plan view (see Figure 7A). Figure 7B schematically shows the second conductive film 12, in which multiple second conductive separation films 2 are arranged at a certain distance apart (see Figure 1). Similarly, Figure 7A schematically shows the first conductive film 11, in which multiple first conductive separation films 1 are arranged at a certain distance apart (see Figure 1).

[0033] If the pressure-resistant embedding layer 25 has a dot shape in plan view, the second conductive separation film 2 also has a dot shape in plan view, corresponding to the pressure-resistant embedding layer 25. In this case, the first conductive separation film 1 also has a dot shape in plan view, corresponding to the second conductive separation film 2. However, considering the ease of design, it is beneficial to form the pressure-resistant embedding layer 25 from an annular shape in plan view, and to form each of the first conductive film 11 and the second conductive film 12 from an annular shape in plan view, as shown in Figures 7A and 7B.

[0034] In a plan view, the first conductive separation film 1 may be provided between each of the second conductive separation films 2. In this case, the first conductive separation film 1 will be provided on a straight line extending from each of the second conductive separation films 2 toward the back side in the thickness direction of the semiconductor device (a straight line extending parallel to the first direction).

[0035] The outermost end of the second conductive separation film 2, which is located on a straight line extending from the peripheral electrode layer 60 toward the back side of the semiconductor device in the thickness direction (a straight line extending parallel to the first direction), may be provided (see "C" in Figure 3). In this case, in a plan view, the outermost end of the second conductive separation film 2, which is located on the outermost side, will overlap with the peripheral electrode layer 60.

[0036] The inner end of the second conductive separation film 2, which is located furthest inward, may be provided on a straight line extending in the thickness direction of the semiconductor device (a straight line extending parallel to the first direction) on the back side of the semiconductor device from the active electrode layer 30 (see "D" in Figure 4). In this case, in a plan view, the inner end of the second conductive separation film 2, which is located furthest inward, will overlap with the active electrode layer 30.

[0037] The interlayer insulating layer 40 in which the first conductive film 11 and the second conductive film 12 of this embodiment are embedded is formed, for example, as follows.

[0038] First, the pressure-resistant embedding layer 25 is formed on the surface region to a thickness of approximately 1 / 3 of the final interlayer insulating layer 40. - An interlayer insulating layer 40 is formed on the semiconductor layer 20. Then, a first conductive film 11 is formed on the formed interlayer insulating layer 40. In this process, a conductive film made of, for example, polysilicon is formed, and by partially removing the conductive film, a plurality of first conductive separation films 1 are formed.

[0039] Next, an interlayer insulating layer 40 is formed to cover multiple first conductive separating films 1, up to approximately 2 / 3 of the final thickness of the interlayer insulating layer 40. After that, a second conductive film 12 is formed on the formed interlayer insulating layer 40. In this process, a conductive film made of, for example, polysilicon is formed, and multiple second conductive separating films 2 are formed by partially removing this conductive film.

[0040] Next, the remaining interlayer insulating layer 40 is formed so as to cover the multiple second conductive separation films 2. In this way, an interlayer insulating layer 40 is formed in which the first conductive film 11 and the second conductive film 12 are embedded.

[0041] In this embodiment, the first conductive film 11 and the second conductive film 12 are described using an arrangement in which they are provided within the interlayer insulating layer 40. However, the embodiment is not limited to this arrangement, and three or more layers may be stacked in the thickness direction (first direction) of the semiconductor device, and a third conductive film, a fourth conductive film, ..., an nth conductive film (where "n" is an integer of 3 or more) may be provided.

[0042] "effect" Next, an example of the effects of this embodiment, which has the configuration described above, will be explained. Note that any of the embodiments described in "Effects" can be adopted in the above configuration.

[0043] In the case of an interlayer insulating layer 40 formed on one side of the pressure-resistant embedded layer 25, in which conductive films 11 and 12 extending in the in-plane direction are embedded, and an interlayer insulating layer 40 having a first conductive film 11 and a second conductive film 12 provided on one side of the first conductive film 11 is adopted, it is possible to prevent problems such as an increase in leakage current and a decrease in withstand voltage from occurring even when a reverse bias is applied between the drain and source for a long time in a high-temperature environment.

[0044] When the first conductive film 11 has multiple first conductive separation films 1 spaced apart from each other, or when the second conductive film 12 has multiple second conductive separation films 2 spaced apart from each other, a pseudo-capacitor can be formed by the low-resistance first and second conductive separation films 1 and 2, and the interlayer insulating layer 40 sandwiched between them (see Figure 5), allowing mobile ions to be captured by the pseudo-capacitor. This makes it possible to more effectively prevent problems such as increased leakage current and decreased breakdown voltage. Figures 6A and 6B are graphs showing the surface electric field strength during HTRB (High Temperature Reverse Bias) testing, where the horizontal axis represents the in-plane distance from the active region and the vertical axis represents the electric field strength. According to the embodiment of this product, as shown in Figure 6B, the electric field strength can be maintained as designed without being affected by mobile ions. On the other hand, unlike in this embodiment, if the first conductive film 11 and the second conductive film 12 are not provided, as shown in Figure 6A, the electric field strength on the surface decreases due to mobile ions, the electric field strength increases at the outermost edge, and breakdown (BD) is more likely to occur.

[0045] In other words, if the first conductive film 11 and the second conductive film 12 are not provided as shown in Figure 6A, the mobile ions in the package resin become more mobile at high temperatures. As a result, the drain-source bias causes the mobile ions to accumulate on the surface of the surrounding structure, and these accumulated mobile ions affect the elongation of the depletion layer, disrupting the electric field strength distribution and potentially causing a decrease in breakdown voltage. In contrast, according to this embodiment, even if a reverse bias is continuously applied in a high-temperature environment, and mobile ions move into the interlayer insulating layer 40, the first conductive film 11 and the second conductive film 12 can block the mobile ions. Furthermore, mobile ions that attempt to slip through the block are captured by the capacitance formed by the first conductive film 11, the second conductive film 12 and the interlayer insulating layer 40 (see Figure 5), and are prevented from approaching the vicinity of the upper part of the interface between the semiconductor layer 20 and the interlayer insulating layer 40 of the surrounding structure (see Figure 6B). Therefore, it is possible to create a configuration that does not affect the elongation of the depletion layer in the surrounding structure and does not cause an increase in leakage current or fluctuations in breakdown voltage.

[0046] The inventors also experimented with a configuration in which multiple first conductive separation films 1 are provided in areas that overlap with the pressure-resistant embedded layer 25 in a plan view, and a second conductive separation film 2 is provided between the multiple first conductive separation films 1 (see Figure 8). However, from the viewpoint of not causing an increase in leakage current or fluctuations in withstand voltage, it was confirmed that the configuration in which multiple second conductive separation films 2 are provided on the upper side (one side) in areas that overlap with the pressure-resistant embedded layer 25 in a plan view, and a first conductive separation film 1 is provided on the lower side (the other side) between the multiple second conductive separation films 2 is preferable.

[0047] Furthermore, the inventors also experimented with a configuration in which multiple conductive separation films 111, each consisting of a single conductive film 110, are provided on the interlayer insulating layer 40 in areas that overlap with the pressure-resistant embedded layer 25 in a plan view (see Figure 12). However, they were unable to obtain sufficient results regarding the effect of preventing an increase in leakage current and fluctuations in withstand voltage.

[0048] When a second conductive separation film 2 is provided in a location that overlaps with the pressure-resistant embedded layer 25 in a plan view, and a first conductive separation film 1 is provided between the second conductive separation film 2 in a plan view, it is possible to position the second conductive separation film 2 on one side of the pressure-resistant embedded layer 25 while forming a pseudo-capacitor between the second conductive separation film 2 and the first conductive separation film 1. This is beneficial because it can more effectively prevent problems such as increased leakage current and decreased breakdown voltage.

[0049] When a second conductive separation film 2 is provided corresponding to each of the multiple withstand-voltage embedded layers 25, and a first conductive separation film 1 is provided between each of the second conductive separation films 2 in a plan view, it is possible to provide a second conductive separation film 2 corresponding to each of the multiple withstand-voltage embedded layers 25, and to form a pseudo-capacitor between the second conductive separation film 2 and the first conductive separation film 1 corresponding to the second conductive separation film 2, which is beneficial in that it can prevent an increase in leakage current and a decrease in withstand voltage caused by each withstand-voltage embedded layer 25.

[0050] In a longitudinal cross-section, if the number of pressure-resistant embedding layers 25 provided between the active electrode layer 30 and the peripheral electrode layer 60 is the same as the number of second conductive separation films 2, and a first conductive separation film 1 is provided between each of the second conductive separation films 2, then it is possible to provide a second conductive separation film 2 that corresponds one-to-one with each pressure-resistant embedding layer 25, which is beneficial in that it can more effectively prevent increases in leakage current and decreases in breakdown voltage caused by each pressure-resistant embedding layer 25. Furthermore, in order to effectively capture the mobile ions described above, it is preferable, as in this embodiment, that the number of pressure-resistant embedding layers 25 provided between the active electrode layer 30 and the peripheral electrode layer 60 is the same as the number of second conductive separation films 2, and that a first conductive separation film 1 is provided between each of the second conductive separation films 2, compared to the arrangements in the second and third embodiments described later.

[0051] In a plan view, when the outermost edge of the second conductive separation film 2, which is located furthest out, overlaps with the surrounding electrode layer 60 (see Figure 3), it is advantageous in that the second conductive separation film 2, which is located furthest out, can be kept in a stable voltage state.

[0052] In a plan view, when the inner end of the innermost second conductive separation film 2 overlaps with the active electrode layer 30 (see Figure 4), it is advantageous in that the innermost second conductive separation film 2 can be kept in a stable voltage state.

[0053] Second Embodiment Next, a second embodiment of the present invention will be described.

[0054] In this embodiment, as shown in Figure 9, a first conductive film 11 (first conductive separation film 1) extending in the plane may be provided. Similarly, a second conductive film 12 (second conductive separation film 2) extending in the plane is provided. The other configurations are the same as in the first embodiment, and any configuration described in the first embodiment can be adopted. The same reference numerals are used to describe the components described in the first embodiment.

[0055] In the embodiment shown in Figure 9, the second conductive film 12 extends longer in the second direction than the first conductive film 11. However, the embodiment is not limited to this configuration; for example, as shown in Figure 10, the first conductive film 11 and the second conductive film 12 may extend to roughly the same length in the second direction. Alternatively, the first conductive film 11 may extend longer in the second direction than the second conductive film 12.

[0056] In this embodiment as well, a pseudo-capacitor can be formed between the first conductive film 11 and the second conductive film 12, preventing problems such as increased leakage current and reduced breakdown voltage. However, it cannot be denied that there is a risk of voltage concentration at one point in the first conductive film 11 or the second conductive film 12, which may reduce the breakdown voltage. For this reason, as shown in the first embodiment, it is more advantageous to adopt an embodiment in which the first conductive film 11 has a plurality of first conductive separation films 1 spaced apart from each other, and the second conductive film 12 has a plurality of second conductive separation films 2 spaced apart from each other.

[0057] Third Embodiment Next, a third embodiment of the present invention will be described.

[0058] In this embodiment, as shown in Figure 11, the second conductive film 12 is provided in a manner that does not correspond one-to-one with the pressure-resistant embedding layer 25, and the first conductive separation film 1 is provided corresponding to the second conductive film 12. The other configurations are the same as in the first embodiment, and any configuration described in the first embodiment can be adopted. The same reference numerals are used to describe the components described in the first embodiment.

[0059] In this embodiment as well, a pseudo-capacitor can be formed between the first conductive film 11 and the second conductive film 12, preventing problems such as increased leakage current and reduced breakdown voltage. However, in terms of effectiveness, adopting the configuration shown in the first embodiment, in which a second conductive separation film 2 is provided in a one-to-one correspondence with the breakdown embedding layer 25, and a first conductive separation film 1 is provided between each of the second conductive separation films 2, is advantageous because it allows for the provision of a second conductive separation film 2 and a first conductive separation film 1 corresponding to each breakdown embedding layer 25, thereby more effectively preventing problems such as increased leakage current and reduced breakdown voltage. Furthermore, from the viewpoint of reducing the risk of reduced breakdown voltage as a result of voltage concentration, as mentioned in the second embodiment, adopting the configuration of the first embodiment is also advantageous.

[0060] The descriptions of the embodiments and the disclosure of the drawings described above are merely examples for illustrating the invention described in the claims, and the invention described in the claims is not limited by the descriptions of the embodiments or the disclosure of the drawings described above. Furthermore, the description of the claims at the time of filing is merely an example, and the description of the claims can be modified as appropriate based on the description in the specification, drawings, etc. [Explanation of symbols]

[0061] 1 First conductive spacing film 2 Second conductive spacing film 11. First conductive film 12 Second conductive film 20 Semiconductor layer 25 Pressure-resistant embedded layer 30 Active electrode layer 40 interlayer insulating layer 60 Peripheral electrode layer

Claims

1. A first-type conductive semiconductor layer, An active electrode layer formed on one side of the semiconductor layer in the active region, Multiple pressure-resistant embedded layers made of a second-conductivity semiconductor material are formed in the semiconductor layer in the pressure-resistant region surrounding the active region, An insulating film formed on one side of the pressure-resistant embedded layer, wherein an insulating film having a conductive film extending in the in-plane direction is embedded, Equipped with, The conductive film comprises a first conductive film and a second conductive film provided on one side of the first conductive film. The first conductive film has a plurality of first conductive films spaced apart from each other. The second conductive film has a plurality of second conductive films spaced apart from each other, A semiconductor device in which the second conductive separation film is provided on a straight line extending in the thickness direction from the pressure-resistant embedding layer, and the first conductive separation film is provided on the entire back surface between the second conductive separation film in the in-plane direction.

2. The second conductive separation film is provided corresponding to each of the multiple pressure-resistant embedding layers. The semiconductor device according to claim 1, wherein, in a plan view, the first conductive separation film is provided between each of the second conductive separation films.

3. The semiconductor layer in the breakdown voltage region comprises a peripheral electrode layer formed on one side of the semiconductor layer, The semiconductor device according to claim 2, wherein in a longitudinal section, the number of pressure-resistant embedding layers provided between the active electrode layer and the peripheral electrode layer is the same as the number of second conductive separation films.

4. The semiconductor layer in the breakdown voltage region comprises a peripheral electrode layer formed on one side of the semiconductor layer, The semiconductor device according to any one of claims 1 to 3, wherein, in a plan view, the outermost end of the second conductive separation film located furthest outward overlaps with the peripheral electrode layer.

5. The semiconductor device according to any one of claims 1 to 3, wherein, in a plan view, the inner end of the second conductive separation film located furthest inward overlaps with the active electrode layer.

Images