Image sensor and imaging device

Abstract

To provide an image capturing element.SOLUTION: An image capturing element includes: a first substrate having a plurality of pixel blocks each including one or more pixels; and a second substrate that has a control circuit unit including a first control block including a first exposure control unit for controlling an exposure time of a pixel included in a first pixel block of the plurality of pixel blocks and a second control block including a second exposure control unit for controlling an exposure time of a pixel included in a second pixel block of the plurality of pixel blocks, and that has a peripheral circuit unit arranged outside the control circuit unit and configured to control signal reading of pixels each included in at least the first pixel block and the second pixel block of the plurality of pixel blocks.SELECTED DRAWING: Figure 1E

Description

Technical Field

[0001] The present invention relates to an imaging device and an imaging apparatus.

Background Art

[0002] In an imaging device having a plurality of pixels, it is known to change the exposure time for each pixel (for example, Patent Document 1). Patent Document 1: Japanese Patent Translation No. 2015-532797

[0003] In a conventional imaging device, simplification of the circuit is desired.

Summary of the Invention

[0004] In a first aspect of the present invention, there is provided an imaging device including: a first substrate having a plurality of pixel blocks including one or more pixels; a first control block including a first exposure control unit for controlling the exposure time of pixels included in a first pixel block among the plurality of pixel blocks; a second control block including a second exposure control unit for controlling the exposure time of pixels included in a second pixel block among the plurality of pixel blocks; a control circuit unit including the first control block and the second control block; and a second substrate disposed outside the control circuit unit and having a peripheral circuit unit for controlling signal readout of pixels included in at least the first pixel block and the second pixel block among the plurality of pixel blocks.

[0005] In a second aspect of the present invention, there is provided an imaging apparatus including the imaging device according to the first aspect.

[0006] Note that the above summary of the invention does not list all the necessary features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0007] [Figure 1A] This is a diagram showing an overview of an imaging device 400 according to an embodiment of the present invention. [Figure 1B] An example of a specific configuration of the pixel unit 110 is shown. [Figure 1C] An example of the circuit configuration for pixel 112 is shown. [Figure 1D] A more specific example of the configuration of the control circuit unit 210 is shown below. [Figure 1E] This is a diagram illustrating an example of a wiring method for the image sensor 400. [Figure 2A] An example of a timing chart showing the imaging operation of the image sensor 400 is shown. [Figure 2B] An example of a timing chart showing the imaging operation of the image sensor 400 is shown. [Figure 3] A timing chart showing the imaging operation of the image sensor in the comparative example is shown. [Figure 4A] An example of a subject captured by the image sensor 400 is shown. [Figure 4B] A timing chart showing the imaging operation of the image sensor 400 is shown. [Figure 5] This diagram shows an overview of the image sensor 400. [Figure 6] An example of the specific configuration of the pixel section 110 is shown. [Figure 7] A more specific example of the configuration of the control circuit unit 210 is shown below. [Figure 8] An example of the circuit configuration for pixel 112 is shown. [Figure 9] This is a diagram illustrating an example of a wiring method for the image sensor 400. [Figure 10] This is a diagram illustrating an example of a wiring method for the image sensor 400. [Figure 11] This is a diagram illustrating an example of a wiring method for the image sensor 400. [Figure 12] An example of a timing chart showing the imaging operation within the pixel block 120 of the image sensor 400 is shown. [Figure 13] An example of exposure timing for every 120 pixel blocks is shown. [Figure 14] This figure shows an overview of the image sensor 800 according to another embodiment. [Figure 15] An example of the specific configuration of the pixel section 610 is shown. [Figure 16] An example of a more specific configuration of the control circuit unit 710 is shown. [Figure 17] An example of the exposure timing for each pixel block 620 is shown. [Figure 18] Another example of the pixel 114 of the imaging devices 400 and 800 is shown. [Figure 19] An example of a timing chart showing the imaging operation within the pixel block 120 using the pixel 114 is shown. [Figure 20] An example of the exposure timing for each pixel block 120 using the pixel 114 is shown. [Figure 21] FIG. 16 is a block diagram showing a configuration example of the imaging device 500 according to the embodiment.

Mode for Carrying Out the Invention

[0008] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0009] In this specification, the X-axis and the Y-axis are orthogonal to each other, and the Z-axis is orthogonal to the XY plane. The XYZ axes form a right-handed system. The direction parallel to the Z-axis may be referred to as the stacking direction of the imaging device 400. In this specification, the terms “upper” and “lower” are not limited to the vertical direction in the gravitational direction. These terms merely indicate the relative direction in the Z-axis direction. Note that in this specification, the arrangement in the X-axis direction will be described as “row” and the arrangement in the Y-axis direction as “column”, but the matrix direction is not limited to this.

[0010] FIG. 1A is a diagram showing an overview of the imaging device 400 according to the present embodiment. The imaging device 400 images a subject. The imaging device 400 generates image data of the imaged subject. The imaging device 400 includes a first substrate 100 and a second substrate 200. As shown in FIG. 1A, the first substrate 100 is laminated on the second substrate 200.

[0011] The first substrate 100 has a pixel section 110. The pixel section 110 outputs a pixel signal based on incident light.

[0012] The second substrate 200 has a control circuit section 210 and a peripheral circuit section 230.

[0013] The control circuit unit 210 receives the pixel signal output from the first substrate 100. The control circuit unit 210 processes the input pixel signal. In this example, the control circuit unit 210 is located on the second substrate 200, opposite the pixel unit 110. The control circuit unit 210 may also output a control signal to the pixel unit 110 to control the driving of the pixel unit 110.

[0014] The peripheral circuit section 230 controls the driving of the control circuit section 210. In one example, the peripheral circuit section 230 controls the signal readout of pixels included in the pixel section 110. The peripheral circuit section 230 is located on the second substrate 200, periphery of the control circuit section 210. Alternatively, the peripheral circuit section 230 may be electrically connected to the first substrate 100 and control the driving of the pixel section 110. In this example, the peripheral circuit section 230 is located along two sides of the second substrate 200, but the arrangement of the peripheral circuit section 230 is not limited to this example.

[0015] Furthermore, the image sensor 400 may have a memory chip stacked on the second substrate 200, in addition to the first substrate 100 and the second substrate 200. For example, the memory chip performs image processing according to the signal output by the second substrate 200. Also, the structure of the image sensor 400 may be back-illuminated or front-illuminated.

[0016] Figure 1B shows an example of the specific configuration of the pixel section 110. In this example, the pixel section 110 and an enlarged view of the pixel block 120 provided in the pixel section 110 are shown.

[0017] The pixel section 110 has multiple pixel groups 115 arranged in a row and column direction. In this example, the pixel section 110 has M × N pixel groups 115 (where M and N are natural numbers). In this example, the case where M is equal to N is illustrated, but M and N may be different.

[0018] A pixel group 115 has at least one pixel 112. In this example, the pixel group 115 has m × n pixels 112 (where m and n are natural numbers). For example, the pixel group 115 has 16 × 16 pixels 112. The number of pixels 112 corresponding to the pixel group 115 is not limited to this. In this example, the case where m is equal to n is illustrated, but m may be different from n. The pixel group 115 has multiple pixels 112 connected to a common control line in the row direction. For example, each pixel 112 of the pixel group 115 is connected to a common control line so that it is set to the same exposure time. In one example, n pixels 112 arranged in the row direction are connected by a common control line.

[0019] On the other hand, each pixel group 115 may be set to a different exposure time. That is, each pixel 112 in pixel group 115 may have the same exposure time, but other pixel groups 115 may have different exposure times. For example, if the pixels 112 of pixel group 115 are connected by a common control line in the row direction, the pixels 112 of other pixel groups 115 may be connected by different control lines.

[0020] A pixel block 120 has one or more pixel groups 115. In this example, the pixel block 120 has two pixel groups 115 arranged side by side along the column direction. The pixel block 120 is arranged in correspondence with the control block 220, which will be described later. That is, two pixel groups 115 are arranged for one control block 220. When the pixel block 120 has multiple pixel groups 115, each pixel group 115 may be set to a different exposure time. When the pixel block 120 has one pixel group 115, one pixel group 115 is arranged for the control block 220. The pixel block 120 has 2m × n pixels 112. For example, the pixel block 120 has 32 × 16 pixels 112. The number of pixels 112 corresponding to the pixel block 120 is not limited to this.

[0021] Pixel 112 has a photoelectric conversion function that converts light into electric charge. Pixel 112 stores the photoelectrically converted charge. 2m pixels 112 are arranged along the column direction and connected to a common signal line 122. The 2m pixels 112 are then arranged in n columns in the row direction within the pixel block 120.

[0022] Figure 1C shows an example of the circuit configuration of pixel 112. Pixel 112 comprises a photoelectric conversion unit 104, a transfer unit 123, an output unit 124, a reset unit 126, and a pixel output unit 127. The pixel output unit 127 includes an amplification unit 128 and a selection unit 129. In this example, the transfer unit 123, output unit 124, reset unit 126, amplification unit 128, and selection unit 129 are described as N-channel FETs, but the type of transistor is not limited to this.

[0023] The photoelectric conversion unit 104 has a photoelectric conversion function that converts light into electric charge. The photoelectric conversion unit 104 stores the photoelectrically converted charge. The photoelectric conversion unit 104 is, for example, a photodiode.

[0024] The transfer unit 123 transfers the charge stored in the photoelectric conversion unit 104 to the storage unit 125. The transfer unit 123 is an example of a transfer gate that transfers the charge from the photoelectric conversion unit 104. The gate terminal of the transfer unit 123 is connected to a local control line for inputting the first transfer control signal φTX1. The local control line will be described later.

[0025] The discharge unit 124 discharges the charge accumulated in the photoelectric conversion unit 104 to the power supply wiring supplied with the power supply voltage VDD. The gate terminal of the discharge unit 124 is connected to the local control line for inputting the second transfer control signal φTX2. In this example, the discharge unit 124 is described as discharging the charge of the photoelectric conversion unit 104 to the power supply wiring supplied with the power supply voltage VDD, but it may also be discharged to power supply wiring supplied with a power supply voltage different from the power supply voltage VDD.

[0026] The storage unit 125 receives charge from the photoelectric conversion unit 104 via the transfer unit 123. The storage unit 125 is an example of floating diffusion (FD).

[0027] The reset unit 126 discharges the charge from the storage unit 125 to the power supply wiring to which a predetermined power supply voltage VDD is supplied. The gate terminal of the reset unit 126 is connected to the global control line 163 for inputting the reset control signal φRST. The global control line 163 will be described later.

[0028] The pixel output unit 127 outputs a signal based on the potential of the storage unit 125 to the signal line 122. The pixel output unit 127 includes an amplification unit 128 and a selection unit 129. The gate terminal of the amplification unit 128 is connected to the storage unit 125, the drain terminal is connected to the power supply wiring to which the power supply voltage VDD is supplied, and the source terminal is connected to the drain terminal of the selection unit 129.

[0029] The selection unit 129 controls the electrical connection between the pixel 112 and the signal line 122. When the selection unit 129 electrically connects the pixel 112 and the signal line 122, a pixel signal is output from the pixel 112 to the signal line 122. The gate terminal of the selection unit 129 is connected to the global control line 163 for inputting the selection control signal φSEL. The source terminal of the selection unit 129 is connected to the load current source 121.

[0030] The load current source 121 supplies current to the signal line 122. The load current source 121 may be provided on the first substrate 100 or on the second substrate 200.

[0031] Figure 1D shows a more specific example of the configuration of the control circuit unit 210. In this example, the control circuit unit 210 and an enlarged view of the control block 220 provided in the control circuit unit 210 are shown.

[0032] The control circuit unit 210 has control blocks 220 arranged along the row and column directions. In this example, the control circuit unit 210 has (M / 2) × N control blocks 220. In this example, the control circuit unit 210 has one control block 220 for two pixel groups 115 arranged side by side along the column direction.

[0033] The control blocks 220 are positioned at locations corresponding to the pixel blocks 120. The control blocks 220 control the driving of the corresponding pixel blocks 120. For example, the control block 220 controls the exposure time of the pixel block 120. The control block 220 may also control the exposure time for each pixel group 115. The control block 220 also has processing circuits such as an AD converter and processes the signals output by the pixel blocks 120. In one example, the control block 220 converts the analog pixel signals output from the corresponding pixel blocks 120 into digital signals. In this example, the control block 220 comprises an exposure control unit 10, a pixel driving unit 20, a junction unit 30, a signal processing unit 40, and a signal output unit 50.

[0034] The exposure control unit 10 controls the exposure of multiple pixels 112. The exposure control unit 10 generates signals to control the exposure time of the pixels 112. In one example, the exposure control unit 10 controls the exposure time for each pixel group 115 by adjusting at least one of the start timing or end timing of the exposure. In this example, the exposure control unit 10 is provided extending in the row direction.

[0035] The pixel drive unit 20 is bonded to the first substrate 100 and drives a plurality of pixels 112. The pixel drive unit 20 selects and drives any pixel 112 from the plurality of pixels 112. In this example, the pixel drive unit 20 is provided extending in the column direction. As a result, the pixel drive unit 20 is positioned in a location corresponding to 2m pixels 112 arranged in the column direction. The exposure control unit 10 and the pixel drive unit 20 are arranged in an L-shape, with the pixel drive unit 20 extending in the column direction and the exposure control unit 10 extending in the row direction.

[0036] The joint 30 joins the first substrate 100 and the second substrate 200. The joint 30 inputs the pixel signal received from the first substrate 100 to the signal processing unit 40. The joint 30 is provided in accordance with n pixels 112 arranged in the row direction and inputs the pixel signal to the signal processing unit 40 column by column.

[0037] The signal processing unit 40 converts the analog signals output by the pixel unit 110 into digital signals. In this example, the signal processing unit 40 converts analog pixel signals into digital signals. The signal processing unit 40 sequentially converts the analog signals from 2m pixels 112 arranged in the column direction into digital signals. The signal processing unit 40 also converts the analog signals from n pixels 112 arranged in the row direction into digital signals in parallel.

[0038] The signal output unit 50 receives a digital signal from the signal processing unit 40. In one example, the signal output unit 50 temporarily stores the digital signal. The signal output unit 50 may have a latch circuit for storing the digital signal. The signal output unit 50 is located in the column direction between the signal processing unit 40 and the exposure control unit 10 and outputs a digital signal. In this example, the signal output unit 50 outputs a digital signal outside the control circuit unit 210. The signal output unit 50 extends in the row direction and is located adjacent to the signal processing unit 40 and the exposure control unit 10.

[0039] The image sensor 400 in this example has a function to read out pixel signals in parallel using a control block 220 provided for each pixel block 120. The image sensor 400 can set the exposure time for each pixel group 115 according to the intensity of the incident light, thereby expanding the dynamic range.

[0040] Figure 1E is a diagram illustrating an example of the wiring method for the image sensor 400. In this example, the global drive unit 234 is provided in the peripheral circuit unit 230, which is arranged on both ends of the control circuit unit 210.

[0041] The local control line 161 is connected to the pixel block 120a. In this example, the local control line 161 is connected to the gate terminals of the transfer unit 123 and the output unit 124 provided in the pixel block 120a. The local control line 161 supplies the first transfer control signal φTX1 and the second transfer control signal φTX2 output from the control block 220a to the pixel block 120a. The local control line 161 is an example of a first control line connected to the first pixel of the pixel block 120. The local control line 161 may also be provided corresponding to the pixel group 115 of the pixel block 120a. For example, in the pixel group 115, a common local control line 161 is connected to n pixels 112 arranged in the row direction.

[0042] The local control line 162 is connected to the pixel block 120b. In this example, the local control line 162 is connected to the gate terminals of the transfer unit 123 and the output unit 124 provided in the pixel block 120b. The local control line 162 supplies the first transfer control signal φTX1 and the second transfer control signal φTX2 output from the control block 220b to the pixel block 120b. The local control line 162 is an example of a second control line connected to the second pixel of the pixel block 120. The local control line 162 may also be provided corresponding to the pixel group 115 of the pixel block 120b. For example, in the pixel group 115, a common local control line 162 is connected to n pixels 112 arranged in the row direction.

[0043] The global drive unit 234 outputs a reset control signal φRST, a selection control signal φSEL, and a transfer selection control signal φTXSEL. The global drive unit 234 is connected to a global control line 163 that outputs signals to each pixel block 120. The global drive unit 234 supplies the reset control signal φRST and the selection control signal φSEL to multiple pixel blocks 120 via the global control line 163. The global drive unit 234 also supplies the transfer selection control signal φTXSEL to multiple control blocks 220 via the global control line 163.

[0044] The transfer selection control signal φTXSEL is supplied from the global drive unit 234 to the control block 220 to control the exposure time for each pixel group 115. The control block 220, upon receiving the transfer selection control signal φTXSEL, outputs it to the corresponding pixel block 120. The pixel block 120 decides whether or not to input the transfer selection control signal φTXSEL to the pixel 112 as either the first transfer control signal φTX1 or the second transfer control signal φTX2. As a result, input of either the first transfer control signal φTX1 or the second transfer control signal φTX2 to the pixel 112 is skipped.

[0045] For example, if the first transfer control signal φTX1 determines the end time of exposure, the control block 220 extends the exposure time by skipping the first transfer control signal φTX1. Conversely, if the first transfer control signal φTX1 determines the start time of exposure, the control block 220 can shorten the exposure time by skipping the first transfer control signal φTX1. In this way, the exposure time of the pixel group 115 can be adjusted by the transfer selection control signal φTXSEL. The same applies when the second transfer control signal φTX2 determines the start or end time of exposure.

[0046] The global control line 163 is provided in common to multiple pixel blocks 120. In this example, the global control line 163 is routed to traverse the first substrate 100 in the row direction. The global control line 163 may also be routed to traverse the first substrate 100 in the column direction. The global control line 163 is an example of a third control line provided in common to pixels connected to local control line 161 and pixels connected to local control line 162.

[0047] For example, the global control line 163 is connected to the gate terminals of the reset unit 126 and the selection unit 129 of the pixel block 120, supplying the reset control signal φRST and the selection control signal φSEL. The global control line 163 is also connected to each of the multiple control blocks 220, supplying the transfer selection control signal φTXSEL to the exposure control unit 10.

[0048] In this example, the global drive unit 234 outputs a transfer selection control signal φTXSEL from the second board 200 to the first board 100. However, it may also output the transfer selection control signal φTXSEL to the control block 220 without supplying it to the first board 100. In this case, the global control line 163 is provided on the second board 200.

[0049] Multiple bumps 152 are provided on the bonding surface where the first substrate 100 and the second substrate 200 are joined to each other. The bumps 152 on the first substrate 100 are aligned with the bumps 152 on the second substrate 200. Multiple opposing bumps 152 are joined and electrically connected by pressurization or other means on the first substrate 100 and the second substrate 200.

[0050] In this example, the image sensor 400 controls the exposure time for each pixel group 115 by changing the timing of at least one of the transfer unit 123 and the ejection unit 124 using local control lines. By combining local control lines and global control lines, the image sensor 400 can achieve exposure time control with fewer control lines.

[0051] Figure 2A shows an example of a timing chart illustrating the imaging operation of the image sensor 400. In this example, the drive of the image sensor 400 is controlled by the first transfer control signal φTX1, the second transfer control signal φTX2, the reset control signal φRST, and the selection control signal φSEL.

[0052] The second transfer control signal φTX2 controls the timing of the exposure start. The exposure start timing corresponds to the falling edge timing of the second transfer control signal φTX2 (for example, time T1). That is, before the exposure start time T1, the second transfer control signal φTX2 turns on the discharge unit 124 to discharge the charge accumulated in the photoelectric conversion unit 104, and exposure starts on the falling edge of the second transfer control signal φTX2. In this example, the second transfer control signal φTX2 is locally controlled, so the exposure time can be adjusted for each pixel group 115.

[0053] The first transfer control signal φTX1 controls the timing of the end of exposure. At time T3, the first transfer control signal φTX1 turns on the transfer unit 123, thereby transferring the charge accumulated in the photoelectric conversion unit 104 to the storage unit 125. The timing of the end of exposure corresponds to the falling edge timing of the first transfer control signal φTX1 (for example, time T4). In this example, the first transfer control signal φTX1 is a globally controlled signal, so the timing of the end of exposure is the same for each pixel group 115.

[0054] The reset control signal φRST controls the timing of discharge of the charge stored in the storage unit 125. At time T2, the reset control signal φRST turns on the reset unit 126, thereby discharging the charge from the storage unit 125. In this example, by discharging the charge from the storage unit 125 before the end of exposure, the influence of the charge remaining in the storage unit 125 during the transfer of charge from the photoelectric conversion unit 104 can be suppressed.

[0055] The selection control signal φSEL is a signal for selecting any pixel 112. The selection control signal φSEL controls the on / off state of the selection unit 129. At time T2, the selection control signal φSEL is set to high. At time T3, the pixel 112 for which the selection control signal φSEL is set to high outputs a pixel signal to the signal line 122 in response to the first transfer control signal φTX1 being turned on. On the other hand, the pixel 112 for which the selection control signal φSEL is not set to high does not output a pixel signal.

[0056] In this example, the image sensor 400 can control the exposure time for each pixel group 115 by locally controlling the second transfer control signal φTX2, thereby changing the exposure start timing for each pixel group 115. Alternatively, the image sensor 400 may control the exposure end timing for each pixel group 115 by locally controlling the first transfer control signal φTX1. Furthermore, the image sensor 400 may control both the exposure start and end timings for each pixel group 115 by locally controlling both the first transfer control signal φTX1 and the second transfer control signal φTX2.

[0057] Figure 2B shows an example of a timing chart illustrating the imaging operation of the image sensor 400. In this example, the drive of the image sensor 400 is controlled by the first transfer control signal φTX1, the reset control signal φRST, and the selection control signal φSEL. The image sensor 400 in this example differs from that in Figure 2A in that the timing of the start of exposure is controlled by the first transfer control signal φTX1. The differences between this example and Figure 2A will be explained in particular.

[0058] The first transfer control signal φTX1 controls the timing of the start and end of exposure. In frame (n), exposure starts at time T5 and ends at time T7.

[0059] At the exposure start time T5, exposure begins when the first transfer control signal φTX1 falls. That is, before the exposure start time T5, the first transfer control signal φTX1 turns on the transfer unit 123 with the reset control signal φRST turned on, thereby discharging the charge accumulated in the photoelectric conversion unit 104, and exposure begins when the first transfer control signal φTX1 falls. In this example, the first transfer control signal φTX1 is a locally controlled signal, so the timing of exposure start can be changed for each pixel group 115. However, the timing of exposure start may be synchronized for each pixel group 115.

[0060] Furthermore, at the exposure end time T7, the exposure ends when the first transfer control signal φTX1 falls. That is, before the exposure end time T7, the first transfer control signal φTX1 turns on the transfer unit 123 with the reset control signal φRST turned off, transferring the charge accumulated in the photoelectric conversion unit 104 to the storage unit 125, and the exposure ends when the first transfer control signal φTX1 falls. In this example, the first transfer control signal φTX1 is a locally controlled signal, so the timing of the exposure termination can be changed for each pixel group 115. However, the timing of the exposure termination may be synchronized for each pixel group 115.

[0061] The selection control signal φSEL is a signal for selecting any pixel 112. At time T6, a pixel 112 for which the selection control signal φSEL is set to high outputs a pixel signal to the signal line 122.

[0062] The reset control signal φRST controls the timing of the discharge of charge stored in the storage unit 125. The reset control signal φRST may be a globally controlled signal. Since the reset control signal φRST is always on except at the readout timing, no charge is stored in the storage unit 125. On the other hand, at the readout timing, the reset control signal φRST is turned off and the first transfer control signal φTX1 is turned on to transfer charge from the photoelectric conversion unit 104 to the storage unit 125. In this example, the reset control signal φRST has the same switching timing at readout, so it can be shared with the pulse of the selection control signal φSEL.

[0063] In this example, the image sensor 400 can control the exposure time for each pixel group 115 by locally controlling the first transfer control signal φTX1, thereby changing the start or end timing of exposure for each pixel group 115. Furthermore, since the image sensor 400 shares pulses for the reset control signal φRST and the selection control signal φSEL, the control circuit can be further simplified.

[0064] Figure 3 shows a timing chart illustrating the imaging operation of an image sensor in a comparative example. In this example, the drive of the image sensor is controlled by the first transfer control signal φTX1, the reset control signal φRST, and the selection control signal φSEL.

[0065] In the comparative example, the start of exposure is controlled by the first transfer control signal φTX1 and the reset control signal φRST. The exposure start timing is the falling edge timing (time t1) of the first transfer control signal φTX1 and the reset control signal φRST. The exposure end timing is the falling edge timing (time t2) of the first transfer control signal φTX1. In the comparative example, the exposure start and end timings are globally controlled, and the exposure time is not controlled for each pixel group 115.

[0066] Figure 4A shows an example of a subject captured by the image sensor 400. In this example, the image sensor 400 controls the exposure time for each pixel group 115 when the setting sun is shining outside the tunnel.

[0067] Regions 1 through 5 are five regions divided according to brightness. Regions 1 through 5 are numbered in order of brightness. Region 1 is the brightest region where the setting sun is directly visible. Region 2 corresponds to the tunnel exit and is darker than Region 1. Region 3 is the region within the tunnel where the setting sun is reflected and is darker than Region 2. Region 4 is the region within the tunnel that is illuminated by the setting sun from the exit and is darker than Region 3. Region 5 is the darkest region within the tunnel that is not illuminated by the setting sun from the exit.

[0068] The image sensor 400 controls the exposure time for each pixel group 115 according to the brightness of each region. The image sensor 400 controls the exposure time so that the exposure time for pixel groups 115 in brighter regions is shorter. The exposure time for region 1 is set to be the shortest, and the exposure time for region 5 is set to be the longest. For example, the exposure times for regions 1 to 5 are 1 / 19200s, 1 / 1920s, 1 / 960s, 1 / 240s, and 1 / 120s.

[0069] Figure 4B shows a timing chart illustrating the imaging operation of the image sensor 400. In this example, the image sensor 400 controls the exposure time for each pixel group 115 in regions 1 to 5. In this example, the interval from time T11 to time T19 corresponds to the video frame rate.

[0070] In region 1, the control block 220 controls the drive so that the exposure time for the pixel group 115 becomes a predetermined exposure time ET1. In this example, the control block 220 controls the start of exposure with the second transfer control signal φTX2 and the end of exposure with the first transfer control signal φTX1. In region 1, exposure ends at each of the times T12 to T19.

[0071] In region 2, the control block 220 controls the drive so that the exposure time ET2 for the pixel group 115 is longer than ET1. The control block 220 sets the exposure start time in region 2 earlier than in region 1 and the exposure end time to coincide with that of region 1. Therefore, in region 2, exposure ends at times T12 to T19. The exposure time ET2 in region 2 is shorter than the period of the sensor rate.

[0072] In region 3, the control block 220 controls the drive so that the exposure time for the pixel group 115 is longer than ET2, resulting in an exposure time ET3. The control block 220 sets the exposure start time in region 3 earlier than in region 2, and the exposure end time to coincide with that of region 2. Therefore, in region 3, exposure ends at times T12 to T19. The exposure time ET3 in region 3 is set to be the same as the period of the sensor rate.

[0073] In region 4, the control block 220 controls the drive so that the exposure time for the pixel group 115 becomes exposure time ET4, which is longer than ET3. The control block 220 sets the exposure start time for region 4 to be the same as for region 3, but skips the exposure end time using the transfer selection control signal φTXSEL. In this example, the control block 220 achieves four times the exposure time of region 3 by skipping three times using the transfer selection control signal φTXSEL. In region 4, the transfer selection control signal φTXSEL is supplied at each of the times T12 to T14.

[0074] In region 5, the control block 220 controls the drive so that the exposure time for the pixel group 115 becomes an exposure time ET5, which is longer than ET4. The control block 220 sets the exposure start time for region 5 to be the same as for region 4, while increasing the number of times the exposure end time is skipped by the transfer selection control signal φTXSEL. In this example, the control block 220 achieves twice the exposure time of region 4 by skipping 7 times using the transfer selection control signal φTXSEL. The exposure time ET5 in region 5 is set to be the same as the period of the video frame rate. In region 5, the transfer selection control signal φTXSEL is supplied at each time from time T12 to time T18.

[0075] In this example, the image sensor 400 achieves short exposure times by reducing the distance between the first transfer control signal φTX1 and the second transfer control signal φTX2. Furthermore, the image sensor 400 achieves long exposure times by skipping the control of the first transfer control signal φTX1 using the transfer selection control signal φTXSEL. This expands the dynamic range.

[0076] Figure 5 shows an overview of the image sensor 400. The image sensor 400 captures an image of a subject. The image sensor 400 generates image data of the captured subject. The image sensor 400 comprises a first substrate 100 and a second substrate 200. As shown in Figure 5, the first substrate 100 is stacked on the second substrate 200.

[0077] The first substrate 100 has a pixel section 110 and a connection area 150. Light is incident on the pixel section 110. The pixel section 110 outputs a pixel signal based on the incident light. The first substrate 100 is sometimes referred to as a pixel chip. The connection area 150 is arranged around the pixel section 110. In the example in Figure 5, a pair of connection areas 150 are arranged along two opposite sides of the first substrate 100, one in front of and one behind the pixel section 110.

[0078] The second substrate 200 includes a control circuit section 210, a peripheral circuit section 230, and a signal processing section 250. The second substrate 200 is sometimes referred to as a processing circuit chip.

[0079] The control circuit unit 210 outputs control signals to the pixel unit 110 to control the driving of the pixel unit 110. In this example, the control circuit unit 210 is located on the second substrate 200 at a position opposite the pixel unit 110.

[0080] The peripheral circuit section 230 controls the driving of the control circuit section 210. The peripheral circuit section 230 is located around the control circuit section 210 on the second substrate 200. The peripheral circuit section 230 may also be electrically connected to the first substrate 100 and control the driving of the pixel section 110. In this example, the peripheral circuit section 230 is located along two opposite sides of the second substrate 200, but the arrangement of the peripheral circuit section 230 is not limited to this example.

[0081] The signal processing unit 250 receives the pixel signals output from the first substrate 100. The signal processing unit 250 performs signal processing on the pixel signals. For example, the signal processing unit 250 performs processing to convert analog signals to digital signals. Specifically, the signal processing unit 250 performs processing to convert the input pixel signals to digital signals. The signal processing unit 250 may also perform other signal processing. Examples of other signal processing include noise reduction processing such as analog or digital CDS (correlated double sampling). The signal processing unit 250 is located around, i.e., outside of, the control circuit unit 210. In the example in Figure 5, a pair of signal processing units 250 are located in front of and behind the control circuit unit 210, along two opposing sides of the second substrate 200.

[0082] Furthermore, the image sensor 400 may have a third substrate stacked on the second substrate 200, in addition to the first substrate 100 and the second substrate 200. The third substrate may have a memory for storing image data. In addition, the third substrate may perform image processing in response to the signal output by the second substrate 200. Moreover, the structure of the image sensor 400 may be back-illuminated or front-illuminated.

[0083] Figure 6 shows an example of the specific configuration of the pixel section 110. In this example, the pixel section 110 and an enlarged view of the pixel block 120 provided in the pixel section 110 are shown.

[0084] The pixel section 110 has a plurality of pixel blocks 120 arranged in a row and column direction. In this example, the pixel section 110 has M × N pixels (where M and N are natural numbers) in the pixel block 120. In this example, the case where M is equal to N is illustrated, but M and N may be different.

[0085] Pixel block 120 has at least one pixel 112. In this example, pixel block 120 has m × n pixels 112 (where m and n are natural numbers). For example, pixel block 120 has 16 × 16 pixels 112. The number of pixels 112 corresponding to pixel block 120 is not limited to this. In this example, the case where m is equal to n is illustrated, but m may be different from n. Pixel block 120 has multiple pixels 112 connected to a common control line in the row direction. For example, each pixel 112 of pixel block 120 is connected to a common control line so that it is set to the same exposure time. In one example, n pixels 112 arranged in the row direction are connected by a common control line.

[0086] On the other hand, multiple pixel blocks 120 may be set to have different exposure times. That is, each pixel 112 in pixel block 120 may have the same exposure time, but other pixel blocks 120 may have different exposure times. For example, if the pixels 112 in pixel block 120 are connected by a common control line in the row direction, the pixels 112 in other pixel blocks 120 may be connected by different control lines.

[0087] The pixel block 120 is arranged in correspondence with the control block 220, which will be described later. In this embodiment, one pixel block 120 is arranged for one control block 220.

[0088] Pixel 112 has a photoelectric conversion function that converts light into electric charge. Pixel 112 stores the photoelectrically converted charge. m pixels 112 are arranged in a row along the column direction and connected to a common signal line 122. Then, in the pixel block 120, the m pixels 112 are arranged in n columns along the row direction.

[0089] In other words, a pixel block 120 is a collection of multiple pixels 112 connected by a common control line. Furthermore, a pixel block 120 can be described as the smallest unit of a circuit of multiple pixels 112 with the same exposure time set.

[0090] Figure 7 shows a more specific example of the configuration of the control circuit unit 210. In this example, the control circuit unit 210 and an enlarged view of the control block 220 provided in the control circuit unit 210 are shown.

[0091] The control circuit unit 210 has control blocks 220 arranged in a row and column direction. In this example, the control circuit unit 210 has M × N control blocks 220.

[0092] The control blocks 220 are positioned at locations corresponding to the pixel blocks 120. For example, the control blocks 220 and the pixel blocks 120 are positioned so that they overlap when viewed from the stacking direction of the first substrate 100 and the second substrate 200. In this case, the areas of the control blocks 220 and the pixel blocks 120 may be approximately the same, including the margins between adjacent blocks.

[0093] The control block 220 controls the driving of the corresponding pixel block 120. For example, the control block 220 controls the exposure time of the corresponding pixel block 120. In this example, the control block 220 comprises an exposure control unit 10 and a pixel driving unit 20.

[0094] The exposure control unit 10 controls the exposure of multiple pixels 112. The exposure control unit 10 generates signals to control the exposure time of the pixels 112. In one example, the exposure control unit 10 controls the exposure time for each pixel block 120 by adjusting at least one of the start timing or end timing of the exposure.

[0095] The pixel drive unit 20 is electrically connected to a plurality of pixels 112 and drives the plurality of pixels 112. The pixel drive unit 20 selects and drives any pixel 112 from the plurality of pixels 112. The pixel drive unit 20 is positioned in a location corresponding to m pixels 112 arranged in the column direction. The image sensor 400 can expand its dynamic range because the exposure time can be set for each pixel block 120 according to the intensity of the incident light.

[0096] Instead of providing one control block 220 for each pixel block 120, one control block may be provided for N pixel blocks 120 (where N is a natural number greater than or equal to 2). N pixel blocks 120 corresponding to one pixel block are sometimes referred to as a pixel block group. For example, two pixel blocks 120 arranged side-by-side in the column direction may be treated as one pixel block group, and one control block 220 may be provided for each. In this case, the control block 220 may control the exposure time for each pixel block 120.

[0097] Furthermore, the control block 220 is electrically connected to at least one pixel block 120 and can be described as the smallest unit of circuitry that controls the exposure of the pixels 112 of that at least one pixel block 120.

[0098] Figure 8 shows an example of the circuit configuration of pixel 112. Pixel 112 comprises a photoelectric conversion unit 104, a transfer unit 123, an output unit 124, a reset unit 126, and a pixel output unit 127. The pixel output unit 127 includes an amplification unit 128 and a selection unit 129. In this example, the transfer unit 123, output unit 124, reset unit 126, amplification unit 128, and selection unit 129 are described as N-channel FETs, but the type of transistor is not limited to this.

[0099] The photoelectric conversion unit 104 has a photoelectric conversion function that converts light into electric charge. The photoelectric conversion unit 104 stores the photoelectrically converted charge. The photoelectric conversion unit 104 is, for example, a photodiode.

[0100] The transfer unit 123 transfers the charge stored in the photoelectric conversion unit 104 to the storage unit 125. The transfer unit 123 is an example of a transfer gate that transfers charge from the photoelectric conversion unit 104. In other words, the transfer unit 123 acts as the gate, the photoelectric conversion unit 104 as the source, and the storage unit 125 as the drain, and these together constitute a so-called transfer transistor. The gate terminal of the transfer unit 123 is connected to a local transfer control line for each pixel block 120 for inputting the control signal φTX1.

[0101] The discharge unit 124 discharges the charge accumulated in the photoelectric conversion unit 104 to the power supply wiring supplied with the power supply voltage VDD. The gate terminal of the discharge unit 124 is connected to a local discharge control line for each pixel block 120 for inputting the discharge control signal φTX2. In this example, the discharge unit 124 is described as discharging the charge of the photoelectric conversion unit 104 to the power supply wiring supplied with the power supply voltage VDD, but it may also discharge to power supply wiring supplied with a power supply voltage different from the power supply voltage VDD.

[0102] The storage unit 125 receives charge from the photoelectric conversion unit 104 via the transfer unit 123. The storage unit 125 is an example of floating diffusion (FD).

[0103] The reset unit 126 discharges the charge from the storage unit 125 to a power supply wiring to which a predetermined power supply voltage VDD is supplied. The gate terminal of the reset unit 126 is connected to a global reset control line spanning multiple pixel blocks 120 for inputting a reset control signal φRST.

[0104] The pixel output unit 127 outputs a signal based on the potential of the storage unit 125 to the signal line 122. The pixel output unit 127 includes an amplification unit 128 and a selection unit 129. The gate terminal of the amplification unit 128 is connected to the storage unit 125, the drain terminal is connected to the power supply wiring to which the power supply voltage VDD is supplied, and the source terminal is connected to the drain terminal of the selection unit 129.

[0105] The selection unit 129 controls the electrical connection between the pixel 112 and the signal line 122. When the selection unit 129 electrically connects the pixel 112 and the signal line 122, a pixel signal is output from the pixel 112 to the signal line 122. The gate terminal of the selection unit 129 is connected to a global selection control line spanning multiple pixel blocks 120 for inputting the selection control signal φSEL. The source terminal of the selection unit 129 is connected to the load current source 121.

[0106] The load current source 121 supplies current to the signal line 122. The load current source 121 may be provided on the first substrate 100 or on the second substrate 200.

[0107] Hereafter, the charge stored in the photoelectric conversion unit 104, the charge transferred to the storage unit 125, and the signal based on the potential of the storage unit 125, or these collectively, may be referred to as the pixel signal.

[0108] In addition, each pixel 112 includes at least one photoelectric conversion unit 104 and a pixel output unit 127, etc., which acts as a readout unit for reading the image signal from the at least one photoelectric conversion unit 104 to the signal line 122. The pixel 112 can also be said to be the smallest unit of the circuit that outputs the pixel signals constituting the image to the signal line 122.

[0109] Figures 9, 10, and 11 illustrate an example of a wiring method for the image sensor 400. Note that in Figures 10 and 11, connection areas have been omitted for simplification.

[0110] As shown in Figure 9, the first substrate 100 includes connection regions 132 and 150 provided around the pixel portion 610 and electrically connected to the pixel portion 610. The second substrate 200 includes connection regions 232 and 255 provided around the control circuit portion 210 and electrically connected to the control circuit portion 210.

[0111] Each pair of connection regions 132 is connected to a pair of connection regions 232 located opposite each other. The mutually connected connection regions 132 and 232 input control signals from the global drive unit 234 to the pixel unit 610 using global control lines.

[0112] Each pair of connection regions 150 is connected to a pair of connection regions 254 and 255 located opposite each other. The interconnected connection regions 150, 254, and 255 input the pixel signals from the pixel region 110 to the corresponding ADC regions 252 and 253 using a common signal line.

[0113] As shown in Figure 10, the global drive unit 234 outputs a reset control signal φRST, a selection control signal φSEL, and a transfer selection control signal φTXSEL. The global drive unit 234 is connected to a reset control line 143 and a selection control line 145 that output signals to each pixel block 120. The global drive unit 234 supplies the reset control signal φRST to multiple pixel blocks 120 via the reset control line 143 and the selection control signal φSEL via the selection control line 145. The global drive unit 234 supplies the transfer selection control signal φTXSEL to multiple control blocks 220 via the transfer selection control line 147.

[0114] The transfer selection control signal φTXSEL is supplied from the global drive unit 234 to the control block 220 to control the exposure time for each pixel block 120. The control block 220, upon receiving the transfer selection control signal φTXSEL, outputs the transfer selection control signal φTXSEL to the corresponding pixel block 120. The pixel block 120 decides whether or not to input the transfer selection control signal φTXSEL to the pixel 112 as either a transfer control signal φTX1 or an ejection control signal φTX2. As a result, input of either the transfer control signal φTX1 or the ejection control signal φTX2 to the pixel 112 is skipped.

[0115] For example, if the transfer control signal φTX1 determines the end time of exposure, the control block 220 extends the exposure time by skipping the transfer control signal φTX1. Conversely, if the transfer control signal φTX1 determines the start time of exposure, the control block 220 can shorten the exposure time by skipping the transfer control signal φTX1. In this way, the exposure time of the pixel block 120 can be adjusted by the transfer selection control signal φTXSEL. The same applies when the ejection control signal φTX2 determines the start or end time of exposure.

[0116] The reset control line 143, the selection control line 145, and the transfer selection control line 147 are globally wired, that is, they are provided in common to multiple pixel blocks 120. In this example, the reset control line 143, the selection control line 145, and the transfer selection control line 147 are wired to traverse the pixel section 110 in the row direction. The reset control line 143, the selection control line 145, and the transfer selection control line 147 may also be wired to traverse the pixel section 110 in the column direction.

[0117] For example, the reset control line 143 is connected to the gate terminal of the reset unit 126 of the pixel block 120 and supplies the reset control signal φRST. The selection control line 145 is connected to the gate terminal of the selection unit 129 of the pixel block 120 and supplies the selection control signal φSEL. In addition, the transfer selection control line 147 is connected to each of the multiple control blocks 220 and supplies the transfer selection control signal φTXSEL to the exposure control unit 10.

[0118] In this example, the global drive unit 234 outputs a transfer selection control signal φTXSEL from the second board 200 to the first board 100. However, it may also output the transfer selection control signal φTXSEL to the control block 220 without supplying it to the first board 100. In this case, the transfer selection control line 147 is provided on the second board 200.

[0119] Meanwhile, the transfer control line 141a and the ejection control line 142a are connected to the pixel block 120a. In this example, the transfer control line 141a is connected to the gate terminal of the ejection unit 123 provided on the pixel block 120a. The transfer control line 141a supplies the transfer control signal φTX1 ejection output from the control block 220a to the pixel block 120a. In this example, the ejection control line 142a is connected to the gate terminal of the ejection unit 124 provided on the pixel block 120a. The ejection control line 142a supplies the ejection control signal φTX2 output from the control block 220a to the pixel block 120a.

[0120] The transfer control line 141b and the ejection control line 142b are connected to the pixel block 120b. In this example, the transfer control line 141b is connected to the gate terminal of the ejection unit 123 provided on the pixel block 120b. The transfer control line 141b supplies the transfer control signal φTX1 ejection output from the control block 220b to the pixel block 120b. In this example, the ejection control line 142b is connected to the gate terminal of the ejection unit 124 provided on the pixel block 120b. The ejection control line 142b supplies the ejection control signal φTX2 output from the control block 220b to the pixel block 120b.

[0121] Multiple bumps 152 are provided on the bonding surface where the first substrate 100 and the second substrate 200 are joined to each other. The bumps 152 on the first substrate 100 are aligned with the bumps 152 on the second substrate 200. Multiple opposing bumps 152 are joined and electrically connected by pressurization or the like on the first substrate 100 and the second substrate 200. In this case, the global control line bumps 152 may be located below the corresponding pixel block 120 or in the connection regions 132 and 232. On the other hand, the local control line bumps 152 are provided below the corresponding pixel block 120 (and also on the control block 220).

[0122] In this example, the image sensor 400 controls the exposure time for each pixel block 120 by changing the timing of at least one of the transfer unit 123 and the output unit 124 using local control lines. By combining local and global control lines, the image sensor 400 can achieve exposure time control with fewer control lines.

[0123] As shown in Figure 11, within each pixel block 120c, a common signal line 122 is provided that extends in the direction of that column. Furthermore, this signal line 122 is common to multiple pixel blocks 120c and 120d arranged in the column direction. Therefore, in this example, one signal line 122 is connected to m × M pixels 112 arranged in a single column, and pixel signals from these pixels 112 are output.

[0124] Each of the signal lines 122 is connected to an ADC (analog-to-digital converter) 256 on the second board 200 side via a bump 152. Multiple ADCs 256 corresponding to multiple signal lines 122 constitute the ADC unit 252.

[0125] In the example shown in Figure 11, ADCs 256 corresponding to the odd-numbered pixel blocks 120c and 120d are provided in the ADC unit 252, and ADCs 256 corresponding to the even-numbered pixel blocks 120e and 120f are provided in the ADC unit 253. However, the arrangement of pixel blocks 120c, etc., and their corresponding ADC units 252, etc., is not limited to this.

[0126] With the above configuration, each ADC 256 converts the pixel signals output sequentially from a connected row of m × M pixels 112 into digital signals and outputs them. In this case, the ADC units 252 and 253 as a whole convert the pixel signals from the n × N rows of pixels 112 into digital signals in parallel. From this viewpoint, this digital conversion can be said to be a type of so-called column ADC. A single-slope ADC is given as an example of an ADC, but other digital conversion methods may be used. Also, the connection position between each pixel 112 and the signal line 122 is not limited to the configuration shown in Figure 11, and may be within each pixel block 120c, etc.

[0127] Figure 12 shows an example of a timing chart illustrating the imaging operation within the pixel block 120 of the image sensor 400. In this example, the drive of the pixel block 120 is controlled by the transfer control signal φTX1, the ejection control signal φTX2, the reset control signal φRST, and the selection control signal φSEL.

[0128] The emission control signal φTX2 controls the timing of the exposure start. The exposure start timing corresponds to the falling edge timing of the emission control signal φTX2 (for example, time T1). That is, before the exposure start time T1, the emission control signal φTX2 turns on the emission unit 124 to discharge the charge accumulated in the photoelectric conversion unit 104, and exposure starts on the falling edge of the emission control signal φTX2. In this example, since the emission control signal φTX2 is controlled locally, the exposure time can be adjusted for each pixel block 120.

[0129] The transfer control signal φTX1 controls the timing of the end of exposure. At time T3, the transfer control signal φTX1 turns on the transfer unit 123, thereby transferring the charge accumulated in the photoelectric conversion unit 104 to the storage unit 125. The timing of the end of exposure corresponds to the falling edge timing of the transfer control signal φTX1 (for example, time T4).

[0130] The reset control signal φRST controls the timing of discharge of the charge stored in the storage unit 125. At time T2, the reset control signal φRST turns on the reset unit 126, thereby discharging the charge from the storage unit 125. In this example, by discharging the charge from the storage unit 125 before the end of exposure, the influence of the charge remaining in the storage unit 125 during the transfer of charge from the photoelectric conversion unit 104 can be suppressed.

[0131] The selection control signal φSEL is a signal for selecting any pixel 112. The selection control signal φSEL controls the on / off state of the selection unit 129. At time T2, the selection control signal φSEL is set to high. At time T3, the pixel 112 for which the selection control signal φSEL is set to high outputs a pixel signal to the signal line 122 in response to the ON state of the transfer control signal φTX1. On the other hand, the pixel 112 for which the selection control signal φSEL is not set to high does not output a pixel signal.

[0132] In this example, the image sensor 400 can control the exposure time for each pixel block 120 by locally controlling the ejection control signal φTX2, thereby changing the exposure start timing for each pixel block 120. Alternatively, the image sensor 400 may control the exposure end timing for each pixel block 120 by locally controlling the transfer control signal φTX1. Furthermore, the image sensor 400 may control both the exposure start and end timings for each pixel block 120 by locally controlling both the transfer control signal φTX1 and the ejection control signal φTX2.

[0133] The pixel signal of each pixel 112 corresponds to the amount of charge stored in the photoelectric conversion unit 104. Therefore, controlling the exposure timing of the pixel 112 can be said to be controlling the timing of charge storage in the photoelectric conversion unit 104. More specifically, controlling the exposure timing of the pixel 112 can be said to be controlling the timing and length of the charge storage time from charge discharge to transfer.

[0134] Figure 13 shows an example of exposure timing for each pixel block 120. In this example, the exposure time is controlled for each of the three pixel blocks 120 arranged in a row. Here, the image sensor 400 changes the exposure amount by shifting the pixel reset time for each pixel block 120.

[0135] On the other hand, the timing of reading out the pixel signals is sequential, starting from the top pixel block 120. That is, the pixel signal is read from pixel 112 of "pixel block 1," then from pixel 112 of "pixel block 2," and then from pixel 112 of "pixel block 3."

[0136] Furthermore, within the pixel block 120, as explained in Figure 12, pixel signals are read sequentially from the top row of pixels 112. Therefore, when considering the entire pixel section 110, pixel signals are read sequentially from the top row of m × M pixels 112 in the same row connected to the common signal line 122. In other words, the global drive unit 234 sets the selection control signal φSEL to high for each row, spanning multiple pixel blocks 120 arranged in a single column from the first row to the m × M rows.

[0137] In this case, as explained in Figure 11, for multiple pixel blocks 120 arranged in a single row, a common selection control line 145 is connected to n × N pixels in the same row. Therefore, pixel signals are read in parallel from n × N pixels 112 connected to the row in which the selection control signal φSEL is set to high. This makes it possible to output pixel signals for one frame.

[0138] These pixel signals are digitally converted by the ADC units 252, 252, as explained in Figure 11. The digitally converted pixel signals are output to the subsequent image processing stage to form an image for one frame.

[0139] As described above, the pixel signal readout is performed sequentially from the top row of the same column among multiple pixel blocks 120. From this perspective, the readout method of this embodiment can be said to be a so-called rolling shutter method for the entire pixel unit 110. However, it should be added that even in this case, different exposure times can be set for each pixel block 120.

[0140] As described above, according to this embodiment, when reading out the pixel signals from multiple pixel blocks 120 arranged in a row, the pixel signals are read out from the pixels 112 of the upper pixel block 120 first, and then from the pixels 112 of the pixel block 120 below it. Therefore, when capturing a moving subject, the distortion of the image due to the reading order is smoothed out, and the sense of discomfort the viewer may feel with the image can be reduced. More specifically, when reading out a moving subject in parallel from multiple pixel blocks 120 arranged in a row, multiple sawtooth-like steps corresponding to the vertical direction of the image (i.e., the direction of the pixel column) appear between the pixel blocks 120, causing discomfort to the viewer. In contrast, according to this embodiment, these multiple steps do not appear in the image.

[0141] Furthermore, in this embodiment, the ADC unit is not provided within the control block 220, and the signal processing unit 250 is placed outside the control circuit unit 210. Therefore, the area of ​​the control block 220 can be reduced, and the size of the pixel block 120 located at the position corresponding to the control block 220 can be reduced, that is, exposure control by the control block 220 can be performed in units of fewer pixels. As a result, the exposure time can be precisely controlled within the image, and the boundaries of the pixel block 120 can be made less noticeable on the image. Moreover, since digital conversion is not performed directly beneath the pixel 112, the impact of noise on the pixel 112 due to heat generation can be suppressed.

[0142] Furthermore, the signal processing unit 250 does not need to be provided in multiple separate regions; it may be provided in a single region for the entire pixel section 110.

[0143] Figure 14 shows an overview of the image sensor 800 according to another embodiment. In the image sensor 800, components that are the same as those of the image sensor 400 are given the same reference numerals and their descriptions are omitted.

[0144] The image sensor 800 comprises a first substrate 600 and a second substrate 700. As shown in Figure 14, the first substrate 600 is stacked on the second substrate 700.

[0145] Similar to the image sensor 400, the first substrate 600 has a pixel section 610, and the second substrate 700 has a control circuit section 210 and a peripheral circuit section 230. On the other hand, the connection area 150 of the first substrate 100 is not provided around the pixel section 610 of the first substrate 600. Also, the signal processing unit 250 of the second substrate 200 is not provided around the control circuit section 710 of the second substrate 700.

[0146] The control circuit unit 710 receives the pixel signal output from the first substrate 100. The control circuit unit 710 processes the input pixel signal. In this example, the control circuit unit 710 is located on the second substrate 200, opposite the pixel unit 610. The control circuit unit 710 further outputs a control signal to the pixel unit 610 to control the driving of the pixel unit 610.

[0147] Figure 15 shows an example of a specific configuration of the pixel section 610. The pixel section 610 has M × N pixel blocks 620, and each pixel block 620 has m × n pixels 112. The configuration of the pixels 112 is the same as that of the pixel section 110.

[0148] Similar to pixel block 120, pixels 112 arranged in a single row within pixel block 620 are connected to a common signal line 122. On the other hand, the signal line 122 is not common among multiple pixel blocks 620 and is independent of each other.

[0149] Figure 16 shows a more specific example of the configuration of the control circuit unit 710. Similar to the control circuit unit 210, the control circuit unit 710 has M × N control blocks 720, each of which is positioned to correspond to a pixel block 620.

[0150] The control block 720 has an exposure control unit 10 and a pixel driving unit 20 similar to those of the control block 220. The control block 720 further includes a junction unit 730, a signal processing unit 740, and a signal output unit 750.

[0151] The joint 730 joins the first substrate 600 and the second substrate 700. The joint 730 inputs the pixel signals received from the first substrate 600 to the signal processing unit 740. The joint 730 is provided in correspondence with n pixels 112 arranged in the row direction, and inputs the pixel signals to the signal processing unit 740 column by column.

[0152] The signal processing unit 740 converts the analog signal output by the pixel unit 610 into a digital signal. In this example, the signal processing unit 740 converts the analog pixel signal into a digital signal. The signal processing unit 740 sequentially converts the analog signals from m pixels 112 arranged in the column direction into digital signals. The signal processing unit 740 has a number of ADCs corresponding to the number of columns in the corresponding pixel block 120, and uses them to convert the analog signals from n pixels 112 arranged in the row direction into digital signals in parallel.

[0153] The signal output unit 750 receives a digital signal from the signal processing unit 740. In one example, the signal output unit 750 temporarily stores the digital signal. The signal output unit 750 may have a latch circuit for storing the digital signal. The signal output unit 750 is located in the column direction between the signal processing unit 740 and the exposure control unit 10 and outputs a digital signal. In this example, the signal output unit 750 outputs a digital signal to the outside of the control circuit unit 710.

[0154] In this example, the control block 720 has a signal processing unit 740 and a signal output unit 750 inside. That is, the circuit for digitally converting the pixel signal is located inside the control circuit unit 710 and not on the outside.

[0155] The image sensor 800 in this example allows for setting the exposure time for each pixel block 620 according to the intensity of the incident light, thus expanding the dynamic range, similar to the image sensor 400. Furthermore, the image sensor 800 can read out pixel signals in parallel for each pixel block 620 using a control block 720 provided for each pixel block 620. However, in this embodiment, the readout timing is controlled as described later.

[0156] Figure 17 shows an example of exposure timing for each pixel block 620. In this example, the exposure time is controlled for each of the three pixel blocks 620 arranged in a row. Here, the image sensor 800, like the image sensor 400, changes the exposure amount by shifting the pixel reset time for each pixel block 620.

[0157] On the other hand, the timing of reading out the pixel signals is sequential, starting from the top pixel block 620. That is, the pixel signal is read from pixel 112 of "pixel block 1," then from pixel 112 of "pixel block 2," and then from pixel 112 of "pixel block 3."

[0158] Furthermore, within the pixel block 620, similar to the image sensor 400, pixel signals are read out sequentially from the top row of pixels 112. Therefore, when considering the entire pixel section 110, pixel signals are read out sequentially from the top row of m × M pixels 112 in the same row connected to the common signal line 122.

[0159] In the image sensor 800, a signal line 122 and a signal processing unit 740 are provided for each of the multiple pixel blocks 620. More specifically, a signal line 122 and an ADC of the signal processing unit 740 are provided for each column of the multiple pixel blocks 620. Therefore, pixel signals can be read simultaneously even between multiple pixel blocks 620 arranged in the column direction. However, in this embodiment, the global drive unit 234 sets the selection control signal φSEL to high for each row, spanning multiple pixel blocks 120 arranged in a single column from the first row to the m × M rows.

[0160] As a result, as shown in Figure 17, among the multiple pixel blocks 120 arranged in a row similar to Figure 13, the pixel signal is read from the pixel 112 of the upper pixel block 120, and then the pixel signal is read from the pixel 112 of the pixel block 120 below it.

[0161] As described above, the readout method of this embodiment can be said to be a so-called rolling shutter method for the entire pixel section 610, as it is such that, similar to the image sensor 400, the pixel signals are read out sequentially from the top row of the same column among the multiple pixel blocks 620. However, even in this case, it is possible to set different exposure times for each pixel block 620, just as with the image sensor 400. As a result, the image distortion caused by the readout order when capturing a moving subject is smoothed out in the image sensor 800, just as in the image sensor 400, and the sense of unnaturalness in the image perceived by the viewer is reduced.

[0162] Figure 18 shows another example of pixels 114 of image sensors 400 and 800. In pixels 114, the same configuration as pixels 112 is given the same reference number and its explanation is omitted. In pixels 114, the ejection unit 124 that was provided in pixels 112 is not provided. Pixel 114 is sometimes called a 4-transistor type.

[0163] Figure 19 shows an example of a timing chart illustrating the imaging operation within a pixel block 120 using pixel 114. In this example, the drive of the image sensor 400 is controlled by a transfer control signal φTX1, a reset control signal φRST, and a selection control signal φSEL. The image sensor 400 in this example differs from that in Figure 12 in that the timing of the start of exposure is controlled by the transfer control signal φTX1. The differences between this example and Figure 12 will be explained in particular.

[0164] The transfer control signal φTX1 controls the start and end timing of exposure. In frame (n), exposure starts at time T5 and ends at time T7.

[0165] At the exposure start time T5, exposure begins when the transfer control signal φTX1 falls. That is, before the exposure start time T5, the transfer control signal φTX1 turns on the transfer unit 123 with the reset control signal φRST turned on, thereby discharging the charge accumulated in the photoelectric conversion unit 104, and exposure begins when the transfer control signal φTX1 falls. Since the transfer control signal φTX1 in this example is a locally controlled signal, the timing of exposure initiation can also be changed for each pixel block 120.

[0166] Furthermore, at the exposure end time T7, the exposure ends when the transfer control signal φTX1 falls. That is, before the exposure end time T7, the transfer control signal φTX1 turns on the transfer unit 123 with the reset control signal φRST turned off, transferring the charge accumulated in the photoelectric conversion unit 104 to the storage unit 125, and the exposure ends when the transfer control signal φTX1 falls. In this example, the transfer control signal φTX1 is a locally controlled signal, so the timing of the exposure termination can also be changed in each pixel block 120.

[0167] The selection control signal φSEL is a signal for selecting any pixel 114. At time T6, a pixel 114 for which the selection control signal φSEL is set to high outputs a pixel signal to the signal line 122.

[0168] The reset control signal φRST controls the timing of discharge of charge stored in the storage unit 125. The reset control signal φRST may be a globally controlled signal. Since the reset control signal φRST is always on except at the readout timing, no charge is stored in the storage unit 125. On the other hand, at the readout timing, the reset control signal φRST is turned off and the transfer control signal φTX1 is turned on, thereby transferring charge from the photoelectric conversion unit 104 to the storage unit 125. In this example, the reset control signal φRST has the same switching timing at readout, so it can be shared with the pulse of the selection control signal φSEL.

[0169] Figure 20 shows an example of exposure timing for each pixel block 120 using pixel 114. As explained in Figure 19, a reset operation is performed in pixel 114 during the operation period of reading the pixel signal. Therefore, in Figure 20 and its description, the timing of the readout is explained, and the explanation of the reset timing is omitted.

[0170] In Figure 20, the timing of pixel signal readout is the same as in Figure 13, starting from the top pixel block 120. That is, the pixel signal is read from pixel 114 of "pixel block 1", then from pixel 114 of "pixel block 2", and then from pixel 114 of "pixel block 3".

[0171] Furthermore, within the pixel block 120, the pixel signals are read out sequentially starting from the top row of pixels 114. Therefore, when considering the entire pixel section 110, the pixel signals are read out sequentially from the top row of the m × M pixels 114 in the same row connected to the common signal line 122.

[0172] As described above, since the pixel signals are read out sequentially from the top row of the same column among the multiple pixel blocks 120, just as in the case where pixel 112 is used, the readout method of this embodiment can also be said to be a so-called rolling shutter method for the entire pixel unit 110.

[0173] In Figure 20, a specific pixel block 120 is not read out in a particular frame (this can also be described as skipping, omitting, or downsampling). This allows the exposure time to be varied for each pixel block 120.

[0174] For example, in the example in Figure 20, in "frame k", "pixel block 1" and "pixel block 3" are read out, but "pixel block 2" is not. In the next "frame k+1", "pixel block 1", "pixel block 2", and "pixel block 3" are all read out. Therefore, in "frame k+1", the exposure time of "pixel block 2" is longer than the exposure time of "pixel block 1" and "pixel block 3". Here, if the temporal frame rate of the readout is constant, the exposure time for a particular pixel block 120 can be increased by (n+1) times by skipping the readout n times.

[0175] Furthermore, the configuration in which a specific pixel block 120 is not read out in a particular frame can also be applied to image sensors 400 and 800 using pixels 112. In this case, if the exposure start timing by the eject control signal φTX2 is set immediately after the readout timing, the same operation as in Figure 20 is possible. On the other hand, by controlling the exposure start timing by the eject control signal φTX2 independently of the readout timing, a readout operation combining the readout in Figure 13 and the readout in Figure 20 can be performed. That is, while controlling the exposure start timing for each pixel block 120 as in Figure 13, it is possible to select whether or not to read out for a specific frame for each pixel block 120 as in Figure 20. This makes it possible to set the exposure time more dynamically and precisely for each pixel block 120, and reduces the sense of unnaturalness in the image perceived by the viewer when imaging a moving subject.

[0176] In any of the above embodiments, the storage unit 125 and the pixel output unit 127 may be shared with other pixels. Also, the pixel 112 may be composed of multiple photoelectric conversion units 104 and transfer units 123.

[0177] Figure 21 is a block diagram showing an example configuration of an imaging device 500 according to an embodiment. The imaging device 500 includes an image sensor 400, a system control unit 501, a drive unit 502, a photometer 503, a work memory 504, a recording unit 505, a display unit 506, a drive unit 514, and a photographic lens 520. The example will be described using an image sensor 400, but an image sensor 800 may be used instead.

[0178] The imaging lens 520 guides the subject light beam incident along the optical axis OA to the image sensor 400. The imaging lens 520 is composed of multiple optical lens groups and forms an image of the subject light beam from the scene near its focal plane. The imaging lens 520 may be an interchangeable lens that can be attached to and detached from the imaging device 500. In Figure 21, the imaging lens 520 is represented by a single hypothetical lens positioned near the pupil.

[0179] The drive unit 514 drives the photographic lens 520. In one example, the drive unit 514 moves the optical lens group of the photographic lens 520 to change the focus position. The drive unit 514 may also drive the iris diaphragm within the photographic lens 520 to control the amount of light beam incident on the image sensor 400.

[0180] The drive unit 502 has a control circuit that performs charge accumulation control such as timing control and area control of the image sensor 400 according to instructions from the system control unit 501. The operation unit 508 receives instructions from the imager via a release button or the like.

[0181] The image sensor 400 passes pixel signals to the image processing unit 511 of the system control unit 501. The image processing unit 511 uses the work memory 504 as a workspace to generate image data after performing various image processing steps. For example, when generating image data in JPEG file format, it generates a color video signal from the signal obtained by the Bayer array and then performs compression processing. The generated image data is recorded in the recording unit 505 and converted into a display signal, which is then displayed in the display unit 506 for a preset time.

[0182] Prior to the series of shooting sequences that generate image data, the photometering unit 503 detects the brightness distribution of the scene. The photometering unit 503 includes, for example, an AE sensor with about 1 million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometering unit 503 and calculates the brightness of each region of the scene.

[0183] The calculation unit 512 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated brightness distribution. The photometering unit 503 may also be integrated into the image sensor 400. The calculation unit 512 also performs various calculations for operating the imaging device 500. The drive unit 502 may be partially or entirely mounted on the image sensor 400. Part of the system control unit 501 may also be mounted on the image sensor 400.

[0184] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0185] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specification, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specification, and drawings is described using phrases such as "first," "next," etc. for convenience, this does not mean that it is essential to implement it in that order. The inventions described herein can also be implemented in the forms described in the following sections. [Item 1] Multiple pixels, A first control line connected to the first pixel among the plurality of pixels, and which outputs a control signal for controlling the first pixel, A second control line connected to the second pixel among the plurality of pixels, and to which a control signal for controlling the second pixel is output, A third control line connected to the first and second pixels, which outputs control signals for controlling the first and second pixels, An image sensor equipped with the following features. [Item 2] Each of the aforementioned plurality of pixels is A photoelectric conversion unit that converts light into electric charge, A transfer unit for transferring the charge of the photoelectric conversion unit, A storage unit that stores the charge transferred by the transfer unit, A reset unit that discharges the charge from the storage unit, A pixel output unit that converts the charge of the storage unit into a pixel signal and outputs it. Having, The image sensor described in item 1. [Item 3] The first control line is connected to the transfer unit of the first pixel, The second control line is connected to the transfer unit of the second pixel, The third control line is connected to the reset section of the first and second pixels. The image sensor described in item 2. [Item 4] The pixel output unit includes a selection unit that selects whether or not to output the pixel signal, The third control line is connected to the selection section of the first pixel and the second pixel. The image sensor described in item 2 or 3. [Item 5] The system comprises multiple pixel blocks, each containing one or more pixels from the aforementioned plurality of pixels, The first control line is connected to the first pixel block among the plurality of pixel blocks, The second control line is connected to the second pixel block among the plurality of pixel blocks. An image sensor as described in any one of items 2 through 4. [Item 6] A pixel chip having the plurality of pixels, A signal processing chip stacked with the aforementioned pixel chip and processing pixel signals from the plurality of pixels Equipped with, The signal processing chip is provided in correspondence with each of the plurality of pixel blocks and has a plurality of control blocks that control exposure for each of the one or more pixels. The image sensor described in item 5. [Item 7] The aforementioned signal processing chip is The main circuit section having the aforementioned plurality of control blocks, In the signal processing chip, a peripheral circuit section is provided around the main circuit section. Equipped with, The peripheral circuit section has a global drive unit connected to the third control line. The image sensor described in item 6. [Item 8] The global drive unit supplies selection control signals to the plurality of control blocks via the third control line for selecting the transfer unit. The image sensor described in item 7. [Item 9] The transfer unit is, A first transfer unit that transfers the charge from the photoelectric conversion unit to the storage unit, A second transfer unit that transfers and discharges the charge from the photoelectric conversion unit. Includes, The plurality of control blocks control the exposure time for each of the one or more pixels by changing the timing of at least one of the first transfer unit and the second transfer unit. An image sensor as described in any one of items 6 through 8. [Item 10] An imaging device comprising an image sensor as described in any one of items 1 to 9. [Item 11] A first control block that controls the exposure of the first pixel included in the first pixel block, A second control block that controls the exposure of the second pixel included in the second pixel block, A conversion unit that converts the first signal output from the first pixel and the second signal output from the second pixel into digital signals. Equipped with, The first pixel block and the second pixel block are arranged in a column direction, The conversion unit is an image sensor that reads out the second signal after reading out the first signal. [Item 12] The first pixel block has a plurality of the first pixels arranged in the row and column directions, The image sensor according to item 11, wherein each of the multiple conversion units is connected to the first pixels arranged in the column direction in the first pixel block. [Item 13] The second pixel block has a plurality of the second pixels arranged in the row and column directions, Each of the other plurality of conversion units is connected to the second pixels arranged in the column direction in the second pixel block, as described in item 12. [Item 14] The second pixel block has a plurality of the second pixels arranged in the row and column directions, The image sensor described in item 12, wherein each of the plurality of conversion units is connected to the first pixels arranged in the column direction in the first pixel block and the second pixels arranged in the column direction in the second pixel block. [Item 15] A first substrate on which the first pixel block and the second pixel block are provided, The first control block, the second control block, and the second substrate on which the conversion unit is provided They are stacked, The first control block is located in the region corresponding to the first pixel block, and the second control block is located in the region corresponding to the second pixel block. The conversion unit is an image sensor according to any one of items 11 to 14, which is located in a region outside the region corresponding to the region corresponding to the first pixel block and the second pixel block. [Item 16] An imaging device having an image sensor as described in any one of items 11 to 15. [Explanation of Symbols]

[0186] 10... Exposure control unit, 20... Pixel drive unit, 30... Bonding unit, 40... Signal processing unit, 50... Signal output unit, 100, 600... First substrate, 104... Photoelectric conversion unit, 110, 610... Pixel unit, 112, 114... Pixel, 115... Pixel group, 120, 620... Pixel block, 121... Load current source, 122... Signal line, 123... Transfer unit, 124 ...Discharge section, 125...Storage section, 126...Reset section, 127...Pixel output section, 128...Amplification section, 129...Selection section, 132...Connection area, 141...Transfer control line, 142...Discharge control line, 143...Reset control line, 145...Selection control line, 147...Transfer selection control line, 150...Connection area, 152...Bump, 161...Local control line 162...Local control line, 163...Global control line, 200, 700...Second board, 210, 710...Control circuit section, 220, 720...Control block, 230...Peripheral circuit section, 232...Connection area, 234...Global drive section, 250, 740...Signal processing section, 252, 253...ADC section, 254, 255...Connection area, 256...AD C, 400, 800... Image sensor, 500... Imaging device, 501... System control unit, 502... Drive unit, 503... Photometer unit, 504... Work memory, 505... Recording unit, 506... Display unit, 508... Operation unit, 511... Image processing unit, 512... Calculation unit, 514... Drive unit, 520... Shooting lens, 730... Bonding unit, 750... Signal output unit

Claims

1. A first pixel block including a first photoelectric conversion unit that converts light into electric charge, a first transfer unit that transfers the electric charge converted by the first photoelectric conversion unit, a first storage unit to which the electric charge converted by the first photoelectric conversion unit is transferred by the first transfer unit, a first amplification unit electrically connected to the first storage unit, and a first selection unit electrically connected to the first amplification unit, A second pixel block comprising: a photoelectric conversion unit that converts light into electric charge and is arranged alongside the first photoelectric conversion unit in the row direction; a second transfer unit that transfers the charge converted by the second photoelectric conversion unit; a second storage unit to which the charge converted by the second photoelectric conversion unit is transferred by the second transfer unit; a second amplification unit electrically connected to the second storage unit; and a second selection unit electrically connected to the second amplification unit. A first substrate having, A substrate that is laminated together with the first substrate, A control circuit unit including a first control block that outputs a first transfer control signal for controlling the first transfer unit, and a second control block that outputs a second transfer control signal for controlling the second transfer unit, A drive unit that outputs a selection control signal for controlling the first selection unit and the second selection unit. A second substrate having Equipped with, The first transfer unit is electrically connected to the first transfer control line from which the first transfer control signal is output. The second transfer unit is electrically connected to the second transfer control line from which the second transfer control signal is output. The first selection unit and the second selection unit are electrically connected to the selection control line on which the selection control signal is output. Image sensor.

2. In the image sensor according to claim 1, The drive unit is located outside the control circuit unit. Image sensor.

3. In the image sensor according to claim 1 or claim 2, The aforementioned drive unit is The timing at which the first transfer control signal is output from the first control block to the first transfer control line, The timing at which the second transfer control signal is output from the second control block to the second transfer control line Outputs a transfer selection control signal to control the transfer, The first control block and the second control block are electrically connected to the transfer selection control line on which the transfer selection control signal is output. Image sensor.

4. In the image sensor according to claim 3, The aforementioned drive unit is The timing at which the first transfer control signal is output from the first control block to the first transfer control line, The timing at which the second transfer control signal is output from the second control block to the second transfer control line The transfer selection control signal is output so that the timings are different. Image sensor.

5. In the image sensor according to claim 3 or claim 4, The first substrate and the second substrate are provided with a plurality of connection points for electrically connecting them, The aforementioned multiple connection parts are A first connection unit electrically connects the transfer selection control line and the drive unit, A second connection section electrically connects the transfer selection control line and the first control block, A third connection part that electrically connects the transfer selection control line and the second control block. Having, Image sensor.

6. In the image sensor according to claim 5, The plurality of connection parts each have a fourth connection part that electrically connects the selection control line and the drive unit. Image sensor.

7. In the image sensor according to any one of claims 1 to 6, The first pixel block has a first discharge unit for discharging the charge from the first photoelectric conversion unit, The second pixel block has a second discharge unit for discharging the charge from the second photoelectric conversion unit, The first control block outputs a first discharge control signal for controlling the first discharge unit. The second control block outputs a second discharge control signal for controlling the second discharge unit. The first discharge unit is electrically connected to the first discharge control line from which the first discharge control signal is output. The second discharge unit is electrically connected to the second discharge control line from which the second discharge control signal is output. Image sensor.

8. In the image sensor according to any one of claims 1 to 7, The first control block is positioned opposite the first pixel block, The second control block is positioned opposite the second pixel block, Image sensor.

9. In the image sensor according to any one of claims 1 to 8, The aforementioned second substrate is A first conversion unit that converts a first signal generated by the charge transferred from the first photoelectric conversion unit to the first storage unit into a digital signal, A second conversion unit converts a second signal generated by the charge transferred from the second photoelectric conversion unit to the second storage unit into a digital signal. Having, Image sensor.

10. In the image sensor according to claim 9, The first conversion unit and the second conversion unit are arranged outside the control circuit unit. Image sensor.

11. In the image sensor according to claim 10, The first conversion unit and the second conversion unit are arranged in positions different from the drive unit. Image sensor.

12. In the image sensor according to claim 10 or claim 11, The control circuit unit is arranged between the first conversion unit and the second conversion unit in the column direction. Image sensor.

13. In the image sensor according to any one of claims 1 to 8, The first control block includes a first conversion unit that converts a first signal generated by the charge transferred from the first photoelectric conversion unit to the first storage unit into a digital signal. The second control block includes a second conversion unit that converts a second signal generated by the charge transferred from the second photoelectric conversion unit to the second storage unit into a digital signal. Image sensor.

14. In the image sensor according to any one of claims 1 to 7, The first substrate has a third pixel block which includes a photoelectric conversion unit that converts light into electric charge and is arranged in the column direction alongside the first photoelectric conversion unit, a third transfer unit that transfers the charge converted by the third photoelectric conversion unit, and a third storage unit to which the charge converted by the third photoelectric conversion unit is transferred by the third transfer unit. The second substrate has a third control block that outputs a third transfer control signal for controlling the third transfer unit. Image sensor.

15. In the image sensor according to claim 14, The first control block is positioned opposite the first pixel block, The second control block is positioned opposite the second pixel block, The third control block is positioned opposite the third pixel block, Image sensor.

16. In the image sensor according to claim 14 or claim 15, The aforementioned second substrate is A first conversion unit that converts a first signal generated by the charge transferred from the first photoelectric conversion unit to the first storage unit into a digital signal, A second conversion unit converts a second signal generated by the charge transferred from the second photoelectric conversion unit to the second storage unit into a digital signal. It has, The first conversion unit converts the third signal generated by the charge transferred from the third photoelectric conversion unit to the third storage unit into a digital signal. Image sensor.

17. In the image sensor according to claim 16, The first conversion unit and the second conversion unit are arranged outside the control circuit unit. Image sensor.

18. In the image sensor according to claim 17, The first conversion unit and the second conversion unit are arranged in positions different from the drive unit. Image sensor.

19. In the image sensor according to claim 17 or claim 18, The control circuit unit is arranged between the first conversion unit and the second conversion unit in the column direction. Image sensor.

20. In the image sensor according to any one of claims 16 to 19, The first signal and the third signal are read out onto the first signal line electrically connected to the first conversion unit. The second signal is read out onto the second signal line electrically connected to the second conversion unit. Image sensor.

21. In the image sensor according to claim 14 or claim 15, The first control block includes a first conversion unit that converts a first signal generated by the charge transferred from the first photoelectric conversion unit to the first storage unit into a digital signal. The second control block includes a second conversion unit that converts a second signal generated by the charge transferred from the second photoelectric conversion unit to the second storage unit into a digital signal. The third control block includes a third conversion unit that converts a third signal generated by the charge transferred from the third photoelectric conversion unit to the third storage unit into a digital signal. Image sensor.

22. In the image sensor according to claim 21, The first conversion unit is electrically connected to the first signal line on which the first signal is output. The second conversion unit is electrically connected to the second signal line on which the second signal is output. The third conversion unit is electrically connected to the third signal line on which the third signal is output. Image sensor.

23. An imaging device comprising an image sensor according to any one of claims 1 to 22.

Images