Magnetic tunnel junction device with minimal stray magnetic field

Abstract

The semiconductor device includes a second BEOL layer including a via dielectric layer surrounding a via including an upper metal stud and a lower metal stud separated by a liner, and a magnetic tunnel junction (MTJ) stack aligned above the via. The semiconductor device includes a first back-end-of-line (BEOL) layer including a BEOL dielectric layer surrounding a via including an upper metal stud and a lower metal stud separated by a liner, and a magnetic tunnel junction (MTJ) stack aligned above the via. The method includes forming the via dielectric layer as the second back-end-of-line (BEOL) layer, an opening, the lower metal stud in the opening, a liner on the lower metal stud and on the exposed side of the opening, and the upper metal stud in the remaining portion of the opening, and forming the magnetic tunnel junction (MTJ) stack aligned above.

Description

[Technical Field]

[0001] This invention generally relates to the field of semiconductor manufacturing, and more specifically to the fabrication of magnetic tunnel junction devices in which the stray magnetic field from the underlying ferromagnetic wiring structure is minimized. [Background technology]

[0002] Magnetoresistive Random-Access Memory ("MRAM") devices are used as non-volatile computer memory. MRAM data is stored by magnetic memory elements. These elements consist of two ferromagnetic layers, each capable of holding a magnetic field separated by a spin-conductor layer. One of the two layers is a reference magnetic layer or reference layer set to a specific polarity, while the magnetic field of the other layer can be changed to match the polarity of an external magnetic field for memory storage and is called a "free magnet" or "free layer." This configuration is called a magnetic tunnel junction (MTJ) and is the simplest structure of MRAM bits in memory.

[0003] Cobalt (Co) is a new metal choice in advanced interconnect technologies because, compared to copper (Cu), it does not require additional liners for metal filling in back-end-of-line (BEOL) manufacturing, and it has significantly lower resistance than tungsten (W) in middle-of-line (MOL) manufacturing. Cobalt is a ferromagnetic material with high susceptibility to magnetization by strong stray electromagnetic fields. [Overview of the Initiative]

[0004] According to one embodiment, a semiconductor device is provided. The semiconductor device includes a second BEOL layer comprising a via dielectric layer surrounding a via, wherein the via comprises an upper metal stud and a lower metal stud, the upper metal stud and the lower metal stud separated by a liner, and a magnetic tunnel junction (MTJ) stack aligned above the via.

[0005] According to one embodiment, a semiconductor device is provided. The semiconductor device includes a first BEOL layer comprising a BEOL dielectric layer surrounding a back-end-of-line (BEOL) metal layer; a second BEOL layer directly above the first BEOL layer, comprising a via dielectric layer surrounding vias, the vias comprising upper and lower metal studs, the upper and lower metal studs being separated by a liner, and the BEOL metal layer being aligned with the vias; and a magnetic tunnel junction (MTJ) stack aligned above the vias.

[0006] According to one embodiment, a method is provided. The method includes forming a via dielectric layer as a second back-end-of-line (BEOL) layer; forming an opening through the via dielectric layer; forming a lower metal stud in part of the opening; forming a liner on the lower metal stud and on the exposed side of the rest of the opening; forming an upper metal stud in the rest of the opening; and forming a magnetic tunnel junction (MTJ) stack aligned above the upper metal stud.

[0007] These and other objects, features, and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the invention, which should be read in conjunction with the accompanying drawings. The drawings are not to a uniform scale, as they are intended to clarify the invention for those skilled in the art, with reference to the detailed description. [Brief explanation of the drawing]

[0008] [Figure 1] This graph shows the vibrational interlayer exchange coupling as a function of the thickness of the nonmagnetic layer between two ferromagnetic layers, according to one embodiment of the example. [Figure 2] This is a cross-sectional view of a semiconductor structure in an intermediate stage of manufacturing, according to one exemplary embodiment. [Figure 3] This figure shows the formation of a via-filled layer according to one exemplary embodiment. [Figure 4]This figure shows a depression in the via-filled layer according to one exemplary embodiment. [Figure 5] This figure shows the formation of a liner according to one exemplary embodiment. [Figure 6] This figure shows the formation of a second via-filled layer according to one exemplary embodiment. [Figure 7] This figure shows a planarization process according to one exemplary embodiment. [Figure 8] This figure shows the formation of the dielectric and the lower electrode according to one exemplary embodiment. [Figure 9] This figure shows the formation of a magnetoresistive random-access memory ("MRAM") stack layer according to one exemplary embodiment. [Figure 10] This figure shows the formation of a magnetic tunnel junction ("MTJ") stack according to one exemplary embodiment. [Figure 11] This figure shows the formation of a sidewall spacer and an upper dielectric according to one exemplary embodiment. [Modes for carrying out the invention]

[0009] For the sake of simplicity and clarity, please understand that the elements shown in the diagrams are not necessarily drawn to a uniform scale. For example, for clarity, the dimensions of some elements may be exaggerated relative to others. Also, where appropriate, reference numbers may be repeated between drawings to indicate corresponding or similar features.

[0010] This specification discloses detailed embodiments of the claimed structures and methods, but these embodiments should be understood as merely illustrative of the various forms in which the claimed structures and methods can be implemented. However, the present invention can be implemented in many different forms and should not be considered limited to the illustrative embodiments described herein. In this specification, well-known mechanisms and technical details may be omitted so as not to make the embodiments presented unnecessarily difficult to understand.

[0011] Where the terms "one embodiment," "one example embodiment," or "exemplary embodiment" are used herein, it is understood that the described embodiment may include certain features, structures, or characteristics, but not all embodiments may necessarily possess those features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, if certain features, structures, or characteristics are described in relation to one embodiment, it is assumed that such features, structures, or characteristics would be present in relation to other embodiments, whether explicitly stated or not, within the knowledge of those skilled in the art.

[0012] When we say that an element is "on" or "on top of" another element as a layer, region, or substrate, that element can be directly above the other element, or there may be intervening elements. In contrast, when we say that an element is "directly above" or "on top of" another element, there are no intervening elements. When we say that an element is "connected" or "bonded" to another element, that element can be directly connected or bonded to the other element, or there may be intervening elements. In contrast, when we say that an element is "directly connected" or "directly bonded" to another element, there are no intervening elements.

[0013] To avoid obscuring the presentation of embodiments of the present invention, some processing steps or operations known in the art may be combined for presentation and illustrative purposes in the following detailed description, and in some cases may not be described in detail. Furthermore, some processing steps or operations known in the art may not be described at all. It should be understood that the following description focuses rather on the unique features or elements of various embodiments of the present invention.

[0014] As described above, a magnetoresistive random access memory (hereinafter, "MRAM") device is a non-volatile computer memory technology. MRAM data is stored by magnetic memory elements. The elements are formed from two ferromagnetic layers, each of which can hold a magnetic field separated by a spin conductor layer. One of the two layers is a reference magnetic layer or reference layer set to a specific polarity, and the magnetic field of the other layer can be changed to match the polarity of an external magnetic field to store memory, and is referred to as a "free magnet" or "free layer". The magnetic reference layer may be called the reference layer, and the other layer may be called the free layer. This configuration is called a magnetic tunnel junction (hereinafter, "MTJ") and is the simplest structure of an MRAM bit of memory.

[0015] Memory devices are constructed from a grid of such memory cells or bits. In some configurations of MRAM, such as those detailed herein, the magnetization of the magnetic reference layer is fixed in one direction (upward or downward), and the direction of the magnetic free layer can be switched by an external magnetic field or an external force such as spin-transfer torque that generates a charge current. A smaller current (either magnetic) can be used to read the resistance of the device, which depends on the relative orientation of the magnetization of the magnetic free layer and the magnetic reference layer. The resistance is typically higher when the magnetization is antiparallel and lower when parallel, although this can be reversed depending on the materials used in the fabrication of the MRAM.

[0016] This application relates to magnetoresistive random access memory (MRAM). More particularly, this application relates to an embedded MRAM (eMRAM) that can be embedded between an M1 layer, i.e., a metal layer 1, and an M2 layer, i.e., a metal layer 2, and incorporated as a magnetic tunnel junction (MTJ) structure in the back end of line (BEOL) of semiconductor technology (such as CMOS technology) and can be incorporated into the back end of line (BEOL) processing of semiconductor technology.

[0017] One type of MRAM that can use MTJ is spin-transfer-torque MRAM (hereinafter referred to as "STT-MRAM"). STT MRAM has the advantages of lower power consumption and better scalability than conventional MRAM that uses a magnetic field to invert active elements. In STT MRAM, spin-transfer torque is used to invert (switch) the orientation of the magnetic free layer. In the case of an STT MRAM device, a current passing through the MTJ structure is used to switch or "write" the bit state of the MTJ memory element. A current passing downward through the MTJ structure aligns the magnetic free layer parallel to the magnetic reference layer, while a current passing upward through the MTJ structure makes the magnetic free layer antiparallel to the magnetic reference layer.

[0018] In advanced front-end-of-line (FEOL) technology, cobalt Co may be used in metal wiring, vias, contacts, and other areas that require electrical connections. Cobalt is ferromagnetic and has a high sensitivity to magnetization by a strong stray magnetic field. When forming an MTJ memory element, cobalt in the FEOL layer and middle-of-line (MOL) layer of the structure may affect the bit state of the MTJ memory element, thereby adversely affecting the stored MTJ memory element. The use of cobalt in this structure may affect the thermal stability and reliability of eMRAM applications.

[0019] The use of Co may introduce a stray magnetic field in the MTJ region, thereby changing the balance between the AP state and the P state of the MTJ. Depending on the direction of the stray magnetic field, the energy barrier of either the AP state or the P state may decrease, thereby making the MTJ more vulnerable to thermal fluctuations and thus affecting the thermal stability. The memory element in the MTJ can store in the AP state (high resistance state) or the P state (low resistance state).

[0020] Similar to thermal stability, the reliability is affected by possible changes in the state of the stored MTJ memory element due to changes in the energy barrier caused by the stray magnetic field.

[0021] The present invention generally relates to the field of semiconductor manufacturing, and more specifically to the fabrication of magnetic tunnel junction devices in structures on FEOL and MOL layers, wherein both the FEOL and MOL layers have a non-magnetic layer within the cobalt layer. This novel FEOL and MOL metallization integration method may help reduce stray electromagnetic fields in MTJ memory elements for eMRAM applications.

[0022] Next, referring to Figure 1, a graph 1000 is shown illustrating the vibrational interlayer exchange coupling as a function of the thickness of the non-magnetic layer between the two magnetic layers, according to one exemplary embodiment.

[0023] On the horizontal axis, we have thickness t, which is the thickness of the non-magnetic layer between the two ferromagnetic layers. NM This is shown. The vertical axis fluctuates in an oscillation pattern from strong positive to strong negative values, and the interlayer exchange coupling J oscillates so that the positive and negative peaks gradually decrease. IEC That is the case.

[0024] J is positive IEC The value of t corresponds to the thickness of the non-magnetic layer between the two ferromagnetic layers. NM This demonstrates that the magnetic field of the first of two ferromagnetic layers has an effect on the second of the two ferromagnetic layers. In other words, if the first layer has a magnetic field, this magnetic field will affect the magnetic field of the second layer. Conversely, if the second layer has a magnetic field, this magnetic field will affect the magnetic field of the first layer. IEC A larger value indicates that the magnetic field of either the first or second layer will have a stronger influence on the magnetic field of either the second or first layer.

[0025] Negative J IEC The value of t corresponds to the thickness of the non-magnetic layer between the two ferromagnetic layers. NMIt shows that the magnetic field of the first layer among the two ferromagnetic layers has no influence on the second layer among the two ferromagnetic layers. In other words, when the first layer has a magnetic field, this magnetic field will not affect the magnetic field of the second layer. Also, when the second layer has a magnetic field, this magnetic field will not affect the magnetic field of the first layer. J IEC A larger negative value of J indicates that the magnetic field of either the first layer or the second layer has little influence on the magnetic field of the other layer.

[0026] As shown in FIG. 1, the NM layer between the two ferromagnetic layers can enhance or increase the strong magnetic field of one layer with respect to the other layer from each of the ferromagnetic layers, as shown by the increase in coupling in graph 1000, or can cause cancellation or reduction of the strong magnetic field of one layer with respect to the other layer from each of the ferromagnetic layers, as shown by the decrease below 0 or cancellation of the coupling in graph 1000, and thus can vary between the strengthening effect and the decreasing effect. At an increased thickness t NM of, the two ferromagnetic layers may be antiferromagnetically coupled or have no influence on each other.

[0027] In one embodiment, a non-magnetic layer can be used when forming an electrical contact, an electrical via or a metal layer when forming an MTJ device, and the non-magnetic layer has a thickness t NM that has a minimum amount of influence on the magnetic field from one side of the non-magnetic layer to the other side. Point A in graph 1000 indicates the point where there is a minimum amount of influence on the magnetic field between the two magnetic layers through the non-magnetic layer having a thickness t IEC equal to the value a when the value of J NM is most negative at the value b.

[0028] Next, referring to FIG. 2, a semiconductor structure 100 (hereinafter referred to as "structure") in an intermediate stage of fabrication according to an exemplary embodiment is shown. FIG. 2 is a cross-sectional view of the structure 100.

[0029] Structure 100 may include several back-end-of-line ("BEOL") layers. Generally, the back-end-of-line (BEOL) is the second part of integrated circuit fabrication in which individual devices (transistors, capacitors, resistors, etc.) are interconnected by wiring on a wafer. As shown in Figure 2, the first BEOL layer includes a BEOL dielectric layer 10 surrounding a BEOL metal layer 12. A second BEOL layer formed on the first BEOL layer includes a via dielectric layer 14.

[0030] The BEOL dielectric layer 10 can be formed by conformally depositing or growing a dielectric and performing an isotropic etching process. The BEOL dielectric layer 10 may include one or more layers. The BEOL dielectric layer 10 may consist of, for example, silicon oxide (SiOx), silicon nitride (SiNx), silicon-boron carbonitride (SiBCN), NBLoK, or low dielectric constant dielectric materials (k<4.0), including but not limited to silicon oxide, spin-on glass, fluid oxide, high-density plasma oxide, and borosilicate glass (BPSG), or any combination thereof or any other suitable dielectric material.

[0031] For example, two openings (not shown) can be formed in the BEOL dielectric layer 10 by reactive ion etching (RIE) and stopping on a layer below the first BEOL layer to later fill the BEOL metal layer 12. The BEOL metal layer 12 can be formed within the two openings (not shown) in the BEOL dielectric layer 10 using known techniques. The BEOL metal layer 12 may include, for example, copper (Cu), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium nitride (TiN), or a combination thereof. The BEOL metal layer 12 can be formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), or a combination thereof. In the structure 100, any number of openings can exist within the BEOL dielectric layer 10, each filled with a BEOL metal layer 12.

[0032] Before forming the second BEOL layer, a planarization process, such as chemical mechanical polishing (CMP), can be performed to remove excess material from the upper surface of the first BEOL layer of the structure 100, so that the upper horizontal plane of the BEOL dielectric layer 10 and the upper horizontal plane of the BEOL metal layer 12 are coplanar.

[0033] The second BEOL layer is formed on the first BEOL layer. The second BEOL layer includes a via dielectric layer 14.

[0034] The via dielectric layer 14 can be formed by conformally depositing or growing a dielectric and performing an isotropic etching process. The via dielectric layer 14 may include one or more layers. The via dielectric layer 14 is formed above the BEOL dielectric layer 10 and the BEOL metal layer 12. The via dielectric layer 14 may be made of substantially the same material as the BEOL dielectric layer 10.

[0035] By stopping on the BEOL metal layer 12 of the first BEOL layer, an opening 16 can be formed in the BEOL via dielectric layer 14, as described above with respect to the opening (not shown) formed in the first BEOL layer. Although two openings 16 are shown, any number of openings 16 can be formed in the structure 100.

[0036] Next, referring to Figure 3, a structure 100 according to one exemplary embodiment is shown. A first via-filled layer 18 can be formed.

[0037] The first via packing layer 18 is formed within the openings 16 of the via dielectric layer 14. In certain embodiments, the first via packing layer 18 may include cobalt (Co), tungsten (W), copper (Cu), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium nitride (TiN), titanium oxide carbon nitride (TiOCN), tantalum oxide carbon (TaOCN), or a combination of these materials. The first via packing layer 18 can be formed, for example, by CVD, PVD, and ALD, or a combination thereof.

[0038] Specifically, the first via-filled layer 18 is aligned with the BEOL metal layer 12, thereby providing an electrical connection between the first via-filled layer 18 and the BEOL metal layer 12.

[0039] After the first via packing layer 18 is formed, the structure 100 is subjected to, for example, CMP to planarize the surface for further processing so that the upper horizontal plane of the via dielectric layer 14 and the upper horizontal plane of the via packing layer 18 are coplanar. The structure 100, including the BEOL layer shown in Figure 2, is the starting structure on which the MTJ stack is to be formed.

[0040] Next, referring to Figure 4, a structure 100 according to one exemplary embodiment is shown. The first via-filled layer 18 can be recessed.

[0041] To remove excess material from the upper surface of the second BEOL layer of the structure 100, a planarization process such as chemical mechanical polishing (CMP) can be performed, so that the upper horizontal surface of the via dielectric layer 14 and the upper horizontal surface of the first via packing layer 18 are coplanar.

[0042] The first via packing layer 18 can be recessed to form a second opening 20. The first via packing layer 18 can be selectively recessed relative to the via dielectric layer 14 such that the upper surface of the first via packing layer 18 is below the upper surface of the via dielectric layer 14. The first via packing layer 18 can be recessed by methods known in the art, such as dry etching or wet etching.

[0043] Next, referring to Figure 5, a structure 100 according to one exemplary embodiment is shown. A liner 24 can be formed.

[0044] The liner 24 can be conformally deposited on the structure 100 on the upper and side surfaces of the via dielectric layer 14 and on the upper surface of the first via packing layer 18. The liner 24 may be made of, for example, ruthenium (Ru), chromium (Cr), or tungsten (W). The liner 24 can be deposited using conventional deposition processes such as CVD, plasma-enhanced chemical vapor deposition (PECVD), PVD, or ALD. The liner 24 can be 10 nm thick, but thicknesses of less than 10 mm or greater than 10 mm are also acceptable. The liner 24 may partially fill the second opening 20 along its lower and side surfaces.

[0045] In one preferred embodiment, the liner 24 may comprise a non-magnetic (NM) conductive material and may have a preferred thickness b to accommodate the influence of a minimum amount of magnetic field between the two magnetic layers via the non-magnetic layer. This corresponds to the value of J at b, as described above with respect to Graph 1000. IEC The value of t is equal to the value a when the value is most negative. NM It corresponds to.

[0046] Next, referring to Figure 6, a structure 100 according to one exemplary embodiment is shown. A second via-filled layer 26 can be formed.

[0047] The second via-packed layer 26 can be formed within the second opening 20 in the via dielectric layer 14. In certain embodiments, the second via-packed layer 26 may include the material defined and formed as the first via-packed layer 18.

[0048] Next, referring to Figure 7, a structure 100 according to one exemplary embodiment is shown. The structure 100 is then flattened.

[0049] For further processing, the structure 100 can be subjected to, for example, CMP to flatten its surface so that the upper horizontal planes of the second via packing layer 26, the via dielectric layer 14, and the liner 24 are coplanar.

[0050] In this preferred embodiment, the first via packing layer 18, the liner 24, and the second via packing layer 26 form the electrical connections in the via dielectric layer 14. The first via packing layer 18 and the second via packing layer 26 are ferromagnetic materials and may contain cobalt, which can be sensitive to magnetization by strong stray electromagnetic fields. The liner 24 between the first via packing layer 18 and the second via packing layer 26 may be made of an NM conductive material that can help reduce stray electromagnetic fields in the MTJ memory element formed in the upper layer.

[0051] Specifically, the second via-packing layer 26 is aligned with the first via-packing layer 18 and the BEOL metal layer 12, thereby providing vias for electrical connections to the BEOL metal layer 12 through the via dielectric layer 14. A via is a metal wire that forms an electrical connection through the via dielectric layer 14 and is divided into two cobalt metal studs within the via dielectric layer 14. The first via-packing layer 18 may be referred to as the lower metal stud, and the second via-packing layer 26 may be referred to as the upper metal stud.

[0052] Next, referring to Figure 8, a structure 100 according to one exemplary embodiment is shown. A dielectric 30 and a lower electrode 32 can be formed.

[0053] The dielectric 30 can conformally cover the via dielectric layer 14. The dielectric 30 may include one or more layers. The dielectric 30 can be formed from the materials described above for the BEOL dielectric layer 10.

[0054] As described above, regarding the openings in the BEOL dielectric layer 10, openings (not shown) can be formed in the dielectric 30.

[0055] The lower electrode 32 can be formed within an opening (not shown) in the dielectric 30 using known techniques. The lower electrode 32 is formed with respect to the BEOL metal layer 12 as described above and may contain the materials described above. The structure 100 may have any number of openings in the dielectric 30, each opening filled with a lower electrode 32.

[0056] Specifically, the lower electrode 32 is aligned with the second via packing layer 26, the first via packing layer 18, and the BEOL metal layer 12, thereby providing an electrical connection between the lower electrode 32, the second via packing layer 26, the first via packing layer 18, and the BEOL metal layer 12.

[0057] Next, referring to Figure 9, a structure 100 according to one exemplary embodiment is shown, in which a magnetoresistive random-access memory ("MRAM") stack layer is formed, including a reference layer 40, a tunnel barrier 42, and a free layer 44, and an upper electrode 38 is also formed.

[0058] Each MRAM stack layer can be conformally formed on the structure 100 using known techniques. In the formation of the MTJ stack layer, the reference layer 40 is formed on the dielectric 30 and the lower electrode 32. The tunnel barrier layer 42 is formed on the reference layer 40. In one embodiment, the tunnel barrier layer 42 is a thin insulating layer or barrier such as potential between two conductive materials. Electrons (or quasiparticles) pass through the tunnel barrier layer 42 by the process of quantum tunneling. In a particular embodiment, the tunnel barrier layer 42 includes at least one sublayer made of MgO. It should be understood that other materials other than MgO can also be used to form the tunnel barrier layer 42. The free layer 44 is a magnetic free layer adjacent to the tunnel barrier 42 so as to be on the opposite side from the reference layer 40. The free layer 44 has a reversible magnetic moment or magnetization. It should also be understood that the MTJ stack layer may include additional layers, certain layers may be omitted, and each layer may include any number of sublayers. Furthermore, combinations of layers, sublayers, or both may differ between different MRAM stacks.

[0059] The upper electrode 38 can be conformally formed on the free layer 44 using known techniques. The upper electrode 38 is formed with respect to the BEOL metal layer 12 as described above and may contain materials as described above.

[0060] Next, referring to Figure 10, a structure 100 according to one exemplary embodiment is shown. An MTJ stack 50 is formed.

[0061] The structure 100 can be patterned and etched using known techniques for forming MTJ stacks 50. As shown in the figure, two MTJ stacks 50 are formed, but any number of MTJ stacks 50 can be formed. The MTJ stacks 50 can be patterned in one or more steps by lithography and ion beam etching (IBE) or RIE. Aligned vertical portions of the upper electrode 46, free layer 44, tunnel barrier layer 42, and reference layer 40 can be selectively removed relative to the dielectric 30. The remaining vertical portions of the upper electrode 46, free layer 44, tunnel barrier layer 42, and reference layer 40 can form MTJ stacks 50 and are alignable on the lower electrode 32, second via packing layer 26, first via packing layer 18, and BEOL metal layer 12.

[0062] Next, referring to Figure 11, a structure 100 according to one exemplary embodiment is shown. A side wall spacer 52 and an upper dielectric 54 can be formed.

[0063] The sidewall spacers 52 can be conformally formed on the structure 100 on the exposed upper surface of the dielectric 30 and on the vertical sides of the upper electrode 46, free layer 44, tunnel barrier layer 42, and reference layer 40. The sidewall spacers 52 can be formed by PVD, ALD, PECVD, and other methods, among others. The material for the sidewall spacers 52 may include silicon nitride (SiN), aluminum oxide (AlOx), titanium oxide (TiOx), silicon oxide (SiOx), boron nitride (BN), silicon-boron carbonitride (SiBCN), or any combination thereof.

[0064] In one preferred embodiment, the sidewall spacer 52 may undergo any pretreatment using plasma oxygen (O), hydrogen (H), nitrogen (N), or ammonia (NH3), or any combination thereof.

[0065] The structure 100 can be patterned using known techniques to selectively remove the sidewall spacers 52 from the upper surface of the dielectric 30 and the upper surface of the upper electrode 46, respectively, so that the remainder of the sidewall spacers 52 are left on the vertical surfaces of the upper electrode 46, the free layer 44, the tunnel barrier layer 42, and the reference layer 40.

[0066] The upper dielectric 54 can be conformally formed on the structure 100 on the exposed upper surfaces of the dielectric 30 and upper electrode 46, and on the vertical sides of the sidewall spacer 52. The upper dielectric 54 may include one or more layers. The upper dielectric 54 can be formed from the same materials as described above for the BEOL dielectric layer 10.

[0067] Chemical mechanical polishing (CMP) techniques can be used to remove excess material and polish the upper surface of the structure 100 so that the upper horizontal planes of the upper dielectric 54, side wall spacers 52, and upper electrode 46 are coplanar.

[0068] The resulting structure 100 includes an MTJ stack 50 formed on a via dielectric layer 14, the via dielectric layer 14 having openings for electrical connections filled with a first via packing layer 18 separated from a second via packing layer 26 by a liner 24. Both the first via packing layer 18 and the second via packing layer 26 are within the via dielectric layer 14 and both consist of a ferromagnetic material, specifically cobalt. The liner 24 may consist of an NM material and may have a thickness t corresponding to the effect of a minimum amount of magnetic field between the two magnetic layers, the first via packing layer 18 and the second via packing layer 26. The liner 24 is an NM layer within the cobalt layer and reduces stray electromagnetic fields that could adversely affect the MTJ stack 50.

[0069] The metal wire forming the electrical connection passing through the via dielectric layer 14 is divided into two cobalt metal studs within the via dielectric layer 14. This method of dividing the cobalt metal wire is applicable to contacts, vias, and other structures made of cobalt. In structure 100, the method of dividing the cobalt metal wire is applicable to the BEOL metal layer 12 of the first BEOL layer and to other cobalt conductive structures in structure 100.

[0070] While various embodiments of the present invention have been described for illustrative purposes, they are not intended to be exhaustive or to limit oneself to the embodiments disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. The terms used herein have been selected to best describe the principles of the embodiments, their practical applications, or the technical improvements to the technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A second back-end-of-line (BEOL) layer comprising a single via dielectric layer surrounding a via, wherein the via includes an upper metal stud and a lower metal stud, and the upper metal stud and the lower metal stud are separated by a liner disposed on the bottom and sides of the upper metal stud; A magnetic tunnel junction (MTJ) stack positioned above the via and Includes, The upper metal stud and the lower metal stud each contain cobalt, The liner is made of a non-ferromagnetic material, The thickness of the liner corresponds to the effect of the minimum amount of magnetic field between the two magnetic layers via the non-magnetic layer. Semiconductor devices.

2. The semiconductor device according to claim 1, further comprising a first back-end-of-line (BEOL) layer including a BEOL dielectric layer surrounding a BEOL metal layer, wherein the first BEOL layer is located below the second BEOL layer and the BEOL metal layer is aligned with the vias.

3. The semiconductor device according to claim 2, wherein the BEOL metal layer includes an upper metal stud and a lower metal stud, and the upper metal stud and the lower metal stud are separated by a BEOL metal layer liner.

4. A first back-end-of-line (BEOL) layer including a BEOL dielectric layer surrounding a BEOL metal layer, A second BEOL layer directly above the first BEOL layer, comprising a single via dielectric layer surrounding a via, wherein the via includes an upper metal stud and a lower metal stud, the upper metal stud and the lower metal stud are separated by a liner positioned on the bottom and sides of the upper metal stud, and the BEOL metal layer is aligned with the via, the second BEOL layer, A magnetic tunnel junction (MTJ) stack positioned above the via and Includes, The upper metal stud and the lower metal stud each contain cobalt, The liner is made of a non-ferromagnetic material, The thickness of the liner corresponds to the effect of the minimum amount of magnetic field between the two magnetic layers via the non-magnetic layer. Semiconductor devices.

5. The semiconductor device according to claim 4, wherein the BEOL metal layer includes an upper metal stud of the BEOL metal layer and a lower metal stud of the BEOL metal layer, and the upper metal stud of the BEOL metal layer and the lower metal stud of the BEOL metal layer are separated by a BEOL metal layer liner.

6. Forming a via dielectric layer as a second back-end-of-line (BEOL) layer, To form an opening that penetrates the via dielectric layer, A lower metal stud containing cobalt is formed in a part of the aforementioned opening, A liner made of a non-ferromagnetic material is formed on the lower metal stud and on the exposed side surface of the remaining portion of the opening, wherein the thickness of the liner corresponds to the effect of the minimum amount of magnetic field between the two magnetic layers via the non-magnetic layer. A cobalt-containing upper metal stud is formed in the remaining portion of the aforementioned opening, To form a magnetic tunnel junction (MTJ) stack aligned above the upper metal studs. Methods that include...

7. Forming a first back-end-of-line (BEOL) layer including a BEOL dielectric layer, To form a second opening in the BEOL dielectric layer, A BEOL metal layer is formed within the aforementioned opening. The method according to claim 6, further comprising the second BEOL layer being located above the first BEOL layer and the BEOL metal layer being aligned with the lower metal stud.

8. The method according to claim 7, wherein the BEOL metal layer includes an upper metal stud and a lower metal stud, and the upper metal stud and the lower metal stud are separated by a BEOL metal layer liner.

9. The method according to claim 8, wherein the upper metal stud of the BEOL metal layer and the lower metal stud of the BEOL metal layer each contain cobalt.

10. The method according to claim 8, wherein the BEOL metal layer liner comprises a non-ferromagnetic material.

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