Method for manufacturing SiC assemblies, power semiconductor devices, and SiC assemblies of power semiconductor devices.

Abstract

An assembly (1) for a power semiconductor device (10) is provided, the assembly (1) comprising a body (1M) based on SiC and a plurality of vias (1V) based on a conductive material. The body (1M) comprises a first layer (11) having a first thickness (11T) and a second layer (12) having a second thickness (12T), the second thickness (12T) being less than the first thickness (11T). The first layer (11) and the second layer (12) are formed from SiC, and the first layer (11) has a higher n-doping concentration than the second layer (12). The vias (1V) extend partially into the first layer (11) along a vertical direction from a bottom side (11B) of the first layer (11) toward the second layer (12), but the vias (1V) do not extend into the second layer (12). The assembly further comprises a SiC substrate (5), and the second layer (12) is disposed between the SiC substrate (5) and the first layer (11). The SiC substrate (5) has a vertical thickness (5T), and the ratio (5T / 12T) of the SiC substrate (5) to the second thickness (12T) is 1.5 to 250. The SiC substrate (5) is free of any vias formed from a conductive material. Furthermore, a power semiconductor device (10) comprising such an assembly (1), as well as a method and a method for manufacturing such an assembly (1) are provided.

Description

[Technical Field]

[0001] This disclosure relates to SiC assemblies, power semiconductor devices, and methods for manufacturing SiC assemblies of power semiconductor devices. [Background technology]

[0002] Conventional low-voltage SiC devices offer the very low on-state voltage drop required for certain applications such as event switching. However, the switch must withstand high-current pulses over long periods ranging from a few microseconds to several seconds. This places a high demand on so-called "single-event" turn-off capability, due not only to high turn-off current density and / or long pulse lengths, but also to very high temperature swings throughout the switch, affecting both the chip and the package.

[0003] In the field of recent SiC technology and material properties, due to the crystal defect density and their limiting effects on manufacturing yield and therefore die cost, the current die size is, for example, 50 mm. 2 This situation is complicated by the fact that it is limited to a typical value that does not exceed a certain threshold. Therefore, under the current circumstances, it is desirable to fully optimize the potential of SiC devices, such as SiC switches, in terms of on-resistance. Thus, in order to keep the SiC die area as low as possible for economic reasons, the current density under normal operating conditions must be as high as possible. However, this results in extremely high current densities during high-current events, leading to significant self-heating of the semiconductor chip and its package. [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] While the semiconductor material SiC can operate very well at high temperatures above 600K under vacuum, current state-of-the-art packaging and the materials used to create them cannot significantly exceed the maximum operating temperature of silicon devices. Therefore, for SiC devices used in applications such as event switching, there is a strong interest in adding as much thermal capacity as possible to the device. This disclosure intends to achieve this goal, for example, by utilizing a highly thermally conductive SiC layer on which a voltage-maintaining drift layer for power semiconductor devices such as switch devices is deposited or grown. [Means for solving the problem]

[0005] For example, embodiments of the present disclosure claimed in an independent claim address, in whole or in part, the aforementioned shortcomings in the art. Further embodiments of SiC assemblies, power semiconductor devices, and methods for manufacturing SiC assemblies of power semiconductor devices are the subject of further claims.

[0006] According to one embodiment of an assembly for a power semiconductor device, it comprises a body made of SiC and a plurality of vias made of a conductive material. The body comprises a first layer having a first thickness and a second layer having a second thickness, the second being less than the first. The first and second layers are formed from SiC. The first layer may have a higher n-doping concentration than the second layer. The vias partially extend into the first layer from the bottom side of the first layer toward the second layer along the vertical direction, and the vias do not extend into the second layer.

[0007] The first and second layers have different n-doping concentrations. However, the first and second layers may be formed from the same material, for example, 4H-SiC. However, it is possible for the second layer to be formed from 4H-SiC and the first layer to be formed from 3C-SiC or polySiC. For example, the second layer is a drift layer. Such a drift layer can be epitaxially grown on the first layer. The first layer can serve as a substrate supporting the second layer and mechanically stabilizing the assembly.

[0008] A via can be a trench completely filled with a conductive material. Alternatively, a via can be a trench partially filled with a conductive material. For example, only the inner wall of the trench may be covered with the conductive material. In this case, the trench may include areas filled with a gaseous medium, such as air.

[0009] The objective of this disclosure is to utilize a thicker first layer that enables a reduction in self-heating without having the drawback of simultaneously increasing the total resistance of the configuration, for example, the power semiconductor device. This objective is achieved by providing holes or trenches in a two-dimensional or three-dimensional arrangement configuration within the first layer, filled with a metal having high electrical conductivity and high thermal conductivity, such as aluminum, copper or silver due to their high inherent conductivity, or graphite in a suitable form. The number of holes or trenches in each assembly may be at least 4, 6, 8, 10, 16, 20, 50, or at least 100.

[0010] According to a further embodiment of the assembly, the ratio of the first vertical thickness to the second vertical thickness is 1.5 to 250. The first thickness can be 100 μm to 1000 μm. The second thickness can be 2 μm to 200 μm.

[0011] The vertical direction is understood to mean the direction perpendicular to the bottom surface of the first layer. The transverse direction is understood to mean the direction parallel to the bottom surface of the first layer. The vertical and transverse directions are orthogonal to each other. The bottom surface of the first layer is the outer surface located on the bottom side of the first layer and can be defined by one vector oriented along the length of the assembly and another vector oriented along the width of the assembly.

[0012] According to further embodiments of the assembly, the maximum vertical distance between the second layer and the via is 0.6 μm to 250 μm, for example, 1 μm to 250 μm. For example, the first thickness is 300 μm or more or 350 μm or more. The second thickness is, for example, 55 μm or less, 25 μm or less, or 10 μm or less. However, the first and second thicknesses are not limited thereto.

[0013] According to a further embodiment of the assembly, the ratio of the average vertical height of the via to the first thickness of the first layer is at least 0.5, for example, at least 0.6, 0.7, 0.8, or at least 0.9. In other words, the via extends into at least 50%, 60%, 70%, 80%, or at least 90% of the total vertical thickness of the first layer. However, the via does not extend vertically throughout the entire first layer. In this sense, the via extends vertically only partially into the first layer from the bottom side of the first layer toward the second layer.

[0014] According to a further embodiment of the assembly, the vias have an average width of 3 μm to 150 μm, for example, 6 μm to 150 μm or 10 μm to 150 μm. The vias have an average lateral length greater than the average width. Along the lateral direction, at least some or all of the vias can be completely or partially sealed by the first layer. However, along one lateral direction, at least some or all of the vias can extend from one first side of the first layer to another side of the first layer opposite to the aforementioned first side of the first layer. In this case, the vias can be exposed not only on the bottom side of the first layer but also at least partially on one or two sides of the first layer.

[0015] According to a further embodiment of the assembly, along the lateral direction, the vias are completely enclosed by a first layer. In this case, the vias are not exposed on the sides of the first layer.

[0016] According to a further embodiment of the assembly, the first layer has a first side and a second side. Along the transverse direction, at least one, some, or all of the vias can extend from the first side of the first layer to the second side. For example, the first side is on the opposite side of the second side. In this case, the vias can have a transverse length greater than or equal to the width or transverse length of the first layer. Along the transverse direction, the vias can extend along the width of the first layer or along the length of the first layer. The first side can also be adjacent to the second side. In this case, along the transverse direction, the vias can extend from the first side to the adjacent second side. Along the transverse direction, the vias are not parallel to the orientation of the width or length of the first layer.

[0017] According to a further embodiment of the assembly, the assembly further comprises a heatsink formed from, for example, metal. The body is configured to be placed on the heatsink, for example, directly on the heatsink. The heatsink has a vertical thickness greater than, for example, the sum of a first thickness and a second thickness.

[0018] The heatsink can be a thick metal plate, such as a copper plate, that serves as an efficient primary heatsink for the assembly or semiconductor device. The heatsink can have the same width and / or length as the main body. The vertical thickness of the heatsink can be 500 μm, 1000 μm, 2000 μm, 3000 μm, or 4000 μm or more.

[0019] According to a further embodiment of the assembly, the heatsink has a larger cross-section than the body such that the body completely overlaps the heatsink in a top view of the heatsink. However, it is also possible that the heatsink has a cross-section that is equal to or approximately equal to the cross-section of the body.

[0020] According to a further embodiment of this assembly, it further comprises a SiC substrate, the second layer being positioned between the SiC substrate and the first layer. The SiC substrate has a vertical thickness, and the ratio of the thickness of the SiC substrate to the second layer can be 1.5 to 250. The SiC substrate does not contain any vias formed from, for example, conductive material.

[0021] The SiC substrate and body may be separated by a metal layer, such as an aluminum or copper layer, which can constitute electrodes, such as a cathode, in the assembly or power semiconductor device. The SiC substrate acts as a top cooler and is, for example, electrically inactive. For this reason, vias, holes, or trenches are not formed within the SiC to reduce potential resistive voltage drops. For example, a thermal boundary electrode is located on the bottom side of the assembly.

[0022] According to a further embodiment of this assembly, the vias have a cross-section whose size varies along the vertical direction. For example, the size of the cross-section of each via increases as the distance from the bottom side of the first layer decreases. Due to this geometric shape of the vias, they can be filled with conductive material in an efficient and simple manner.

[0023] According to an embodiment of a power semiconductor device, it comprises an assembly, particularly the assembly described herein in the present disclosure. The assembly comprises a body based on SiC and a plurality of vias based on a conductive material. The body comprises a first layer having a first thickness and a second layer, and the second thickness is smaller than the first thickness. The first layer and the second layer are formed from SiC, and the first layer has a higher n-doping concentration than the second layer. The vias partially extend into the first layer vertically from the bottom side of the first layer towards the second layer and do not extend into the second layer. The second layer comprises a functional region configured to execute the functions of the power semiconductor device. The functional region can include, for example, the p-region and n-region of a transistor. For example, the second layer is formed as a drift layer.

[0024] According to a further embodiment of a power semiconductor device, it is formed as a metal-oxide-silicon field-effect transistor (MOSFET), a junction field-effect transistor (JFET), an insulated-gate bipolar transistor (IGBT), a Schottky diode, a Junction Barrier Schottky (JBS) diode, or a SiC power device for event switching. The second layer can include the functional region of such a transistor or diode.

[0025] According to one embodiment of a method for manufacturing an assembly of power semiconductor devices, a wafer is provided. The wafer comprises at least one body based on SiC. The wafer or the body comprises a first layer having a first thickness and a second layer having a second thickness, and the second thickness is smaller than the first thickness. The first layer and the second layer are formed from SiC. The first layer can have a higher n-doping concentration than the second layer. According to the method, a plurality of trenches are formed that extend partially into the first layer from the bottom side of the first layer towards the second layer along the vertical direction, and the trenches do not extend into the second layer. The trenches are filled with a conductive material for forming a plurality of vias, and the vias extend partially into the first layer from the bottom side of the first layer towards the second layer along the vertical direction and do not extend into the second layer.

[0026] According to a further embodiment of the method, the wafer is diced into a plurality of bodies along dicing lines, and at least some of the dicing lines pass through the vias such that at least some of the diced bodies include a side surface that includes the side surface of the via.

[0027] According to a further embodiment of the method, the wafer is diced into a plurality of bodies along dicing lines, and at least some of the dicing lines do not pass through the vias such that at least some of the diced bodies include all side surfaces where the side surface of the via does not exist.

[0028] This disclosure includes, based on those embodiments and examples, several aspects of power semiconductor device assemblies, power semiconductor devices comprising such assemblies, and methods for manufacturing such assemblies of such power semiconductor devices. All features described in relation to one aspect are also disclosed herein in relation to other aspects, even if each feature is not explicitly mentioned in the context of a particular aspect. For example, a method of this disclosure relates to a method for manufacturing an assembly described herein, and a power semiconductor device described herein may comprise such an assembly. Thus, the features and advantages described in relation to the assembly can be applied to the method and the power semiconductor device, and vice versa.

[0029] This disclosure accepts various modifications and alternative forms, the details of which are shown in the drawings and described in detail as examples. However, it should be understood that the intent is not to limit this disclosure to specific embodiments and examples described. Rather, the intent is to cover all modifications, equivalents, and alternatives that fall within the scope of this disclosure as defined by the appended claims.

[0030] The attached drawings are included to provide further understanding. In the drawings, elements of the same structure and / or function may be assigned the same reference numeral. Please understand that the embodiments shown in the drawings are illustrative and not necessarily to scale. [Brief explanation of the drawing]

[0031] [Figure 1A] This is a schematic cross-sectional view illustrating a general concept of an assembly for a power semiconductor device according to one embodiment of the present disclosure. [Figure 1B] This figure shows one of the different via arrangement configurations in one of the different embodiments of the assembly, viewed from above with respect to the bottom of the assembly. [Figure 1C]This figure shows one of the different via arrangement configurations in one of the different embodiments of the assembly, viewed from above with respect to the bottom of the assembly. [Figure 2] This figure shows a further embodiment of an assembly or power semiconductor device. [Figure 3] This figure shows a further embodiment of an assembly or power semiconductor device. [Figure 4] This figure shows a further embodiment of an assembly or power semiconductor device. [Figure 5] This figure shows a further embodiment of an assembly or power semiconductor device. [Figure 6] This figure shows a further embodiment of an assembly or power semiconductor device. [Figure 7] This figure shows a further embodiment of an assembly or power semiconductor device. [Figure 8A] This figure shows one of several simulation results for different embodiments of the assembly. [Figure 8B] This figure shows one of several simulation results for different embodiments of the assembly. [Figure 8C] This figure shows one of several simulation results for different embodiments of the assembly. [Figure 8D] This figure shows one of several simulation results for different embodiments of the assembly. [Figure 9A] This figure shows some exemplary method steps for a method of manufacturing at least one assembly for a power semiconductor device. [Figure 9B] This figure shows some exemplary method steps for a method of manufacturing at least one assembly for a power semiconductor device. [Figure 9C] This figure shows some exemplary method steps for a method of manufacturing at least one assembly for a power semiconductor device. [Figure 10A]This figure shows several exemplary method steps of different embodiments of a method for manufacturing multiple assemblies for power semiconductor devices. [Figure 10B] This figure shows several exemplary method steps of different embodiments of a method for manufacturing multiple assemblies for power semiconductor devices. [Figure 11A] This figure shows several exemplary method steps of different embodiments of a method for manufacturing multiple assemblies for power semiconductor devices. [Figure 11B] This figure shows several exemplary method steps of different embodiments of a method for manufacturing multiple assemblies for power semiconductor devices. [Figure 12] This figure shows several exemplary method steps of different embodiments of a method for manufacturing multiple assemblies for power semiconductor devices. [Figure 13] This figure shows several exemplary method steps of different embodiments of a method for manufacturing multiple assemblies for power semiconductor devices. [Modes for carrying out the invention]

[0032] Figure 1A shows a cross-sectional view of assembly 1 for a power semiconductor device 10 according to an exemplary embodiment. Assembly 1 comprises a body 1M having a first layer 11 having a first thickness 11T and a second layer 12 having a second thickness 12T. The body 1M is based on SiC. The first layer 11 is formed from SiC such as 4H-SiC, 3C-SiC, or polySiC. The second layer 12 is formed from SiC such as 4H-SiC. The first layer 11 has a higher n-doping concentration than the second layer 12. As shown in Figure 1A, the second thickness 12T is smaller than the first thickness 11T. The second layer 12 can be directly adjacent to the first layer 11.

[0033] The ratio of the first thickness 11T to the second thickness 12T, 11T / 12T, can be between 1.5 and 250, for example, 5 to 250, 5 to 200, 5 to 100, 5 to 50, 5 to 25, or 5 to 25. For example, the ratio 11T / 12T is 5 or more, 10 or more, 30 or more, 50 or more, or 100 or more. For example, the ratio 11T / 12T is 1.5 or more and 5 or more, but can be 10 or less, 15 or less, 20 or less, 30 or less, 50 or less, or 100 or less.

[0034] The first thickness 11T can be 100 μm to 1000 μm, for example, 100 μm to 800 μm, 100 μm to 600 μm, or 100 μm to 400 μm. For example, the first thickness 11T is 600 μm ± 300 μm, 600 μm ± 200 μm, or 600 μm ± 50 μm.

[0035] The second thickness 12T can be 2μm to 200μm, for example, 2μm to 100μm, 2μm to 50μm, or 2μm to 10μm. For example, the second thickness 12T is 50μm ± 10μm, 30μm ± 10μm, or 10μm ± 5μm.

[0036] For example, the first thickness 11T is 300 μm or more or 500 μm or more, and the second thickness 12T is 55 μm or less, 35 μm or less, 20 μm or less, or 10 μm or less.

[0037] Assembly 1 comprises a plurality of vias 1V based on a conductive material. For example, vias 1V are trenches filled with, for example, aluminum, copper, or silver. Vias 1V partially extend into the first layer 11 from the bottom side 11B of the first layer 11 toward the second layer 12 along the vertical direction, but do not extend into the second layer 12 and terminate before the second layer 12.

[0038] The maximum vertical distance between the second layer 12 and via 1V can be 0.6 μm to 250 μm, for example 1 μm to 250 μm, for example 1 μm to 150 μm, 1 μm to 100 μm, 1 μm to 50 μm, 1 μm to 30 μm, or 1 μm to 10 μm.

[0039] As shown in Figure 1A, via 1V extends only partially into the first layer. The ratio of the average vertical height of via 1V to the first thickness 11T of the first layer 11 can be at least 0.5, 0.6, 0.7, 0.8, or at least 0.9, for example, 0.8 to 0.98.

[0040] Via 1V can have an average width of 3 μm to 150 μm, for example 6 μm to 150 μm, 10 μm to 150 μm, for example 10 μm to 100 μm, 10 μm to 80 μm, 10 μm to 60 μm, 10 μm to 40 μm, or 10 μm to 20 μm. Via 1V can have an average lateral length greater than its average width. The lateral dimension of Via 1V can be the lateral length or width of Assembly 1.

[0041] For example, in a top view of the bottom side 11B of the first layer 11 as shown in Figures 1B and 1C, the vias 1V are strip-shaped. The vias 1V are parallel to each other. The ratio of the lateral length to the width of a single via 1V or via 1V can be 1.5 to 50, 1.5 to 30, 1.5 to 10, or 1.5 to 5. It is also possible that the vias 1V have other shapes in a top view of the bottom side 11B of the first layer 11, such as square, circular, trapezoidal, or other regular and irregular shapes.

[0042] As shown in Figure 1A, assembly 1 comprises a plurality of vias 1V, for example eight vias 1V, which extend laterally along the first side surface 11F to the second side surface 11S of the first layer 11, as shown in Figure 1B, with the first side surface 11F being opposite the second side surface 11S. Thus, the vias 1V can have a lateral length equal to or approximately equal to the width of the first layer 11. The vias 1V may be partially exposed on the first side surface 11F and / or the second side surface 11S. The eight vias 1V are parallel to each other.

[0043] Deviating from Figure 1B, via 1V can be rotated by an angle of 90°. In this case, via 1V can have a lateral length equal to or approximately equal to the length of the first layer 11. Other orientations of via 1V are also possible. For example, along the lateral direction, via 1V can extend from the first side 11F or the second side 11S to another side of the first layer 11, with the other side of the first layer adjacent to the first side 11F or the second side 11S.

[0044] Compared to via 1V in Figure 1B, via 1V in Figure 1C has the same lateral orientation when viewed from above relative to the bottom side 11B of the first layer 11. However, via 1V in Figure 1C does not extend to any side of the first layer 11. Therefore, in the lateral direction, via 1V is completely sealed or completely enclosed by the first layer 11.

[0045] Deviating from Figure 1C, via 1V can have other orientations along the lateral direction; for example, via 1V can be rotated by an angle of 90° or another angle.

[0046] Deviating from Figures 1A, 1B, and 1C, other arrangements and / or other numbers of vias 1V are also possible. For example, the number of vias 1V may be greater than or less than 8, for example, greater than 10, 15, 20, 30, 40, or 50. Combinations of vias 1V as shown in Figures 1B and 1C are also possible. In a top view relative to the bottom side 11B of the first layer 11, the vias 1V can be arranged in a matrix, i.e., arranged in multiple columns and rows. It is also possible that only one or both ends of some vias 1V are partially exposed on the side surface of the first layer 11, while some other vias 1V are completely enclosed by the first layer 11 and therefore not exposed on any side surface of the first layer 11.

[0047] The assembly 1 or power semiconductor device 10 shown in Figure 2 is essentially identical to the assembly 1 or power semiconductor device 10 shown in Figure 1A, except that Figure 2 shows only four vias 1V.

[0048] The assembly 1 or power semiconductor device 10 shown in Figure 3 is essentially identical to the assembly 1 or power semiconductor device 10 shown in Figure 1A, except that the vias 1V have cross-sections that vary in size along the vertical direction. The size of the cross-section of each via 1V increases as the distance to the bottom side 11B of the first layer 11 decreases. Here, the inner wall of the via 1V may be inclined, for example, to facilitate metallization at the end of semiconductor processing. Thus, at the bottom side 11B, each of the vias 1V has the largest cross-section or largest opening. This simplifies the material filling of the vias 1V and ensures that the vias 1V can be completely filled with electrical materials such as aluminum, copper, or silver.

[0049] The assembly 1 or power semiconductor device 10 shown in Figure 4 is essentially identical to the assembly 1 or power semiconductor device 10 shown in Figure 1A, except that the substrate 5 is placed on the main body 1M. The substrate 5 and the main body 1M can have the same geometric size, for example, the same length, width, and thickness. The substrate 5 can also have a vertical thickness 5T that is smaller or larger than that of the main body 1M. The substrate 5 can be formed from SiC. For example, the substrate 5 is formed from the same material as the first layer 11 of the main body 1M.

[0050] As shown in Figure 4, the second layer 12 is placed between the SiC substrate 5 and the first layer 11. The substrate 5 has a vertical thickness of 5T, and the ratio of the substrate 5 to the second layer thickness 12T, 5T / 12T, can be 1.5 to 250, for example, 5 to 250, 5 to 200, 5 to 100, 5 to 50, 5 to 25, or 5 to 25. For example, the ratio 5T / 12T is 5 or more, 10 or more, 30 or more, 50 or more, or 100 or more. For example, the ratio 5T / 12T is 1.5 or more and 5 or more, but can be 10 or less, 15 or less, 20 or less, 30 or less, 50 or less, or 100 or less.

[0051] The ratio of substrate 5 to the first thickness 11T, 5T / 11T, can be 0.3 to 3, for example, 0.5 to 3, 1 to 3, 0.5 to 2, 0.5 to 1.5, 0.75 to 1.25, 0.8 to 1.2, or 0.9 to 1.1. However, compared to the main body 1M or the first layer 11, substrate 5 does not contain any vias formed from conductive material.

[0052] The substrate 5 may act as a top cooler. The substrate 5 and the main body 1M may be separated by a metal layer, such as an aluminum or copper layer, which may constitute an electrode, such as a cathode, of the assembly 1 or the power semiconductor device 10. The substrate 5 acting as a top cooler is electrically inactive. For this reason, vias, holes, or trenches to reduce resistive voltage drop are not required. A thermal boundary electrode may be located on the bottom side of the assembly 1 or the power semiconductor device 10, for example, on the bottom side 11B of the first layer 11 of the main body 1M.

[0053] The assembly 1 or power semiconductor device 10 shown in Figure 5 is essentially identical to the assembly 1 or power semiconductor device 10 shown in Figure 1A, except that the main body 1M is placed on the heat sink 3. The heat sink 3 can be made of a metal, for example, copper. The heat sink 3 has a vertical thickness 3T that is greater than the sum of the first thickness 11T and the second thickness 12T, for example, at least 1.5, 2, 3, or 5 times greater than the sum of the first thickness 11T and the second thickness 12T.

[0054] Here, the heatsink 3 acts as the main heatsink or main cooler for the assembly 1 or the power semiconductor device 10. The presence of the heatsink 3 results in reduced self-heating and improved current density. These effects are enhanced when the heatsink 3 is used in combination with vias 1V formed in the first layer 11. As shown in Figure 5, the body 1M and the heatsink 3 may have substantially the same geometric size with respect to lateral length and / or width.

[0055] The assembly 1 or power semiconductor device 10 shown in Figure 6 is essentially identical to the assembly 1 or power semiconductor device 10 shown in Figure 5, except that the heatsink 3 has a larger cross-section than the main body 1M. In a top view relative to the heatsink 3, the main body 1M can completely overlap the heatsink 3. For example, the lateral length and width of the heatsink 3 are greater than the lateral length and width of the main body 1M. The heatsink 3 shown in Figure 5 and the heatsink shown in Figure 6 may have the same volume. It was found that using the heatsink 3 shown in Figure 6 resulted in further reduction of self-heating and improvement of current density compared to the heatsink 3 shown in Figure 5.

[0056] The assembly 1 or power semiconductor device 10 shown in Figure 7 is basically identical to the assembly 1 or power semiconductor device 10 shown in Figure 4, except that the assembly 1 or power semiconductor device 10 shown in Figure 7 includes a heat sink 3, as shown in Figure 6.

[0057] Several simulation results are shown in relation to Figures 8A, 8B, 8C, and 8D.

[0058] The procedure for manufacturing a SiC power device can begin with a first layer 11, which is a thick, highly doped SiC layer. For example, in the case of a SiC unipolar power device for 600V and 1.2kV applications, a second layer 12 is a thin, low-doped voltage-maintaining SiC drift layer, which can be epitaxially grown on top of the first layer 11. The thickness of the drift layer can range from a few μm to about 10 μm for the voltage classes mentioned above, which is very thin compared to the thick first layer 11, which has a vertical thickness of 100 μm, 200 μm, 300 μm or more 11T.

[0059] For example, in such low-voltage class devices, the resistive contribution of the first layer 11 cannot be ignored, so so far, the thickness of the first layer 11 has been made thin to allow the minimum on-state voltage drop to be achieved.

[0060] For self-heating simulation, this assembly 1, which is a resistor, or this power semiconductor device 10, has two electrical contacts used to energize the device. Since aluminum is widely used for metal contacts in power semiconductor devices, the simulated contacts are selected to be formed from aluminum. On the bottom side 11B of the first layer 11, there is a metallization, which is a thermal electrode where the thermal boundary conditions are implied. The initial temperature is set to 300K in this embodiment, and the thermal electrode is 10cm 2 Characterized by its thermal surface resistance in K / W, this value exemplifies the ability to mount power semiconductor devices on a small heatsink without forced cooling.

[0061] The simulation described here uses a thermal boundary surface temperature of 300K. In the self-heating simulation, a current pulse with a length of 3 seconds is applied to assembly 1 or power semiconductor device 10 comprising a first layer 11 and a second layer 12. The height of the current density pulse is variable, and therefore results in different maximum device temperatures at the end of the current pulse.

[0062] For comparison, in the 2D numerical simulation, the typical conventional thickness of the first SiC layer 11 was selected to be 100 μm, and the typical conventional thickness of the second SiC layer 12, which is the drift layer, was selected to be 8 μm, with 1.4 mΩcm above the first layer 11. 2 The assembly has a typical resistance for a 1.2kV SiC JFET with an on-resistance of . The widths of the first layer 11 and the second layer are selected to be 5120 μm, and a variable-height current is applied through the second layer 12 and the first layer 11, flowing from the top to the bottom of assembly 1. The top and bottom surfaces are electrical contacts, and the bottom surface also has a thermal contact with a thermal boundary condition T=300K.

[0063] The results for such a conventional assembly 1 or power semiconductor device 10 are shown by curve A1 in Figure 8A, where dT represents the average temperature rise in Kelvin and dI represents A / cm². 2This shows the pulse current density in units. Here, the first layer 11 does not contain any vias.

[0064] Curve A2 corresponds to the same configuration of assembly 1 or power semiconductor device 10 as curve A1, but the first layer 11 has a thickness of 600 μm 11T and there are no vias 1V at all.

[0065] Curve A3 corresponds to the same configuration of assembly 1 or power semiconductor device 10 as curve A2, but has four vias 1V as shown in Figure 2. Here, each of the four vias 1V is in the form of a trench 40 μm wide and 590 μm high, assumed to be filled with copper. They provide an electrical bypass from the upper drift layer, the second layer 12, to the electrical contacts on the bottom side 11B of the first layer 11. The thermal boundary / electrode is also located on the bottom side 11B of the first layer 11.

[0066] Curve A4 corresponds to the same configuration of assembly 1 or power semiconductor device 10 as curve A2, but has eight vias 1V as shown in Figure 1A. Here, each of the eight vias 1V is in the form of a trench 20 μm wide and 590 μm high, assumed to be filled with copper. They provide an electrical bypass from the upper drift layer, the second layer 12, to the electrical contacts on the bottom side 11B of the first layer 11. The thermal boundary / electrode is also located on the bottom side 11B of the first layer 11.

[0067] As shown in Figure 8A, due to the good thermal properties of silicon carbide, a thicker first layer 11 adds a considerable amount of heat capacity. This results in a slower increase in the assembly temperature when a current pulse is applied. However, it has also been observed that a second opposite effect occurs: as the thickness 11T of the first layer increases, the total resistance of the assembly 1 or power semiconductor device 10 also increases. This means that the heat generated by the exact same current pulse is higher in the second case. Thus, there exists a maximum thickness 11T of the first layer 11, at which point the final maximum temperature reached after a current pulse no longer decreases but instead rises again.

[0068] However, in the presence of via 1V, even a relatively thick first layer 11 can be guaranteed reduced self-heating and improved current density. The top of via 1V can be short, for example, in the range of 1μm to 50μm in the case of curves A3 and A4, and 10μm here, before the second layer 12, thereby contributing to the maximum path for bypassing the resistance of the first layer 11. The widths of the four vias 1V in the case of curve A3 and the eight vias 1V in the case of curve A4 were deliberately chosen to be different, indicating that the width of via 1V and the lateral spacing between vias 1V are parameters suitable for optimization. The results of self-heating simulations for various configurations are provided by curves A1 to A4. The density of vias 1V remains at a low level, with only four or eight vias 1V across an assembly width of 5120μm here, but the results provided by curves A3 and A4 already indicate the possibility of a peak temperature limit above 100K when measured against the base case provided by curve A1, especially at higher current densities. The peak temperature can be further limited by increasing the number and / or dimensions of vias 1V in the first layer 11.

[0069] Therefore, by using two-dimensional simulations, the effectiveness of this method is demonstrated in the configurations shown in Figures 1A and 2. It has been shown that a thick first layer 11 having multiple vias 1V can significantly delay thermal runaway. To enhance this effect, the density of vias 1V per unit area can be much higher than that used in the numerical examples presented herein.

[0070] Figure 8B shows further curves B1, B2, and B3 as a function of temperature rise with respect to current density after a 3-second current pulse.

[0071] Curve B1 corresponds to the same configuration of assembly 1 or power semiconductor device 10, comprising a first SiC layer 11 with a thickness 11T of 600 μm and no vias 1V, and a second SiC layer 12 which is a drift layer with a thickness of 8 μm, and a further configuration of assembly 1 or power semiconductor device 10 as shown by curve A2. In addition, assembly 1 or power semiconductor device 10 is placed on a heat sink 3 which is a copper plate with a thickness 3T of 4180 μm. Such assembly 1 or power semiconductor device 10 is shown in Figure 5, but the first layer 11 has no vias 1V.

[0072] Curve B2 corresponds to the same configuration of assembly 1 or power semiconductor device 10 as curve B1, but the first SiC layer 11 has a thickness of 600 μm 11T and four vias 1V, as shown in Figure 2. Such assembly 1 or power semiconductor device 10 is shown in Figure 5, where the first layer 11 has four vias 1V, each of the four vias 1V is in the form of a trench with a width of 40 μm and a vertical height of 590 μm and is filled with copper.

[0073] Curve B3 corresponds to the same configuration of assembly 1 or power semiconductor device 10 as curve B1, but has eight vias 1V. Such assembly 1 or power semiconductor device 10 is shown in Figure 5, where the first layer 11 has eight vias 1V, each of the eight vias 1V is in the form of a trench with a width of 20 μm and a vertical height of 590 μm, and is filled with copper.

[0074] As shown in Figure 8B, using the thickest first SiC with the highest via density (1V) allows for the most efficient delay of thermal runaway. This effect is enhanced in the presence of heatsink 3. According to Figure 8B, the maximum temperature is reached after a 3-second current pulse with a given current density. Compared to Figure 8A, as shown in Figure 8B, it is clear that the presence of heatsink 3 significantly limits the final temperature reached at the end of the current pulse. Here, for a given allowable temperature rise, the maximum current density can be approximately doubled by adding a thick copper heatsink 3, such as that used in the numerical example. This can be seen, for example, with a temperature rise of 150K, by comparing curve A4 in Figure 8A with curve B3 in Figure 8B.

[0075] Figure 8B also shows the advantage of a thick SiC first layer 11 featuring copper-filled vias 1V, resulting in a higher current density, e.g., 300 A / cm². 2 Nevertheless, it continues to be evident at lower current densities, for example, 150 A / cm². 2 Therefore, the maximum allowable current density increases by more than 10%.

[0076] Figure 8C shows curves B1, B2, and B3 already shown in Figure 8B, as well as additional curves C4 and C5.

[0077] Curve C4 corresponds to the same configuration of assembly 1 or power semiconductor device 10 as curve B3, but has a heatsink 3 that exceeds the width or cross-section of the main body 1M, as shown in Figure 6. Here, the size of the heatsink 3 has been changed from 5120 μm × 4180 μm to 10240 μm × 2090 μm, while the volume of the heatsink 3 remains unchanged.

[0078] Compared to the heat sink 3 shown in Figure 5, the heat sink 3 in Figure 6 has a larger width or a larger cross-section, but a smaller thickness 3T. Therefore, the volume of the heat sink 3 shown in Figure 5 and the volume of the heat sink 3 shown in Figure 6 can be the same, which applies to the configuration of assembly 1 or power semiconductor device 10 according to curves B3 and C4. In other words, curve B3 corresponds to assembly 1 or power semiconductor device 10 shown in Figure 5, and curve C4 corresponds to assembly 1 or power semiconductor device 10 shown in Figure 5. For a quantitative evaluation of the additional effect of the dimensions of the heat sink 3, from curves B3 and C4, a wider heat sink 3 with the same volume has a load of 300 A / cm². 2 It can be seen that this provides a reduction of approximately 50K at a current density.

[0079] Curve C5 corresponds to the same configuration of assembly 1 or power semiconductor device 10 as curve C4, except that assembly 1 or power semiconductor device 10 has a SiC substrate 5, i.e., a top cooler, as shown in Figure 7. The SiC substrate 5 can be approximately the same size as the first layer 11 or body 1M. However, the substrate 5 does not have vias 1V. For the simulation, the SiC substrate and the first SiC layer 11 have the same thickness of 600 μm.

[0080] Figure 8D is essentially identical to Figure 8A, except that Figure 8D shows an additional curve D5. Curve D5 corresponds to the same configuration of Assembly 1 or power semiconductor device 10 as curve A4 shown in Figure 1A, except that Assembly 1 comprises an additional SiC substrate 5 having a thickness of 5T as shown in Figure 4. For numerical simulation, the thickness 5T is selected to be 600 μm. Curve D5 shows that the additional substrate 5 can further delay thermal runaway, resulting in further reduction of self-heating and further improvement of current density.

[0081] Since the additional SiC substrate 5 acts as an additional heat sink in the SiC top cooler, the final maximum temperature after the completion of the current pulse with a pulse width of 3 seconds can be further reduced. Investigated configurations using a 1.2 kV JFET with an on-resistance of 1.4 mΩcm 2 can withstand current pulses of 150 - 160 A / cm 2 and the final temperature rise is 150 K. An initial configuration such as curve A1 reaches this temperature rise after a current pulse of 70 - 80 A / cm 2 . It is clear that the configuration shown in FIG. 4 may be extended for top and / or bottom cooling, i.e., may be extended for an additional substrate 5 and / or heat sink 3. In this case, the additional substrate 5 can accept a second thermal boundary / electrode.

[0082] In FIGS. 8A - 8D, some of the main concepts of the present disclosure are shown for a 1200 V device. This can be extended to other voltage classes to achieve similar advantages in reducing device temperature, thereby increasing the operating current density. This advantage may be more pronounced in low voltage classes such as 600 V devices typically used in event switching applications. This is because the contribution from the thick first layer 11 to the total device resistance becomes larger in such voltage ranges. The illustration is made using a first SiC layer 11 with a thickness of 600 μm. This can be applied to a standard first SiC layer 11 acting as a substrate with a thickness 11T of about 350 μm, and a similar trend in benefits is observed by using metal-filled trenches or vias 1V within the first layer 11 and / or in combination with the heat sink 3 and additional substrate 5.

[0083] FIGS. 9A, 9B, and 9C show some exemplary method steps for manufacturing at least one assembly 1 for the power semiconductor device 10.

[0084] According to Figure 9A, a wafer 100 is provided comprising at least one body 1M made of SiC, the body 1M comprising a first layer 11 having a first thickness 11T and a second layer 12 having a second thickness 12T. The second thickness 12T is smaller than the first thickness 11T, and the first layer 11 and the second layer 12 are formed from SiC. The first layer 11 has a higher n-doping concentration than the second layer 12. For example, the first layer 11 is formed as a substrate, and the second layer 12 is formed as a drift layer of assembly 1 or power semiconductor device 10.

[0085] According to Figure 9B, multiple trenches 1H partially extend into the first layer 11 from the bottom side 11B of the first layer 11 toward the second layer 12 along the vertical direction, while the trenches 1H do not extend into the second layer 12. Several possible arrangements of the trenches 1H are described in relation to Figures 10A to 13. The trenches 1H can be formed by drilling and / or etching processes.

[0086] According to Figure 9C, the trench 1H is filled with conductive material to form multiple vias 1V, which partially extend into the first layer 11 from the bottom side 11B toward the second layer 12 along the vertical direction, but not into the second layer 12. Therefore, the vias 1V do not provide a connection between the bottom side 11B and the top side of the first layer 11. In other words, the trench 1H is not formed as a through-hole extending vertically through the entire first layer 11. For this reason, the vias 1V are not formed as through-vias.

[0087] Trench 1H can be completely filled with conductive material, as shown in Figure 9C. However, it is possible for trench 1H to be partially filled with conductive material. For example, only the inner wall of trench 1H may be covered with conductive material. In this case, trench 1H may include areas filled with a gaseous medium, such as air.

[0088] Figure 10A shows possible arrangements of trenches 1H or vias 1V relative to the edge 100E of wafer 100 and to multiple assemblies 1 or power semiconductor devices 10 to be manufactured. The trenches 1H or vias 1V extend perpendicular to the edge 100E. In a top view relative to the bottom side of the wafer, some of the trenches 1H or vias 1V overlap with the multiple assemblies 1 or power semiconductor devices 10 to be manufactured. The trenches 1H or vias 1V are parallel to each other. The trenches 1H or vias 1V can also be formed within regions between the assemblies 1 or power semiconductor devices 10 to be manufactured. The trenches 1H or vias 1V can extend across the entire lateral extension range of wafer 100.

[0089] When the wafer 100 is pieced into a plurality of bodies 1M, assemblies 1, or power semiconductor devices 10 along a piecementation line 1S, at least some of the pieced bodies 1M, assemblies 1, or power semiconductor devices 10 pass through via 1V such that at least some of the pieced bodies 1M, assemblies 1, or power semiconductor devices 10 include sides that include the sides of via 1V.

[0090] Figure 10B shows a cross-sectional view of wafer 100 along line AB as shown in Figure 10A. Deviating from Figures 10A and 10B, other lateral orientations of trench 1H or via 1V are also possible. For example, trench 1H or via 1V may be parallel to the wafer edge 100E or form an acute angle with the edge 100E.

[0091] The wafer 100 shown in Figure 11A is essentially identical to the wafer 100 shown in Figure 10A, which has trenches 1H or vias 1V, except that it does not have trenches 1H or vias 1V located in the region between the assembly 1 or power semiconductor device 10 that will be manufactured. Therefore, it can be ensured that no part of the framing lines passes through trenches 1H or vias 1V. Figure 11B shows a cross-sectional view of the wafer 100 as shown in Figure 11A, along line AB.

[0092] The wafer 100 shown in Figure 12 is essentially identical to the wafer 100 having the trench 1H or via 1V shown in Figure 10A, except that the trench 1H or via 1V is parallel to the wafer edge 100E.

[0093] The wafer 100 shown in Figure 13 is essentially identical to the wafer 100 with trenches 1H or vias 1V shown in Figure 10A, except that the trenches 1H or vias 1V are formed only within the region of the assembly 1 or power semiconductor device 10 to be manufactured. Therefore, in the lateral direction, the trenches 1H or vias 1V are completely surrounded by the first layer 11.

[0094] As shown in Figure 13, when the wafer 100 is pieced into multiple bodies 1M, assemblies 1, or power semiconductor devices 10 along the pieceping line 1S, none of the pieceping lines 1S pass through any vias 1V so that vias 1V do not exist on any of the sides of all the pieced bodies 1M, assemblies 1, or power semiconductor devices 10.

[0095] Deviating from Figure 13, via 1V can rotate by an angle of 90° or another angle, for example, 45°±10°, 45°±15°, 45°±20°, or 45°±30°. As shown in Figure 13, in a top view relative to the bottom side of the first layer 11, via 1V can extend across the entire width or lateral length of the power semiconductor device 10 to be manufactured. Via 1V can also have a lateral extension range that is smaller than the width and / or lateral length of the power semiconductor device 10 to be manufactured. Deviating from Figure 13, it is also possible that via 1V may have a lateral extension range that is larger than the width and / or lateral length of the power semiconductor device 10 to be manufactured before the wafer 100 is pieced into multiple power semiconductor devices 10.

[0096] The embodiments shown in the figures above represent exemplary embodiments of assemblies, power semiconductor devices, and methods for manufacturing assemblies for power semiconductor devices. Therefore, they do not constitute a complete list of all embodiments and methods with improved configurations of assemblies, power semiconductor devices, and methods. Actual configurations of assemblies, power semiconductor devices, and methods may differ from the exemplary embodiments described above.

[0097] This application claims priority to European Patent Application No. 23160696.3, the disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0098] Reference sign 100 wafers 10 Power semiconductor devices 1 Assembly 1M Assembly Body 1V via 1H Trench / Hole 1S singulation wire 11 The first layer of the main body 11B Bottom side of the first layer 11F First side of the first layer 11S Second side of the first layer 11T 1st thickness 12 The second layer of the main body 12T Second thickness 3 Heatsink 3T heatsink thickness 5 circuit boards 5T substrate thickness 100E wafer edge

Claims

1. An assembly (1) for a power semiconductor device (10), - The assembly (1) comprises a main body (1M) made of SiC and a plurality of vias (1V) made of a conductive material. - The main body (1M) comprises a first layer (11) having a first thickness (11T) and a second layer (12) having a second thickness (12T), wherein the second thickness (12T) is smaller than the first thickness (11T). - The first layer (11) and the second layer (12) are formed from SiC, and the first layer (11) has a higher n-doping concentration than the second layer (12). - The via (1V) partially extends into the first layer (11) from the bottom side (11B) of the first layer (11) toward the second layer (12) along the vertical direction, and the via (1V) does not extend into the second layer (12). - The assembly further comprises a SiC substrate (5), - The second layer (12) is placed between the SiC substrate (5) and the first layer (11). - The SiC substrate (5) has a vertical thickness (5T), and the ratio of the SiC substrate (5) to the second thickness (12T) (5T / 12T) is 1.5 to 250. - The SiC substrate (5) has no vias formed from conductive material whatsoever in the assembly (1).

2. - The ratio of the first thickness (11T) to the second thickness (12T) (11T / 12T) is 1.5 to 250. - The assembly (1) according to claim 1, wherein the first thickness (11T) is 100 μm to 1000 μm and the second thickness (12T) is 2 μm to 200 μm.

3. - The first thickness (11T) is 300 μm or more, - The second thickness (12T) is 55 μm or less, - The assembly (1) according to claim 1, wherein the maximum vertical distance between the second layer (12) and the via (1V) is 0.6 μm to 250 μm.

4. The ratio of the average vertical height of the via (1V) to the first thickness (11T) of the first layer (11) is at least 0.

5. - The assembly (1) according to claim 1, wherein the via (1V) has an average width of 10 μm to 150 μm.

5. The assembly (1) according to any one of claims 1 to 4, wherein the via (1V) is completely surrounded by the first layer (11) along the transverse direction.

6. The assembly (1) according to any one of claims 1 to 4, wherein the first layer (11) has a first side surface (11F) and a second side surface (11S), and at least one of the vias (1V) extends laterally from the first side surface (11F) to the second side surface (11S).

7. The assembly (1) according to claim 1, further comprising a heat sink (3) formed of metal, wherein the main body (1M) is disposed on the heat sink (3), and the heat sink (3) has a vertical thickness (3T) greater than the sum of the first thickness (11T) and the second thickness (12T).

8. The assembly (1) according to claim 7, wherein the heat sink (3) has a larger cross-section than the main body (1M) such that the main body (1M) completely overlaps the heat sink (3) in a plan view of the heat sink (3).

9. - The SiC substrate (5) and the main body (1M) are separated by a metal layer that constitutes the electrode of the assembly (1), - The assembly (1) according to claim 1, wherein the SiC substrate (5) acts as an upper cooler and is not electrically active.

10. The assembly (1) according to claim 1, wherein the via (1V) has a cross section whose size changes along the vertical direction, and the size of each of the cross sections of the via (1V) increases as the distance to the bottom side (11B) of the first layer (11) decreases.

11. A power semiconductor device (10) comprising an assembly (1), - The assembly (1) comprises a main body (1M) made of SiC and a plurality of vias (1V) made of a conductive material. - The main body (1M) comprises a first layer (11) having a first thickness (11T) and a second layer (12) having a second thickness (12T), wherein the second thickness (12T) is smaller than the first thickness (11T). - The first layer (11) and the second layer (12) are formed from SiC, and the first layer (11) has a higher n-doping concentration than the second layer (12). - The via (1V) partially extends into the first layer (11) from the bottom side (11B) of the first layer (11) toward the second layer (12) along the vertical direction, and the via (1V) does not extend into the second layer (12). - The second layer (12) comprises a functional region configured to perform the function of the power semiconductor device (10), - The assembly further comprises a SiC substrate (5), - The second layer (12) is placed between the SiC substrate (5) and the first layer (11). - The SiC substrate (5) has a vertical thickness (5T), and the ratio of the SiC substrate (5) to the second thickness (12T) (5T / 12T) is 1.5 to 250. - A power semiconductor device (10) in which the SiC substrate (5) does not contain any vias formed from conductive material.

12. The power semiconductor device (10) according to claim 11, which is a MOSFET, JFET, IGBT, Schottky diode, junction barrier Schottky diode, or SiC power device for event switching.

13. A method for manufacturing an assembly (1) for a power semiconductor device (10), - To provide a wafer (100) comprising at least one body (1M) made of SiC, wherein the body (1M) comprises a first layer (11) having a first thickness (11T) and a second layer (12) having a second thickness (12T), wherein the second thickness (12T) is smaller than the first thickness (11T). - To provide a wafer (100) in which the first layer (11) and the second layer (12) are formed from SiC, and the first layer (11) has a higher n-doping concentration than the second layer (12), - To form a plurality of trenches (1H) that partially extend into the first layer (11) from the bottom side (11B) of the first layer (11) toward the second layer (12) along the vertical direction, wherein the trenches (1H) do not extend into the second layer (12), - Filling the trench (1H) with a conductive material to form a plurality of vias (1V), wherein the vias (1V) partially extend into the first layer (11) from the bottom side (11B) of the first layer (11) toward the second layer (12) along the vertical direction, but do not extend into the second layer (12), and the trench (1H) is filled with a conductive material to form a plurality of vias (1V), The assembly comprises a SiC substrate (5), - The second layer (12) is placed between the SiC substrate (5) and the first layer (11). - The SiC substrate (5) has a vertical thickness (5T), and the ratio of the SiC substrate (5) to the second thickness (12T) (5T / 12T) is 1.5 to 250. - A method in which the SiC substrate (5) does not contain any vias formed from conductive material.

14. - The wafer (100) is separated into multiple bodies (1M) along the separation line (1S), The method according to claim 13, wherein at least some of the individualized bodies (1M) have sides that include sides of the via (1V) and at least some of the individualized lines (1S) pass through the via (1V).

15. - The wafer (100) is separated into multiple bodies (1M) along the separation line (1S), The method according to claim 13, wherein at least some of the individualized body (1M) includes all sides of which no side of the via (1V) is present, and at least some of the individualized lines (1S) do not pass through the via (1V).

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