Method for manufacturing a photoelectric converter
By laminating substrates with a trench and recessed dielectric in the thinning process, the method addresses stress-induced defects on the light-receiving surface, improving the characteristics of photoelectric conversion devices.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- CANON KK
- Filing Date
- 2021-12-14
- Publication Date
- 2026-06-19
AI Technical Summary
The thinning process in manufacturing back-illuminated photoelectric conversion devices can cause defects on the light-receiving surface due to stress around the termination detection portion, leading to deterioration of device characteristics.
A method involving lamination of substrates with a trench and embedded dielectric, followed by selective etching and polishing to expose the dielectric, ensuring the dielectric is recessed from the light-receiving surface, thereby reducing stress-induced defects.
This approach improves the characteristics of photoelectric conversion devices by minimizing defects on the light-receiving surface, enhancing device performance and reliability.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention ,light relates to a method for manufacturing an electrical conversion device.
Background Art
[0002] In a photoelectric conversion device such as an image sensor, a back-illuminated photoelectric conversion device may be used for miniaturization and multifunctionality. In Patent Document 1, when manufacturing a back-illuminated solid-state imaging device, a termination detection portion having a hardness greater than that of the semiconductor substrate is embedded on the surface side of the semiconductor substrate, and the semiconductor substrate is thinned by chemical mechanical polishing from the back surface until the termination detection portion is exposed.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] In the thinning process shown in Patent Document 1, due to the influence of stress generated around the termination detection portion of the semiconductor substrate when exposing the termination detection portion, defects may occur on the light-receiving surface of the photoelectric conversion element. Defects on the light-receiving surface of the photoelectric conversion element can cause deterioration of the characteristics of the photoelectric conversion device.
[0005] An object of the present invention is to provide a technique advantageous for improving the characteristics of a photoelectric conversion device.
Means for Solving the Problems
[0006] In view of the above problems, the photoelectric conversion device according to an embodiment of the present invention A method for manufacturing a photoelectric conversion device comprising a first substrate on which a plurality of photoelectric conversion elements are arranged, and a second substrate laminated on the first substrate, comprising the steps of: preparing a structure in which the first substrate and the second substrate are laminated; and thinning the first substrate of the structure, wherein the first substrate comprises a first surface located on the side of the second substrate and a second surface located on the opposite side of the first surface, the first surface has a trench, and a dielectric having a third surface located on the side of the second substrate is embedded in the trench, and the thinning step comprises thinning the first substrate until the dielectric is exposed from the side of the second surface The thinning process includes: a first step, a second step of etching the dielectric from the side of the second surface so that, after the first step, the fourth surface of the etched dielectric, located on the opposite side of the third surface, is located between a virtual plane including the surface of the first substrate exposed by the first step and a virtual plane including the first surface; and a third step of polishing the first substrate from the side of the surface of the first substrate exposed by the first step, wherein in the third step, the thinning is completed with the fourth surface located between a virtual plane including the surface of the first substrate exposed by the third step and a virtual plane including the first surface. is characterized by the following.
Effects of the Invention
[0007] According to the present invention, it is possible to provide a technology that is advantageous for improving the characteristics of photoelectric conversion devices. [Brief explanation of the drawing]
[0008] [Figure 1] A cross-sectional view showing an example configuration of the photoelectric conversion device of this embodiment. [Figure 2] Figure 1 shows a modified example of the photoelectric conversion device. [Figure 3] A cross-sectional view showing the manufacturing method of the photoelectric conversion device shown in Figure 1. [Figure 4] A cross-sectional view showing the manufacturing method of the photoelectric conversion device shown in Figure 1. [Figure 5] This figure shows an example of the configuration of a device incorporating the photoelectric conversion device of this embodiment. [Modes for carrying out the invention]
[0009] The embodiments will be described in detail below with reference to the attached drawings. Note that the following embodiments do not limit the invention as defined in the claims. While the embodiments describe multiple features, not all of these features are essential to the invention, and the features may be combined in any way. Furthermore, in the attached drawings, identical or similar configurations are given the same reference numerals, and redundant descriptions are omitted.
[0010] A photoelectric conversion device according to an embodiment of the present disclosure will be described with reference to Figures 1 to 5. Figure 1 is a cross-sectional view showing an example of the configuration of the photoelectric conversion device 930 of this embodiment. It comprises a substrate 200 on which a plurality of photoelectric conversion elements 222 are arranged, and a substrate 100 on which a plurality of transistors 120 for operating the plurality of photoelectric conversion elements 222 are arranged and laminated on the substrate 200. Semiconductors such as silicon are used for the substrates 100 and 200.
[0011] On the surface 151 of substrate 100 that is located on the side of substrate 200, a wiring structure 1010 including a wiring pattern is arranged, and together with the substrate 100 and the transistor 120 and other components arranged on the surface 151 of substrate 100, it constitutes a semiconductor component 1001. On the surface 251 of substrate 200 that is located on the side of substrate 100, a wiring structure 1020 including a wiring pattern is arranged, and together with the substrate 200 and other components, it constitutes a semiconductor component 1002.
[0012] In this embodiment, the substrate 200 has a thickness of, for example, about 2 to 9 μm. The semiconductor component 1001 and the semiconductor component 1002 overlap each other and are joined together at the bonding surface 400. In the direction Z in which the substrates 100 and 200 are stacked, the insulating film 112 of the semiconductor component 1001 (wiring structure 1010) and the insulating film 212 of the semiconductor component 1002 (wiring structure 1020) are stacked so as to be located between the substrates 100 and 200. In the wiring structure 1010, each of the plurality of conductive parts 113 is arranged in each of the plurality of recesses provided in the insulating film 112. Similarly, in the wiring structure 1020, each of the plurality of conductive parts 213 is arranged in each of the plurality of recesses provided in the insulating film 212. Semiconductor component 1001 and semiconductor component 1002 are joined to each other by a conductive portion 113 located in a recess provided in the insulating film 112 and a conductive portion 213 located in a recess provided in the insulating film 212.
[0013] Let the plane intersecting direction Z be the XY plane. Direction Z and the XY plane can intersect perpendicularly. The XY plane is parallel to at least one of the surfaces 151 of substrate 100 and 251 of substrate 200. Directions X and Y are orthogonal to each other and parallel to at least one of the surfaces 151 of substrate 100 and 251 of substrate 200. Figure 1 shows a cross-section of the photoelectric converter 930 in the direction (direction Z) in which substrates 100 and 200 are stacked.
[0014] The conductive portion 113 includes a pad 311 surrounded by an insulating film 112 in the XY plane, and a plug 312 coupled to the pad 311 so as to be located between the pad 311 and the substrate 100 in the Z direction. The plug 312 is connected to a conductive layer 111 located between the plug 312 and the substrate 100 in the Z direction. The conductive layer 111 is in close proximity to the plug 312.
[0015] The conductive portion 213 comprises a pad 321 surrounded by an insulating film 212 in the XY plane, and a plug 322 coupled to the pad 321 so as to be located between the pad 321 and the substrate 200 in the Z direction. The plug 322 is connected to a conductive layer 211 located between the plug 322 and the substrate 200 in the Z direction. The conductive layer 211 is in close proximity to the plug 322.
[0016] Semiconductor component 1001 is a semiconducting component (semiconductor chip) comprising a substrate 100 and a wiring structure 1010, and semiconductor component 1002 is a semiconducting component (semiconductor chip) comprising a substrate 200 and a wiring structure 1020. The wiring structure 1010 and the wiring structure 1020 each have a plurality of stacked wiring layers and a plurality of stacked insulating films, as will be described later. For this reason, the wiring structure 1010 and the wiring structure 1020 joined together can also be called the wiring structure portion of the photoelectric converter 930. The photoelectric converter 930 is constructed by joining semiconductor component 1001 and semiconductor component 1002.
[0017] The structure between the substrate 100 and the semiconductor component 1002 (between the substrate 100 and the wiring structure 1020) is the wiring structure 1010. The wiring structure 1010 includes the conductive part 113 and the conductive layer 111 described above. In addition to the conductive part 113 and the conductive layer 111, the wiring structure 1010 may include a plug 110 disposed between the conductive layer 111 and the substrate 100, a wiring layer 107, a plug 108, a wiring layer 105, a plug 104, etc. Further, the wiring structure 1010 includes the insulating film 112 described above, and in addition to the insulating film 112, may include insulating films 109, 106, 103 disposed between the insulating film 112 and the substrate 100. However, the configuration of the wiring structure 1010 is not limited to the structure shown in FIG. 1, and the number and arrangement of the wiring layers, plugs, and insulating films may be appropriately adjusted according to the functions and performance required for the photoelectric conversion device 930.
[0018] The structure between the substrate 200 and the semiconductor component 1001 (between the substrate 200 and the wiring structure 1010) is the wiring structure 1020. The wiring structure 1020 includes the conductive part 213 and the conductive layer 211 described above. In addition to the conductive part 213 and the conductive layer 211, the wiring structure 1020 may include a plug 210 disposed between the conductive layer 211 and the substrate 200, a wiring layer 207, a plug 208, a wiring layer 205, a plug 204, etc. Further, the wiring structure 1020 includes the insulating film 212 described above, and in addition to the insulating film 212, may include insulating films 209, 206, 203 disposed between the insulating film 212 and the substrate 200. However, the configuration of the wiring structure 1020 is not limited to the structure shown in FIG. 1, and the number and arrangement of the wiring layers, plugs, and insulating films may be appropriately adjusted according to the functions and performance required for the photoelectric conversion device 930.
[0019] The conductive layers 111 and 211 can also be called wiring layers, but here they are referred to as conductive layers 111 and 211 to distinguish the wiring layers adjacent to the plugs 312 and 322 from the other wiring layers. Plug 208 connects wiring layer 205 and wiring layer 207, and plug 210 connects wiring layer 207 and conductive layer 211. The conductive portion 213 may have a damascene structure embedded in a recess provided in the insulating film 212. At least a portion of the conductive portion 213 is connected to the conductive layer 211. In this embodiment, the conductive portion 213 has a dual damascene structure and is composed of a pad 321 and a plug 322. Semiconductor component 1001 and semiconductor component 1002 are electrically connected by the conductive portion 113 and conductive portion 213.
[0020] The main component of conductive parts 113 and 213 may be copper, but is not limited to copper; the main component of conductive parts 113 and 213 may be gold or silver. The main component of insulating film 112 and insulating film 212 may be silicon compounds such as silicon oxide, silicon nitride, or silicon oxynitride. Furthermore, insulating film 112 and insulating film 212 may have a multilayer structure consisting of multiple materials, such as a laminated structure in which a layer that suppresses metal diffusion (e.g., a silicon nitride layer) and a silicon oxide layer or a low-k material layer are laminated. By providing a layer that suppresses metal diffusion, the effect of metal diffusion caused by bonding misalignment between conductive parts 113 and 213, which occurs due to alignment misalignment that occurs when semiconductor component 1001 and semiconductor component 1002 are joined, can be suppressed. Also, for example, the main component of insulating film 112 and insulating film 212 may be resin.
[0021] Here, the conductive portion 113 and the insulating film 112 are collectively referred to as the joining member 411, and the conductive portion 213 and the insulating film 212 are collectively referred to as the joining member 421. The joining member 411 included in the semiconductor component 1001 is joined to the joining member 421 included in the semiconductor component 1002. From the substrate 100 to the substrate 200, the plug 104, the wiring layers 105 and 107, the conductive layer 111, the conductive portions 113 and 213, the conductive layer 211, the wiring layers 207 and 205, and the plug 204 are electrically continuous. These constitute the conductive pattern (interlayer wiring pattern) between the substrate 100 and the substrate 200. The interlayer wiring pattern may have one end connected to the gate electrode of the transistor 120 and the other end connected to the source / drain of the transistor 120, or the interlayer wiring pattern may have one end and the other end both connected to the source / drain of the transistor 120.
[0022] In the photoelectric conversion device 930, the wiring structure 1010 and the wiring structure 1020 are joined. More specifically, the wiring structure 1010 and the wiring structure 1020 are joined at the joining surface 400 constituted by the joining member 411 of the wiring structure 1010 and the joining member 421 of the wiring structure 1020. The joining surface 400 includes the surface of the joining member 411 and the surface of the joining member 421.
[0023] On the surface 151 of the substrate 100, an element isolation portion 101 and a plurality of transistors 120 are provided. The surface 151 of the substrate 100 may be referred to as the main surface of the substrate 100. In the photoelectric conversion device 930, the integrated circuit on the substrate 100 can include signal processing circuits such as an analog signal processing circuit, an AD conversion circuit, a noise removal circuit, and a digital signal processing circuit that process pixel signals. That is, at least a part of the plurality of transistors 120 may constitute a digital signal processing circuit for digitally processing the signals output from the plurality of photoelectric conversion elements 222 on the substrate 200. Also, the substrate 100 can be referred to as a "semiconductor layer".
[0024] The element isolation section 101 has an STI (Shallow Trench Isolation) structure and defines the element region (active region) of the substrate 100. Multiple transistors 120 can constitute, for example, a CMOS circuit. The source / drain 121 of the transistor 120 may have a silicide layer 122 such as cobalt silicide or nickel silicide. Therefore, the conductive part 113 is electrically connected to the substrate 100 via the silicide layer 122. More specifically, the plug 104 electrically connected to the conductive part 113 is in contact with the silicide layer 122 formed between the interlayer insulating film 103 and the substrate 100 via a salicide process. When the conductive part 113 is electrically connected to the substrate 100 via the silicide layer 122, the contact resistance may be lower compared to when it is electrically connected to the substrate 100 without the silicide layer. The gate electrode 102 of the transistor 120 may have a silicide layer, a metal layer, or a metal compound layer. The gate insulating film of transistor 120 can be made of silicon oxide, silicon nitride, metal oxides such as hafnium oxide, etc.
[0025] Surface 251 of the substrate 200 is provided with a trench 600 penetrating the substrate 200, an element isolation section 201, a gate electrode 202, a photoelectric conversion section 220, a floating diffusion 221, and the like. The photoelectric conversion section 220 is composed of a photodiode or photogate. The photodiode may be an avalanche diode. The surface of the substrate 200 on which multiple transistors are provided is the main surface of the substrate 200. Surface 151 of the substrate 200 located on the side of the substrate 100 is sometimes referred to as the main surface of the substrate 100. The substrate 200 can also be called a "semiconductor layer".
[0026] A dielectric 601 is embedded in a trench 600 that penetrates the substrate 200. The dielectric 601 has a surface 651 located on the side of the substrate 100 and a surface 652 located on the opposite side of surface 651. The dielectric 601 includes, for example, silicon nitride. However, it is not limited to this. For example, a material with higher hardness than the substrate 200 may be used for the dielectric 601. Surface 651 of the dielectric may be located on the same plane as surface 251 of the substrate 200, as shown in Figure 1. In other words, the inner wall of the trench 600 does not have to be exposed on the side of surface 251 of the substrate 200. On the other hand, surface 652 of the dielectric 601 is located between a virtual plane including surface 252 of the substrate 200 and a virtual plane including surface 251 of the substrate 200. Therefore, the inner wall of the trench 600, from the height of the substrate 200 surface 252 to the height where the dielectric surface 601 surface 652 is located, is not covered by the dielectric 601 (recessed region 602). On the side of the substrate 200 surface 252, the surface (surface 652) of the dielectric 601 is recessed compared to the substrate 200 surface 251. This configuration between the trench 600 and the dielectric 601 will be described later.
[0027] The element isolation unit 201 has, for example, an STI structure and defines the element region (active region) of the substrate 200. The gate electrode 202 transfers the charge from the photoelectric conversion unit 220 to the floating diffusion 221. The substrate 200 is also provided with a pixel circuit that converts the charge generated by the photoelectric conversion unit 220 into a pixel signal. The pixel circuit may include a reset transistor, an amplification transistor, a selection transistor, etc. A pixel signal corresponding to the charge transferred to the floating diffusion 221 is generated by the amplification transistor. The potential of the floating diffusion 221 is reset to a reset potential by the reset transistor. The photoelectric conversion element 222 described above includes the photoelectric conversion unit 220, the gate electrode 202, the floating diffusion 221, and their respective pixel circuits.
[0028] As described above, the conductive portion 113 is electrically connected to the substrate 100 via the silicide layer 122. On the other hand, the conductive portion 213 is electrically connected to the substrate 200 without a silicide layer. In this embodiment, the plug 204 electrically connected to the conductive portion 213 is in contact (ohmic contact) with the impurity region of the substrate 200, which was formed without the salicide process. However, the embodiment is not limited to this, and the plug 204 may also be electrically connected to the substrate 200 via a silicide layer, such as titanium silicide or tungsten silicide, which is locally formed beneath the plug 204.
[0029] In this embodiment, semiconductor component 1001 has a digital circuit and semiconductor component 1002 has an analog circuit, however, semiconductor component 1001 may have an analog circuit and semiconductor component 1002 may have a digital circuit. The photoelectric conversion unit 220 provided on the substrate 200 is connected to the floating diffusion 221 via the gate electrode 202. The floating diffusion 221 is connected to the gate electrode of the source follower transistor of the pixel circuit described above. An analog pixel signal is output from the source of the source follower transistor. The pixel circuit including the gate electrode 202 and the source follower transistor may be the analog circuit of semiconductor component 1002. The analog pixel signal is converted to a digital pixel signal by an AD conversion circuit. The digital pixel signal is processed by a digital signal processing circuit (DSP). The digital signal processing circuit that performs image processing may be an image processing circuit (ISP). This digital signal processing circuit may be a circuit arranged on semiconductor component 1001. In addition, digital circuits placed on semiconductor component 1002 include interface circuits such as LVDS (Low Voltage Differential Signaling) and MIPI (Mobile Industry Processor Interface).
[0030] In the photoelectric converter 930 of this embodiment, a dielectric film 500 including dielectrics 511, 512, and 513 is arranged on the surface 252 of the substrate 200. The dielectric film 500 may be a laminated structure including multiple dielectrics 511 to 513 as shown in Figure 1, or it may be a single-layer structure.
[0031] Of the dielectric film 500, dielectric 511 is arranged in the trench 600 so as to be in contact with the surface 652 of dielectric 601. Furthermore, dielectric 511 is in contact with the inner wall of the trench 600 in a recessed region 602 of the substrate 200 that is exposed because the surface 652 of dielectric 601 is located between a virtual plane including surface 252 of the substrate 200 and a virtual plane including surface 251.
[0032] A metal oxide having a negative fixed charge may be used as the dielectric 511. By placing the dielectric 511 having a negative fixed charge near the substrate 200, noise caused by electrons generated near the substrate 200 can be reduced. Examples of materials that can be used for the dielectric 511 having a negative fixed charge include hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, tantalum oxide, and ruthenium oxide. For example, the dielectric 511 may be hafnium oxide or aluminum oxide. The thickness of the dielectric 511 may be, for example, 5 nm to 20 nm. In the configuration shown in Figure 1, the dielectric 511 is arranged to cover the surface 251 of the substrate 200, and furthermore, the dielectric 511 is in contact with the substrate 200. However, it is not limited to this, and another dielectric with a thickness of less than 10 nm may be placed between the dielectric 511 and the surface 251 of the substrate 200. For example, silicon oxide less than 10 nm in size may be placed between the dielectric 511 formed of hafnium oxide or the like and the surface 251 of the substrate 200.
[0033] The dielectric 512 may function as an anti-reflective layer. When the dielectric 512 is used as an anti-reflective layer, the thickness of the dielectric 512 may be greater than the thickness of the dielectric 511. When the dielectric 512 is used as an anti-reflective layer, the thickness of the dielectric 512 may be, for example, in the range of 20 nm to 100 nm. Metal oxide layers such as hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, tantalum oxide, and ruthenium oxide may be used for the dielectric 512. Alternatively, silicon compounds such as silicon oxide, silicon nitride, and silicon oxynitride may be used for the dielectric 512. Since tantalum oxide has a high dielectric constant among these dielectrics, tantalum oxide may be used for the dielectric 512 that functions as an anti-reflective layer.
[0034] The dielectric 513 is made of a material having a lower refractive index than the dielectric 512 in order to provide the dielectric 512 with appropriate anti-reflective properties. The dielectric 513 may be a silicon compound such as silicon oxide, silicon nitride, or silicon oxynitride, or a resin material may be used.
[0035] A color filter 514 and a microlens 515 are arranged on the dielectric film 500. Furthermore, for example, a light-shielding film made of a metal such as tungsten may be provided between the dielectric film 500 and the color filter 514 and microlens 515 to form an OB (Optical Black) region. Alternatively, for example, light-shielding walls may be provided on the dielectric film 500 and the color filter 514 to separate light between the photoelectric conversion elements 222.
[0036] In this embodiment, the dielectric 601 embedded in the trench 600 penetrating the substrate 200 is recessed from the surface 251 of the substrate 200, and the surface 652 of the dielectric 601 is located between a virtual plane including the surface 252 of the substrate 200 and a virtual plane including the surface 251. The effects resulting from adopting this configuration will be explained below with reference to Figures 3(a) to 4(b). Figures 3(a) to 4(b) show a method for manufacturing the photoelectric converter 930.
[0037] First, as shown in Figure 3(a), a semiconductor component 1001 including a substrate 100 and a semiconductor component 1002 including a substrate 200 are joined to each other at a bonding surface 400 to prepare a structure 1003 in which the substrates 100 and 200 are stacked. Next, a thinning process is performed to thin the substrate 200 within the structure 1003. Through a thinning process in which a portion of the substrate 200 is removed from the side of the substrate 200 opposite to the side 151 on the substrate 100 side (side 262), the aforementioned side 252 of the substrate 200 becomes the light-receiving surface of the photoelectric converter 930.
[0038] After preparing the structure 1003, first, the substrate 200 is thinned from the side of surface 262, as shown in Figure 3(b). The process shown in Figure 3(b) may involve mechanical grinding or chemical mechanical polishing (CMP). Alternatively, wet etching may be used in the process shown in Figure 3(b). The substrate 200 is thinned until the dielectric 601 embedded in the trench 600 formed on surface 251 of the substrate 200 is exposed, as shown in Figure 3(b). The process shown in Figure 3(b) exposes the surface 272 of the substrate 200 along with the surface 662 of the dielectric 601. The surface 272 of the substrate 200 and the surface 662 of the dielectric 601 may be on the same plane, or the dielectric 601 may protrude convexly beyond the surface 272 of the substrate 200.
[0039] Next, as shown in Figure 4(a), a portion of the dielectric 601 is etched so that its surface is recessed compared to the surface 272 of the substrate 200 exposed by the process shown in Figure 3(b). In other words, the dielectric 601 is etched from the side of surface 252 of the substrate 200 so that surface 652, which is located opposite to surface 651 of the dielectric 601 after etching, is located between a virtual plane containing the surface 272 of the substrate 200 exposed by the process shown in Figure 3(b) and a virtual plane containing surface 251 of the substrate 200. In this process, the dielectric 601 may be etched by wet etching. A suitable etching solution can be used that can selectively etch the dielectric 601 depending on the combination of the substrate material and the dielectric material of the dielectric 601.
[0040] After etching the dielectric 601, an additional thinning step (hereinafter sometimes referred to as an additional step) is performed to further thin the substrate 200 from the side of the surface 272 of the substrate 200 exposed by the process shown in Figure 3(b), as shown in Figure 4(b). For example, chemical mechanical polishing is used for the additional step. In this additional step, the thinning is completed when the surface 652 of the dielectric 601 exposed by etching in Figure 4(a) is located between a virtual plane containing the surface of the substrate 200 exposed by the additional step (surface 252 of the substrate 200) and a virtual plane containing the surface 251 of the substrate 200. In other words, the thinning of the substrate 200 is completed when the surface (surface 652) of the dielectric 601 is recessed compared to the surface 252 of the substrate 200. In the additional step, for example, by performing the processing while optically monitoring the film thickness of the substrate 200, the polishing can be completed with the surface 652 of the dielectric 601 recessed compared to the surface 252 of the substrate 200. However, the process is not limited to this, and depending on the combination of process conditions and process time, the thinning may be completed such that the surface 652 of the dielectric 601 is located between a virtual plane including the surface 252 of the substrate 200 and a virtual plane including the surface 251 of the substrate 200.
[0041] If the dielectric 601 protrudes from the surface 252 of the substrate 200 during the additional chemical mechanical polishing process, there is a possibility that the dielectric 601 may be damaged during polishing, or that stress may be generated between the substrate 200 and the dielectric 601 due to the force applied to the dielectric 601 during polishing. Damage to the dielectric 601 or stress between the substrate 200 and the dielectric 601 may cause defects around the trench 600 of the substrate 200. Since the surface 252 of the substrate 200 becomes the light-receiving surface of the photoelectric conversion element 222, if a defect occurs on the surface 252, it may cause a decrease in the characteristics of the photoelectric conversion device 930.
[0042] On the other hand, in this embodiment, in this additional step, as shown in Figure 4(b), the dielectric 601 embedded in the trench 600 is positioned recessed from the surface 252 of the substrate 200. Therefore, defects in the substrate 200 caused by polishing of the dielectric 601 in the additional step can be suppressed. In other words, it is possible to suppress the occurrence of defects on the surface 252 of the substrate 200 that becomes the light-receiving surface, thereby improving the characteristics of the photoelectric converter 930.
[0043] Figure 2 is a cross-sectional view showing a modified example of the photoelectric converter 930 shown in Figure 1. As shown in Figure 2, the substrate 200 is provided with a trench 600 that penetrates the substrate 200, and a dielectric 601, for example, made of silicon nitride, is embedded in the trench 600. By forming a trench 600 on the surface 251 of the substrate 200, embedding the dielectric 601 in the trench 600, and using the thinning process described above, a trench 600 penetrating the substrate 200 with the dielectric 601 embedded in a position recessed from the surface 252 of the substrate 200 can be formed.
[0044] As shown in Figure 2, in this embodiment, by arranging the trenches 600 to separate adjacent photoelectric conversion elements 222, adjacent photoelectric conversion elements 222 are electrically isolated by the dielectric 601 embedded in the trenches 600. In other words, the dielectric 601 functions as an element isolation region between multiple photoelectric conversion elements 222. This makes it possible to suppress the leakage of charge generated in a photoelectric conversion element 222 (photoelectric conversion unit 220) to an adjacent photoelectric conversion element 222. Furthermore, since the dielectric 601 embedded in the trenches 600 is recessed compared to the surface 252 of the substrate 200, the increase in dark current due to embedded film stress is suppressed. Thus, in this embodiment as well, it is possible to suppress the occurrence of defects on the light-receiving surface 252 of the substrate 200 and improve the characteristics of the photoelectric conversion device 930.
[0045] An example of the application of the photoelectric converter 930 of this embodiment will be described using Figure 5. Figure 5 is a schematic diagram of a device 9191 equipped with the photoelectric converter 930. The photoelectric converter 930 may include a semiconductor device 910 containing the semiconductor components 1001 and 1002 described above, as well as a package 920 housing the semiconductor device 910, but the photoelectric converter 930 does not have to include the package 920. Substrates 100 and 200 are included in the semiconductor device 910. In this embodiment, the photoelectric converter 930 is a photoelectric converter (imaging device). The semiconductor device 910 has a pixel region 901 in which photoelectric conversion elements 222 are arranged in a matrix and a peripheral region 902 around it. Peripheral circuits and input / output terminals can be provided in the peripheral region 902. The device 9191 may include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990.
[0046] The following describes in detail the device 9191 equipped with the photoelectric converter 930, as shown in Figure 5. As described above, the photoelectric converter 930 may include a package 920 that houses the semiconductor device 910, in addition to the semiconductor device 910 having a substrate 100. The package 920 may include a base on which the semiconductor device 910 is fixed, and a lid made of glass or the like that faces the semiconductor device 910. The package 920 may further include bonding members such as bonding wires or bumps that connect terminals provided on the base and terminals provided on the semiconductor device 910.
[0047] The device 9191 may include at least one of the following: an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the photoelectric converter 930. The optical device 940 is, for example, a lens, a shutter, or a mirror. The control device 950 controls the photoelectric converter 930. The control device 950 is, for example, a semiconductor device such as an ASIC.
[0048] The processing unit 960 processes the signal output from the photoelectric converter 930. The processing unit 960 is a semiconductor device such as a CPU or ASIC that constitutes an AFE (analog front end) or DFE (digital front end). The display device 970 is an EL display device or liquid crystal display device that displays the information (image) obtained by the photoelectric converter 930. The storage device 980 is a magnetic device or semiconductor device that stores the information (image) obtained by the photoelectric converter 930. The storage device 980 is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive.
[0049] The mechanical device 990 has movable parts or propulsion parts such as a motor or engine. The device 9191 displays the signal output from the photoelectric converter 930 on the display device 970 or transmits it to the outside using a communication device (not shown) provided in the device 9191. For this purpose, it is preferable that the device 9191 further includes a storage device 980 and a processing device 960, separate from the memory circuit and arithmetic circuit of the photoelectric converter 930. The mechanical device 990 may be controlled based on the signal output from the photoelectric converter 930.
[0050] Furthermore, the device 9191 is suitable for electronic devices such as information terminals with shooting capabilities (e.g., smartphones and wearable devices) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). In a camera, the mechanical device 990 can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in a camera can move the photoelectric converter 930 for vibration damping.
[0051] Furthermore, the device 9191 may be a transport device such as a vehicle, ship, or aircraft. The mechanical device 990 in the transport device may be used as a moving device. The device 9191 as a transport device is suitable for transporting the photoelectric converter 930 or for assisting and / or automating driving (piloting) through its imaging function. The processing device 960 for assisting and / or automating driving (piloting) can process information obtained from the photoelectric converter 930 to operate the mechanical device 990 as a moving device. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring instrument such as a distance sensor, an analytical instrument such as an electron microscope, or an office machine such as a copier.
[0052] The embodiments described above can be modified as appropriate without departing from the technical concept. Furthermore, the disclosures in this specification include not only what is described herein, but also all matters that can be understood from this specification and the drawings attached thereto. The disclosures in this specification also include the complement of the concepts described herein. That is, if this specification contains a statement such as "A is B," then even if a statement such as "A is not B" is omitted, this specification shall be deemed to disclose that "A is not B." This is because the statement "A is B" presupposes that the case where "A is not B" is being considered.
[0053] The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, claims are attached to disclose the scope of the invention. [Explanation of symbols]
[0054] 100,200: substrate, 120: transistor, 151,251,252,651,652: surface, 222: photoelectric conversion element, 600: trench, 601: dielectric, 930: photoelectric conversion device
Claims
1. A method for manufacturing a photoelectric conversion device comprising a first substrate on which a plurality of photoelectric conversion elements are arranged, and a second substrate laminated on the first substrate, A step of preparing a structure in which the first substrate and the second substrate are stacked, The process includes a thinning step of thinning the first substrate of the structure, The first substrate comprises a first surface located on the side of the second substrate and a second surface located on the opposite side from the first surface. The first surface has trenches, A dielectric material having a third surface located on the side of the second substrate is embedded in the trench. The thinning process is as follows: A first step of thinning the first substrate until the dielectric is exposed from the second surface, A second step is performed, following the first step, to etch the dielectric from the side of the second surface, such that the fourth surface of the etched dielectric, which is located on the opposite side of the third surface, is located between a virtual plane including the surface of the first substrate exposed in the first step and a virtual plane including the first surface. The process includes, after the second step, a third step of polishing the first substrate from the side of the surface of the first substrate that was exposed by the first step, A manufacturing method characterized in that, in the third step, the thinning is completed when the fourth surface is located between a virtual plane including the surface of the first substrate exposed in the third step and a virtual plane including the first surface.
2. The manufacturing method according to claim 1, characterized in that the dielectric material includes silicon nitride.
3. The photoelectric converter includes a peripheral area for connection to the outside of the photoelectric converter, The manufacturing method according to claim 1 or 2, characterized in that the trench in the first substrate is arranged between the peripheral region and the plurality of photoelectric conversion elements.
4. The manufacturing method according to claim 3, characterized in that a terminal and a bonding wire connected to the terminal are arranged in the peripheral region.
5. An opening is provided in the aforementioned peripheral region. The manufacturing method according to claim 4, characterized in that the terminal and the bonding wire are arranged in the opening.
6. The dielectric and the trench are designated as the first dielectric and the first trench, A second trench is provided on the first surface. The second trench is embedded with a second dielectric made of the same material as the first dielectric, which has a fifth surface located on the side of the second substrate. In the first step, the second dielectric is exposed from the side of the second surface, After the second step, the sixth surface of the second dielectric, which is located on the opposite side of the fifth surface, is located between a virtual plane including the surface of the first substrate exposed in the first step and a virtual plane including the first surface. After the third step, the sixth surface is located between a virtual plane including the surface of the first substrate exposed by the third step and a virtual plane including the first surface. The manufacturing method according to any one of claims 1 to 5, characterized in that the second trench is arranged between the plurality of photoelectric conversion elements.
7. The manufacturing method according to claim 1 or 2, characterized in that the dielectric functions as an element isolation region between the plurality of photoelectric conversion elements.
8. The aforementioned dielectric is the first dielectric, The manufacturing method according to any one of claims 1 to 7, characterized in that a third dielectric material, which is made of a different material from the first dielectric material that is in contact with the fourth surface, is disposed in the trench.
9. The manufacturing method according to claim 8, characterized in that the third dielectric is in contact with the inner wall of the trench.
10. The manufacturing method according to claim 8 or 9, characterized in that the third dielectric is arranged to cover the second surface.
11. The manufacturing method according to any one of claims 8 to 10, characterized in that the third dielectric comprises a metal oxide.
12. The manufacturing method according to claim 11, characterized in that the metal oxide includes at least one of hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, tantalum oxide, and ruthenium oxide.
13. The manufacturing method according to any one of claims 1 to 12, characterized in that the first surface and the third surface are arranged on the same plane.
14. The second substrate is provided with a plurality of transistors for operating the plurality of photoelectric conversion elements. The manufacturing method according to any one of claims 1 to 13, characterized in that at least a portion of the plurality of transistors constitute a digital signal processing circuit for digitally processing the signals output from the plurality of photoelectric conversion elements.
15. The manufacturing method according to any one of claims 1 to 14, characterized in that, in the third step, the first substrate is polished while optically monitoring the film thickness of the first substrate.
16. The manufacturing method according to any one of claims 1 to 15, characterized in that the dielectric is etched by wet etching in the second step.
17. The manufacturing method according to any one of claims 1 to 16, characterized in that the first substrate is polished by chemical mechanical polishing in the third step.
18. The photoelectric conversion device comprises a first semiconductor component and a second semiconductor component. The first semiconductor component comprises the first substrate, the first conductive portion, and the first insulating film. The second semiconductor component comprises the second substrate, the second conductive portion, and the second insulating film. The first semiconductor component and the second semiconductor component are joined to each other at the bonding surface. The first conductive portion and the second conductive portion are directly joined at the bonding surface, and the first insulating film and the second insulating film are directly joined at the bonding surface. The manufacturing method according to any one of claims 1 to 17, characterized in that the trench is arranged to overlap the first conductive portion and the second conductive portion.
19. The manufacturing method according to any one of claims 1 to 18, characterized in that the fourth surface is flat.
20. The manufacturing method according to any one of claims 1 to 19, characterized in that the dielectric has a higher hardness than the first substrate.