Resistive random-access memory integrated with stacked vertical transistors

The integration of ReRAMs with stacked VTFETs in semiconductor structures addresses the challenge of high-speed content-addressable memory applications by enhancing drive current efficiency and reducing footprint, suitable for high-speed lookups in computer networks.

JP7876447B2Inactive Publication Date: 2026-06-19INTERNATIONAL BUSINESS MACHINE CORPORATION
View PDF 3 Cites 0 Cited by

Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
INTERNATIONAL BUSINESS MACHINE CORPORATION
Filing Date
2021-02-25
Publication Date
2026-06-19
Estimated Expiration
Not applicable · inactive patent

AI Technical Summary

Technical Problem

Existing semiconductor structures face challenges in integrating resistive random-access memory (ReRAM) with stacked vertical transport field-effect transistors (VTFETs) to achieve high-speed content-addressable memory applications, particularly in reducing the footprint and enhancing drive current efficiency.

Method used

A semiconductor structure is developed with two ReRAMs integrated between stacked VTFETs, featuring faceted epitaxy with pointed tips and a metal layer, allowing for a common drain and separate gate contacts, which enables larger fin lengths and nearly doubles the drive current.

Benefits of technology

The integration of ReRAMs with VTFETs enhances drive current efficiency and reduces the footprint, making it suitable for high-speed lookups in computer networks like routing MAC addresses.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure 0007876447000001
    Figure 0007876447000001
  • Figure 0007876447000002
    Figure 0007876447000002
  • Figure 0007876447000003
    Figure 0007876447000003
Patent Text Reader

Abstract

The method may include forming two vertical transport field effect transistors stacked one on top of the other and separated by a resistive random access memory structure. The two vertical transport field effect transistors may include a source, a channel, and a drain, with a contact layer of the resistive random access memory structure serving as the drain of the two vertical transport field effect transistors. Forming the two vertical transport field effect transistors may further include forming a first source and a second source. The first source is a bottom source and the second source is a top source. The method may include forming a gate conductor layer surrounding the channel. The resistive random access memory structure may include faceted epitaxy defined by pointed tips. The pointed tips of the faceted epitaxy may extend vertically toward each other. The faceted epitaxy may be between the two vertical transport field effect transistors.
Need to check novelty before this filing date? Find Prior Art