Sidewall notch reduction for high aspect ratio 3D NAND etching
Incorporating WF6 in the etching plasma for 3D NAND structures addresses sidewall notching by promoting uniform etching rates, ensuring smooth sidewalls and maintaining etching selectivity.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- LAM RES CORP
- Filing Date
- 2025-01-09
- Publication Date
- 2026-06-19
Smart Images
Figure 0007876647000001 
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Abstract
Description
Technical Field
[0001] Incorporation by Reference As part of this application, a PCT application form is submitted simultaneously with this specification. For all purposes, each application for which this application claims the benefits as set forth in the simultaneously submitted PCT application form or the priority for what is set forth therein is incorporated by reference in its entirety into this application.
[0002] Embodiments of this specification relate to methods and apparatuses for manufacturing semiconductor devices, and more particularly, to methods and apparatuses for etching high aspect ratio features in a dielectric-containing material while reducing sidewall notches without profile trade-offs.
Background Art
[0003] One process frequently used in the manufacturing process of semiconductor devices is to form etched cylinders or other recessed features in a stack of dielectric-containing materials. For example, such a process is widely used in memory applications such as the manufacture of 3D NAND (also called vertical NAND or V-NAND) structures. As the semiconductor industry advances and device dimensions become smaller, it has become increasingly difficult to etch such features uniformly, especially in the case of high aspect ratio cylinders with narrow widths and / or deep depths.
[0004] The background description described in this specification is intended to present the situation of the present disclosure as a whole. Within the scope described in this background section, aspects of the research of the currently named inventors and descriptions that may not be eligible as prior art at the time of filing are not recognized as prior art that explicitly or implicitly opposes the present disclosure.
Summary of the Invention
[0005] Certain embodiments of this specification relate to methods and apparatus for etching features into a laminate containing a dielectric material. Typically, features are etched into a laminate when fabricating a 3D NAND structure on a substrate.
[0006] One embodiment of the embodiments herein provides a method for etching features onto a laminate containing dielectric material when fabricating a 3D NAND structure, the method comprising receiving a substrate on a substrate support in a reaction chamber, the substrate comprising a laminate and a mask layer patterned on top of the laminate, the laminate comprising either (a) alternating layers of silicon oxide and silicon nitride, or (b) alternating layers of silicon oxide and polysilicon, and exposing the substrate to a plasma in the reaction chamber, thereby etching features onto the laminate on the substrate, the plasma comprising WF6, one or more fluorocarbons and / or hydrofluorocarbons, and one or more oxides The WF6 is generated from raw gas, with a flow rate of approximately 0.1 to 10 sccm, and the plasma is capacitively coupled. The substrate is biased at a frequency of approximately 20 kHz to 1.5 MHz and an RF power level of approximately 500 W to 20 kW per substrate. The WF6 and fluorocarbons and / or hydrofluorocarbons form a tungsten-based polymer film on the sidewalls of features during the etching process. This tungsten-based polymer film promotes a uniform etching rate between alternating layers of silicon oxide and silicon nitride, or between alternating layers of silicon oxide and polysilicon, preventing notching of the feature sidewalls during the etching process.
[0007] In certain embodiments, during the etching process, WF6 may dissociate into tungsten-containing and fluorine-containing fragments, the tungsten-containing fragments remaining relatively concentrated near the top of the feature compared to the fluorine-containing fragments, and the fluorine-containing fragments penetrating deeper into the feature compared to the tungsten-containing fragments. In some such embodiments, the tungsten-based polymer film has a non-uniform composition along the sidewalls of the feature, such that the proportion of tungsten in the tungsten-based polymer film near the top of the feature is higher compared to the tungsten-based polymer film near the bottom of the feature.
[0008] In some cases, specific conditions may be used during the processing. For example, the plasma may be generated with an excitation frequency of approximately 20 MHz to 100 MHz and an RF power of approximately 6.3 kW or less. In these and other cases, the oxidizer may be O2, and the flow rate of O2 may be approximately 20 to 150 sccm. In these and other cases, the plasma generating gas may further contain SF6, and the flow rate of SF6 may be approximately 1 to 20 sccm. In these and other cases, the plasma generating gas may further contain Kr, and the flow rate of Kr may be approximately 30 to 120 sccm. In these and other cases, the plasma generating gas may further contain NF3, and the flow rate of NF3 may be approximately 30 sccm or less. In these and other cases, the fluorocarbon or hydrofluorocarbon may contain one or more of C4F8, C3F8, C4F6, and CH2F2, and the total flow rate of fluorocarbon and hydrofluorocarbon may be approximately 30 to 240 sccm. In these and other cases, the substrate support may be maintained at a temperature of approximately 20–80°C during substrate etching. In these and other cases, the pressure in the reaction chamber may be maintained at approximately 10–80 mTorr during substrate etching. In these and other cases, the features may be etched into alternating layers of silicon oxide and silicon nitride. In these and other cases, the WF6 flow rate may be approximately 0.02%–10% of the total plasma generation gas flow rate. In these and other cases, the WF6 flow rate may be approximately 0.02%–1% of the total plasma generation gas flow rate. In these and other cases, the WF6 flow rate may be approximately 0.02%–0.5% of the total plasma generation gas flow rate. In these and other cases, the substrate may be biased at an RF frequency of approximately 300 kHz–600 kHz. For example, the substrate may be biased at an RF frequency of approximately 400 kHz. In these and other cases, the tungsten-based polymer film may be formed with a first thickness on a silicon oxide layer and a second thickness on a silicon nitride or polysilicon layer, where the first and second thicknesses are different.
[0009] Another aspect of the disclosed embodiment provides an apparatus for etching features onto a laminate containing dielectric material when fabricating a 3D NAND structure on a substrate, the apparatus comprising: a reaction chamber having a substrate support in it; a capacitively coupled plasma generator; an inlet for introducing material into the reaction chamber; an outlet for removing material from the reaction chamber; and a controller configured to perform any of the methods described herein.
[0010] For example, in a particular aspect of the disclosed embodiment, an apparatus is provided for etching features onto a laminate containing dielectric material when fabricating a 3D NAND structure on a substrate, the apparatus comprising a reaction chamber having a substrate support, a capacitively coupled plasma generator, an inlet for introducing material into the reaction chamber, an outlet for removing material from the reaction chamber, and a controller that receives a substrate on the substrate support within the reaction chamber, the substrate comprising a laminate and a mask layer patterned on top of the laminate, the laminate comprising either (a) alternating layers of silicon oxide and silicon nitride, or (b) alternating layers of silicon oxide and polysilicon, and generating plasma from a plasma generating gas comprising WF6, one or more fluorocarbons and / or hydrofluorocarbons, and one or more oxidizers The WF6 flow rate is approximately 0.1 to 10 sccm, the substrate is biased at an RF power level of approximately 500 W to 20 kW at a frequency of approximately 20 kHz to 1.5 MHz, the substrate is exposed to the plasma in a reaction chamber, thereby etching features into the laminate on the substrate, the WF6 and fluorocarbon and / or hydrofluorocarbon form a tungsten-based polymer film on the sidewalls of the features during the etching process, the tungsten-based polymer film is configured to promote a uniform etching rate between alternating layers of silicon oxide and silicon nitride, or between alternating layers of silicon oxide and polysilicon, so as notching of the sidewalls of the features during the etching process, and includes a controller.
[0011] These features and other features are described below with reference to the relevant drawings. [Brief explanation of the drawing]
[0012] [Figure 1] This diagram shows a laminated structure in which materials are stacked alternately.
[0013] [Figure 2] This figure shows that after etching the substrate in Figure 1, a considerable number of notches have formed on the sidewall.
[0014] [Figure 3] This figure shows the substrate of Figure 1 after etching according to the embodiment described herein.
[0015] [Figure 4] This is a flowchart illustrating etching methods according to various embodiments of this specification.
[0016] [Figure 5A] This is a diagram of a reaction chamber that may be used to carry out the etching process described herein according to a particular embodiment. [Figure 5B] This is a diagram of a reaction chamber that may be used to carry out the etching process described herein according to a particular embodiment. [Figure 5C] This is a diagram of a reaction chamber that may be used to carry out the etching process described herein according to a particular embodiment. [Modes for carrying out the invention]
[0017] Figures 1 and 2 show a substrate 101 containing a 3D NAND structure partially fabricated by etching high-aspect-ratio features 102 onto a laminate 103 containing alternating layers of a first material 104 and a second material 105. Figure 1 shows the structure before etching, and Figure 2 shows the structure after etching the high-aspect-ratio features 102. In one example, the first material is silicon oxide and the second material is silicon nitride. In another example, the first material is silicon oxide and the second material is polysilicon. The alternating layers form material pairs. For clarity, Figures 1 and 2 show the etched features with only a small number of material pairs. However, it is understood that the etching operation typically etches with many more material pairs than this. In some cases, the number of material pairs may be at least about 20, at least about 30, at least about 40, at least about 60, or at least about 75. The thickness of each layer of the laminate 103 may be approximately 20-50 nm, for example, approximately 30-40 nm. Above the laminate 103 is a mask layer 106. The mask layer 106 is patterned with openings where high aspect ratio features 102 are to be etched. Examples of mask materials include, but are not limited to, amorphous carbon, polysilicon, and other common mask materials. The thickness of the mask layer before etching may be approximately 1-2.5 μm. The depth of the high aspect ratio features 102 etched into the laminate 103 may be approximately 3-10 μm, for example, approximately 5-10 μm. The width / diameter of the high aspect ratio features 102 may be approximately 50-150 nm, for example, approximately 60-110 nm. In some cases, the width of the features may be approximately 100 nm or less. The pitch between adjacent features may be approximately 100-200 nm, for example, approximately 120-170 nm.
[0018] The substrate 101 shown in Figure 1 is prepared in a semiconductor processing apparatus for etching. A suitable apparatus is described below. After the substrate 101 is introduced into the processing apparatus, plasma is generated within the apparatus, and the substrate 101 is exposed to the plasma. After a certain period of time, this exposure to plasma causes etching in the areas of the substrate 101 not protected by the mask layer 106, thereby forming high aspect ratio features 102 as shown in Figure 2. The mask layer 106 is resistant to etching chemicals, but it usually undergoes some erosion during the etching process. Therefore, the mask layer 106 shown in Figure 2 is thinner than the mask layer 106 shown in Figure 1. When the laminate 103 is etched, a passivation layer 107 is formed on the sidewalls of the high aspect ratio features 102. The passivation layer 107 is a mixed layer formed from a combination of the material of the laminate 103 and one or more materials derived from the etching chemicals. Therefore, the composition of the passivation layer 107 varies depending on the composition of the layer formed. For example, a portion of the passivation layer 107 forming the sidewall of a silicon oxide layer typically has a composition containing at least silicon, oxygen, and carbon, while a portion of the passivation layer 107 forming the sidewall of a silicon nitride layer typically has a composition containing at least silicon, nitrogen, and carbon. Similarly, a portion of the passivation layer 107 forming the sidewall of a polysilicon layer typically has a composition containing at least silicon and carbon. In many cases, the passivation layer is a fluorocarbon film, which may be a polymer.
[0019] Figure 2 shows that the passivation layer 107 is deposited relatively uniformly with a consistent shape, but this is not always the case. In some cases, the passivation layer 107 is concentrated near the top of high-aspect-ratio features 102, with little to no passivation layer 107 near the bottom of the feature. In some cases, the passivation layer 107 may form non-uniformly between the first material layer 104 and the second material layer 105, as will be discussed further below.
[0020] As shown in FIG. 2, one problem that can occur when etching a stack of alternating layers is that the etching rate becomes non-uniform between two different layers. In many cases, a silicon oxide material is etched vertically faster than a silicon nitride or polysilicon material. When the vertical etching rate of the oxide material is thus fast, the horizontal etching of the oxide layer becomes relatively less. In contrast, the nitride layer is etched slowly vertically and widely horizontally. As a result of this non-matching etching rate, an over-etched region may be formed on the sidewalls of the silicon nitride material (or polysilicon material), resulting in a sidewall with notches (having notches). In the example of FIG. 2, the layer of the first material 104 (e.g., silicon oxide) has less horizontal etching than the layer of the second material 105 (e.g., silicon nitride or polysilicon). Over time, as a result of this non-uniform etching, a sidewall with notches as shown in FIG. 2 is formed. Such notches are undesirable. Although not shown in FIG. 2, notches can cause significant ion scattering, which can lead to the formation of large curvatures (e.g., when the central part of a feature is over-etched compared to the upper part of the feature). Notches can also have an adverse effect on the dielectric properties of the materials in the stack.
[0021] FIG. 2 shows each layer of the stack 103 as having vertical sidewalls, but this is not necessarily the case. In various implementations, a layer of material over-etched horizontally (e.g., silicon nitride in a stack of oxide and nitride, or polysilicon in a stack of oxide and polysilicon) is most over-etched near the top of the layer, so an undercut is formed just below another material layer. The lower part of the over-etched layer may be less over-etched or not over-etched at all. Therefore, the sidewalls of the over-etched layer may be inclined, curved, or not vertical.
[0022] Although not wishing to be bound by theory or mechanism of action, it is thought that the sidewall notch may be caused by the non-uniform formation of the passivation layer 107 on different materials of the laminate 103. For example, the passivation layer 107 may be formed with a greater thickness on the sidewalls of the layer of the first material 104 (e.g., silicon oxide) compared to the sidewalls of the layer of the second material 105 (e.g., silicon nitride or polysilicon). The thicker the passivation layer 107, the greater the protection against lateral etching. Thus, the layer of the first material is less etched laterally than the layer of the second material with a thin passivation layer 107 thereon.
[0023] Alternatively, or in addition, the sidewall notch may be caused by the non-uniform etching rates of two different materials. In some cases, this may particularly result in the formation of corners at the intersection between the upper layer etched at the first rate and the lower layer etched at a different rate. Such corners are exposed to ion bombardment, which may cause the formation of undercuts, particularly in the upper regions of the over-etched layer.
[0024] The sidewall notch may also be caused by the stress difference between two different types of layers. Regardless of one or more causes, it is clear that the sidewall notch has occurred.
[0025] Specific techniques have been developed to reduce sidewall notches. Often, these techniques involve adjusting the composition of etching chemicals. More specifically, etching chemicals have been adjusted by controlling the ratios of nitrogen-containing, oxygen-containing, carbon-containing, and fluorine-containing species in the plasma used to etch the substrate. However, these techniques typically introduce trade-offs related to the etched feature profile. For example, such techniques can lead to curvature (e.g., over-etching of the central portion of a feature compared to its upper portion), reduced selectivity, increased capping, or decreased etching rate. None of these outcomes are desirable.
[0026] It was found that including tungsten hexafluoride (WF6) in the etching chemical eliminates or substantially reduces sidewall notches without trade-offs related to curvature, selectivity, capping, or etching rate. As a result, the sidewalls of etched features become much smoother. This result is highly desirable.
[0027] While we do not wish to be bound by theory or mechanism of action, it is conceivable that WF6 may make the vertical and / or horizontal etching rates of a first material (e.g., silicon oxide) and a second material (e.g., silicon nitride or polysilicon) more equal. For example, WF6 may decrease the vertical etching rate of the first material (e.g., thereby increasing the horizontal etching rate of the first material) and / or increase the vertical etching rate of the second material (e.g., thereby decreasing the horizontal etching rate of the second material). Alternatively, or in addition to this, WF6 may decrease the rate of passivation layer formation on the sidewalls of the first material (e.g., silicon oxide) and / or increase the rate of passivation layer formation on the sidewalls of the second material (e.g., silicon nitride or polysilicon). Alternatively, or in addition to this, WF6 may counteract differences in stress or other properties of the films between two different types of layers.
[0028] WF6 may result in a more uniform etching rate between the first and second materials due to the excess F* in the plasma. Alternatively, or in addition to this, WF6 may generate a tungsten-based (e.g., possibly tungsten oxide-based) sidewall polymer film, similar to the passivation layer 107 in Figure 2. The tungsten-based sidewall polymer film may be smoothly deposited on the sidewalls of the various layers, thereby preventing notch formation.
[0029] WF6 is widely used for depositing tungsten-based films. However, WF6 is not commonly used as part of etching chemicals. The observation of improved sidewall notching with the addition of WF6 to etching chemicals was unexpected.
[0030] Figure 3 shows the substrate 101 of Figure 1 after an etching process according to one embodiment of this specification. In this case, the etching chemical contains WF6. As a result, the first material 104 and the second material 105 are etched at a uniform rate, and the resulting sidewalls are smooth. The passivation layer 107 is shown to be uniform in shape in Figure 3, however, it is not necessarily so. The passivation layer 107 does not have to be uniform in thickness and / or composition. For example, it may be relatively thick near the top of the feature and relatively thin or absent near the bottom of the feature (or vice versa). In one case, the passivation layer 107 may have a composition that is relatively high in tungsten near the top of the feature and relatively low in tungsten near the bottom of the feature (or vice versa). In these and other cases, the passivation layer 107 may have a composition that is relatively low in carbon near the top of the feature and relatively high in carbon near the bottom of the feature (or vice versa). In certain embodiments, the passivation layer 107 may consist of two passivation layers, one of which is tungsten-based and the other is carbon-based. The two passivation layers may overlap each other (e.g., as separate layers or as mixed layers) and / or be formed at different vertical locations within the feature (e.g., the tungsten-based passivation layer may be closer to the top or bottom of the feature compared to the carbon-based passivation layer). As previously mentioned with respect to Figure 2, the composition of the passivation layer 107 may also depend on the composition of the layers formed in contact with it.
[0031] In one particular embodiment, the tungsten within the passivation layer may be concentrated towards the top of the feature compared to the bottom of the feature. In other words, much of the tungsten from WF6 remains near the top of the feature. This may, in some cases, help to retain the mask layer. The concentration of tungsten near the top of the feature may be a result of a high adhesion coefficient for tungsten and tungsten-containing species. When such highly adhesive species come into contact with the sidewall, they are very likely to "adhere" rather than bounce off, penetrating deep into the feature. The fluorine from WF6 has a much lower adhesion coefficient and can penetrate even more easily into the bottom of the feature, in which case it contributes to an increased etching rate. Both of these factors (e.g., tungsten-containing species remaining near the top of the feature and fluorine-containing species moving to the bottom of the feature to further etch the laminate) result in the etching selectivity remaining as desired.
[0032] Figure 4 is a flowchart illustrating a method for etching features of a laminate containing a dielectric material according to various embodiments of the present invention. The method begins with operation 401, in which a substrate is prepared in a reaction chamber. The substrate may be, for example, the substrate described with respect to Figure 1. Next, in operation 403, plasma is generated from a plasma generating gas. The plasma generating gas contains at least WF6. The plasma generating gas also contains etching chemicals suitable for etching the material of the laminate. In various examples, the etching chemicals include, for example, one or more oxygen-containing species, one or more carbon-containing species, and one or more fluorine-containing species. Examples of materials commonly used as etching chemicals include, but are not limited to, fluorocarbons and hydrofluorocarbons such as C3F8, C4F8, C4F6, CH2F2, CH3F, CHF3, C5F8, C6F6, oxidizers such as O2, O3, CO, CO2, COS, and NF3. Inert species may also be provided to the plasma generating gas.
[0033] The flow rate of WF6 in the plasma generating gas may be at least about 0.1 sccm, or at least about 0.2 sccm, or at least about 0.5 sccm, or at least about 1 sccm. In these and other cases, the flow rate of WF6 may be about 20 sccm or less, for example, about 10 sccm or less, or about 5 sccm or less, or about 2 sccm or less, or about 1 sccm or less, or about 0.5 sccm or less. In certain embodiments, the flow rate of WF6 may be about 0.1 to 10 sccm. The total flow rate of the plasma generating gas may be at least about 1 sccm, at least about 10 sccm, at least about 50 sccm, or at least about 80 sccm. In these and other cases, the total flow rate of the plasma generating gas may be about 600 sccm or less, or about 500 sccm or less, or about 300 sccm or less, or about 200 sccm or less, or about 100 sccm or less, or about 50 sccm or less. In some cases, one or more fluorocarbon sources may be mixed (before or after being supplied to the reaction chamber) to supply, for example, a desired ratio of carbon and fluorine. In some examples, the flow rate of C4F8 and / or C3F8 and / or C4F6 may be about 20 to 120 sccm. In these and other examples, the flow rate of CH2F2 may be about 10 to 120 sccm. In various embodiments, the total flow rate of fluorocarbons and hydrofluorocarbons may be about 30 to 240 sccm. In these and other examples, the flow rate of NF3 may be about 0 to 30 sccm. In these and other examples, the flow rate of O2 may be about 20 to 150 sccm. In these and other examples, the flow rate of SF6 may be about 1 to 20 sccm. In these and other examples, the flow rate of Kr may be about 30 to 120 sccm. In various cases, WF6 may account for at least approximately 0.02%, at least approximately 0.05%, at least approximately 0.1%, at least approximately 0.5%, at least approximately 1%, or at least approximately 3% of the volumetric flow rate of the plasma generating gas. In these and other cases, WF6 may account for approximately 10% or less, at least approximately 5%, at least approximately 1%, or at least approximately 0.5% of the volumetric flow rate of the plasma generating gas.
[0034] In various cases, the following conditions may be used to generate plasma. The plasma may be capacitively coupled. The plasma may be generated at an excitation frequency of approximately 13 to 169 MHz, for example, approximately 20 to 100 MHz (for example, 60 MHz in certain cases), with a power level of approximately 0 watts to 6.3 kW per 300 mm substrate. In various cases, the power level used to generate the plasma may be particularly high, for example, approximately 5 kW or more, or approximately 6 kW or more, per 300 mm substrate. For example, a relatively high bias may be applied to the substrate to promote a high-speed etching rate in the vertical direction. The bias may be applied to the substrate at a frequency of approximately 20 kHz to 1.5 MHz, or approximately 200 kHz to 1.5 MHz, or approximately 300 kHz to 600 kHz (for example, approximately 400 kHz in certain cases), with a power level of approximately 500 W to 20 kW per 300 mm substrate, or approximately 2 to 10 kW per 300 mm substrate. In certain embodiments, the substrate is biased at 400 kHz with a power level of approximately 500 W to 20 kW. The pressure inside the reaction chamber may be at least approximately 10 mTorr or at least approximately 30 mTorr. In these and other cases, the pressure inside the reaction chamber may be less than approximately 500 mTorr, e.g., less than 100 mTorr, or less than approximately 80 mTorr, or less than approximately 30 mTorr. In some cases, the pressure may remain relatively low during etching (e.g., 10 to 80 mTorr), but may rise to a higher pressure (e.g., 100 to 500 mTorr, or 300 to 500 mTorr, or 400 to 500 mTorr) during cleaning operations to clean the inner walls of the reaction chamber. The substrate support beneath the substrate to be prepared may be maintained at a temperature of approximately -80°C to 130°C (e.g., by heating and / or cooling). In some cases, the substrate support is maintained at a temperature of at least approximately -80°C, or at least approximately -50°C, or at least approximately -20°C, or at least approximately 0°C, or at least approximately 20°C, or at least approximately 50°C, or at least approximately 70°C.In these and other cases, the substrate support may be maintained at a temperature of approximately 130°C or below, or approximately 120°C or below, or approximately 100°C or below, or approximately 80°C or below, or approximately 50°C or below, or approximately 20°C or below, or approximately 0°C or below, or approximately -20°C or below, or approximately -50°C or below. In specific cases, the substrate support may be maintained at a temperature of approximately 20 to 80°C. These temperatures may be considered to be the temperature of the substrate support that is controlled while the substrate is exposed to the plasma.
[0035] After a certain period of time, features begin to form on the laminate. As shown in Figure 3, after the features reach the final etching depth, the substrate is removed from the reaction chamber in operation 405. Compared to conventional methods, the method described in Figure 4 makes it possible to form deep features with relatively few (or no) notches. By including WF6 in the plasma generation gas, when supplied at the appropriate flow rate and under appropriate plasma conditions, sidewall notches are substantially reduced or eliminated. Advantageously, this reduction in sidewall notches does not result in any trade-offs with respect to feature curvature, selectivity, capping, or etching rate.
[0036] Device The methods described herein may be carried out in any suitable apparatus. A suitable apparatus includes hardware for implementing processing operations and a system controller, including instructions for controlling the processing operations according to this embodiment. For example, in some embodiments, the hardware may have one or more processing stations included in the processing tool.
[0037] Figures 5A to 5C show embodiments of a capacitively coupled confined RF plasma reactor 500 having an adjustable gap that may be used to carry out the etching operation described herein. As shown, the vacuum chamber 502 has a chamber housing 504 surrounding an internal space that houses the lower electrode 506. At the top of the chamber 502, the upper electrode 508 is perpendicularly separated from the lower electrode 506. The planar surfaces of the upper and lower electrodes 508, 506 are substantially parallel and perpendicular to the vertical direction between the electrodes. Preferably, the upper and lower electrodes 508, 506 are circular and coaxial with respect to the vertical axis. The lower surface of the upper electrode 508 faces the upper surface of the lower electrode 506. The separated opposing electrode surfaces define an adjustable gap 510 between the two surfaces. During operation, the lower electrode 506 is supplied with RF power by an RF power supply (matched) 520. RF power is supplied to the lower electrode 506 via an RF supply tube 522, an RF strap 524, and an RF power member 526. To achieve a uniform RF field by the lower electrode 506, a grounding shield 536 may surround the RF power member 526. As described in the jointly owned U.S. Patent Application No. 7,732,728 (the entirety of which is incorporated herein by reference), a wafer is inserted through a wafer port 582 and supported in a gap 510 above the lower electrode 506 for processing, and a processing gas is supplied to the gap 510 and excited by RF power to become a plasma state. The upper electrode 508 can be powered or grounded.
[0038] In the embodiments shown in Figures 5A to 5C, the lower electrode 506 is supported on the lower electrode support plate 516. An insulating ring 514 interposed between the lower electrode 506 and the lower electrode support plate 516 insulates the lower electrode 506 from the support plate 516.
[0039] The RF bias housing 530 supports the lower electrode 506 on the RF bias housing bowl 532. The bowl 532 is coupled to the conduit support plate 538 via an opening in the chamber wall plate 518 by an arm 534 of the RF bias housing 530. In a preferred embodiment, the RF bias housing bowl 532 and the RF bias housing arm 534 are formed integrally as a single component, but the arm 534 and the bowl 532 can also be two separate components that are bolted or joined together.
[0040] The RF bias housing arm 534 has one or more hollow passages for passing RF power and equipment (such as gaseous coolant, liquid coolant, RF energy, cables for lift pin control, and electrically monitored and activated signals) from the outside of the vacuum chamber 502 to the inside of the vacuum chamber 502 in the space behind the lower electrode 506. The RF supply pipe 522 is isolated from the RF bias housing arm 534, which serves as the return path for RF power back to the RF power supply 520. Equipment conduits 540 serve as passages for equipment elements. Further details of the equipment elements are described in U.S. Patents 5,948,704 and 7,732,728 and are not presented herein for the sake of brevity. The gap 510 is preferably surrounded by a containment ring assembly or shroud (not shown), details of which can be found in the jointly owned U.S. Patent Publication No. 7,740,736, which is incorporated herein by reference. The inside of the vacuum chamber 502 is maintained at a low pressure by connecting to a vacuum pump through the vacuum inlet 580.
[0041] The conduit support plate 538 is mounted on the actuation mechanism 542. Details of the actuation mechanism are described in U.S. Patent No. 7,732,728, jointly owned, which is incorporated herein by reference. The actuation mechanism 542, such as a servo mechanical motor or a stepping motor, is mounted on the vertical linear bearing 544 by a screw gear 546, such as a ball screw and a motor that rotates the ball screw. In the operation to adjust the size of the gap 510, the actuation mechanism 542 moves along the vertical linear bearing 544. Figure 5A shows the configuration when the actuation mechanism 542 is in a high position on the linear bearing 544, thereby creating a small gap 510a. Figure 5B shows the configuration when the actuation mechanism 542 is in an intermediate position on the linear bearing 544. As shown, the lower electrode 506, RF bias housing 530, conduit support plate 538, and RF power supply 520 are all moved downward relative to the chamber housing 504 and upper electrode 508, resulting in an intermediate-sized gap 510b.
[0042] Figure 5C shows the large gap 510c when the operating mechanism 542 is in a low position on the linear bearing. Preferably, the upper and lower electrodes 508, 506 remain coaxial while adjusting the gap, and the opposing surfaces of the upper and lower electrodes remain parallel throughout the gap.
[0043] In this embodiment, the gap 510 between the lower electrode 506 and the information electrode 508 in the CCP chamber 502 can be adjusted during a multi-step processing recipe (such as BARC, HARC, and STRIP) to maintain uniform etching across the entire surface of a large-diameter substrate, such as a 300 mm wafer or a flat panel display. In particular, the chamber is mechanically arranged to allow the linear motion necessary to achieve an adjustable gap between the lower electrode 506 and the upper electrode 508.
[0044] Figure 5A shows a laterally flexible bellows 550, which is sealed at its proximal end to a conduit support plate 538 and at its distal end to a stepped flange 528 of a chamber wall plate 518. The inner diameter of the stepped flange defines an opening 512 in the chamber wall plate 518 through which the RF bias housing arm 534 passes. The distal end of the bellows 550 is clamped by a clamping ring 552.
[0045] The laterally flexed bellows 550 achieves vacuum sealing and allows the RF bias housing 530, conduit support plate 538, and operating mechanism 542 to move vertically. The RF bias housing 530, conduit support plate 538, and operating mechanism 542 can be referred to as the cantilever assembly. Preferably, the RF power supply 520 moves together with the cantilever assembly and can be mounted on the conduit support plate 538. Figure 5B shows the bellows 550 in the neutral position when the cantilever assembly is in the intermediate position. Figure 5C shows the bellows 550 laterally flexed when the cantilever assembly is in the low position.
[0046] The labyrinth seal 548 acts as a particle barrier between the bellows 550 and the interior of the plasma processing chamber housing 504. The fixed shield 556 is mounted immovably to the inside of the inner wall of the chamber housing 504 by the chamber wall plate 518, creating a labyrinth groove 560 (slot), within which the movable shield plate 558 moves vertically to accommodate the vertical movement of the cantilever assembly. The outer portion of the movable shield plate 558 remains within the slot at any vertical position of the lower electrode 506.
[0047] In the illustrated embodiment, the labyrinth seal 548 has a fixed shield 556 mounted on the inner surface of the chamber wall plate 518 around an opening 512 in the chamber wall plate 518 defining the labyrinth groove 560. The movable shield plate 558 is mounted on the RF bias housing arm 534, from which the arm 534 extends radially where it passes through the opening 512 in the chamber wall plate 518. The movable shield plate 558 extends into the labyrinth groove 560 but is separated from the fixed shield 556 by a first gap and from the inner surface of the chamber wall plate 518 by a second gap, allowing the cantilever assembly to move vertically. The labyrinth seal 548 prevents particles detached from the bellows 550 from moving into the interior 505 of the vacuum chamber and prevents radicals from the processing gas plasma from moving to the bellows 550. Radicals may form deposits on the bellows, which are later detached.
[0048] Figure 5A shows the movable shield plate 558 in the high position of the labyrinth groove 560 on the RF bias housing arm 534 when the cantilever assembly is in the high position (small gap 510a). Figure 5C shows the movable shield plate 558 in the low position of the labyrinth groove 560 on the RF bias housing arm 534 when the cantilever assembly is in the low position (large gap 510c). Figure 5B shows the movable shield plate 558 in the neutral or intermediate position within the labyrinth groove 560 when the cantilever assembly is in the intermediate position (mid-level gap 510b). The labyrinth seal 548 is shown as symmetrical with respect to the RF bias housing arm 534, but in other embodiments, the labyrinth seal 548 may be asymmetrical with respect to the RF bias arm 534.
[0049] Figure 6 depicts a semiconductor process cluster architecture in which various modules interface with a vacuum transport module 638 (VTM). The configuration of transport modules for “transporting” substrates among multiple storage facilities and processing modules is sometimes called a “cluster tool architecture” system. An airlock 630, also known as a load lock or transport module, is shown within the VTM 638, which has four processing modules 620a–620d, and the processing modules may be individually optimized to perform various manufacturing processes. For example, processing modules 620a–620d may be implemented to perform substrate etching, deposition, ion implantation, substrate cleaning, sputtering, and / or other semiconductor processes, as well as laser measurement and other methods for detecting and identifying defects. One or more processing modules (any of 620a–620d) may be implemented as disclosed herein, i.e., to etch recessed features in the substrate. The airlock 630 and processing modules 620a–620d are sometimes referred to as a “station”. Each station has a small face 636 that interfaces the station to the VTM638. Inside the small face, sensors 1-18 are used to detect the passage of the substrate 626 as it moves between each station.
[0050] Robot 622 transports the substrates between stations. In one configuration, the robot may have one arm, and in another configuration, the robot may have two arms, in which case each arm has an end effector 624 for picking up and transporting the substrates. A front-end robot 632 in the air transport module (ATM) 640 may be used to transport the substrates from the cassette in the load port module (LPM) 642 or from the FOUP (Front Opening Unified Pod) 634 to the airlock 630. A module center 628 inside the processing modules 620a-620d may be one location for positioning the substrates. An aligner 644 in the ATM 640 may be used to align the substrates.
[0051] In one exemplary processing method, the substrate is placed in one of the FOUPs 634 within the LPM 642. A front-end robot 632 transports the substrate from the FOUP 634 to the aligner 644, thereby enabling the substrate 626 to be correctly centered, deposited on top of, or processed before etching. After alignment, the substrate is moved by the front-end robot 632 to the airlock 630. The airlock module has the function of adapting the environment between the ATM and VTM, so that the substrate can move between the two pressure environments without damage. From the airlock module 630, the substrate is moved by robot 622 through the VTM 638 to one of the processing modules 620a-620d, for example, processing module 620a. To achieve this movement of the substrate, robot 622 uses end effectors 624 on each arm. In processing module 620a, the substrate undergoes etching as described. Next, robot 622 moves the substrate from processing module 620a to the next desired position.
[0052] It should be noted that the computer controlling the movement of the circuit board can be located locally within the cluster architecture, outside the cluster architecture at the manufacturing site, or remotely connected to the cluster architecture via a network.
[0053] In some implementations, the controller is part of the system, and the system may be part of the examples above. Such a system may comprise a semiconductor processing apparatus including one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (such as wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronic equipment that controls the operation of the system before, during, and after processing semiconductor wafers or substrates. The electronic equipment may be called a “controller” and may control various components or sub-parts of one or more systems. Depending on the processing requirements and / or type of the system, the controller may be programmed to control any of the processes disclosed herein, such as supplying processing gases, setting temperature (e.g., heating and / or cooling), setting pressure, setting vacuum, setting power, setting radio frequency (RF) generating tools, setting RF matching circuits, setting frequency, setting flow rate, setting fluid supply, setting potential and operation, wafer transfer into and out of tools and other transfer tools, and / or load locks connected to or bounding a particular system.
[0054] Generally, a controller may be defined as an electronic device having various integrated circuits, logic circuits, memory, and / or software that receives and issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, and so on. An integrated circuit may comprise a firmware-type chip that stores program instructions, a digital signal processor (DSP), a chip defined as an application-specific integrated circuit (ASIC), and / or one or more microprocessors, or a microcontroller that executes program instructions (e.g., software). Program instructions may be instructions transmitted to the controller in the form of various separate settings (or program files) that define operating parameters that perform specific operations on or for a semiconductor wafer, or for a system. In some embodiments, the operating parameters may be part of a recipe defined by a processing engineer to achieve one or more processing steps in the process of manufacturing one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.
[0055] In some embodiments, the controller may be part of a computer that is integrated with the system, networked with the system, or a combination of both, or connected to this computer. For example, the controller may be in the “cloud” or be part of a fab host computer system that enables remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of a manufacturing operation, investigate the history of past manufacturing operations, investigate trends or performance metrics from multiple manufacturing operations, change parameters for the current process, set processing steps to follow the current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide processing recipes to the system over a network, which may include a local network or the internet. The remote computer may include a user boundary that allows input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, the controller receives instructions in data form that specify parameters for each processing step performed during one or more operations. It should be understood that the parameters may be specific to the type of processing being performed and the type of tool that the controller is configured to interface with or control. Therefore, as mentioned above, the controllers may be distributed by having one or more separate controllers that are networked together and function toward a common purpose, such as processing and control, as described herein. An example of a distributed controller for this purpose would be one or more integrated circuits located on a chamber that communicates with one or more integrated circuits located remotely (for example, at the platform level or as part of a remote computer), and which work together to control processing on this chamber.
[0056] Non-limitingly, example systems may include plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems that may be used in connection with or for the manufacture and / or production of semiconductor wafers.
[0057] As described above, depending on one or more processing steps performed by the tool, the controller may communicate with one or more tools used for transporting materials to and from tool locations and / or loading ports within the semiconductor manufacturing plant, other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the plant, a main computer, another controller, or wafer containers.
[0058] Additional Embodiments The various hardware and method embodiments described above may be used in conjunction with lithography patterning tools or processes for the fabrication or manufacture of, for example, semiconductor devices, displays, LEDs, photovoltaic panels, etc. Typically, such tools / processes are used or performed together in a common manufacturing facility, though not necessarily.
[0059] Film lithography patterning typically involves some or all of the following steps, each of which can be performed with a number of possible tools: (1) Applying a photoresist to a workpiece, for example, a substrate on which a silicon nitride film is formed, using a spin-on or spray-on tool. (2) Curing the photoresist using a hot plate, furnace, or other suitable curing tool. (3) Exposing the photoresist to visible light, UV light, or X-ray light using a tool such as a wafer stepper. (4) Developing the resist to selectively remove it, thereby patterning the resist using a tool such as a wet bench or spray developer. (5) Transferring the resist pattern to the underlying film or workpiece using a dry etching or plasma-assisted etching tool. And (6) Removing the resist using a tool such as an RF or microwave plasma resist stripper. In some embodiments, an ashable hard mask layer (such as an amorphous carbon layer) and another suitable hard mask (such as an anti-reflective layer) may be deposited before applying the photoresist.
[0060] The configurations and / or techniques described herein are illustrative in nature and can be modified in many ways; therefore, these particular embodiments or examples should not be interpreted as limiting. The specific procedures or methods described herein may represent one or more of any number of processing strategies. Thus, the various actions illustrated may be performed in the illustrated order, in other orders, in parallel, or, in some cases, omitted. Similarly, the order of the processing described above may be changed. Certain references are incorporated herein by reference. It should be understood that any denials or disclaimers in such references do not necessarily apply to the embodiments described herein. Similarly, features described as necessary in such references may be omitted in the embodiments herein.
[0061] In this specification, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially manufactured integrated circuit” are interchangeable. Those skilled in the art will understand that the term “partially manufactured integrated circuit” may refer to a silicon wafer at any stage of the many integrated circuit manufacturing processes. The diameters of wafers or substrates used in the semiconductor device industry are typically 200 mm, 300 mm, or 450 mm. The above detailed description assumes that the embodiments are realized on a wafer; however, the embodiments are not limited thereto. The shape, size, and material of the workpiece may vary. In addition to semiconductor wafers, other workpieces that may utilize the disclosed embodiments include a variety of articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, and micromechanical devices. Unless otherwise specified for a particular parameter, the terms “about” and “approximately” as used herein are intended to mean ±10% of the relevant value.
[0062] The above description includes many specific details in order to fully understand the embodiments. The disclosed embodiments may be carried out without some or all of these specific details. In other cases, known processing operations are not described in detail so as not to unnecessarily obscure the disclosed embodiments. The disclosed embodiments are described in conjunction with specific embodiments, but it should be understood that there is no intention to limit the disclosed embodiments. The subject matter of this disclosure includes all novel and non-obvious combinations and subcombinations of the various processes, systems and configurations disclosed herein, as well as other features, functions, operations, and / or properties, and any and all equivalents thereof. [Application Example 1] A method for etching features onto a laminate containing dielectric material when fabricating a 3D NAND structure, A substrate is received onto a substrate support in a reaction chamber, the substrate comprising the laminate and a mask layer patterned on top of the laminate, the laminate comprising either (a) alternating layers of silicon oxide and silicon nitride, or (b) alternating layers of silicon oxide and polysilicon, The process involves exposing the substrate to plasma within the reaction chamber, thereby etching the features onto the laminate on the substrate, The aforementioned plasma is WF 6 , generated from a plasma generating gas containing one or more fluorocarbons and / or hydrofluorocarbons, and one or more oxidizers, WF 6 The flow rate is approximately 0.1 to 10 sccm. The aforementioned plasma is a capacitively coupled plasma, The aforementioned substrate is biased at a frequency of approximately 20kHz to 1.5MHz and an RF power level of approximately 500W to 20kW per substrate. The aforementioned WF 6 The fluorocarbon and / or hydrofluorocarbon form a tungsten-based polymer film on the sidewalls of the feature during the etching process, and the tungsten-based polymer film promotes a uniform etching rate between the alternating layers of silicon oxide and silicon nitride, or between the alternating layers of silicon oxide and polysilicon, so that the sidewalls of the feature are notched during the etching process. method. [Application Example 2] The method according to Application Example 1, wherein in the etching process, the WF 6 A method wherein the material dissociates into tungsten-containing fragments and fluorine-containing fragments, the tungsten-containing fragments remaining relatively concentrated near the top of the feature compared to the fluorine-containing fragments, and the fluorine-containing fragments penetrating deeper into the feature compared to the tungsten-containing fragments. [Application Example 3] A method according to Application Example 2, wherein the tungsten-based polymer film has a non-uniform composition along the sidewall of the feature such that the proportion of tungsten in the tungsten-based polymer film near the top of the feature is greater than that of the tungsten-based polymer film near the bottom of the feature. [Application Example 4] A method relating to Application Example 1, wherein the plasma is generated with an excitation frequency of about 20 MHz to 100 MHz and an RF power of about 6.3 kW or less. [Application Example 5] The method according to Application Example 4, wherein the oxidizing agent is O 2 The above O 2 The flow rate is approximately 20-150 sccm. [Application Example 6] The method according to Application Example 5, wherein the plasma generating gas is further SF 6 Including the SF 6 The flow rate is approximately 1-20 sccm. [Application Example 7] A method according to Application Example 6, wherein the plasma generating gas further comprises Kr, and the flow rate of the Kr is about 30 to 120 sccm. [Application Example 8] The method described in Application Example 7, wherein the plasma generating gas is further NF 3 Including the NF 3 The flow rate is approximately 30 sccm or less. [Example 9] The method described in Example 8, wherein the fluorocarbon or hydrofluorocarbon is C 4 F 8 、C 3 F 8 、C 4 F 6 , and CH 2 F 2 A method comprising one or more of the above, wherein the total flow rate of the fluorocarbon and hydrofluorocarbon is approximately 30 to 240 sccm. [Application Example 10] A method according to Application Example 9, wherein the substrate support is maintained at a temperature of about 20 to 80°C while the substrate is being etched. [Application Example 11] A method according to Application Example 10, wherein the pressure in the reaction chamber is maintained at approximately 10 to 80 mTorr while etching the substrate. [Example 12] A method relating to Example 11, wherein the feature is etched into the alternating layers of silicon oxide and silicon nitride. [Application Example 13] The method described in Application Example 11, and WF 6 The flow rate is approximately 0.02% to 10% of the total flow rate of the plasma generating gas, in this method. [Application Example 14] The method described in Application Example 13, WF 6 The flow rate is approximately 0.02% to 1% of the total flow rate of the plasma generating gas, in this method. [Example 15] The method described in Example 14, WF 6 The flow rate is approximately 0.02% to 0.5% of the total flow rate of the plasma generating gas, in this method. [Application Example 16] A method according to Application Example 1, wherein the substrate is biased with an RF frequency of approximately 300 kHz to 600 kHz. [Application Example 17] A method relating to Application Example 16, wherein the substrate is biased at an RF frequency of approximately 400 kHz. [Example 18] A method according to any one of Examples 1 to 17, wherein the tungsten-based polymer film is formed on the silicon oxide layer with a first thickness and on the silicon nitride or polysilicon layer with a second thickness different from the first and second thicknesses. [Application Example 19] An apparatus for etching features onto a laminate containing dielectric material when fabricating a 3D NAND structure on a substrate, Inside is a reaction chamber having a substrate support, A capacitively coupled plasma generator, An inlet for introducing the material into the reaction chamber, An outlet for removing material from the reaction chamber, A controller is provided, and the controller is The substrate is received onto the substrate support within the reaction chamber, and the substrate comprises the laminate and a mask layer patterned on top of the laminate, the laminate comprises either a) alternating layers of silicon oxide and silicon nitride, or (b) alternating layers of silicon oxide and polysilicon. WF 6 A plasma is generated from a plasma generating gas containing one or more fluorocarbons and / or hydrofluorocarbons, and one or more oxidizers, and WF 6 The flow rate is approximately 0.1 to 10 sccm. The aforementioned substrate is biased at an RF power level of approximately 500W to 20kW at a frequency of approximately 20kHz to 1.5MHz. The substrate is exposed to the plasma within the reaction chamber, thereby etching the features onto the laminate on the substrate. The aforementioned WF 6 The fluorocarbon and / or hydrofluorocarbon form a tungsten-based polymer film on the sidewalls of the feature during the etching process, and the tungsten-based polymer film promotes a uniform etching rate between the alternating layers of silicon oxide and silicon nitride, or between the alternating layers of silicon oxide and polysilicon, so as to prevent the sidewalls of the feature from being notched during the etching process. A device configured in such a way.
Claims
1. A method for etching features onto a laminate containing dielectric material when fabricating a 3D NAND structure, A substrate is received on a substrate support within a reaction chamber, the substrate comprising the laminate and a mask layer patterned on top of the laminate, the laminate comprising either (a) alternating layers of silicon oxide and silicon nitride, or (b) alternating layers of silicon oxide and polysilicon. The process involves exposing the substrate to plasma within the reaction chamber, thereby etching the features onto the laminate on the substrate, The aforementioned plasma is WF ６ , generated from a plasma generating gas containing one or more fluorocarbons and / or hydrofluorocarbons, and one or more oxidizers, WF ６ The flow rate is 0.1 sccm to 10 sccm, and the plasma generating gas is SF ６ Furthermore, SF ６ The flow rate is 1 sccm to 20 sccm. The aforementioned plasma is a capacitively coupled plasma, The aforementioned substrate is biased at a frequency of 20 kHz to 1.5 MHz and an RF power level of 500 W to 20 kW per substrate. The aforementioned WF ６ A method wherein the fluorocarbon and / or hydrofluorocarbon form a tungsten-based polymer film on the sidewalls of the feature during the etching process.
2. The method according to claim 1, A method wherein the tungsten-based polymer film promotes a uniform etching rate between the alternating layers of silicon oxide and silicon nitride, or between the alternating layers of silicon oxide and polysilicon, so that the sidewalls of the features are notched during the etching process.
3. The method according to claim 1, wherein in the etching process, the WF ６ A method wherein the material dissociates into tungsten-containing fragments and fluorine-containing fragments, the tungsten-containing fragments remaining relatively concentrated near the top of the feature compared to the fluorine-containing fragments, and the fluorine-containing fragments penetrating deeper into the feature compared to the tungsten-containing fragments.
4. A method according to claim 3, wherein the tungsten-based polymer film is non-uniform in composition along the sidewall of the feature such that the proportion of tungsten in the tungsten-based polymer film near the top of the feature is greater than that of the tungsten-based polymer film near the bottom of the feature.
5. A method according to claim 1, wherein the plasma is generated with an excitation frequency of 20 MHz to 100 MHz and an RF power of 6.3 kW or less.
6. The method according to claim 5, wherein the oxidizer is O ２ And the above O ２ The flow rate is 20 sccm to 150 sccm.
7. The method according to claim 1, wherein the plasma generating gas further comprises NF ３ and the flow rate of the NF ３ is 30 sccm or less.
8. The method according to claim 7, wherein the fluorocarbon or hydrofluorocarbon is C ４ F ８ , C ３ F ８ , C ４ F ６ , and CH ２ F ２ A method comprising one or more of the above, wherein the total flow rate of the fluorocarbon and hydrofluorocarbon is 30 sccm to 240 sccm.
9. A method according to claim 1, wherein the substrate support is maintained at a temperature of 20°C to 80°C while the substrate is being etched.
10. A method according to claim 1, wherein the pressure in the reaction chamber is maintained between 10 mTorr and 80 mTorr while etching the substrate.
11. A method according to claim 1, wherein the feature is etched into the alternating layers of silicon oxide and silicon nitride.
12. The method according to claim 1, WF ６ The method wherein the flow rate is 0.02% to 10% of the total flow rate of the plasma generating gas.
13. A method according to claim 12, wherein WF ６ The flow rate is 0.02% to 1% of the total flow rate of the plasma generating gas, in a method.
14. A method according to claim 13, WF ６ The flow rate is 0.02% to 0.5% of the total flow rate of the plasma generating gas, in a method.
15. A method according to claim 1, wherein the substrate is biased with an RF frequency of 300 kHz to 600 kHz.
16. A method according to claim 15, wherein the substrate is biased at an RF frequency of 400 kHz.
17. A method according to any one of claims 1 to 16, wherein the tungsten-based polymer film is formed on the alternating layers of silicon oxide with a first thickness and on the alternating layers of silicon nitride or polysilicon with a second thickness different from the first thickness and the second thickness.
18. An apparatus for etching features onto a laminate containing dielectric material when fabricating a 3D NAND structure on a substrate, Inside is a reaction chamber having a substrate support, A capacitively coupled plasma generator, An inlet for introducing the material into the reaction chamber, An outlet for removing material from the reaction chamber, A controller is provided, and the controller is The substrate is received onto the substrate support within the reaction chamber, and the substrate comprises the laminate and a mask layer patterned on top of the laminate, the laminate comprises either (a) alternating layers of silicon oxide and silicon nitride, or (b) alternating layers of silicon oxide and polysilicon. WF ６ A plasma is generated from a plasma generating gas containing one or more fluorocarbons and / or hydrofluorocarbons, and one or more oxidizers, and WF ６ The flow rate is 0.1 to 10 sccm, and the plasma generating gas is SF ６ Furthermore, SF ６ The flow rate is 1 sccm to 20 sccm. The aforementioned substrate is biased at an RF power level of 500W to 20kW at a frequency of 20kHz to 1.5MHz. The substrate is exposed to the plasma within the reaction chamber, thereby etching the features onto the laminate on the substrate. The aforementioned WF ６ The fluorocarbon and / or hydrofluorocarbon form a tungsten-based polymer film on the sidewalls of the feature during the etching process, and the tungsten-based polymer film promotes a uniform etching rate between the alternating layers of silicon oxide and silicon nitride, or between the alternating layers of silicon oxide and polysilicon, so as to prevent the sidewalls of the feature from being notched during the etching process. A device configured in such a way.