Semiconductor equipment

Abstract

Provided is a semiconductor device having an excellent heat dissipation effect for a crystalline oxide semiconductor layer. This semiconductor device includes: a gate electrode of which at least a part is embedded in a crystalline oxide semiconductor layer; and a heat dissipation part having a higher thermal conductivity than the crystalline oxide semiconductor layer, wherein at least a portion of the heat dissipation part is disposed in the vicinity of an embedded end portion of the gate electrode in the crystalline oxide semiconductor layer and / or at a position deeper than the embedded end portion, and thus the heat dissipation effect for the crystalline oxide semiconductor layer is made more efficient and more excellent.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device comprising a crystalline oxide semiconductor layer. [Background technology]

[0002] Semiconductor devices using gallium oxide (Ga2O3), which has a large bandgap, are attracting attention as a next-generation crystalline oxide semiconductor material that can achieve high voltage resistance, low loss, and high heat resistance. Semiconductor devices containing crystalline oxide semiconductors are expected to be applied as switching elements in power semiconductor devices such as inverters. Furthermore, due to their wide bandgap, they are also expected to be applied as light-emitting and receiving devices such as LEDs and sensors.

[0003] It is known that gallium oxide has five crystal structures: α, β, γ, δ, and ε (Non-Patent Document 1). Among these, gallium oxide with a corundum structure has a high band gap and is attracting attention as a semiconductor material for next-generation power devices. However, since the most stable phase of gallium oxide is the β-gallia structure, there have been challenges in depositing crystalline films containing gallium oxide with the metastable corundum structure without using special deposition methods, and the thermal behavior of such crystalline films in semiconductor devices has also been unknown. In response to this, several studies are currently being conducted on crystalline oxide semiconductor films containing gallium oxide and / or its mixed crystals, including the deposition of crystalline semiconductors with a corundum structure. For example, Patent Document 1 describes that the band gap of gallium oxide can be controlled by mixing it with indium or aluminum, either individually or in combination, and it is described as an InAlGaO-based semiconductor. Here, an InAlGaO-based semiconductor is In X Al Y Ga Z It exhibits the O3 property (0≦X≦2, 0≦Y≦2, 0≦Z≦2, X+Y+Z=1.5~2.5) and can be viewed as part of the same material system containing gallium oxide.

[0004] Incidentally, conventionally, the heat generated when applying electric current to a semiconductor device has been a problem that affects the characteristics and lifespan of the semiconductor device, and for example, heat dissipation structures using heat sinks have been considered. Patent document 2 describes a semiconductor device having a pair of metal plates connected to a semiconductor element, in which the metal plates serve as both electrodes and heat sinks. However, even with such a heat dissipation structure, the heat dissipation properties of gallium oxide were not entirely satisfactory, and there was a strong demand for gallium oxide semiconductor devices that could more efficiently improve heat dissipation. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] International release WO2014-050793A1 [Patent Document 2] Japanese Patent Publication No. 2007-73743 [Non-patent literature]

[0006] [Non-Patent Document 1] R. Roy VG Hill, and EF Osborn: J. Am. Chem. Soc. 74 (1952) 719 [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] The present invention aims to provide a semiconductor device with efficient heat dissipation properties for a crystalline oxide semiconductor layer. [Means for solving the problem]

[0008] As a result of diligent research to achieve the above objective, the present inventors have found that in a semiconductor device comprising a crystalline oxide semiconductor layer containing gallium oxide or a mixed crystal thereof, and a gate electrode embedded in the crystalline oxide semiconductor layer, a heat dissipation portion having at least a portion of it located deeper than the embedded end of the gate electrode can be arranged to provide a semiconductor device with an efficient heat dissipation structure for the crystalline oxide semiconductor layer. Furthermore, after obtaining the above findings, the inventors conducted further studies and completed the present invention.

[0009] In other words, the present invention relates to the following invention. [1] A semiconductor device comprising a gate electrode, at least a portion of which is embedded in a crystalline oxide semiconductor layer, and a heat dissipation portion having a thermal conductivity higher than that of the crystalline oxide semiconductor layer, wherein at least a portion of the heat dissipation portion is located near the embedded end of the gate electrode in the crystalline oxide semiconductor layer and / or at a position deeper than the embedded end. [2] The semiconductor device according to [1], wherein the embedded end of the gate electrode is the embedded lower end. [3] The semiconductor device according to [2], wherein at least a portion of the heat dissipation section is located deeper than the buried lower end. [4] The semiconductor device according to [2] or [3], further comprising a deep p layer, at least a portion of which is embedded in the crystalline oxide semiconductor layer to the same depth as the lower embedded end or to a position deeper than the lower embedded end. [5] The semiconductor device according to any one of [1] to [4], wherein the heat dissipation portion includes a conductive material. [6] The semiconductor device according to [5], wherein the conductive material is a p-type semiconductor. [7] The semiconductor device according to [6], wherein the p-type semiconductor has a carrier concentration gradient. [8] The semiconductor device according to [6], wherein the p-type semiconductor has a carrier concentration that increases with respect to the depth. [9] The semiconductor device according to any one of [1] to [8] above, wherein the crystalline oxide semiconductor layer contains one or more metals selected from gallium, indium, and aluminum.

[10] The semiconductor device according to any one of [1] to [9] above, wherein the crystalline oxide semiconductor layer contains gallium.

[11] The semiconductor device according to any one of [1] to

[10] above, which is normally-off type.

[12] The semiconductor device according to any one of [1] to

[11] above, which is a power device.

[13] The semiconductor device according to any one of [1] to

[11] above, which is a power module, an inverter, or a converter.

[14] The semiconductor device according to any one of [1] to

[11] above, which is a power card.

[15] A semiconductor system including a semiconductor device, wherein the semiconductor device is the semiconductor device according to any one of [1] to

[14] above. [Effect of the Invention]

[0010] The semiconductor device of the present invention has excellent heat dissipation properties with respect to the crystalline oxide semiconductor layer and exhibits good semiconductor characteristics. [Brief Description of the Drawings]

[0011] [Figure 1] It is a schematic perspective cross-sectional view of a semiconductor device having a laminate including a crystalline oxide semiconductor layer. [Figure 2] The simulation evaluation results of the heat distribution around the gate electrode generated when a current is applied to the semiconductor device of FIG. 1 are shown. [Figure 3] It is a perspective cross-sectional view schematically showing a preferred example of a semiconductor device having a heat dissipation structure. [Figure 4] It is a view schematically showing a cross-section of the semiconductor device of FIG. 3. [Figure 5] It is a perspective cross-sectional view schematically showing a preferred example of a semiconductor device having a heat dissipation structure. [Figure 6]This figure schematically shows a cross-section of the semiconductor device shown in Figure 5. [Figure 7] This is a schematic perspective cross-sectional view showing a suitable example of a semiconductor device having a heat dissipation structure. [Figure 8] This figure schematically shows a cross-section of the semiconductor device shown in Figure 7. [Figure 9] This is a schematic perspective cross-sectional view showing a suitable example of a semiconductor device having a heat dissipation structure. [Figure 10] This figure schematically shows a cross-section of the semiconductor device shown in Figure 9. [Figure 11] This diagram schematically shows a suitable example of a power supply system. [Figure 12] This diagram schematically shows a suitable example of a power supply circuit diagram for a power supply unit. [Figure 13] This diagram schematically shows a suitable example of a power supply circuit diagram for a power supply unit. [Figure 14] This is a schematic diagram of a film deposition apparatus (mist CVD apparatus) used for forming crystalline oxide semiconductor layers. [Figure 15] This is a schematic diagram of a film deposition apparatus (mist CVD apparatus) used for forming crystalline oxide semiconductor layers. [Figure 16] This diagram schematically illustrates a suitable example of a power card. [Modes for carrying out the invention]

[0012] The semiconductor device of the present invention is a semiconductor device comprising a gate electrode embedded in a crystalline oxide semiconductor layer, at least a portion of which is embedded, and a heat dissipation portion having a thermal conductivity higher than that of the crystalline oxide semiconductor layer, characterized in that at least a portion of the heat dissipation portion is located near the embedded end of the gate electrode in the crystalline oxide semiconductor layer and / or at a position deeper than the embedded end.

[0013] "Near the buried end of the gate electrode" means being located at a close enough distance to prevent or suppress localized overheating caused by electric field concentration originating from the gate electrode, which is at least partially buried, and includes the area around the gate electrode. It is not necessary to be in contact with the gate electrode; it is sufficient to be located around all or part of the gate electrode via the gate insulating film. "Buried end" means all or part of the buried surface of the gate electrode, and includes not only all or part of the bottom of the gate electrode, but also all or part of the buried side surface of the gate electrode.

[0014] "A position deeper than the buried end" means a depth sufficient to prevent or suppress localized overheating caused by electric field concentration originating from the gate electrode, of which at least a portion is buried. It does not have to be directly below the gate electrode, but in the present invention, it is preferable that the buried end is the lower buried end.

[0015] "Buried lower end" refers to all or part of the bottom of the gate electrode. When the buried end is the buried lower end, it is preferable to further include a deep p layer, at least a portion of which is buried in the crystalline oxide semiconductor layer to the same depth as the buried lower end or deeper, as this can better mitigate electric field concentration in the crystalline oxide semiconductor layer.

[0016] The gate electrode is not particularly limited as long as it is an electrode capable of controlling the flow of the main current, and includes semiconductor regions, diffusion regions, electrodes, etc.

[0017] The "heat dissipation section" is not particularly limited as long as it is capable of releasing heat from within the crystalline oxide semiconductor layer, and may be layered, a part of, or a part connected in a certain direction. The heat dissipation section includes, for example, a heat dissipation section or heat dissipation layer made of a heat dissipation member, or a cooling section having a cooling function. The heat dissipation member is not particularly limited as long as it has a higher thermal conductivity than the crystalline semiconductor layer. In the present invention, the thermal conductivity of the heat dissipation member is preferably 30 W / m·K or higher, more preferably 50 W / m·K or higher, and most preferably 100 W / m·K or higher. In addition, in the present invention, it is also preferable that the heat dissipation member includes a conductive material. The conductive material is not particularly limited, but it is preferable that it has a higher conductivity than the crystalline oxide semiconductor layer, and such preferred conductive materials include, for example, p-type semiconductors. The p-type semiconductor is not particularly limited, but in the present invention, it is preferably a p-type crystalline oxide semiconductor, more preferably has a carrier concentration gradient, and most preferably the carrier concentration increases in the depth direction. By using such a suitable heat dissipation component, it is possible to achieve even better semiconductor characteristics.

[0018] The crystalline oxide semiconductor layer typically contains a crystalline oxide semiconductor as its main component. The crystalline oxide semiconductor preferably contains gallium, and more preferably contains gallium oxide and its mixed crystal as its main component. Furthermore, the crystal structure of the crystalline oxide semiconductor is not particularly limited. Examples of the crystal structure of the crystalline oxide semiconductor include a corundum structure, a β-gallia structure, a hexagonal structure (e.g., an ε-type structure), etc. In the present invention, it is preferable that the crystalline oxide semiconductor has a corundum structure or a β-gallia structure, and more preferably a corundum structure. The crystalline oxide semiconductor having the corundum structure is not particularly limited, but it is preferable that it contains at least one or more metals from the 3rd to 6th periods of the periodic table, and more preferably at least one selected from gallium, indium, rhodium, iridium, and aluminum. For n-type crystalline oxide semiconductors, it is preferable that it contains at least gallium. For p-type crystalline oxide semiconductors, it is preferable that it contains at least one selected from iridium and rhodium, and more preferably iridium. Examples of the crystalline oxide semiconductor containing gallium include α-Ga2O3 or a mixed crystal thereof. Examples of the metal oxide containing iridium include α-Ir2O3 or a mixed crystal thereof (for example, a mixed crystal of iridium oxide and gallium oxide). A crystalline oxide semiconductor layer containing such a preferred crystalline oxide semiconductor as the main component may have better crystallinity and heat dissipation, and may also have even better semiconductor properties. The term "main component" refers to the composition ratio in the crystalline oxide semiconductor layer, where the crystalline oxide is present in an amount of 50% or more, preferably 70% or more, and more preferably 90% or more. For example, if the crystalline oxide semiconductor is α-Ga2O3, it is sufficient if the atomic ratio of gallium in the metal elements of the crystalline oxide semiconductor layer is 0.5 or more. In the present invention, it is preferable that the atomic ratio of gallium in the metal elements of the crystalline oxide semiconductor layer is 0.7 or more, and more preferably 0.8 or more. The crystalline oxide semiconductor may be a single crystal or a polycrystalline material.In addition, the crystalline oxide semiconductor is usually in the form of a film, but is not particularly limited as long as it does not inhibit the object of the present invention, and may be plate-shaped, sheet-shaped, layered, or a laminate including a plurality of layers.

[0019] The crystalline oxide semiconductor may contain a dopant. The dopant is not particularly limited as long as it does not inhibit the object of the present invention. It may be an n-type dopant or a p-type dopant. Examples of the n-type dopant include tin, germanium, silicon, titanium, zirconium, vanadium, or niobium. Examples of the p-type dopant include magnesium, calcium, etc. The concentration of the dopant may be set appropriately. Specifically, for example, it may be about 1×10 16 / cm 3 ~1×10 22 / cm 3 It may also be, or the concentration of the dopant may be, for example, about 1×10 17 / cm 3 or less at a low concentration. Further, according to the present invention, the dopant may be contained at a high concentration of about 1×10 20 / cm 3 or more.

[0020] The crystalline oxide semiconductor can be preferably obtained by epitaxial crystal growth by, for example, a mist CVD method or a mist epitaxy method.

[0021] <Crystal substrate> The crystalline substrate is not particularly limited as long as it does not hinder the objectives of the present invention, and may be a known substrate. It may be an insulating substrate, a conductive substrate, or a semiconductor substrate. It may be a single-crystal substrate or a polycrystalline substrate. Examples of the crystalline substrate include a substrate containing a crystalline material having a corundum structure as its main component. The "main component" refers to a material that contains 50% or more of the crystalline material in the composition ratio of the substrate, preferably 70% or more, and more preferably 90% or more. Examples of the crystalline substrate having a corundum structure include a sapphire substrate and an α-type gallium oxide substrate.

[0022] In the present invention, the crystal substrate is preferably a sapphire substrate. Examples of the sapphire substrate include a c-plane sapphire substrate, an m-plane sapphire substrate, an a-plane sapphire substrate, and an r-plane sapphire substrate. The sapphire substrate may also have an off-angle. The off-angle is not particularly limited and is, for example, 0.01° or more, preferably 0.2° or more, and more preferably 0.2° to 12°. The sapphire substrate is preferably an a-plane, m-plane, or r-plane crystal growth surface, and is also preferably a c-plane sapphire substrate having an off-angle of 0.2° or more. The thickness of the crystal substrate is not particularly limited, but is usually 10 μm to 20 mm, and more preferably 10 to 1000 μm.

[0023] Furthermore, the crystal substrate may have a shape that includes at least a first crystal axis and a second crystal axis, or grooves corresponding to the first crystal axis and the second crystal axis may be formed therein. Suitable shapes for the crystal substrate include, for example, circles, triangles, squares (e.g., rectangles or trapezoids), polygonal shapes such as pentagons or hexagons, and sector shapes.

[0024] In this invention, other layers such as a buffer layer or a stress relaxation layer may be provided on the crystal substrate. Examples of buffer layers include layers made of metal oxide having the same crystal structure as the crystal substrate or the crystalline oxide semiconductor. Examples of stress relaxation layers include ELO mask layers.

[0025] The method for epitaxial crystal growth is not particularly limited and may be a known method, as long as it does not hinder the objectives of the present invention. Examples of the epitaxial crystal growth method include CVD, MOCVD, MOVPE, mist CVD, mist epitaxy, MBE, HVPE, pulsed growth, or ALD. In the present invention, it is preferable that the epitaxial crystal growth is carried out using the mist CVD method or the mist epitaxy method.

[0026] In the aforementioned mist CVD method or mist epitaxy method, the raw material solution containing the metal is atomized (atomization step), the droplets are suspended, the resulting atomized droplets are transported to the vicinity of the crystal substrate using a carrier gas (transportation step), and then the atomized droplets are subjected to a thermal reaction (film formation step).

[0027] (Raw material solution) The raw material solution contains a metal as a film-forming raw material and is not particularly limited as long as it is atomizable; it may contain inorganic materials or organic materials. The metal may be a pure metal or a metal compound, and is not particularly limited as long as it does not hinder the objectives of the present invention, but examples include gallium (Ga), iridium (Ir), indium (In), rhodium (Rh), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), copper (Cu), iron (Fe), manganese (Mn), nickel (Ni), palladium (Pd), cobalt (Co), ruthenium (Ru), chromium (Cr), molybdenum (Mo), tungsten (W), tantalum (Ta), zinc (Zn), Examples include one or more metals selected from lead (Pb), rhenium (Re), titanium (Ti), tin (Sn), magnesium (Mg), calcium (Ca), and zirconium (Zr). However, in the present invention, it is preferable that the metals include at least one or more metals from the 3rd to 6th periods of the periodic table, more preferably at least one selected from gallium, indium, rhodium, iridium, and aluminum, and most preferably at least gallium. Furthermore, in the present invention, it is also preferable that the metals include gallium and indium and / or aluminum. By using such preferred metals, it is possible to form the crystalline oxide semiconductor film which can be suitably used in semiconductor devices and the like.

[0028] In the present invention, the raw material solution can preferably be a solution in which the metal is dissolved or dispersed in an organic solvent or water in the form of a complex or salt. Examples of complexes include acetylacetonate complexes, carbonyl complexes, ammine complexes, and hydride complexes. Examples of salts include organometallic salts (e.g., metal acetates, metal oxalates, metal citrates, etc.), metal sulfide salts, metal nitrate salts, metal phosphorylate salts, and metal halide salts (e.g., metal chloride salts, metal bromide salts, metal iodide salts, etc.).

[0029] The solvent of the raw material solution is not particularly limited as long as it does not hinder the objective of the present invention, and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In the present invention, it is preferable that the solvent contains water.

[0030] Furthermore, additives such as hydrohalic acid and oxidizing agents may be mixed into the raw material solution. Examples of hydrohalic acid include hydrobromic acid, hydrochloric acid, and hydroiodic acid. Examples of oxidizing agents include peroxides such as hydrogen peroxide (H2O2), sodium peroxide (Na2O2), barium peroxide (BaO2), and benzoyl peroxide (C6H5CO)2O2, as well as organic peroxides such as hypochlorous acid (HClO), perchloric acid, nitric acid, ozonated water, peracetic acid, and nitrobenzene.

[0031] The raw material solution may contain a dopant. The dopant is not particularly limited as long as it does not hinder the objectives of the present invention. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, or p-type dopants such as magnesium or calcium. The concentration of the dopant is usually about 1 × 10⁻⁶. 16 / cm 3 ~1 × 10 22 / cm 3 Alternatively, the concentration of the dopant may be set to, for example, approximately 1 × 10⁻⁶. 17 / cm 3 The following low concentrations may also be used. Furthermore, according to the present invention, the dopant can be approximately 1 × 10⁻⁶ 20 / cm 3 It may be included at the above high concentrations.

[0032] (Atomization process) The atomization step involves preparing a raw material solution containing a metal, atomizing the raw material solution, suspending droplets, and generating atomized droplets. The proportion of the metal is not particularly limited, but preferably 0.0001 mol / L to 20 mol / L relative to the total raw material solution. The atomization method is not particularly limited as long as it can atomize the raw material solution, and any known atomization method may be used, but in the present invention, an atomization method using ultrasonic vibration is preferred. The mist used in the present invention is suspended in the air, and is more preferably a mist that has zero initial velocity and can be transported as a gas, rather than being sprayed like a spray. The droplet size of the mist is not particularly limited, and may be several millimeters in size, but is preferably 50 μm or less, and more preferably 1 to 10 μm.

[0033] (Conveying process) In the transport process, the atomized droplets are transported to the substrate by the carrier gas. The type of carrier gas is not particularly limited as long as it does not hinder the objective of the present invention, and suitable examples include oxygen, ozone, inert gases (e.g., nitrogen or argon), or reducing gases (e.g., hydrogen gas or foaming gas). There may be one type of carrier gas, or there may be two or more types, and a dilution gas with a changed carrier gas concentration (e.g., a 10-fold dilution gas) may be used as a second carrier gas. There may also be two or more locations for supplying the carrier gas, not just one. The flow rate of the carrier gas is not particularly limited, but is preferably 1 LPM or less, and more preferably 0.1 to 1 LPM.

[0034] (Film forming process) In the film formation process, the atomized droplets are reacted to form a film on the crystal substrate. The reaction is not particularly limited as long as it is a reaction that forms a film from the atomized droplets, but in the present invention, a thermal reaction is preferred. The thermal reaction only needs to involve the reaction of the atomized droplets with heat, and the reaction conditions are not particularly limited as long as they do not hinder the objective of the present invention. In this process, the thermal reaction is usually carried out at a temperature above the evaporation temperature of the solvent in the raw material solution, but a temperature that is not too high is preferred, and a temperature of 650°C or lower is more preferred. Furthermore, the thermal reaction may be carried out under any atmosphere, such as vacuum, non-oxygen atmosphere, reducing gas atmosphere, or oxygen atmosphere, as long as it does not hinder the objective of the present invention, and may also be carried out under any conditions, such as atmospheric pressure, pressurized, or reduced pressure, but in the present invention, carrying out the reaction under atmospheric pressure is preferred because it makes it easier to calculate the evaporation temperature and simplifies the equipment, etc. Furthermore, the film thickness can be set by adjusting the film formation time.

[0035] Hereinafter, a film deposition apparatus 601 suitably used in the present invention will be described with reference to the drawings. The film deposition apparatus 601 shown in Figure 14 comprises a carrier gas device 622a for supplying carrier gas, a flow control valve 623a for adjusting the flow rate of carrier gas discharged from the carrier gas device 622a, a carrier gas (dilution) device 622b for supplying carrier gas (dilution), a flow control valve 623b for adjusting the flow rate of carrier gas (dilution) discharged from the carrier gas (dilution) device 622b, a mist source 624 containing raw material solution 624a, a container 625 for water 625a, an ultrasonic transducer 626 attached to the bottom of the container 625, a film deposition chamber 630, a quartz supply pipe 627 connecting the mist source 624 to the film deposition chamber 630, and a hot plate (heater) 628 installed in the film deposition chamber 630. A substrate 603 is placed on the hot plate 628.

[0036] Then, as shown in Figure 14, the raw material solution 624a is placed in the mist generating source 624. Next, the substrate 603 is placed on the hot plate 628, and the hot plate 628 is operated to raise the temperature inside the film deposition chamber 630. Next, the flow control valves 623 (623a, 623b) are opened to supply carrier gas from the carrier gas source (carrier gas device 622a and carrier gas (dilution) device 622b) into the film deposition chamber 630. After the atmosphere inside the film deposition chamber 630 has been sufficiently replaced with carrier gas, the flow rate of the carrier gas and the flow rate of the carrier gas (dilution) are adjusted, respectively. Next, the ultrasonic transducer 626 is vibrated, and the vibration is transmitted to the raw material solution 624a through the water 625a, thereby atomizing the raw material solution 624a and generating atomized droplets 624b. These atomized droplets 624b are introduced into the deposition chamber 630 by a carrier gas and transported to the substrate 603. Then, under atmospheric pressure, the atomized droplets 624b undergo a thermal reaction in the deposition chamber 630, forming a film on the substrate 603.

[0037] It is also preferable to use the mist CVD apparatus (film deposition apparatus) 602 shown in Figure 15. The mist CVD apparatus 602 in Figure 15 comprises a susceptor 621 on which a substrate 603 is placed, a carrier gas supply device 622a for supplying carrier gas, a flow control valve 623a for adjusting the flow rate of carrier gas discharged from the carrier gas supply device 622a, a carrier gas (dilution) supply device 622b for supplying carrier gas (dilution), a flow control valve 623b for adjusting the flow rate of carrier gas discharged from the carrier gas (dilution) supply device 622b, a mist source 624 containing a raw material solution 624a, a container 625 into which water 625a is placed, an ultrasonic transducer 626 attached to the bottom of the container 625, a supply pipe 627 made of a quartz tube with an inner diameter of 40 mm, a heater 628 installed around the supply pipe 627, and an exhaust port 629 for discharging mist, droplets and exhaust gas after the thermal reaction. The susceptor 621 is made of quartz, and the surface on which the substrate 603 is placed is inclined from the horizontal plane. By making both the supply tube 627, which serves as the deposition chamber, and the susceptor 621 from quartz, the contamination of the film formed on the substrate 603 with impurities originating from the apparatus is suppressed. This mist CVD apparatus 602 can be operated in the same manner as the aforementioned deposition apparatus 601.

[0038] By using the aforementioned suitable film deposition apparatus, the crystalline oxide semiconductor can be formed more easily on the crystal growth surface of the crystal substrate. The crystalline oxide semiconductor is typically formed by epitaxial crystal growth.

[0039] The crystalline oxide semiconductor is useful for semiconductor devices, particularly power devices. Examples of semiconductor devices formed using the crystalline oxide semiconductor include metal semiconductor field-effect transistors (MESFETs), high electron mobility transistors (HEMTs), metal oxide semiconductor field-effect transistors (MOSFETs), electrostatic induction transistors (SITs), junction field-effect transistors (JFETs), and insulated gate bipolar transistors (IGBTs). In the present invention, the crystalline oxide semiconductor can be used in a semiconductor device after being peeled from the crystalline substrate, if desired.

[0040] Furthermore, the semiconductor device can be suitably used as either a horizontal element (horizontal device) in which electrodes are formed on one side of the semiconductor layer, or a vertical element (vertical device) in which electrodes are formed on both the front and back sides of the semiconductor layer, respectively. However, in the present invention, it is preferable to use it as a vertical device. Suitable examples of the semiconductor device include, for example, metal-semiconductor field-effect transistors (MESFETs), high electron-mobility transistors (HEMTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), electrostatic induction transistors (SITs), junction field-effect transistors (JFETs), and insulated-gate bipolar transistors (IGBTs).

[0041] The following describes preferred examples of semiconductor devices in which the crystalline oxide semiconductor of the present invention is applied to an n-type semiconductor layer (such as an n+-type semiconductor or an n-type semiconductor layer) or a p-type semiconductor layer, using the drawings as a reference. However, the present invention is not limited to these examples.

[0042] Figure 1 shows a perspective cross-sectional view of a semiconductor device 100 having a laminate 50 including a crystalline oxide semiconductor layer and a gate electrode 13 that is at least partially embedded in the laminate 50. Note that the diagonal lines indicating a cross-sectional view have been omitted to make the structure around the gate electrode easier to see. The semiconductor device 100 in Figure 1 has at least a first crystalline oxide semiconductor layer 1 of a first conductivity type, a second crystalline oxide semiconductor layer 2 disposed on the first crystalline oxide semiconductor layer 1, and a third crystalline oxide semiconductor layer 3 of a second conductivity type formed on the second crystalline oxide semiconductor layer 2. It also includes an insulating film (interlayer insulating film) 25 and a drain electrode 26. Furthermore, to prevent damage to the insulating film 12, the semiconductor device 100 has an outer-positioned deep p layer 6 that has a surface in contact with the second surface 3b of the third crystalline oxide semiconductor layer 3, is partially embedded in the second crystalline oxide semiconductor layer 2, and is located outside the gate electrode 13. As shown in Figure 1, the two outer deep p-layers 6 are arranged so as to sandwich the gate electrode.

[0043] The electrode material may be any known electrode material, and examples of such electrode materials include metals or alloys thereof such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag; metal oxide conductive films such as tin oxide, zinc oxide, rhenium oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, or polypyrrole; or mixtures thereof; and laminates. The electrode formation method is not particularly limited and can be formed on the substrate according to a method appropriately selected from wet methods such as printing, spraying, and coating; physical methods such as vacuum deposition, sputtering, and ion plating; and chemical methods such as CVD and plasma CVD, taking into consideration the suitability with the material.

[0044] The semiconductor device 100 includes a first electrode 26 (drain electrode) electrically connected to a first crystalline oxide semiconductor layer 1, an insulating film 12 disposed on the inner surface of the trench 11, a second electrode 13 (gate electrode) which is a gate electrode disposed on the insulating film 12 disposed on the inner surface of the trench 11, and a third electrode 24 (source electrode) electrically connected to a third crystalline oxide semiconductor layer 3.

[0045] Figure 2 shows the results of a simulation evaluation of the heat distribution around the gate electrode 13 when an electric current is applied to the semiconductor device 100, which includes a crystalline oxide semiconductor layer. It was found that high temperatures occur inside the laminate 50, which includes the crystalline oxide semiconductor layer, at a position deeper than the embedded end 13b of the gate electrode 13. In detail, as shown in Figure 2, the area below the gate electrode 13 is particularly hot within the second crystalline oxide semiconductor layer 2 (n-type semiconductor layer), which is a crystalline oxide semiconductor layer.

[0046] Figure 3 shows a schematic diagram of a semiconductor device having a heat dissipation structure. The semiconductor device in Figure 3 differs from Figure 1 in that it has a heat dissipation section 21. The semiconductor device 200 has a laminate 50 including a crystalline oxide semiconductor layer 1, a gate electrode 13 which is at least partially embedded in the laminate 50, and a heat dissipation section 21 which is at least partially located deeper than the embedded end 13b of the gate electrode 13. The heat dissipation section 21 is located below the embedded end 13b of the gate electrode 13. The heat dissipation section 21 is embedded inside the second crystalline oxide semiconductor layer 2 (n-type semiconductor layer). In a plan view, the heat dissipation section 21 is located closer to the gate electrode than the deep p layer 6 which is located on the outside. That is, in a plan view, the heat dissipation section 21 at least partially overlaps with the gate electrode.

[0047] Furthermore, the semiconductor device 200 may have a first semiconductor region 4 (source region) disposed on a third crystalline oxide semiconductor layer 3 (p-type semiconductor layer) and having a carrier density higher than that of the second crystalline oxide semiconductor layer 2 (n-type semiconductor layer), and a second semiconductor region 5 (contact region) disposed on the third crystalline oxide semiconductor layer 3 (p-type semiconductor layer) and having a carrier density higher than that of the third crystalline oxide semiconductor layer 3 (p-type semiconductor layer). The gate electrode 13 extends in a first direction (depth direction) that penetrates from the first surface 4a of the first semiconductor region 4 (source region) to the opposite second surface 4b, and further penetrates from the first surface 3a of the third crystalline oxide semiconductor layer 3 (p-type semiconductor layer) to the opposite second surface 3b, and in a second direction at an angle to the first direction. Depending on the design of the semiconductor device, the second direction may be oblique or perpendicular to the first direction. If the center of the heat dissipation section 21 is positioned at the intersection of the first direction (depth direction) of the gate electrode and the virtual extension line of the embedded lower end 6b of the deep p layer 6, the heat inside the crystalline oxide semiconductor layer can be diffused more efficiently. In another embodiment, the heat dissipation section 21 may have a contact surface with the deep p layer 6. When the heat dissipation section 21 is thermally connected to the deep p layer 6, the heat trapped inside the crystalline oxide semiconductor layer can be released to the outside of the semiconductor device more efficiently. Note that "thermally connected" refers to a configuration in which, for example, the deep p layer and the heat dissipation section are in contact directly or indirectly (via a medium having a higher thermal conductivity than air), and the heat from the deep p layer is transferred to the heat dissipation section. In Figure 3, the gate electrode is shown extending in the first direction and in a direction perpendicular to the first direction (the longitudinal direction of the semiconductor device in Figure 3). The embedded end 13b of the gate electrode 13 extends in a second direction as an embedded end face, and the heat dissipation section 21 located below the embedded end face of the gate electrode 13 may also be arranged extending in a second direction along the embedded end face of the gate electrode 13. Furthermore, as shown in the cross-sectional view of Figure 4, the heat dissipation section 21 may be provided as a single unit, or as shown in Figure 8, two or more heat dissipation sections 21 may be arranged adjacent to each other or spaced apart from each other.Figure 4 schematically shows a cross-section of the semiconductor device in Figure 3, obtained by cutting it through a plane that includes the IV-IV line and is parallel to the longitudinal direction of the semiconductor device 200. Figure 8 schematically shows a cross-section of the semiconductor device in Figure 7, obtained by cutting it through a plane that includes the VIII-VIII line and is parallel to the longitudinal direction of the semiconductor device 400. Note that if the semiconductor device 200 is a metal-oxide-semiconductor field-effect transistor (MOSFET), the crystalline oxide semiconductor layer 1 becomes an n-type semiconductor layer. If the semiconductor device is an insulated-gate bipolar transistor (IGBT), the crystalline oxide semiconductor layer 1 becomes a p+-type semiconductor layer.

[0048] The material of the heat dissipation section 21 may be a known material, but the thermal conductivity of the heat dissipation section 21 must be higher than the thermal conductivity of the crystalline oxide semiconductor layer in which the heat dissipation section is embedded. For example, if the main component of the first crystalline oxide semiconductor layer 2 is gallium oxide, the heat dissipation section 21 contains a material with higher thermal conductivity than gallium oxide. For example, the heat dissipation section 21 may contain a metal with high thermal conductivity (e.g., aluminum or copper), a metal compound, and / or a metal oxide, or it may contain a material with high thermal conductivity such as silicide, polysilicon, or graphite. The heat dissipation section 21 may also be electrically conductive.

[0049] The heat dissipation section 21 may contain impurities of the second conductivity type (p-type). The concentration of the impurities of the second conductivity type may differ between the position near the first surface 21a of the heat dissipation section 21, which is closer to the gate electrode, and the position near the second surface 21b, which is opposite the first surface 21a. The concentration of the heat dissipation section 21 may increase in the first direction (depth direction). It is preferable that the second surface 21b of the heat dissipation section 21 is located deeper than the second surface 6b of the deep p-layer 6 located on the outside.

[0050] Figure 5 shows another schematic diagram of a semiconductor device having a heat dissipation structure. The semiconductor device in Figure 5 differs from the semiconductor device in Figure 3 in that the heat dissipation section 21 has a first concentration region 23 and a second concentration region 22. The semiconductor device 300 may have a heat dissipation section 21 located below the embedded end 13b of the gate electrode, which has a first concentration region 23(p-) and a second concentration region 22(p) in which the concentration of the second conductivity type impurity is higher than that of the first concentration region 23. Figure 6 is a schematic diagram showing a cross-section of the semiconductor device in Figure 5, obtained by cutting it in a plane that includes the line VI-VI and is parallel to the longitudinal direction of the semiconductor device 300. As shown in the cross-sectional view of Figure 6, the heat dissipation section 21 may be provided integrally, or, as shown in the cross-sectional view of Figure 8, two or more heat dissipation sections 21 may be arranged adjacent to or spaced apart along the embedded end 13b of the gate electrode 13 (in the second direction). However, as shown in the simulation evaluation results of Figure 2, by arranging the heat dissipation section 21 at a position deeper than the embedded end 13b of the gate electrode 13 and inside the laminate 50 containing the crystalline oxide semiconductor layer, heat inside the oxide semiconductor layer can be efficiently diffused.

[0051] Figure 7 shows another schematic diagram of a semiconductor device having a heat dissipation structure. The semiconductor device 400 has a heat dissipation portion 21 that is thermally connected via an insulating film 12 to at least two surfaces, including the embedded end 13b of the gate electrode. The heat dissipation portion 21 has a recess extending in a second direction on its upper surface, and the recess of the heat dissipation portion 21 may constitute part of the trench 11, and the lower part including the embedded end 13b of the gate electrode is connected to the heat dissipation portion 21 via the insulating film 12. The heat dissipation portion 21 may be narrower toward the bottom surface. In addition, the second crystalline oxide semiconductor layer 2 may have a current diffusion region disposed between two or more heat dissipation portions of the second conductivity type. In Figure 7, the upper end portion 13a of the gate electrode is not embedded in the trench, but in the present invention, it is more preferable that the upper end portion 13a of the gate electrode is embedded in the trench.

[0052] Figure 9 shows another schematic diagram of a semiconductor device having a heat dissipation structure. The semiconductor device 500 has a heat dissipation section 21 that is thermally connected via an insulating film 12 to at least two surfaces, including the embedded end 13b of the gate electrode. The heat dissipation section 21 has a recess on its upper surface that extends in a second direction, and the recess of the heat dissipation section 21 may constitute part of the trench 11, and the lower part including the embedded end 13b of the gate electrode is connected to the heat dissipation section 21 via the insulating film 12. The heat dissipation section 21 may contain impurities of a second conductivity type (p-type), and the concentration of the second conductivity type impurities may differ between the upper surface of the heat dissipation section 21 with the recess and the bottom surface of the heat dissipation section 21. The concentration of the heat dissipation section 21 may increase in the first direction (depth direction). Figure 10 is a schematic diagram showing a cross-section of the semiconductor device of Figure 9 cut by a plane including line XX and parallel to the longitudinal direction of the semiconductor device 500. As shown in the cross-sectional view of Figure 10, the heat dissipation section 21 may be provided as a single unit, or two or more heat dissipation sections 21 may be arranged adjacent to each other or spaced apart, as shown in Figure 8. The first concentration region 23 of the heat dissipation section 21 is located closer to the trench side than the second concentration region 22. When a voltage is applied to the second electrode 13, the first concentration region forms an inversion layer at a position close to the trench side.

[0053] Furthermore, when α-Ga2O3 was used for the crystalline oxide semiconductor layer and a p-type oxide semiconductor (α-Ir2O3 or Mg-doped α-Ga2O3) was used for the heat dissipation part, the heat distribution around each gate electrode of the semiconductor device shown in Figures 3, 5, 7, and 9 was examined, and no high-temperature areas like those shown in Figure 2 were generated. This also indicates that, according to the present invention, it is possible to prevent or suppress localized high temperatures caused by electric field concentration originating from the gate electrode, which is at least partially embedded, and that the semiconductor properties are excellent.

[0054] The means for forming each layer of the semiconductor device are not particularly limited as long as they do not hinder the objective of the present invention, and may be known means. For example, means of forming a film by vacuum deposition, CVD, sputtering, various coating techniques, etc., followed by patterning by photolithography, or means of directly patterning using printing technology, etc.

[0055] The semiconductor device is useful, particularly for power devices, and is especially suitable for use as a normally-off type semiconductor device. In the present invention, the crystalline oxide semiconductor can be used in a semiconductor device by optionally peeling it from the crystal substrate using known means, and is preferably used as a vertical device. The semiconductor device can be suitably used as either a horizontal element (horizontal device) in which electrodes are formed on one side of the semiconductor layer, or a vertical element (vertical device) in which electrodes are formed on both the front and back sides of the semiconductor layer, respectively, but in the present invention, it is preferable to use it as a vertical device. Suitable examples of the semiconductor device include, for example, metal semiconductor field-effect transistors (MESFETs), high electron-mobility transistors (HEMTs), metal oxide semiconductor field-effect transistors (MOSFETs), electrostatic induction transistors (SITs), junction field-effect transistors (JFETs), and insulated-gate bipolar transistors (IGBTs). In the present invention, insulated-gate semiconductor devices (e.g., MOSFETs or IGBTs) or semiconductor devices having a Schottky gate (e.g., MESFETs) are preferred, and MOSFETs or IGBTs are more preferred.

[0056] In addition to the matters described above, the semiconductor device of the present invention can be suitably used as a power module, inverter, or converter by known methods, and can also be suitably used in semiconductor systems, for example, using a power supply device. The power supply device can be manufactured from or as the semiconductor device by connecting it to a wiring pattern, etc., using known methods. Figure 11 shows a power supply system 170 configured using a plurality of power supply devices 171, 172 and a control circuit 173. As shown in Figure 12, the power supply system can be used in a system device 180 by combining an electronic circuit 181 and a power supply system 182. An example of a power supply circuit diagram for a power supply device is shown in Figure 13. Figure 13 shows the power supply circuit of a power supply device consisting of a power circuit and a control circuit. The inverter 192 (composed of MOSFETs A to D) switches the DC voltage at high frequency and converts it to AC, then the transformer 193 performs isolation and voltage transformation, the rectifier MOSFET 194 (A to B') rectifies the voltage, and then the DC voltage is output by DCL 195 (smoothing coils L1, L2) and a capacitor. At this time, the voltage comparator 197 compares the output voltage with a reference voltage, and the PWM control circuit 196 controls the inverter 192 and rectifier MOSFET 194 to obtain the desired output voltage.

[0057] In the present invention, the semiconductor device is preferably a power card, and includes a cooler and an insulating member. It is more preferable that the cooler is provided on both sides of the semiconductor layer, at least via the insulating member. It is most preferable that a heat dissipation layer is provided on both sides of the semiconductor layer, and the cooler is provided on the outside of the heat dissipation layer, at least via the insulating member. Figure 16 shows a power card, which is one of the preferred embodiments of the present invention. The power card in Figure 16 is a double-sided cooling type power card 201, and comprises a coolant tube 202, a spacer 203, an insulating plate (insulating spacer) 208, a sealing resin part 209, a semiconductor chip 301a, a metal heat transfer plate (protruding terminal part) 302b, a heat sink and electrode 303, a metal heat transfer plate (protruding terminal part) 303b, a solder layer 304, a control electrode terminal 305, and a bonding wire 308. The cross-section in the thickness direction of the coolant tube 202 has many flow paths 222 partitioned by a number of partition walls 221 that extend in the flow direction at predetermined intervals from each other. Such a suitable power card allows for better heat dissipation and thus higher reliability.

[0058] The semiconductor chip 301a is joined to the inner main surface of the metal heat transfer plate (protruding terminal portion) 302b by a solder layer 304, and the remaining main surface of the semiconductor chip 301a is joined to the metal heat transfer plate (protruding terminal portion) 303b by a solder layer 304, thereby connecting the collector electrode surface and emitter electrode surface of the IGBT to the anode electrode surface and cathode electrode surface of the flywheel diode in antiparallel. Examples of materials for the metal heat transfer plates (protruding terminal portions) 302b and 303b include Mo or W. The metal heat transfer plates (protruding terminal portions) 302b and 303b have a thickness difference that absorbs the thickness difference of the semiconductor chip 301a, so that the outer surfaces of the metal heat transfer plates 302b and 303b are flat.

[0059] The resin encapsulation portion 209 is made of, for example, epoxy resin and is molded to cover the sides of the metal heat transfer plates 302b and 303b, and the semiconductor chip 301a is molded in the resin encapsulation portion 209. However, the outer main surface, i.e., the contact heat receiving surface, of the metal heat transfer plates 302b and 303b is completely exposed. The metal heat transfer plates (protruding terminal portions) 302b and 303b protrude to the right in Figure 16 from the resin encapsulation portion 209, and the control electrode terminal 305, which is a so-called lead frame terminal, connects the gate (control) electrode surface of the semiconductor chip 301a on which the IGBT is formed, for example, to the control electrode terminal 305.

[0060] The insulating spacer, the insulating plate 208, is made of, for example, an aluminum nitride film, but other insulating films may be used. The insulating plate 208 completely covers and tightly adheres to the metal heat transfer plates 302b and 303b, but the insulating plate 208 and the metal heat transfer plates 302b and 303b may simply be in contact, or a good heat transfer material such as silicone grease may be applied, or they may be joined by various methods. Alternatively, an insulating layer may be formed by ceramic spraying or the like, the insulating plate 208 may be joined to the metal heat transfer plates, or it may be joined or formed on the refrigerant tubes.

[0061] The refrigerant tube 202 is manufactured by cutting a sheet material formed from an aluminum alloy by drawing or extrusion to the required length. The cross-section in the thickness direction of the refrigerant tube 202 has many flow channels 222 partitioned by a number of partition walls 221 that extend in the flow direction at predetermined intervals from each other. The spacer 203 may be a soft metal plate such as a solder alloy, but it may also be a film (membrane) formed by coating or other means on the contact surface of the metal heat transfer plates 302b and 303b. The surface of this soft spacer 203 deforms easily and conforms to minute irregularities and warping of the insulating plate 208 and minute irregularities and warping of the refrigerant tube 202, thereby reducing thermal resistance. Note that a known good thermal conductivity grease may be applied to the surface of the spacer 203, and the spacer 203 may be omitted. [Industrial applicability]

[0062] The semiconductor device of the present invention can be used in a wide range of fields, such as compound semiconductor electronic devices, electronic components, electrical equipment components, optical and electrophotographic equipment, and industrial materials, but is particularly useful for power devices containing an oxide semiconductor layer. [Explanation of symbols]

[0063] 1. First crystalline oxide semiconductor layer 2. Second crystalline oxide semiconductor layer 3. Third crystalline oxide semiconductor layer 3a First surface of the third crystalline oxide semiconductor layer 3b Second surface of the third crystalline oxide semiconductor layer 4. The first semiconductor area 4a First surface of the first semiconductor region 4b Second surface of the first semiconductor region 5. The second semiconductor area 6. Deep p-layers at outer positions 6b Lower end of the buried deep p layer 11 Trench 12 Insulating film 13 gates 13a Upper end of gate 13b Lower buried end of gate electrode 21 Heat radiation part 22 Second concentration region 23 1st concentration region 24 Source electrodes 25. Insulating film (interlayer insulating film) 26 Drain electrode 50-layer structure 100 Semiconductor Equipment 170 Power Systems 171 Power supply 172 Power supply 173 Control circuits 180 System Devices 181 Electronic circuit 182 Power Systems 192 Inverter 193 Transformer 194 Rectifier MOSFET 195 DCL 196 PWM control circuit 197 Voltage comparator 200 Semiconductor Equipment 201 Double-sided cooling power card 202 Refrigerant Tube 203 Spacer 208 Insulating plate (insulating spacer) 209 Sealing resin part 221 Bulkhead 222 Channel 300 semiconductor equipment 301a Semiconductor Chip 302b Metal heat transfer plate (protruding terminal portion) 303 Heat sink and electrodes 303b Metal heat transfer plate (protruding terminal portion) 304 solder layer 305 Control electrode terminal 308 Bonding Wire 400 semiconductor devices 500 Semiconductor Equipment 601 Misting apparatus (film deposition apparatus) 602 Misting apparatus (film deposition apparatus) 603 circuit board 621 Susceptor 622a Carrier gas supply device 622b Carrier gas (dilution) supply device 623a Flow control valve 623b Flow control valve 624 Mist source 624a Raw material solution 625 Container 625a water 626 Ultrasonic transducer 627 Supply pipe 628 Heater 629 Exhaust vent 630 Deposition chamber

Claims

1. A semiconductor device comprising a gate electrode embedded in a crystalline oxide semiconductor layer, at least a portion of which is embedded, and a heat dissipation portion having a thermal conductivity higher than that of the crystalline oxide semiconductor layer, wherein at least a portion of the heat dissipation portion is located near and / or deeper than the embedded end of the gate electrode in the crystalline oxide semiconductor layer, and the heat dissipation portion contains iridium oxide.

2. The semiconductor device according to claim 1, wherein the buried end of the gate electrode is the buried lower end.

3. The semiconductor device according to claim 2, wherein at least a portion of the heat dissipation portion is located at a position deeper than the buried lower end.

4. The semiconductor device according to claim 2 or 3, further comprising a deep p layer, the deep p layer being embedded in the crystalline oxide semiconductor layer to a depth equal to or greater than the depth of the buried lower end.

5. The semiconductor device according to claim 1, wherein the iridium oxide is a p-type semiconductor.

6. The semiconductor device according to claim 5, wherein the p-type semiconductor has a carrier concentration gradient.

7. The semiconductor device according to claim 5, wherein the carrier concentration of the p-type semiconductor increases with respect to the depth.

8. The semiconductor device according to any one of claims 1 to 7, wherein the crystalline oxide semiconductor layer comprises one or more metals selected from gallium, indium, and aluminum.

9. The semiconductor device according to any one of claims 1 to 8, wherein the crystalline oxide semiconductor layer contains gallium.

10. A semiconductor device according to any one of claims 1 to 9, which is of the normally-off type.

11. A semiconductor device according to any one of claims 1 to 10, which is a power device.

12. A semiconductor device according to any one of claims 1 to 10, which is a power module, an inverter, or a converter.

13. A semiconductor device according to any one of claims 1 to 10, which is a power card.

14. The semiconductor device according to Claims 1 to 13, wherein the thermal conductivity is 30 W / m·K or more.

15. A semiconductor system comprising a semiconductor device, wherein the semiconductor device is the semiconductor device described in any one of claims 1 to 13.

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