Indication device
By uniformly distributing load capacitance and resistance across wirings using a conductive layer, the solution addresses display malfunctions caused by varying load capacitance, enhancing display performance.
JP7883636B2Active Publication Date: 2026-07-01SEMICON ENERGY LAB CO LTD
Patent Information
- Application Number
- JP2025057707
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2010-06-04
- Filing Date
- 2025-03-31
- Publication Date
- 2026-07-01
- Estimated Expiration
- 2031-06-01
AI Technical Summary
Technical Problem
Increasing the number of wirings in display devices leads to discrepancies in load capacity, causing display malfunctions such as display gradation deviation and signal delay due to variations in load capacitance between different wirings.
Method used
The solution involves connecting the terminals of selection transistors to data or scan lines using a conductive layer that forms uniform load capacitance across all wirings, ensuring equal load capacitance and resistance across each wiring.
Benefits of technology
This approach reduces the differences in load capacitance and resistance, minimizing display gradation deviations and signal delays by ensuring consistent signal potential supply to each pixel.
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Smart Images
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Abstract
To provide a display device that can, when plural lines are used to supply different signals to plural pixels at the same timing, reduce difference in load capacity between the lines and reduce a gap in display gradation and / or signal delay.SOLUTION: A display device comprises a first data line to an N-th (N is a natural number of 3 or more) data line for supplying different video signals, and a pixel including a selection transistor connected to any one of the first data line to the N-th data line. One of the first data line to the N-th data line is connected to one terminal of the selection transistor by disposing the one of the first data line to the N-th data line at a place closest to the one terminal of the selection transistor in a manner that the first data line to the N-th data line cross each other.SELECTED DRAWING: Figure 1
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Citation Information
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