Plasma processing equipment

Abstract

To provide a technique for cleaning the inner walls of a chamber body.SOLUTION: A plasma processing device includes a DC power supply that generates a DC voltage of negative polarity applied to a lower electrode of a stage. In the cleaning using this plasma processing device, a high frequency wave is supplied for exciting gas in a chamber to generate plasma. Further, to draw ions from the plasma to the inner walls of the chamber body, a negative polarity DC voltage from the DC power supply is periodically applied to the lower electrode. The ratio of a period during which the DC voltage is applied to the lower electrode in each cycle is set to a value greater than 40%.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a cleaning method and a plasma processing apparatus.

Background Art

[0002] In the manufacture of electronic devices, plasma processing apparatuses are used. A plasma processing apparatus generally includes a chamber body, a stage, and a high-frequency power supply. The chamber body provides its internal space as a chamber. The chamber body is grounded. The stage is provided in the chamber and is configured to support a substrate placed thereon. The stage includes a lower electrode. The high-frequency power supply supplies high-frequency power to excite the gas in the chamber. In this plasma processing apparatus, ions are accelerated by the potential difference between the potential of the lower electrode and the potential of the plasma, and the accelerated ions are irradiated onto the substrate.

[0003] In a plasma processing apparatus, a potential difference also occurs between the chamber body and the plasma. When the potential difference between the chamber body and the plasma is large, the energy of the ions irradiated onto the inner wall of the chamber body becomes high, and particles are released from the chamber body. The particles released from the chamber body contaminate the substrate placed on the stage. In order to prevent the generation of such particles, in Patent Document 1, a technique using an adjustment mechanism for adjusting the grounding capacitance of the chamber has been proposed. The adjustment mechanism described in Patent Document 1 is configured to adjust the area ratio of the anode and the cathode facing the chamber, that is, the A / C ratio.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] This disclosure provides a technique for cleaning the inner wall of a chamber body. [Means for solving the problem]

[0006] In one embodiment, a cleaning method performed in a plasma processing apparatus is provided. The plasma processing apparatus comprises a chamber body, a stage, a high-frequency power supply, and one or more DC power supplies. The chamber body provides its internal space as a chamber. The stage is located within the chamber body. The stage includes a lower electrode. The stage is configured to support a substrate placed on it. The high-frequency power supply is configured to supply high frequency to excite a gas supplied to the chamber. One or more DC power supplies are configured to generate a negative polarity DC voltage applied to the lower electrode. The cleaning method according to one embodiment includes (i) supplying high frequency from the high-frequency power supply to generate a plasma of the gas supplied to the chamber, and (ii) applying a negative polarity DC voltage from one or more DC power supplies to the lower electrode in order to draw ions in the plasma to the inner wall of the chamber body. In the step of applying the DC voltage, the DC voltage is applied periodically to the lower electrode, and the proportion of the period during which the DC voltage is applied to the lower electrode within each period is set to a value greater than 40%. [Effects of the Invention]

[0007] A technique for cleaning the inner wall of the chamber body is provided. [Brief explanation of the drawing]

[0008] [Figure 1] This figure schematically shows a plasma processing apparatus according to one embodiment. [Figure 2] Figure 1 shows one embodiment of the power supply and control system of the plasma processing apparatus shown in Figure 1. [Figure 3] Figure 2 shows the circuit configuration of the DC power supply, switching unit, high-frequency filter, and matching unit. [Figure 4] This is a timing chart related to a plasma processing method of one embodiment, which is performed using the plasma processing apparatus shown in Figure 1. [Figure 5] This is a timing chart showing the potential of the plasma. [Figure 6] Figures 6(a) and 6(b) are timing charts related to a plasma processing method of another embodiment. [Figure 7] This figure shows the power supply system and control system of a plasma processing apparatus according to another embodiment. [Figure 8] This figure shows a power supply system and control system for a plasma processing apparatus according to yet another embodiment. [Figure 9] This is a timing chart related to a plasma processing method of one embodiment, which is performed using the plasma processing apparatus shown in Figure 8. [Figure 10] This figure shows a power supply system and control system for a plasma processing apparatus according to yet another embodiment. [Figure 11] This is a circuit diagram showing an example of a waveform adjuster. [Figure 12] Figure 12(a) is a graph showing the relationship between the duty cycle obtained in the first evaluation experiment and the amount of etching of the silicon oxide film of the sample attached to the chamber 12c side of the top plate 34, and Figure 12(b) is a graph showing the relationship between the duty cycle obtained in the first evaluation experiment and the amount of etching of the silicon oxide film of the sample attached to the side wall of the chamber body 12. [Figure 13] This graph shows the relationship between the duty cycle, determined in the first evaluation experiment, and the amount of etching of the silicon oxide film of the sample placed on the electrostatic chuck 20. [Figure 14] Figure 14(a) is a graph showing the amount of etching of the silicon oxide film of the sample attached to the chamber 12c side of the top plate 34, obtained in each of the second evaluation experiment and comparative experiment, and Figure 14(b) is a graph showing the amount of etching of the silicon oxide film of the sample attached to the side wall of the chamber body 12, obtained in each of the second evaluation experiment and comparative experiment. [Modes for carrying out the invention]

[0009] Various embodiments will be described in detail below with reference to the drawings. In each drawing, the same or corresponding parts will be denoted by the same reference numerals.

[0010] Figure 1 is a schematic diagram showing a plasma processing apparatus according to one embodiment. Figure 2 is a diagram showing one embodiment of the power supply system and control system of the plasma processing apparatus shown in Figure 1. The plasma processing apparatus 10 shown in Figure 1 is a capacitively coupled plasma processing apparatus.

[0011] The plasma processing apparatus 10 includes a chamber body 12. The chamber body 12 has a substantially cylindrical shape. The chamber body 12 provides its internal space as a chamber 12c. The chamber body 12 is made of, for example, aluminum. The chamber body 12 is connected to ground potential. A plasma-resistant film is formed on the inner wall surface of the chamber body 12, that is, the wall surface defining the chamber 12c. This film may be a ceramic film, such as a film formed by anodizing or a film formed from yttrium oxide. A passage 12p is also formed on the side wall of the chamber body 12. When a substrate W is loaded into the chamber 12c and when the substrate W is unloaded from the chamber 12c, the substrate W passes through the passage 12p. A gate valve 12g is provided along the side wall of the chamber body 12 for opening and closing this passage 12p.

[0012] Inside the chamber 12c, the support portion 15 extends upward from the bottom of the chamber body 12. The support portion 15 has a substantially cylindrical shape and is formed of an insulating material such as ceramic. A stage 16 is mounted on the support portion 15. The stage 16 is supported by the support portion 15. The stage 16 is configured to support the substrate W inside the chamber 12c. The stage 16 includes a lower electrode 18 and an electrostatic chuck 20. In one embodiment, the stage 16 further includes an electrode plate 21. The electrode plate 21 is formed of a conductive material such as aluminum and has a substantially disk shape. The lower electrode 18 is provided on the electrode plate 21. The lower electrode 18 is formed of a conductive material such as aluminum and has a substantially disk shape. The lower electrode 18 is electrically connected to the electrode plate 21.

[0013] A flow path 18f is provided in the lower electrode 18. The flow path 18f is a flow path for a heat exchange medium. As the heat exchange medium, a liquid refrigerant or a refrigerant (e.g., Freon) that cools the lower electrode 18 by its vaporization is used. The heat exchange medium is supplied to the flow path 18f via a pipe 23a from a chiller unit provided outside the chamber body 12. The heat exchange medium supplied to the flow path 18f is returned to the chiller unit via a pipe 23b. That is, the heat exchange medium is supplied to the flow path 18f so as to circulate between the flow path 18f and the chiller unit.

[0014] The electrostatic chuck 20 is provided on the lower electrode 18. The electrostatic chuck 20 has a main body formed of an insulator and a film-like electrode provided in the main body. A DC power supply is electrically connected to the electrode of the electrostatic chuck 20. When a voltage is applied from the DC power supply to the electrode of the electrostatic chuck 20, an electrostatic attraction force is generated between the substrate W placed on the electrostatic chuck 20 and the electrostatic chuck 20. Due to the generated electrostatic attraction force, the substrate W is attracted to the electrostatic chuck 20 and held by the electrostatic chuck 20. A focus ring FR is disposed on the peripheral region of the electrostatic chuck 20. The focus ring FR has a substantially annular plate shape and is formed of, for example, silicon. The focus ring FR is disposed so as to surround the edge of the substrate W.

[0015] The plasma processing apparatus 10 is provided with a gas supply line 25. The gas supply line 25 supplies a heat transfer gas from a gas supply mechanism, for example, He gas, between the upper surface of the electrostatic chuck 20 and the back surface (lower surface) of the substrate W.

[0016] A cylindrical portion 28 extends upward from the bottom of the chamber body 12. The cylindrical portion 28 extends along the outer periphery of the support portion 15. The cylindrical portion 28 is formed of a conductive material and has a substantially cylindrical shape. The cylindrical portion 28 is connected to a ground potential. An insulating portion 29 is provided on the cylindrical portion 28. The insulating portion 29 has insulating properties and is formed of, for example, quartz or ceramic. The insulating portion 29 extends along the outer periphery of the stage 16.

[0017] The plasma processing apparatus 10 further includes an upper electrode 30. The upper electrode 30 is provided above the stage 16. The upper electrode 30 closes the upper opening of the chamber body 12 together with the member 32. The member 32 has insulating properties. The upper electrode 30 is supported on the upper portion of the chamber body 12 through this member 32. When a first high-frequency power supply 61 described later is electrically connected to the lower electrode 18, the upper electrode 30 is connected to a ground potential.

[0018] The upper electrode 30 includes a top plate 34 and a support 36. The lower surface of the top plate 34 defines the chamber 12c. The top plate 34 is provided with a plurality of gas discharge holes 34a. Each of the plurality of gas discharge holes 34a penetrates the top plate 34 in the thickness direction (vertical direction). The top plate 34 is formed from, for example, silicon, although this is not limited to the above. Alternatively, the top plate 34 may have a structure in which a plasma-resistant film is provided on the surface of an aluminum base material. This film may be a ceramic film, such as a film formed by anodizing or a film formed from yttrium oxide.

[0019] The support 36 is a component that detachably supports the top plate 34. The support 36 may be made of a conductive material such as aluminum. A gas diffusion chamber 36a is provided inside the support 36. Multiple gas holes 36b extend downward from the gas diffusion chamber 36a. Each of the multiple gas holes 36b communicates with a multiple gas discharge hole 34a. The support 36 has a gas inlet 36c that guides gas into the gas diffusion chamber 36a, and a gas supply pipe 38 is connected to this gas inlet 36c.

[0020] A gas source group 40 is connected to the gas supply pipe 38 via a valve group 42 and a flow controller group 44. The gas source group 40 includes multiple gas sources. The valve group 42 includes multiple valves, and the flow controller group 44 includes multiple flow controllers. Each of the multiple flow controllers in the flow controller group 44 is either a mass flow controller or a pressure-controlled flow controller. Each of the multiple gas sources in the gas source group 40 is connected to the gas supply pipe 38 via a corresponding valve in the valve group 42 and a corresponding flow controller in the flow controller group 44. The plasma processing apparatus 10 can supply gas from one or more selected gas sources from the multiple gas sources of the gas source group 40 to the chamber 12c at individually adjusted flow rates.

[0021] A baffle plate 48 is provided between the cylindrical portion 28 and the side wall of the chamber body 12. The baffle plate 48 can be constructed, for example, by coating an aluminum base material with a ceramic such as yttrium oxide. Numerous through holes are formed in this baffle plate 48. Below the baffle plate 48, an exhaust pipe 52 is connected to the bottom of the chamber body 12. An exhaust device 50 is connected to this exhaust pipe 52. The exhaust device 50 has a pressure controller such as an automatic pressure control valve and a vacuum pump such as a turbomolecular pump, and can reduce the pressure in the chamber 12c.

[0022] As shown in Figures 1 and 2, the plasma processing apparatus 10 further comprises a first high-frequency power supply 61. The first high-frequency power supply 61 is a power supply that generates a first high frequency for exciting the gas in the chamber 12c and generating plasma. The first high frequency has a frequency in the range of 27 to 100 MHz, for example, a frequency of 60 MHz. The first high-frequency power supply 61 is connected to the lower electrode 18 via the first matching circuit 65 and electrode plate 21 of the matching unit 64. The first matching circuit 65 is a circuit for matching the output impedance of the first high-frequency power supply 61 with the impedance of the load side (lower electrode 18 side). Note that the first high-frequency power supply 61 does not necessarily have to be electrically connected to the lower electrode 18, and may be connected to the upper electrode 30 via the first matching circuit 65.

[0023] The plasma processing apparatus 10 further includes a second high-frequency power supply 62. The second high-frequency power supply 62 is a power supply that generates a second high frequency for biasing ions to be drawn into the substrate W. The frequency of the second high frequency is lower than the frequency of the first high frequency. The frequency of the second high frequency is in the range of 400 kHz to 13.56 MHz, for example, 400 kHz. The second high-frequency power supply 62 is connected to the lower electrode 18 via the second matching circuit 66 and electrode plate 21 of the matching unit 64. The second matching circuit 66 is a circuit for matching the output impedance of the second high-frequency power supply 62 with the impedance of the load side (lower electrode 18 side).

[0024] The plasma processing apparatus 10 further comprises a DC power supply 70 and a switching unit 72. The DC power supply 70 is a power supply that generates a negative polarity DC voltage. The negative polarity DC voltage is used as a bias voltage for drawing ions into the substrate W placed on the stage 16. The DC power supply 70 is connected to the switching unit 72. The switching unit 72 is electrically connected to the lower electrode 18 via a high-frequency filter 74. In the plasma processing apparatus 10, either the DC voltage generated by the DC power supply 70 or the second high frequency generated by the second high-frequency power supply 62 is selectively supplied to the lower electrode 18.

[0025] The plasma processing apparatus 10 further includes a controller PC. The controller PC is configured to control the switching unit 72. The controller PC may also be configured to further control one or both of the first high-frequency power supplies 61 and the second high-frequency power supplies 62.

[0026] In one embodiment, the plasma processing apparatus 10 may further include a main control unit MC. The main control unit MC is a computer equipped with a processor, a memory device, an input device, a display device, etc., and controls each part of the plasma processing apparatus 10. Specifically, the main control unit MC executes a control program stored in the memory device and controls each part of the plasma processing apparatus 10 based on recipe data stored in the memory device. Through such control, the plasma processing apparatus 10 executes the process specified by the recipe data.

[0027] Refer to Figures 2 and 3 below. Figure 3 is a diagram showing the circuit configuration of the DC power supply, switching unit, high-frequency filter, and matching unit shown in Figure 2. The DC power supply 70 is a variable DC power supply that generates a negative polarity DC voltage applied to the lower electrode 18.

[0028] The switching unit 72 is configured to stop the application of a DC voltage from the DC power supply 70 to the lower electrode 18. In one embodiment, the switching unit 72 includes a field-effect transistor (FET) 72a, an FET 72b, a capacitor 72c, and a resistor 72d. FET 72a is, for example, an N-channel MOS FET. FET 72b is, for example, a P-channel MOS FET. The source of FET 72a is connected to the negative terminal of the DC power supply 70. One end of the capacitor 72c is connected to the negative terminal of the DC power supply 70 and the source of FET 72a. The other end of the capacitor 72c is connected to the source of FET 72b. The source of FET 72b is connected to ground. The gates of FET 72a and FET 72b are connected to each other. A pulse control signal from the controller PC is supplied to node NA, which is connected between the gates of FET 72a and FET 72b. The drain of FET 72a is connected to the drain of FET 72b. Node NB, connected to the drains of FET 72a and FET 72b, is connected to the high-frequency filter 74 via resistor element 72d.

[0029] The high-frequency filter 74 is a filter that reduces or blocks high frequencies. In one embodiment, the high-frequency filter 74 includes an inductor 74a and a capacitor 74b. One end of the inductor 74a is connected to a resistor 72d. One end of the capacitor 74b is connected to one end of the inductor 74a. The other end of the capacitor 74b is connected to ground. The other end of the inductor 74a is connected to a matching circuit 64.

[0030] The matching circuit 64 has a first matching circuit 65 and a second matching circuit 66. In one embodiment, the first matching circuit 65 has a variable capacitor 65a and a variable capacitor 65b, and the second matching circuit 66 has a variable capacitor 66a and a variable capacitor 66b. One end of the variable capacitor 65a is connected to the other end of the inductor 74a. The other end of the variable capacitor 65a is connected to the first high-frequency power supply 61 and one end of the variable capacitor 65b. The other end of the variable capacitor 65b is connected to ground. One end of the variable capacitor 66a is connected to the other end of the inductor 74a. The other end of the variable capacitor 66a is connected to the second high-frequency power supply 62 and one end of the variable capacitor 66b. The other end of the variable capacitor 66b is connected to ground. One end of the variable capacitor 65a and one end of the variable capacitor 66a are connected to terminal 64a of the matching circuit 64. Terminal 64a of the matching circuit 64 is connected to the lower electrode 18 via the electrode plate 21.

[0031] The following describes the control by the main control unit MC and the controller PC. The following description refers to Figures 2 and 4. This is a timing chart related to a plasma processing method of one embodiment performed using the plasma processing apparatus shown in Figure 1. In Figure 4, the horizontal axis represents time. In Figure 4, the vertical axis represents the power of the first high frequency, the DC voltage applied to the lower electrode 18 from the DC power supply 70, and the control signal output by the controller PC. In Figure 4, a high level of the first high frequency power indicates that the first high frequency is being supplied for plasma generation, and a low level of the first high frequency power indicates that the supply of the first high frequency has been stopped. Also in Figure 4, a low level of the DC voltage indicates that a negative polarity DC voltage is being applied to the lower electrode 18 from the DC power supply 70, and a DC voltage of 0V indicates that no DC voltage is being applied to the lower electrode 18 from the DC power supply 70.

[0032] The main control unit MC specifies the power and frequency of the first high-frequency to the first high-frequency power supply 61. In one embodiment, the main control unit MC also specifies the timing for starting the supply of the first high-frequency to the first high-frequency power supply 61 and the timing for ending the supply of the first high-frequency to

[0033] The main control unit MC specifies to the controller PC the frequency and duty cycle that define the period during which a negative DC voltage from the DC power supply 70 is applied to the lower electrode 18. The duty cycle is the percentage of a cycle ("PDC" in Figure 4) occupied by the period during which a negative DC voltage from the DC power supply 70 is applied to the lower electrode 18 ("T1" in Figure 4). This duty cycle is set to 40% or less. In one embodiment, this duty cycle is set to 35% or less.

[0034] The controller PC generates a control signal according to the frequency and duty cycle specified by the main control unit MC. The control signal generated by the controller PC may be a pulse signal. In one example, as shown in Figure 4, the control signal generated by the controller PC has a high level in period T1 and a low level in period T2. Period T2 is the period within one cycle PDC excluding period T1. Alternatively, the control signal generated by the controller PC may have a low level in period T1 and a high level in period T2.

[0035] In one embodiment, a control signal generated by the controller PC is provided to node NA of the switching unit 72. Upon receiving the control signal, the switching unit 72 connects the DC power supply 70 and node NB to each other so that a negative DC voltage from the DC power supply 70 is applied to the lower electrode 18 during period T1. On the other hand, during period T2, the switching unit 72 disconnects the connection between the DC power supply 70 and node NB so that a negative DC voltage from the DC power supply 70 is not applied to the lower electrode 18. As a result, as shown in Figure 4, during period T1, a negative DC voltage from the DC power supply 70 is applied to the lower electrode 18, and during period T2, the application of the negative DC voltage from the DC power supply 70 to the lower electrode 18 is stopped. That is, in the plasma processing method of one embodiment, step S2 is performed in which a negative DC voltage from the DC power supply 70 is periodically applied to the lower electrode 18.

[0036] Refer to Figures 5(a) and 5(b) below. Figures 5(a) and 5(b) are timing charts showing the plasma potential. During period T1, a negative DC voltage from the DC power supply 70 is applied to the lower electrode 18, so positive ions in the plasma move toward the substrate W. Therefore, as shown in Figures 5(a) and 5(b), the plasma potential is low during period T1. On the other hand, during period T2, the application of a negative DC voltage from the DC power supply 70 to the lower electrode 18 is stopped, so the movement of positive ions decreases, and mainly electrons in the plasma move. Therefore, the plasma potential is high during period T2.

[0037] In the timing chart shown in Figure 5(a), the duty cycle is smaller compared to the timing chart shown in Figure 5(b). If the conditions for plasma generation are the same, the total amount of positive ions and electrons in the plasma do not depend on the duty cycle. That is, the ratio of area A1 to area A2 shown in Figure 5(a) is the same as the ratio of area A1 to area A2 shown in Figure 5(b). Therefore, if the duty cycle is small, the plasma potential PV during period T2 will be small.

[0038] The etching rate of the substrate W has little dependence on the duty cycle, i.e., the proportion of the period T1 during which a negative DC voltage is applied to the lower electrode 18 within each periodic PDC. On the other hand, when the duty cycle is small, especially when it is 40% or less, the plasma potential decreases, and the etching rate of the chamber body 12 decreases significantly. Therefore, by setting the duty cycle for the periodic application of a negative DC voltage to the lower electrode 18 to 40% or less, it is possible to suppress the decrease in the etching rate of the substrate W and to reduce the energy of the ions irradiated to the inner wall of the chamber body 12. As a result, the generation of particles from the chamber body 12 is suppressed. Furthermore, when the duty cycle is 35% or less, it is possible to further reduce the energy of the ions irradiated to the inner wall of the chamber body 12.

[0039] Another embodiment will be described below. Figures 6(a) and 6(b) are timing charts related to a plasma processing method of another embodiment. In each of Figures 6(a) and 6(b), the horizontal axis represents time. In each of Figures 6(a) and 6(b), the vertical axis represents the power of the first high frequency and the DC voltage applied from the DC power supply 70 to the lower electrode 18. In each of Figures 6(a) and 6(b), a high level of the first high frequency power indicates that the first high frequency is being supplied for plasma generation, and a low level of the first high frequency power indicates that the supply of the first high frequency has been stopped. Furthermore, in both Figure 6(a) and Figure 6(b), a low DC voltage indicates that a negative DC voltage is applied to the lower electrode 18 from the DC power supply 70, while a DC voltage of 0V indicates that no DC voltage is applied to the lower electrode 18 from the DC power supply 70.

[0040] In the embodiment shown in Figure 6(a), a negative polarity DC voltage from a DC power supply 70 is periodically applied to the lower electrode 18, and a first high frequency is periodically supplied for plasma generation. In the embodiment shown in Figure 6(a), the application of the negative polarity DC voltage from the DC power supply 70 to the lower electrode 18 and the supply of the first high frequency are synchronized. That is, the first high frequency is supplied during period T1 when the DC voltage from the DC power supply 70 is applied to the lower electrode 18, and the supply of the first high frequency is stopped during period T2 when the application of the DC voltage from the DC power supply 70 to the lower electrode 18 is stopped.

[0041] In the embodiment shown in Figure 6(b), a negative polarity DC voltage from a DC power supply 70 is periodically applied to the lower electrode 18, and a first high frequency is periodically supplied for plasma generation. In the embodiment shown in Figure 6(b), the phase of the supply of the first high frequency is inverted with respect to the phase of the application of the negative polarity DC voltage from the DC power supply 70 to the lower electrode 18. That is, the supply of the first high frequency is stopped during period T1 when the DC voltage from the DC power supply 70 is applied to the lower electrode 18, and the first high frequency is supplied during period T2 when the application of the DC voltage from the DC power supply 70 to the lower electrode 18 is stopped.

[0042] In the embodiments shown in Figure 6(a) and Figure 6(b), the aforementioned control signal from the controller PC is supplied to the first high-frequency power supply 61. The first high-frequency power supply 61 starts supplying the first high frequency at the timing of the rising (or falling) edge of the control signal from the controller PC, and stops supplying the first high frequency at the timing of the falling (or rising) edge of the control signal from the controller PC. In the embodiments shown in Figure 6(a) and Figure 6(b), the generation of unintended high frequencies due to intermodulation distortion can be suppressed.

[0043] The following describes several other embodiments of plasma processing apparatuses. Figure 7 shows the power supply and control systems of a plasma processing apparatus according to another embodiment. As shown in Figure 7, the plasma processing apparatus 10A according to another embodiment differs from the plasma processing apparatus 10 in that the first high-frequency power supply 61 includes a controller PC. That is, in the plasma processing apparatus 10A, the controller PC is part of the first high-frequency power supply 61. On the other hand, in the plasma processing apparatus 10, the controller PC is separate from the first high-frequency power supply 61 and the second high-frequency power supply 62. In the plasma processing apparatus 10A, since the controller PC is part of the first high-frequency power supply 61, the control signals (pulse signals) from the controller PC are not transmitted to the first high-frequency power supply 61.

[0044] Figure 8 shows the power supply and control systems of a plasma processing apparatus according to yet another embodiment. The plasma processing apparatus 10B shown in Figure 8 comprises a plurality of DC power supplies 701 and 702, and a plurality of switching units 721 and 722. Each of the plurality of DC power supplies 701 and 702 is a power supply similar to DC power supply 70 and is configured to generate a negative polarity DC voltage applied to the lower electrode 18. Each of the plurality of switching units 721 and 722 has a configuration similar to switching unit 72. DC power supply 701 is connected to switching unit 721. Switching unit 721, like switching unit 72, is configured to stop the application of the DC voltage from DC power supply 701 to the lower electrode 18. DC power supply 702 is connected to switching unit 722. Switching unit 722, like switching unit 72, is configured to stop the application of the DC voltage from DC power supply 702 to the lower electrode 18.

[0045] Figure 9 is a timing chart related to a plasma processing method of one embodiment performed using the plasma processing apparatus shown in Figure 8. In Figure 9, the horizontal axis represents time. In Figure 9, the vertical axis represents the combined DC voltage (i.e., the DC voltage applied to the lower electrode 18), the DC voltage of the DC power supply 701 (i.e., the DC voltage applied to the lower electrode from the DC power supply 701), and the DC voltage of the DC power supply 702 (the DC voltage applied to the lower electrode from the DC power supply 702). As shown in Figure 9, in the plasma processing apparatus 10B, the DC voltage applied to the lower electrode 18 within each periodic PDC is formed by a plurality of DC voltages output sequentially from a plurality of DC power supplies 701 and 702. That is, in the plasma processing apparatus 10B, the DC voltage applied to the lower electrode 18 within each periodic PDC is generated by the temporal combination of a plurality of DC voltages output sequentially from a plurality of DC power supplies 701 and 702. This plasma processing apparatus 10B reduces the load on each of the multiple DC power supplies 701 and 702.

[0046] In the plasma processing apparatus 10B, the controller PC supplies a control signal to the switching unit 721 that has a high level (or low level) during the period when a DC voltage from the DC power supply 701 is applied to the lower electrode 18, and a low level (or high level) during the period when a DC voltage from the DC power supply 701 is not applied to the lower electrode 18. The controller PC also supplies a control signal to the switching unit 722 that has a high level (or low level) during the period when a DC voltage from the DC power supply 702 is applied to the lower electrode 18, and a low level (or high level) during the period when a DC voltage from the DC power supply 702 is not applied to the lower electrode 18. In other words, each of the multiple switching units connected to the multiple DC power supplies is supplied with a control signal (pulse signal) having a different phase.

[0047] Figure 10 shows the power supply and control systems of a plasma processing apparatus according to yet another embodiment. The plasma processing apparatus 10C shown in Figure 10 differs from the plasma processing apparatus 10 in that it further includes a waveform adjuster 76. The waveform adjuster 76 is connected between the switching unit 72 and the high-frequency filter 74. The waveform adjuster 76 adjusts the waveform of the DC power supply output from the DC power supply 70 via the switching unit 72, that is, the DC voltage which alternates between negative polarity values ​​and 0V values. Specifically, the waveform adjuster 76 adjusts the waveform of the DC voltage applied to the lower electrode 18 so that the waveform of the DC voltage has a substantially triangular shape. The waveform adjuster 76 is, for example, an integrating circuit.

[0048] Figure 11 is a circuit diagram showing an example of a waveform adjuster 76. The waveform adjuster 76 shown in Figure 11 is configured as an integrating circuit and includes a resistor 76a and a capacitor 76b. One end of the resistor 76a is connected to the resistor 72d of the switching unit 72, and the other end of the resistor 76a is connected to the high-frequency filter 74. One end of the capacitor 76b is connected to the other end of the resistor 76a. The other end of the capacitor 76b is connected to ground. In the waveform adjuster 76 shown in Figure 11, a delay occurs in the rising and falling edges of the DC voltage output from the switching unit 72, according to the time constant determined by the resistance value of the resistor 76a and the capacitance value of the capacitor 76b. Therefore, with the waveform adjuster 76 shown in Figure 11, it is possible to apply a voltage having a pseudo-triangular wave waveform to the lower electrode 18. With the plasma processing apparatus 10C equipped with such a waveform adjuster 76, it is possible to adjust the energy of the ions irradiated onto the inner wall of the chamber body 12.

[0049] Although various embodiments have been described above, various modified forms can be constructed without being limited to the embodiments described above. For example, the plasma processing apparatus of the various embodiments described above may not have a second high-frequency power supply 62. That is, the plasma processing apparatus of the various embodiments described above may have a single high-frequency power supply.

[0050] Furthermore, in the various embodiments described above, the application and cessation of a negative polarity DC voltage from the DC power supply to the lower electrode 18 is switched by a switching unit. However, if the DC power supply itself is configured to switch between outputting a negative polarity DC voltage and stopping that output, a switching unit is unnecessary.

[0051] Furthermore, the characteristic configurations of the various embodiments described above can be used in any combination. In addition, although the plasma processing apparatuses according to the various embodiments described above are capacitively coupled plasma processing apparatuses, the plasma processing apparatuses in the modified embodiments may be inductively coupled plasma processing apparatuses.

[0052] Furthermore, when the duty cycle is high, the energy of the ions irradiated onto the chamber body 12 increases. Therefore, by setting the duty cycle to a high value, for example, a value greater than 40%, it becomes possible to clean the inner wall of the chamber body 12.

[0053] Furthermore, this disclosure includes the following aspects and embodiments.

[0054] In one embodiment, a plasma processing method is provided that is performed in a plasma processing apparatus. The plasma processing apparatus comprises a chamber body, a stage, a high-frequency power supply, and one or more DC power supplies. The chamber body provides its internal space as a chamber. The stage is located inside the chamber body. The stage includes a lower electrode. The stage is configured to support a substrate placed on it. The high-frequency power supply is configured to supply high frequency to excite a gas supplied to the chamber. One or more DC power supplies are configured to generate a negative polarity DC voltage applied to the lower electrode. The plasma processing method according to one embodiment includes (i) supplying high frequency from the high-frequency power supply to generate plasma of the gas supplied to the chamber, and (ii) applying a negative polarity DC voltage from one or more DC power supplies to the lower electrode in order to draw ions in the plasma onto a substrate. In the step of applying the DC voltage, the DC voltage is applied periodically to the lower electrode, and the proportion of the period in which the DC voltage is applied to the lower electrode within each period is set to 40% or less.

[0055] The substrate etching rate has little dependence on the duty cycle, i.e., the proportion of time during which a negative DC voltage is applied to the lower electrode within each cycle. On the other hand, when the duty cycle is small, especially when it is 40% or less, the etching rate of the chamber body decreases significantly. That is, the energy of the ions irradiated onto the inner wall of the chamber body decreases. Therefore, according to one embodiment of the plasma processing method, it is possible to suppress the decrease in the substrate etching rate and to reduce the energy of the ions irradiated onto the inner wall of the chamber body.

[0056] In one embodiment, the above ratio, i.e., the duty cycle, is set to 35% or less. According to this embodiment, it is possible to further reduce the energy of the ions irradiated onto the inner wall of the chamber body.

[0057] In one embodiment, the plasma processing apparatus is equipped with multiple DC power supplies as one or more DC power supplies. The DC voltage applied to the lower electrode within each cycle is formed by multiple DC voltages output sequentially from the multiple DC power supplies. According to this embodiment, the load on each of the multiple DC power supplies is reduced.

[0058] In one embodiment of the plasma processing method, high frequency is supplied during the period when a DC voltage is applied, and the supply of high frequency is stopped during the period when the application of the DC voltage is stopped. In another embodiment of the plasma processing method, the supply of high frequency is stopped during the period when a DC voltage is applied, and high frequency is supplied during the period when the application of the DC voltage is stopped.

[0059] In another embodiment, a plasma processing apparatus is provided. The plasma processing apparatus comprises a chamber body, a stage, a high-frequency power supply, one or more DC power supplies, a switching unit, and a controller. The chamber body provides its internal space as a chamber. The stage is located within the chamber body. The stage includes a lower electrode. The stage is configured to support a substrate placed on it. The high-frequency power supply is configured to supply a high frequency for exciting the gas supplied to the chamber. One or more DC power supplies are configured to generate a negative polarity DC voltage applied to the lower electrode. The switching unit is configured to stop the application of the DC voltage to the lower electrode. The controller is configured to control the switching unit. The controller controls the switching unit to periodically apply a negative polarity DC voltage from one or more DC power supplies to the lower electrode in order to draw ions in the plasma of the gas generated in the chamber onto the substrate, and to set the proportion of the period during which the DC voltage is applied to the lower electrode within each period to 40% or less.

[0060] In one embodiment, the controller may control the switching unit to set the above ratio, i.e., the duty cycle, to 35% or less.

[0061] In one embodiment, the plasma processing apparatus includes multiple DC power supplies as one or more DC power supplies. The controller controls the switching unit so that the DC voltage applied to the lower electrode within each cycle is formed by multiple DC voltages output sequentially from the multiple DC power supplies.

[0062] In one embodiment, the controller controls the high-frequency power supply such that high frequency is supplied during periods when a DC voltage is applied and high frequency is stopped during periods when the DC voltage is not applied. In another embodiment, the controller controls the high-frequency power supply such that high frequency is stopped during periods when a DC voltage is applied and high frequency is supplied during periods when the DC voltage is not applied.

[0063] The following describes evaluation experiments conducted regarding the plasma treatment method using the plasma treatment apparatus 10.

[0064] (First evaluation experiment)

[0065] In the first evaluation experiment, samples having a silicon oxide film were attached to the chamber 12c side surface of the top plate 34 of the plasma processing apparatus 10 and to the side wall of the chamber body 12, and a sample having a silicon oxide film was placed on the electrostatic chuck 20, and plasma processing was performed under the conditions shown below. In the first evaluation experiment, the duty cycle of the negative polarity DC voltage periodically applied to the lower electrode 18 was used as a variable parameter.

[0066] <Conditions for plasma treatment in the first evaluation experiment> • Chamber 12c pressure: 20 mTorr (2.66 Pa) • Flow rate of gas supplied to chamber 12c C4F8 gas: 24 sccm O2 gas: 16 sccm Ar gas: 150 sccm • First high frequency: 100MHz, 500W continuous wave • Negative polarity DC voltage to the lower electrode 18 Voltage value: -3000V Frequency: 200kHz Processing time: 60 seconds

[0067] In the first evaluation experiment, the amount of etching (thickness reduction) of the silicon oxide film of the sample attached to the chamber 12c side of the top plate 34, the amount of etching (thickness reduction) of the silicon oxide film of the sample attached to the side wall of the chamber body 12, and the amount of etching (thickness reduction) of the silicon oxide film of the sample placed on the electrostatic chuck 20 were measured. Figure 12(a) is a graph showing the relationship between the duty cycle and the amount of etching of the silicon oxide film of the sample attached to the chamber 12c side of the top plate 34, as determined in the first evaluation experiment. Figure 12(b) is a graph showing the relationship between the duty cycle and the amount of etching of the silicon oxide film of the sample attached to the side wall of the chamber body 12, as determined in the first evaluation experiment. Figure 13 is a graph showing the relationship between the duty cycle and the amount of etching of the silicon oxide film of the sample placed on the electrostatic chuck 20, as determined in the first evaluation experiment.

[0068] As shown in Figure 13, the etching amount of the silicon oxide film of the sample placed on the electrostatic chuck 20 did not depend much on the duty cycle. Also, as shown in Figures 12(a) and 12(b), when the duty cycle was 35% or less, the etching amount of the silicon oxide film of the sample attached to the chamber 12c side of the top plate 34, and the etching amount of the silicon oxide film of the sample attached to the side wall of the chamber body 12 were considerably smaller. Therefore, the first evaluation experiment confirmed that the substrate etching rate does not depend much on the duty cycle of the period during which a negative polarity DC voltage is applied to the lower electrode 18 within each periodic PDC. Furthermore, it was confirmed that when the duty cycle is small, especially when the duty cycle is 35% or less, the etching rate of the chamber body 12 decreases significantly, that is, the energy of the ions irradiated onto the inner wall of the chamber body 12 decreases. Furthermore, from the graphs in Figure 12(a) and Figure 12(b), it can be inferred that if the duty cycle is 40% or less, the energy of the ions irradiated onto the inner wall of the chamber body 12 will be considerably smaller.

[0069] (Second evaluation experiment)

[0070] In the second evaluation experiment, samples having a silicon oxide film were attached to the chamber 12c side surface of the top plate 34 of the plasma processing apparatus 10 and to the side wall of the chamber body 12, and samples having a silicon oxide film were placed on the electrostatic chuck 20, and plasma processing was performed under the conditions shown below.

[0071] <Conditions for plasma treatment in the second evaluation experiment> • Chamber 12c pressure: 20 mTorr (2.66 Pa) • Flow rate of gas supplied to chamber 12c C4F8 gas: 24 sccm O2 gas: 16 sccm Ar gas: 150 sccm • First high frequency: 100MHz, 500W continuous wave • Negative polarity DC voltage to the lower electrode 18 Voltage value: -3000V Frequency: 200kHz Duty cycle: 35% Processing time: 60 seconds

[0072] Furthermore, in the comparative experiment, samples having a silicon oxide film were attached to the chamber 12c side surface of the top plate 34 of the plasma processing apparatus 10 and to the side wall of the chamber body 12, respectively, and a sample having a silicon oxide film was placed on the electrostatic chuck 20, and plasma processing was performed under the conditions shown below. The second high-frequency conditions in the comparative experiment were set so that the amount of etching (reduction in film thickness) of the silicon oxide film of the sample placed on the electrostatic chuck 20 was approximately the same as that of the plasma processing in the second evaluation experiment and the plasma processing in the comparative experiment.

[0073] <Conditions for plasma treatment in comparative experiments> • Chamber 12c pressure: 20 mTorr (2.66 Pa) • Flow rate of gas supplied to chamber 12c C4F8 gas: 24 sccm O2 gas: 16 sccm Ar gas: 150 sccm • First high frequency: 100MHz, 500W continuous wave • Second high frequency: 400kHz, 2500W continuous wave Processing time: 60 seconds

[0074] In each of the second evaluation and comparative experiments, the amount of etching (reduction in film thickness) of the silicon oxide film of the sample attached to the chamber 12c side surface of the top plate 34, and the amount of etching (reduction in film thickness) of the silicon oxide film of the sample attached to the side wall of the chamber body 12 were measured. Figure 14(a) is a graph showing the amount of etching of the silicon oxide film of the sample attached to the chamber 12c side surface of the top plate 34, obtained in each of the second evaluation and comparative experiments, and Figure 14(b) is a graph showing the amount of etching of the silicon oxide film of the sample attached to the side wall of the chamber body 12, obtained in each of the second evaluation and comparative experiments. In the graph of Figure 14(a), the horizontal axis represents the radial distance from the center of the chamber 12c to the measurement position in the sample attached to the chamber 12c side surface of the top plate 34, and the vertical axis represents the amount of etching of the silicon oxide film of the sample attached to the chamber 12c side surface of the top plate 34. In the graph of Figure 14(b), the horizontal axis represents the vertical distance from the top plate 34 to the chamber 12c side of the measurement position in the sample attached to the side wall of the chamber 12c, and the vertical axis represents the amount of etching of the silicon oxide film of the sample attached to the side wall of the chamber body 12.

[0075] As shown in Figures 14(a) and (b), in the second evaluation experiment, in which a negative DC voltage was periodically applied to the lower electrode 18, the amount of etching of the silicon oxide film of the sample attached to the chamber 12c side of the top plate 34 and the silicon oxide film of the sample attached to the side wall of the chamber body 12 was considerably smaller compared to the comparative experiment using the second high frequency. Therefore, it was confirmed that by periodically applying a negative DC voltage to the lower electrode 18, it is possible to suppress the decrease in the energy of the ions irradiated to the substrate on the electrostatic chuck 20 while significantly reducing the energy of the ions irradiated to the wall surface of the chamber body 12 and the wall surface of the upper electrode 30, compared to the case using the second high frequency, i.e., the high frequency for biasing. [Explanation of Symbols]

[0076] 10...Plasma processing apparatus, 12...Chamber body, 12c...Chamber, 16...Stage, 18...Lower electrode, 20...Electrostatic chuck, 30...Upper electrode, 34...Top plate, 50...Exhaust device, 61...First high-frequency power supply, 62...Second high-frequency power supply, 64...Matching unit, 70...DC power supply, 72...Switching unit, 74...High-frequency filter, 76...Waveform adjuster, PC...Controller, MC...Main control unit.

Claims

1. A chamber body that provides the chamber, A first high-frequency power supply that supplies high frequency to excite the gas supplied to the chamber, A stage is provided inside the chamber body, and includes a lower electrode and an electrostatic chuck. A switching unit including a first transistor and a second transistor that are electrically connected to the stage and connected in series with each other, A DC power supply for biasing is electrically connected to the switching unit, A controller electrically connected to the first transistor and the second transistor, Equipped with, The controller periodically switches the control signals applied to the first transistor and the second transistor, thereby periodically repeating the process of applying a negative polarity DC voltage from the DC power supply to the stage and not applying a DC voltage from the DC power supply to the stage, and controls the switching unit to set the proportion of the period during which the negative polarity DC voltage is applied to the stage in each cycle, which includes both applying the negative polarity DC voltage from the DC power supply to the stage and not applying the DC voltage from the DC power supply to the stage, to be 25% or more and 35% or less. Plasma processing equipment.

2. The system further includes a second high-frequency power supply for biasing that is electrically connected to the aforementioned stage. The controller selectively applies a negative polarity DC voltage from the DC power supply or a high frequency from the second high-frequency power supply to the stage. The plasma processing apparatus according to claim 1.

3. The first transistor is a first field-effect transistor, The second transistor is a second field-effect transistor having a different channel polarity from the first field-effect transistor. The plasma processing apparatus according to claim 1 or 2.

4. The plasma processing apparatus according to claim 3, wherein the controller is electrically connected to the gate of the first field-effect transistor and the gate of the second field-effect transistor.

5. A plasma processing apparatus according to any one of claims 1 to 4, wherein a high-frequency filter is disposed between the switching unit and the stage.

6. The switching unit includes a resistive element electrically connected to the first transistor and the second transistor. The high-frequency filter is disposed between the resistive element and the stage, The plasma processing apparatus according to claim 5.

7. The plasma processing apparatus according to any one of claims 1 to 6, wherein the high frequency is supplied during the period when the negative polarity DC voltage is applied to the stage, and the supply of the high frequency is stopped during the period when the application of the DC voltage to the stage is stopped.

8. A plasma processing apparatus according to any one of claims 1 to 6, wherein the supply of the high frequency is stopped during the period when the negative polarity DC voltage is applied to the stage, and the high frequency is supplied during the period when the application of the DC voltage to the stage is stopped.

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