Thin-film semiconductor switching devices

Abstract

A novel semiconductor device is taught. The novel device includes a thin film transistor (TFT) having an n-type semiconductor layer forming a channel between a source and a drain. The TFT further includes a source-channel interface member adjacent at least a source contact of the device, which provides depletion layer control of the operation of the TFT.

Description

[Technical Field]

[0001] Priority This application claims the benefit of treaty priority of U.S. Provisional Patent Application No. 63 / 221292, filed on 13 July 2021, which is incorporated herein by reference in its entirety.

[0002] This invention relates to semiconductor devices. More specifically, this invention relates to thin-film semiconductor switching devices such as transistors.

[0003] Background of the Invention Thin-film semiconductor switching devices, such as thin-film transistors (TFTs), are widely used in a variety of applications.

[0004] TFTs are perhaps the most common example of thin-film semiconductor switching devices, and are three-terminal field-effect devices with "source," "drain," and "gate." The gate is a control terminal used to enable or block the flow of current from the source to the drain depending on the voltage applied to it.

[0005] The electrical behavior of a TFT is determined by the dominant charge carrier in the active material, which is usually a semiconductor. The dominant charge carrier transports most of the charge or current through the semiconductor. Typically, the dominant charge carrier accumulates at the interface between the gate insulator and the semiconductor material, forming a "channel" through which charge can move through the semiconductor material. When the channel has sufficient conductivity from source to drain, the TFT is considered "on," and current flows from source to drain through the channel.

[0006] For various reasons, there is increasing interest in manufacturing smaller TFTs. However, conventional TFTs do not scale well to smaller dimensions, such as TFTs where the semiconductor length at which the channel can be formed is less than approximately 1000 nm, and especially TFTs with a channel length of less than 200 nm. Below these dimensions, controlling the TFT becomes difficult, and known TFTs, when manufactured in small dimensions, have a threshold voltage that occurs below 0V (the gate voltage point at which the channel is formed so that the TFT is "on" and conducts current), causing the TFT to be normally "on". Such low (often negative) threshold voltages can degrade the output resistance and overall transistor performance of conventional TFTs manufactured in small dimensions, and these TFTs often need to apply a negative voltage to their gate to achieve the "off" state and reduce leakage current.

[0007] There is a desire to obtain thin-film semiconductor devices that can be fabricated with semiconductor or channel lengths of less than 1000 nm, have an inherent enhancement threshold voltage, and are thus normally "off" and easier to control. Ideally, such devices should also be fabricable as a back-end ("BEOL") process in a semiconductor fabrication line.

[0008] Summary of the Invention The object of the present invention is to provide a novel thin-film semiconductor switching device that avoids or mitigates at least one drawback of the prior art.

[0009] According to a first aspect of the present invention, a thin-film transistor comprising a substrate, an insulating layer formed on the substrate, a source formed on the insulating layer, a drain formed on the insulating layer and spaced apart from the source, and a source formed on the insulating layer and spaced apart from the source. drainA thin-film transistor is provided, comprising an n-type semiconductor material extending between a source and a channel, a source-channel interface member electrically connecting at least the source to the semiconductor material, a gate dielectric layer formed above the semiconductor layer, and a gate formed above the dielectric layer such that when a positive voltage is applied, current can flow from the source through the source-channel interface member and the channel formed in the semiconductor material to the drain.

[0010] Preferably, the n-type semiconductor material is a metal oxide. More preferably, the n-type semiconductor material is selected from the group including zinc oxide, tin oxide, indium gallium zinc oxide, gallium oxide, germanium oxide, or combinations thereof.

[0011] Preferably, the source-channel interface member is an oxide formed by catalytic growth of the source. Also preferably, the source-channel interface member is formed by atomic layer deposition. Furthermore, if the source-channel interface member is an oxide formed by catalytic growth, oxygen preferably migrates to the source-channel interface and forms the source-channel interface member.

[0012] According to another aspect of the present invention, a vertical thin-film transistor is provided, comprising: a substantially flat substrate; an insulating layer formed on the substrate; a source formed on the insulating layer; a second insulating layer formed on the source and having an inner surface, forming a vertical well; a source-channel interface member formed on the inner surface of the vertical well and on the source; an n-type semiconductor material formed on the source-channel interface member such that the source is electrically connected to an n-type semiconductor material by the source-channel interface member; a gate dielectric layer formed above the n-type semiconductor layer; a gate formed above the dielectric layer; and a drain formed on the insulating layer in contact with the n-type semiconductor material, wherein when a positive voltage is applied to the gate, current can flow from the source through the source-channel interface member and the channel formed in the semiconductor material to the drain.

[0013] According to another aspect of the present invention, a vertical thin-film transistor is provided, comprising: a substantially flat substrate; an insulating layer formed on the substrate; a drain formed on the insulating layer; a second insulating layer formed on the drain and having an inner surface extending upward from the drain, forming a vertical well; an n-type semiconductor material formed on the inner surface of the well and on the drain; a gate dielectric layer formed above the semiconductor layer; a gate formed above the dielectric layer; a source; and a source-channel interface member formed on the second insulating layer and electrically connecting the source to the n-type semiconductor material, wherein when a positive voltage is applied to the gate, current can flow from the source through the source-channel interface member and the channel formed in the semiconductor material to the drain.

[0014] According to yet another aspect of the present invention, a vertical thin-film transistor is provided, comprising: a substantially flat substrate; an insulating layer formed on the substrate; a drain formed on the insulating layer; a second insulating layer formed on the drain and having an inner surface extending upward from the drain, forming a vertical well; an n-type semiconductor material formed on the inner surface of the well and on the drain; a gate dielectric layer formed above the semiconductor layer; a gate formed above the dielectric layer; a source; and a source-channel interface member formed on the second insulating layer and electrically connecting the source to the n-type semiconductor material, wherein when a positive voltage is applied to the gate, current can flow from the source through the source-channel interface member and the channel formed in the semiconductor material to the drain.

[0015] Other features and advantages of the present invention will become apparent from the following detailed description, along with the accompanying drawings. It should be understood that the detailed description and the specific examples contained herein are merely illustrative, although they represent preferred embodiments as of the time of filing. This is because the idea and scope of the present invention are defined solely by the claims, and various changes and modifications therein will be apparent to those skilled in the art.

[0016] For a better understanding of the various embodiments of the present invention described herein, reference is made to the accompanying drawings. The drawings are not intended to limit the scope of the present invention described herein, but are for improving the clarity of understanding of this specification and are not drawn to scale. Each figure shows the following.

Brief Description of the Drawings

[0017] [Figure 1a] It is a cross-sectional view showing a conventional TFT. [Figure 1b] It is a cross-sectional view showing a conventional TFT. [Figure 1c] It is a cross-sectional view showing a conventional TFT. [Figure 1d] It is a cross-sectional view showing a conventional TFT. [Figure 1e] It is a cross-sectional view showing a conventional TFT. [Figure 2a] It is a cross-sectional view showing a TFT according to an embodiment of the present invention cut along the line A-A in FIG. 2b. [Figure 2b] It is a top view showing the TFT of FIG. 2a. [Figure 2c] It is a cross-sectional view showing a TFT according to another embodiment of the present invention. [Figure 2d] It is a cross-sectional view showing a TFT according to another embodiment of the present invention. [Figure 3a] It is a schematic symbol of the TFT of FIG. 2a. [Figure 3b] It is a cross-sectional view showing a part of the TFT of FIG. 2a operating in the forward active state. [Figure 3c] It is a cross-sectional view showing a part of the TFT of FIG. 2a operating in the off state. [Figure 3d] It is a cross-sectional view showing a part of the TFT of FIG. 2a operating in the zero voltage state. [Figure 4a] It is a schematic symbol of the TFT of FIG. 2c. [Figure 4b] It is a cross-sectional view showing a part of the TFT of FIG. 2c operating in the forward active state. [Figure 4c] This is a cross-sectional view showing a portion of the TFT in Figure 2c, operating in the off state. [Figure 4d] This is a cross-sectional view showing a portion of the TFT in Figure 2c operating in a zero-voltage state. [Figure 5a] Figure 2d shows a schematic symbol for a TFT. [Figure 5b] This is a cross-sectional view showing a portion of the TFT in Figure 2d, operating in a forward-active state. [Figure 5c] This is a cross-sectional view showing a portion of the TFT in Figure 2d, operating in the OFF state. [Figure 5d] This is a cross-sectional view showing a portion of the TFT in Figure 2d operating under zero voltage conditions. [Figure 6] This is a flowchart showing a method for fabricating a TFT according to one embodiment of the present invention. [Figure 7a] This is a cross-sectional view showing one step in TFT fabrication using the method shown in Figure 6. [Figure 7b] This is a cross-sectional view showing one step in TFT fabrication using the method shown in Figure 6. [Figure 7c] This is a cross-sectional view showing one step in TFT fabrication using the method shown in Figure 6. [Figure 7d] This is a cross-sectional view showing one step in TFT fabrication using the method shown in Figure 6. [Figure 7e] This is a cross-sectional view showing one step in TFT fabrication using the method shown in Figure 6. [Figure 7f] This is a cross-sectional view showing one step in TFT fabrication using the method shown in Figure 6. [Figure 7g] This is a cross-sectional view showing one step in TFT fabrication using the method shown in Figure 6. [Figure 7h] Figure 7a is a top view of the TFT fabrication process. [Figure 7i] Figure 7b is a top view of the TFT fabrication process. [Figure 7j] Figure 7c is a top view of the TFT fabrication process. [Figure 7k] Figure 7d is a top view of the TFT fabrication process. [Figure 7l] Figure 7e is a top view of the TFT fabrication process. [Figure 7m] Figure 7f is a top view of the TFT fabrication process. [Figure 7n] Figure 7g is a top view of the TFT fabrication process. [Figure 8a] This is a cross-sectional view showing a TFT being fabricated according to one embodiment of the present invention. [Figure 8b] This is a cross-sectional view showing a TFT being manufactured according to another embodiment of the present invention. [Figure 8c] Figure 8a is a top view of the TFT. [Figure 8d] Figure 8b is a top view of the TFT. [Figure 9a] This is a cross-sectional view showing a vertical TFT according to another embodiment of the present invention. [Figure 9b] This is a cross-sectional view showing another vertical TFT according to one embodiment of the present invention. [Figure 9c] This is a cross-sectional view showing another vertical TFT according to one embodiment of the present invention. [Figure 9d] This is a cross-sectional view showing a vertical TFT fabricated as an asymmetrical embodiment, similar to that of Figure 9b. [Figure 10a] This flowchart shows a method for fabricating TFTs according to another embodiment of the present invention. [Figure 10b] This flowchart shows a method for fabricating TFTs according to another embodiment of the present invention. [Figure 11a] Figures 10a and 10b show a cross-sectional view illustrating one step in the manufacturing process of a TFT. [Figure 11b] Figures 10a and 10b show a cross-sectional view illustrating one step in the manufacturing process of a TFT. [Figure 11c] Figures 10a and 10b show a cross-sectional view illustrating one step in the manufacturing process of a TFT. [Figure 11d] Figures 10a and 10b show a cross-sectional view illustrating one step in the manufacturing process of a TFT. [Figure 11e] Figures 10a and 10b show a cross-sectional view illustrating one step in the manufacturing process of a TFT. [Figure 11f]Figures 10a and 10b show a cross-sectional view illustrating one step in the manufacturing process of a TFT. [Figure 11g] Figures 10a and 10b show a cross-sectional view illustrating one step in the manufacturing process of a TFT. [Figure 11h] Figures 10a and 10b show a cross-sectional view illustrating one step in the manufacturing process of a TFT. [Figure 11i] Figures 10a and 10b show a cross-sectional view illustrating one step in the manufacturing process of a TFT. [Figure 11j] Figures 10a and 10b show a cross-sectional view illustrating one step in the manufacturing process of a TFT. [Figure 11k] Figures 10a and 10b show a cross-sectional view illustrating one step in the manufacturing process of a TFT. [Figure 11l] Figure 11a is a top view of the TFT. [Figure 11m] Figure 11b is a top view of the TFT. [Figure 11n] Figure 11c is a top view of the TFT. [Figure 11o] Figure 11d is a top view of the TFT. [Figure 11p] Figure 11e is a top view of the TFT. [Figure 11q] Figure 11f is a top view of the TFT. [Figure 11r] Figure 11g is a top view of the TFT. [Figure 11s] Figure 11h is a top view of the TFT. [Figure 11t] Figure 11i is a top view of the TFT. [Figure 11u] Figure 11j is a top view of the TFT. [Figure 11v] Figure 11k is a top view of the TFT. [Figure 12a] This flowchart shows a method for fabricating a TFT according to another embodiment of the present invention. [Figure 12b] This flowchart shows a method for fabricating a TFT according to another embodiment of the present invention. [Figure 13a]These are cross-sectional views showing the TFT being fabricated using the methods shown in Figures 12a and 12b. [Figure 13b] These are cross-sectional views showing the TFT being fabricated using the methods shown in Figures 12a and 12b. [Figure 13c] These are cross-sectional views showing the TFT being fabricated using the methods shown in Figures 12a and 12b. [Figure 13d] These are cross-sectional views showing the TFT being fabricated using the methods shown in Figures 12a and 12b. [Figure 13e] These are cross-sectional views showing the TFT being fabricated using the methods shown in Figures 12a and 12b. [Figure 13f] These are cross-sectional views showing the TFT being fabricated using the methods shown in Figures 12a and 12b. [Figure 13g] These are cross-sectional views showing the TFT being fabricated using the methods shown in Figures 12a and 12b. [Figure 13h] These are cross-sectional views showing the TFT being fabricated using the methods shown in Figures 12a and 12b. [Figure 13i] These are cross-sectional views showing the TFT being fabricated using the methods shown in Figures 12a and 12b. [Figure 13j] These are cross-sectional views showing the TFT being fabricated using the methods shown in Figures 12a and 12b. [Figure 13k] These are cross-sectional views showing the TFT being fabricated using the methods shown in Figures 12a and 12b. [Figure 13l] Figure 13a is a top view of the TFT. [Figure 13m] Figure 13b is a top view of the TFT. [Figure 13n] Figure 13c is a top view of the TFT. [Figure 13o] Figure 13d is a top view of the TFT. [Figure 13p] Figure 13e is a top view of the TFT. [Figure 13q] Figure 13f is a top view of the TFT. [Figure 13r] Figure 13g is a top view of the TFT. [Figure 13s] Figure 13h is a top view of the TFT. [Figure 13t]Figure 13i is a top view of the TFT. [Figure 13u] Figure 13j is a top view of the TFT. [Figure 13v] Figure 13 is a top view of the TFT.

[0018] Further aspects and features of the exemplary embodiments described herein will become apparent from the following description in conjunction with the accompanying drawings.

[0019] Detailed description of the invention In the following description, similar components and elements are sometimes given the same reference numbers. Furthermore, as will be understood by those skilled in the art, most semiconductor devices are manufactured in a series of steps, namely, substantially flat layers of material are formed to obtain the desired semiconductor device, and portions of these layers are subsequently removed, processed, and / or replaced with subsequent layers. Thus, as used herein, the terms “horizontal” and “vertical” are used with respect to the planes of these layers, where horizontal refers to a direction substantially parallel to the plane of the layer and vertical refers to a direction substantially perpendicular to the plane of the layer. Similarly, terms such as “up,” “down,” “on top of,” and “below” are also used with respect to these flat layers.

[0020] Furthermore, with respect to the manufacturing of the layers and / or features of the semiconductor devices described herein, the term "forming" these layers and / or features is intended to include, as will be apparent to those skilled in the art, all semiconductor manufacturing techniques suitable for and applicable to the manufacturing herein, namely, but not limited to, deposition (chemical vapor deposition, atomic layer deposition, physical vapor deposition, etc.), sputtering, PECVD (plasma-enhanced chemical vapor deposition), injection and annealing, oxidation, and the like.

[0021] Before describing embodiments of the present invention, examples of prior art TFTs will be explained with reference to Figures 1a to 1e for easier understanding.

[0022] Figure 1a shows a first example of a prior art TFT, which is shown as 100a overall. The TFT 100a has a substrate 120 on which an insulating layer 118 is formed. The TFT 100a further includes a gate 102, a source 106, and a drain 110.

[0023] The gate 102 includes a gate electrode 104 and a gate contact 103, the source 106 includes a source electrode 107 and a source contact 108, and the drain 110 includes a drain electrode 111 and a drain contact 112. As will be apparent to those skilled in the art, the source electrode 107 and the source contact 108 may be made of the same or different materials. In particular, the material of the source contact 108 can be selected to provide a desired work function, while the material of the source electrode 107 can be selected to simplify the connection of the source electrode 107 to other devices, etc. The gate electrode 104 and the gate contact 103, and the drain electrode 111 and the drain contact 112 can also be formed from the same or different materials, as desired.

[0024] The TFT100a also includes a dielectric layer 114 and a semiconductor layer 116. As will be understood by those skilled in the art, the TFT100a may optionally include a gate tuning layer 122.

[0025] The operation of the TFT100a relies on the use of a semiconductor layer 116 as an active material capable of forming a channel. When the semiconductor layer 116 is active, a channel is formed between the source contact 108 and the drain contact 112, and current flows between them. In the illustrated embodiment, an n-type semiconductor is shown.

[0026] In an n-type semiconductor-based TFT (or "n-type TFT"), for example, in TFT100a, the voltage applied to gate 102 (i.e., V) g ) is the threshold voltage (i.e., V) defined by the structure and material of the TFT100a. thWhen the voltage (i.e., V) is exceeded, the TFT becomes active ("on" state). In TFTs containing n-type semiconductors, when a positive gate voltage exceeding the threshold voltage is applied, negatively charged electrons are injected from the source into the n-type semiconductor. d When a current is applied, the injected electrons move from the source to the drain through channels formed in the semiconductor, thereby generating a current, i.e., a source-drain current (I). ds ) or drain current (I d ) occurs.

[0027] Figure 1b, which shows a detailed view of the relevant portion of interest in TFT100a, illustrates the storage layer 130. The storage layer 130 is indicated by a gradient showing the varying electron concentration along the channel through the semiconductor layer 116, where higher electron concentrations (indicated by the darker color of the storage layer 130) are located closer to the source contact 107 than to the drain contact 111.

[0028] When a low drain voltage (compared to the gate voltage) is applied, the charge carrier concentration in the channel tends to become uniform across the channel, and the TFT100a is thought to become "ohmic". When a high drain voltage is applied, the channel becomes "pinch-off", and as shown in Figure 1c, a highly insulated region adjacent to the drain contact 111 begins to form a depletion layer 135, which shows a decrease in charge carrier density.

[0029] Conventional TFTs typically have two channels for current flow. The first channel is formed through an ohmic connection between the source contact 107 and the drain contact 111, and the second channel is formed by an accumulation layer at the interface between the gate dielectric layer 114 and the semiconductor layer 116.

[0030] Due to the channel available below the gate contact 103, the TFT 100a has a limited "off" state due to the current flow through this channel. Therefore, conventional TFTs do not always "pinch off" properly and may have a substantial leakage problem where some current continues to flow even though they are intended to be "off".

[0031] Furthermore, conventional TFTs can experience output resistance problems if the source contact 107 and drain contact 111 are too close to each other. For example, as mentioned above, significant leakage occurs when the distance between the source contact 107 and drain contact 111 is less than approximately 1000 nm, especially less than 200 nm. Therefore, conventional TFTs are typically in an "on" state even under zero bias. In many cases, a negative gate voltage must be applied to a conventional TFT to create a depletion layer or depletion region in order to effectively "turn off" the TFT by limiting the current flow between the source contact 107 and drain contact 111.

[0032] Figure 1d shows a source-gate type TFT 100d. The TFT 100d is similar to the TFT 100a, except that the source 106' of the TFT 100d is made of Schottky metal and the source 106 and drain 110 of the TFT 100a are ohmic contacts. In some cases, the TFT 100d may also differ from the TFT 100a in terms of manufacturing method, semiconductor material, or both. The TFT 100d can utilize the asymmetry between the source 106' and the drain 110 to enhance conductivity between the source 106' and the drain 110.

[0033] Figure 1e shows another type of source-gate TFT100e. The TFT100e is similar to the TFT100a, except that both the source 106' and drain 110' of the TFT100e are made of Schottky metal. Unlike the TFT100d, the TFT100e utilizes the symmetry between the source contact 106' and the drain contact 110'.

[0034] However, both TFT100d and TFT100e face similar challenges to those described above for TFT100a, especially when fabricated in smaller dimensions.

[0035] Figure 2a shows a cross-sectional view of a TFT200a according to one embodiment of the present invention, cut along line 2A-2A in Figure 2b. As shown, the TFT200a includes a gate 202, a source 206, and a drain 210. The gate 202 includes a gate electrode 204 and a gate contact 203, the source 206 includes a source electrode 208 and a source contact 207, and the drain 210 includes a drain electrode 212 and a drain contact 211. Similar to the case of the conventional TFT100a described above, each electrode and contact of these features can be formed from the same material, or the materials can be selected separately as desired. For example, the source contact 207 can be formed from a material selected for its desired work function, while the source electrode 208 can be selected from a material that is better suited for connection to other components of the circuit, such as a metallization layer.

[0036] The TFT200a also includes a dielectric layer 214 and a semiconductor layer 216. The TFT200a may have a gate tuning layer 222 as an optional means. These layers and the TFT200a as a whole are formed on an insulating layer 218 formed on top of the substrate 220. In many environments, the substrate 220 is assumed to be a silicon wafer commonly used in semiconductor manufacturing, but the present invention is not limited thereto, and the substrate 220 may actually be a broad range of materials including, but not limited to, glass, ceramics, metals, flexible polymers or other plastics.

[0037] In the illustrated embodiment, the semiconductor layer 216 is an n-type semiconductor layer. The n-type semiconductor layer 216 is a semiconductor material selected so that it can be formed at a temperature of less than 300°C, preferably. Examples of materials suitable for the semiconductor layer 216 include, but are not limited to, zinc oxide, tin oxide, indium gallium zinc oxide, gallium oxide, germanium oxide, and the like.

[0038] Unlike conventional TFTs, the TFT200a further includes a source-channel interface member 250, which in this embodiment is a layer of p-type semiconductor material extending from a source contact 207 to a drain contact 211 below the semiconductor layer 216. The source-channel interface member 250 electrically connects the source contact 207 to the semiconductor layer 216, while the source contact 207 is electrically isolated from the semiconductor layer 216 elsewhere. Furthermore, in this example, the source-channel interface member 250 electrically connects the semiconductor layer 216 to the drain contact 211.

[0039] The gate contact 203 may include any conductive elemental material or material compound. Examples of materials usable for the gate contact 203 include titanium, titanium nitride, chromium, hafnium, tantalum nitride, or any other single or bimetallic element or bimetallic compound. The gate electrode 204 may be formed from the same material as the gate contact 203, or from other materials that provide the desired properties for connecting the gate electrode 204 to other components.

[0040] Source 206 and drain 210 may include any conductive elemental material or material compound. In particular, source contact 207 and drain contact 211 may be metals or degenerate (highly doped) semiconductors. Examples of suitable materials that can be used in source contact 207 and / or drain contact 211 include nickel, tungsten, molybdenum, aluminum, gold, copper, cobalt, ruthenium, titanium nitride, tantalum nitride, silicon, and / or any III-V compound semiconductor having high conductivity. In some cases, drain contact 211 is made of the same material as source contact 207. In other cases, drain contact 211 is made of a material with higher conductivity that can reduce the barrier to electron transport than the material used in source contact 207.

[0041] The source-channel interface member 250 is provided to store complementary excess negative charge and functions to deplete the channel in at least the region of the semiconductor layer 216 adjacent to the source contact 207. In this way, the source-channel interface member 250 functions as an electron transport barrier, thereby substantially preventing current from passing through the semiconductor layer 216 when the TFT 200a is in the "off" state.

[0042] The operation of the source-channel interface member 250 can be achieved in a variety of configurations, including p-type semiconductors, piezoelectric inductive dipoles, controllable tunnel barriers, combinations thereof, or other mechanisms that modulate the injected current by an externally applied electric field.

[0043] For example, when implemented as a p-type semiconductor, the source-channel interface member 250 can be formed from the element germanium, or by using a p-type dopant in the relevant portion of the semiconductor layer 216. In other cases, the source-channel interface member 250 can be made of an oxide or sulfide, or another element corresponding to Group VI(A) of the periodic table, or a chalcogen, such as oxygen, sulfur, selenium, tellurium, or polonium.

[0044] The source-channel interface member 250 can also be formed by catalytic growth of the material forming the source contact 207. In this case, oxygen can preferentially move to the source-channel interface, thereby creating the source-channel interface member. In other cases, the source-channel interface member 250 can be formed by depositing a p-type dopant, such as a p-type metal oxide or other semiconductor, by deposition techniques, such as atomic layer deposition, sputtering physical deposition, or chemical deposition.

[0045] In the embodiment of TFT200a, the source-channel interface member 250 is formed as a continuous member extending from the source contact 207 to the drain contact 211. The source-channel interface member 250 only needs to be positioned adjacent to the source contact 207 for electrical connection between the source contact 207 and the semiconductor layer 216, but depending on the manufacturing process used to produce the TFT200a, it can also be formed as a layer extending between the source contact 207 and the drain contact 211, as a layer adjacent only to the source contact 207, or as a layer adjacent to both the source contact 207 and the drain contact 211, respectively.

[0046] To prevent charge depletion during the "on" state of the TFT200a, it may be desirable to form the semiconductor layer 216 by compositional control so that it is highly n-type near the source contact 207 and the drain contact 211. In other embodiments, the semiconductor layer 216 is formed to be highly n-type near the source contact 207, the drain contact 211, and the gate contact 203 so that the threshold voltage of the TFT200a can be adjusted. Thus, the characteristics of the TFT200a can be controlled based on the location and degree of n-type doping in the semiconductor layer 216.

[0047] As shown in Figure 2a, the dielectric layer 214 isolates the gate contact 203 from the semiconductor layer 216. The dielectric layer 214 prevents electron flow to the gate contact 203, allowing electrons to form a channel between the source contact 207 and the drain contact 211, which has a high electron concentration. The dielectric layer 214 may consist of a material such as hafnium oxide (HfO2), zirconium dioxide (ZrO2), silicon dioxide (SiO2), silicon nitride (Si3N4), or any other suitable material conceivable to those skilled in the art.

[0048] The TFT200a may also have a gate tuning layer 222 as an optional means. As will be apparent to those skilled in the art, the gate tuning layer 222 may, if desired, be a layer of metal atoms used to adjust the effective barrier height and / or the work function of the gate contact 203.

[0049] In a TFT200a, typically the gate electrode 204, source electrode 208, and drain electrode 212 are each formed from a metal with high conductivity, such as copper or aluminum, and these metals are used to electrically connect the corresponding electrodes to the appropriate elements of the rest of the integrated circuit on which the TFT200a is formed.

[0050] The TFT200a also includes an insulating layer 218 formed on a substrate 220. The substrate 220 serves as the foundation for building components and devices such as transistors and integrated circuits, and the insulating layer 218 is the substrate 220 dielectrically isolated from the source contacts 207 and drain contacts 211. Examples of materials for the insulating layer 218 include silicon dioxide (SiO2), silicon nitride (Si3N4), and aluminum oxide (Al2O3), and examples of materials for the substrate 220 include silicon, glass, plastic materials and / or flexible polymers, printed circuit boards, etc. In some environments, for example in the case shown in Figure 2a, the source-channel interface member 250 extends between the source contacts 207 and the drain contacts 211, but depending on the material of the substrate 220, it can also function as an insulating layer 218, in which case the insulating layer 218 would be formed before the source contacts 207 and drain contacts 211 are formed.

[0051] As described above, the TFT200a has improved operating characteristics compared to conventional TFTs, and is intended to operate at particularly high threshold voltages, especially when fabricated with channel length dimensions of 1000 nm or less.

[0052] As described above, the source-channel interface member 250 is used to form a complementary excess negative charge storage area and functions to deplete the channel in at least the region of the semiconductor layer 216 adjacent to the source contact 207. In a TFT fabricated according to an embodiment of the present invention, for example, TFT200a, the distance from the gate contact 203 to the source contact 207 through the gate dielectric layer 214, the semiconductor layer 216, and the source-channel interface member 250 is selected such that the electric field induced by the voltage applied to the gate contact 203 lowers the stopping potential of the complementary excess negative charge storage area introduced by the source-channel interface member 250, causing the TFT, i.e., TFT200a, to be in the "on" state. In the absence of such a gate voltage application, the stopping potential causes the TFT to be in the "off" state.

[0053] The TFT200a can be fabricated with its various elements formed within a specified thickness range. As will be apparent to those skilled in the art, the primary limiting factor is that the gate contact 203 must be sufficiently electrically close to the source contact 207, thereby allowing the threshold voltage applied to the gate 202 to effectively reduce the barrier to electron flow into the semiconductor layer 216 induced by the source-channel interface member 250. Insufficient electric field induction reduces the ability of the TFT200a to be turned on. This is very similar to a well-known criterion such as the Ada(η) coefficient, typically referred to as the Ada(η) coefficient.

[0054] In the first example of TFT200a, the semiconductor layer 216 is formed with a thickness of approximately 20 nm (dielectric constant of approximately 8), the source-channel interface member 250 is formed with a thickness of approximately 2 nm (dielectric constant of approximately 10), and the dielectric layer 214 is formed with a thickness of approximately 10 nm (dielectric constant of approximately 24).

[0055] In another example of the TFT200a, the semiconductor layer 216 is formed with a thickness of approximately 5 nm (dielectric constant of 17), the source-channel interface member 250 is formed with a thickness of approximately 0.5 nm (dielectric constant of approximately 10), and the dielectric layer 214 is formed with a thickness of approximately 5 nm (dielectric constant of approximately 24).

[0056] The actual selection of the vertical thicknesses of the semiconductor layer 216, the dielectric layer 214, and the source-channel interface member 250 depends to some extent on the properties of the selected materials and the fabrication techniques used. However, given the disclosures herein, certain of these selections are well within the capabilities of those skilled in the art.

[0057] Figure 2c shows a cross-sectional view of a TFT200c according to another embodiment of the present invention. In the TFT200c, the source-channel interface member 250 is not a continuous layer extending between the source contact 207 and the drain contact 211, but rather is formed only at the respective locations of the source contact 207 and the drain contact 211. In the TFT200c, the source-channel interface member 250 can be formed by catalytic growth of the metal forming the source contact 207 and the drain contact 211. In some cases, the source-channel interface member 250 consists of an oxide or sulfide, or another element corresponding to Group VI(A) of the periodic table, or a chalcogen.

[0058] Figure 2d shows a cross-sectional view of another TFT200d according to another embodiment of the present invention. In the TFT200d, the source-channel interface member 250 is formed only at the source contact 207 and can be formed by catalytic growth of the metal forming the source contact 207. In this case, the material forming the drain contact 211 can be selected to be "noble," that is, not to interact immediately with the oxidizing agent. The source-channel interface member 250 can be formed from an oxide or sulfide, or another element corresponding to Group VI(A) of the periodic table, or a chalcogen.

[0059] The presence or absence of the source-channel interface member 250 on the drain contact 211 alters the electrical characteristics of the TFT200c. In the TFT200c, the absence of the source-channel interface member 250 on the drain contact 211 causes the threshold voltage of the TFT200c to increase by approximately 0.1V to 2V compared to the TFT200a and TFT200b. If the source-channel interface member 250 is formed by catalytic growth of oxide or sulfide, it becomes easy to form the source-channel interface member 250 on the drain contact 211 in addition to forming it on the source contact 207, eliminating the need for additional processing to remove the source-channel interface member 250 from the drain contact 211 unless a reduction in the threshold voltage is desired.

[0060] Next, we refer to Figures 3a to 3d, which show a TFT300 according to one embodiment of the present invention and its performance under various operating conditions. In the following set of Figures 3, 4, and 5, the substrate and insulating layer have been omitted from the figures for ease of understanding.

[0061] In the various embodiments illustrated herein, a source-channel interface member 250 adjacent to the source contact 207 introduces a structure functionally similar to that of a bipolar junction transistor (BJT). In the TFT embodiments disclosed herein, a field-effect transistor (FET) architecture is effectively combined with a structure at the source contact that is similar to the emitter of a BJT.

[0062] These BJT-like structures have a collector and base coupled by either direct ion short-circuiting or collection of recombination centers, and electrons are injected from the emitter-like structure into the source contact 207. A schematic diagram of the TFT 300 having source-channel interface members 350 at the source contact 307 and drain contact 311 is schematically shown in Figure 3a.

[0063] Figure 3b shows the TFT300 in the forward active state (here, V DS >0VGS >.V Threshold ) shows a cross-sectional view of an example of the TFT300 when it is in the state. In FIG. 3c, the TFT300 is in the off state (here V DS > 0V GS < V Threshold ). The cross-sectional view of FIG. 3b when in the state is shown. In FIG. 3d, the TFT300 a is in the 0V state (here V DS > 0V GS < V Threshold ). A cross-sectional view of an example of the TFT300 is shown.

[0064] The TFT300 is similar to the TFT200a in FIG. 2a. The source contact 307, source electrode 306, drain contact 311, drain electrode 310, gate electrode 302, gate contact 303, dielectric layer 314, source-channel interface member 350, and n-type semiconductor layer 316 are the same as the respective elements described above with respect to the TFT200a in FIG. 2a.

[0065] In an embodiment of the TFT300, similar to the TFT200a, the source-channel interface member 350 extends between the source contact 307 and the drain contact 311, whereby a structure similar to a gate-limited junction field-effect transistor (JFET) or an accumulation MOSFET having a BJT equivalent at the locations of the source contact 307 and the drain contact 311 is formed.

[0066] FIG. 3b shows the operation of the TFT300 in the forward active state (or "on" state). The forward active state occurs when the drain voltage (V DS ) is greater than 0V and the gate voltage (V GS ) is greater than the threshold voltage (V Threshold ). In the forward active state, an electron accumulation layer 330 is formed under the gate contact 303 below the dielectric layer 314. In this operating state, the accumulation layer 330 enables the electron flow from the source contact 307 to the drain contact 311.

[0067] Figure 3c shows the TFT300 in "off" mode. The gate voltage (V) of the TFT300 is GS ) is the threshold voltage (V Threshold The operation turns off when the drain voltage (V) falls below this level. In the illustrated embodiment, the drain voltage (V) falls below this level. DS A depletion region 335 is formed in the semiconductor layer 316 below the gate contact 303 so that the electron flow between the source contact 307 and the drain contact 311 is significantly reduced or substantially eliminated even when the voltage becomes greater than 0V.

[0068] Figure 3d shows the TFT300 in a "0V" state, where no voltage is applied to the TFT300. Gate voltage (V GS When the voltage is 0V or near 0V, the depletion region 335 becomes more prominent and approaches both the source contact 307 and the drain contact 311, thereby significantly reducing or substantially eliminating the electron flow between the source contact 307 and the drain contact 311. This causes the TFT 300 to enter an enhanced-off state, reducing or substantially eliminating parasitic channels in the TFT 300.

[0069] Next, refer to Figures 4a to 4d, which show a TFT400 according to one embodiment of the present invention and its performance under various operating conditions. The TFT400 is the same as the TFT200c in Figure 2c, and the source contact 407, drain contact 411, gate contact 403, dielectric layer 414, source-channel interface member 450, and n-type semiconductor layer 416 are the same as the respective elements described above with respect to the TFT200c in Figure 2c.

[0070] Figure 4a shows a schematic model of the TFT400. 402In the embodiment of the TFT400, the source-channel interface member 450 is formed on the source contact 407 and the drain contact 411 respectively, but does not extend between the two. This effectively forms a JFET-like device with a structure similar to a BJT on the source contact 407 and the drain contact 411, as in Figure 3a.

[0071] Figure 4b shows the forward active state (here, V DS >0V GS >V Threshold A TFT400 is shown in the diagram. Similar to the TFT300 in the forward-active state, the electron storage layer 430 is formed below the gate contact 403, beneath the dielectric layer 414. In this operating state, the storage layer 430 enables the flow of electrons from the source contact 406 to the drain contact 410.

[0072] Figure 4c shows the "off" state (here, V DS >0V GS <V Threshold A TFT400 is shown in this case, where the depletion region 435 blocks the electron flow between the source contact 407 and the drain contact 411.

[0073] Figure 4d shows the TFT400 in the 0V state. Similar to the TFT300, the gate voltage of the TFT400 (V GS When the voltage is 0V or near 0V, the depletion region 435 becomes more prominent and approaches both the source contact 407 and the drain contact 411, thereby significantly reducing or substantially eliminating the electron flow between the source contact 407 and the drain contact 411. As a result, the TFT 400 enters an enhanced-off state, and the parasitic channels of the TFT 400 are reduced or substantially eliminated.

[0074] The differences in the gradient and configuration (e.g., thickness) of the storage layer and depletion region between TFT300 and TFT400 arise from the difference in the degree of presence or absence of source-channel interface material in the device. The presence of source-channel interface material at a higher concentration and with greater dispersion achieves better depletion layer control of the n-type semiconductor channel.

[0075] Next, refer to Figures 5a to 5e, which show a TFT500 according to one embodiment of the present invention and its performance in various operating states. The TFT500 is similar to the TFT200d in Figure 2d, and the source electrode 507, source contact 506, drain electrode 511, drain contact 510, gate electrode 503, gate contact 502, dielectric layer 514, source-channel interface member 550, and n-type semiconductor layer 516 are the same as the source electrode 208, source contact 207, drain electrode 212, drain contact 211, gate electrode 204, gate contact 203, dielectric layer 214, source-channel interface member 250, and semiconductor layer 216 in Figure 2d.

[0076] Figure 5a is a schematic model of the TFT500. In the TFT500, the source-channel interface member 550 is adjacent only to the source contact 506, thereby effectively forming a JFET with a BJT at the source contact 506.

[0077] Figure 5b shows the TFT500 in the forward active state, Figure 5c shows the TFT500 in the "off" state, and Figure 5d shows the TFT500 in the 0V state.

[0078] The characteristics of the storage layer 530 and depletion regions 535,540 of TFT500 are similar to those of TFT300 in Figure 3a and TFT400 in Figure 4a, where depletion region 540 is an asymmetrical version of depletion region 435 in Figure 4d under the 0V condition.

[0079] Next, we refer to Figure 6, which is a flowchart illustrating a method 600 for manufacturing a TFT according to one embodiment of the present invention. The method 600 in Figure 6 is shown for TFT 700 with reference to Figures 7a to 7n, which show examples of various steps related to the method, and for TFT 800 with reference to Figures 8a to 8d. a We will also discuss the TFT800b.

[0080] As used herein, the terms “form” or “to form” are intended to encompass any suitable method for manufacturing the structures described herein. Here, “form” or “to form” may include processes such as atomic layer deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, sputtering, ion implantation, oxidation, electrochemical deposition, and molecular beam epitaxy. The selection of a particular suitable process is entirely at the discretion of those skilled in the art.

[0081] Method 600 begins with step 605, in which the source contact 707 and Drain Contact 711 A layer is formed on the top of the insulating layer 718, which is then formed on the top of the substrate 720 as shown in Figure 7a. Figure 7a shows a cross-sectional view of the TFT 700 cut along line BB in Figure 7h, and Figure 7h shows the corresponding top view.

[0082] As described above, the insulating layer 718 can be formed from materials such as silicon dioxide (SiO2), silicon nitride (Si3N4), and aluminum oxide (Al2O3). The substrate 720 may be any suitable substrate that is suitable for functioning as a foundation for building components and devices such as transistors and integrated circuits, image sensors and displays, and includes, but is not limited to, silicon, flexible polymers and other plastics, ceramic materials, optical glass, and metals.

[0083] In some cases, the source contact 707 and drain contact 711 are formed by deposition via a lithography process. However, as will be apparent to those skilled in the art, the method of forming the source contact 707 and drain contact 711 is not particularly limited and may be formed by various other processes that will be apparent to those skilled in the art.

[0084] If the source contact 707 and the drain contact 711 are formed from the same material, both the source contact 707 and the drain contact 711 can be formed simultaneously in the same step 605. If the source contact 707 and the drain contact 711 are made from different materials, the source contact 707 and the drain contact 711 can be formed in separate steps.

[0085] In step 610, the source-channel interface member 750 is formed. In the example shown in Figure 7b, a cross-sectional view taken along line CC in Figure 7i, the source-channel interface member 750 is formed on the tops of the source contact 707 and drain contact 711 and extends across the region of the insulating layer 718 between them. The source-channel interface member 750 may be a p-type semiconductor formed by any suitable technique, including, but not limited to, a deposition technique such as atomic layer deposition, sputtering, or chemical vapor deposition.

[0086] However, the source-channel interface member 750 can also be formed in a different manner, for which refer to Figure 8a, a cross-sectional view of the TFT800 cut along line DD in Figure 8c, similar to that in Figure 7b, according to another embodiment of the present invention. In the TFT800, the source-channel interface member 850 is then Formed on an insulating layer 818 formed on a substrate 820These are formed by controlled oxidation of the metallic structures beneath both the source contact 807 and the drain contact 811. As shown in the figure, this results in a source-channel interface member 850 formed on the source contact 807 and a source-channel interface member 850 formed on the drain contact 811.

[0087] Figure 8b shows a cross-sectional view of TFT800b according to another embodiment of the present invention, cut along line EE in Figure 8d. In TFT800b, the drain contact 811 is formed from a noble (i.e., non-oxidizing) material, and the source-channel interface member 850 is formed by controlled oxidation of a metallic structure just below the source contact 807. As illustrated, in this way the source-channel interface member 850 is produced only on the source contact 807.

[0088] Referring again to Figures 7a to 7n and method 600, in step 615, the n-type semiconductor layer 716 is formed. Figure 7c shows a cross-sectional view cut along line FF in Figure 7j after the semiconductor layer 716 has been formed across the TFT 700, including the top of the source-channel interface member 750.

[0089] In step 620, the dielectric layer 714 is formed. As shown in Figure 7d, a cross-sectional view taken along line GG in Figure 7k, the dielectric layer 714 is formed throughout the device, including the top of the semiconductor layer 716. The dielectric layer 714 is preferably formed from a material having a high dielectric constant, but other materials such as SiO2 or Si3N4 may also be used.

[0090] In step 625, the gate contact 703 is formed. As shown in Figure 7e, a cross-sectional view taken along line HH in Figure 7l, the gate contact 703 is formed on the dielectric layer 714. In some cases, a gate tuning layer 722 can be formed between the dielectric layer 714 and the gate contact 703 as an optional means. In this case, as shown in Figure 7e, the gate tuning layer 722 is formed first, and the gate contact 703 is formed on top of this gate tuning layer 722.

[0091] In step 630, unwanted portions of the dielectric layer 714 and the semiconductor layer 716 and source-channel interface member 750 beneath it are removed. Figure 7f, a cross-sectional view of the TFT 700 cut along line II in Figure 7m, shows that the gate contact 703 can be used as a mask to remove portions of the dielectric layer 714 and the semiconductor layer 716 and source-channel interface layer 750 beneath it.

[0092] In step 635, the gate electrode 704, source electrode 708, and drain electrode 712 are formed, as shown in Figure 7g, which is a cross-sectional view taken along line JJ in Figure 7n.

[0093] In some situations, it may be desirable to fabricate TFTs according to embodiments of the present invention in a vertical configuration. Accordingly, Figures 9a, 9b, and 9c show embodiments of TFTs formed in this vertical orientation. As will be understood by those skilled in the art, vertically formed TFTs enable an increase in "packaging density" (i.e., an increase in the number of devices in a given horizontal region), which can be important for several applications, such as display screens or image sensors. Furthermore, since TFTs according to the present invention can be fabricated on various substrates, TFTs according to the present invention can be "stacked" vertically against each other to increase device density, which can be highly desirable for many different applications. For example, the present invention allows for the formation of layers of vertical TFTs and any associated interconnects or other components, and then allows for the formation of layers of insulating material, such as silicon dioxide, on these layers, and further allows this insulating layer to be used as a substrate and insulating layer for another set of TFTs formed on it. It is envisioned that by forming multiple layers of TFTs in this manner, circuit density can be significantly increased compared to the prior art.

[0094] Figure 9a shows a TFT900a including a gate 902, a source 906, and a drain 910. The gate 902 includes a gate contact 903 and a gate electrode 904, the source 906 includes a source contact 907 and a source electrode 908, and the drain 910 includes a drain contact 911 and a drain electrode 912. The TFT900a also includes a dielectric layer 914 around the gate 902 of the TFT900a, and further includes a first insulating layer 918 and a second insulating layer 925 formed above the substrate 920. The TFT900a further includes an n-type semiconductor layer 916 and a source-channel interface member 950. Optionally, the TFT900a may also include a gate tuning layer 922 as shown.

[0095] In the TFT900a, the source 906, including the source contact 907 and source electrode 908, is located at the bottom (with respect to the orientation of the figure) of the TFT900a, which is formed on top of the first insulating layer 918. The second insulating layer 925 is formed above the portion of the source contact 907, leaving the portion of the source contact 907 exposed in the center of the TFT900a. The drain contact 911 and the drain electrode 912 formed on it are formed on both sides of the exposed portion of the source contact 907. The source contact 907 is insulated from the drain contact 911 by the second insulating layer 925.

[0096] In the TFT900a, the source-channel interface member 950 is formed on the exposed portion of the source contact 907, the inner surface of the second insulating layer 925, and on the drain contact 911. The gate contact 903 is surrounded by a gate tuning layer 922 (as an optional means), which in turn is surrounded by a dielectric layer 914. The semiconductor layer 916 is formed between the dielectric layer 914 and the source-channel interface member 950.

[0097] Figure 9b shows TFT900b, which is similar to TFT900a but with a modified extent and position of the source-channel interface member 950, and is another embodiment of the present invention.

[0098] In particular, in the TFT900b, the source-channel interface member 950 is formed as a layer extending across the entire upper surface of the source contact 907. As shown in Figure 9b, unlike the embodiment in Figure 9a, the source-channel interface member 950 is not present on the inner surfaces of the second insulating layer 925 and the drain contact 911 of the TFT900b. Instead, a semiconductor layer 916 is formed between the dielectric layer 914, the inner surface of the second insulating layer 925 and the drain contact 911.

[0099] Figure 9c shows a cross-sectional view of TFT900c according to another embodiment of the present invention. TFT in Figure 9a 900aAnd, similar to TFT900b in Figure 9b, TFT900c is a realization of a vertical TFT according to one embodiment of the present invention.

[0100] However, TFT900c differs from TFT900a and TFT900b described above in that its bottom contact is the drain contact 911. In contrast, the top contact of TFT900c is the source contact 907. As shown in Figure 9c, the source-channel interface member 950 is formed around the source contact 907. The source-channel interface member 950 is separated from the drain contact 911 by the presence of the second insulating layer 925 and separated from the dielectric layer 914 by the semiconductor layer 916.

[0101] Embodiments in Figures 9a, 9b, and 9c illustrate a "symmetrical" realization of a vertical TFT according to an aspect of the present invention; however, it will be readily apparent to those skilled in the art that such symmetry is not essential. For example, Figure 9d shows an asymmetrical realization of TFT900d, where the right side (with respect to the orientation of the figure) of TFT900b is omitted. Various other asymmetrical and / or reduced-area realizations of the vertical TFT according to an aspect of the present invention will also be apparent here to those skilled in the art.

[0102] As will be apparent to those skilled in the art, TFT900a, TFT900b, TFT900c, and TFT900d function similarly to other embodiments of the present invention disclosed herein. As described above, TFT900a, TFT900b, TFT900c, and TFT900d can be formed as vertical cylinders, parallelepipeds, hexagonal prisms, etc., and these various possible shapes allow for the selection of the "footprint" of TFT900a, TFT900b, TFT900c, and TFT900d so as to optimize the density at which TFT900a, TFT900b, TFT900c, and TFT900d can be formed within a single device. This provides several advantages, particularly in applications such as DRAM memory where increasing memory cell density is a critical objective.

[0103] Furthermore, as mentioned above, TFT900a, TFT900b, and TFT900c can be "stacked" to increase the circuit element density. In particular, arrays of TFT900a, TFT900b, or TFT900c can be formed on a substrate and / or insulator that covers the lower layer of the circuit elements (including TFT900a, TFT900b, and TFT900c), and these are then covered by another array of TFT900a, TFT900b, and TFT900c formed on the substrate and / or insulator and on top of it, thereby forming a true 3D integrated circuit.

[0104] Next, we refer to Figures 10a and 10b, which are flowcharts of Method 1000 for manufacturing a vertical TFT 1200, similar to the TFT 900a described above. Method 1000 in Figures 10a and 10b will be explained with reference to Figures 11a to 11v, which show the various steps related to the method.

[0105] Method 1000 is initiated in step 1005, in which a source electrode 908 and a source contact 907 are formed on a first insulating layer 918, which itself is then formed on a substrate 920 as shown in Figure 11a. Figure 11a is a cross-sectional view of Figure 11l cut along line KK. The source contact 907 may consist of copper, tungsten, or any other material that can be used to fabricate a vertical transistor as conceivable to those skilled in the art. In particular, the material of the source contact 907 is selected based on the work function and surface oxidation properties of the material in order to provide the desired effect of electron injection into the storage layer during operation of the TFT 1200, as will become apparent below to those skilled in the art. It is also conceivable that the source electrode 908 and the source contact 907 may, if desired, be identical elements.

[0106] In step 1010, a second insulating layer 925 is formed above the source contact 907, as shown in Figure 11b, which is a cross-sectional view taken along line LL in Figure 11m. As can be seen, the second insulating layer 925 is formed over the entire upper surface of the source contact 907. The second insulating layer 925 can be formed using any suitable technique conceivable to those skilled in the art, including polymer spin coating, dielectric chemical deposition, and the like.

[0107] In step 1015, the drain contact 911 is formed as shown in Figure 11c, which is a cross-sectional view taken along line MM in Figure 11n. As shown, the drain contact 911 is formed over the entire upper surface of the second insulating layer 925.

[0108] In step 1020, unwanted material is removed from the drain contact 911. This unwanted material can be removed by any suitable method conceivable to those skilled in the art, such as patterning and etching. Figure 11d, a cross-sectional view taken along line NN in Figure 11o, shows the result of step 1020. It will be apparent to those skilled in the art that by removing unwanted material from the drain contact 911 as desired, the drain contact 911 may be formed in a geometric shape such as a hexagon, thereby increasing the packaging density of the TFT 1200.

[0109] In step 1025, the unwanted portion of the second insulating layer 925 is removed down to the location of the source contact 907, as shown in Figure 11e, which is a cross-sectional view taken along line OO in Figure 11p. In some embodiments, the unwanted portion of the second insulating layer 925 is removed by an etching process selected to stop on the source contact 907 below, but any other suitable method for removing the unwanted portion of the second insulating layer 925, as conceivable to those skilled in the art, may also be used.

[0110] In step 1030, the source-channel interface member 950 is formed on top of the result of step 1025. As shown in Figure 11f, a cross-sectional view taken along line PP in Figure 11q, the source-channel interface member 950 is formed at this point over the entire upper surface of the TFT 1200, including above the drain contact 911 and above the exposed portion of the source contact 907. The source-channel interface member 950 can be formed in various ways, and in one embodiment it is deposited using atomic layer deposition techniques.

[0111] In step 1035, an n-type semiconductor layer 916 is formed above the source-channel interface member 950, as shown in Figure 11g, which is a cross-sectional view taken along line QQ in Figure 11r. The semiconductor layer 916 can be formed in various ways, and in one embodiment, it is deposited using atomic layer deposition techniques.

[0112] In step 1040, a dielectric layer 914 is formed as shown in Figure 11h, which is a cross-sectional view taken along line RR in Figure 11s. The dielectric layer 914 is formed on the semiconductor layer 916. The choice of material for the dielectric layer 914 is not particularly limited, and the dielectric layer 914 may be any suitable material having a high dielectric constant that can be conceived by those skilled in the art.

[0113] In step 1045, a gate tuning layer 922 (as an optional means) can be formed above the dielectric layer 914, and a gate contact 903 is formed above the gate tuning layer 922. The gate tuning layer 922 and the gate contact 903 can be formed in various ways, including atomic layer deposition techniques, as can be imagined by those skilled in the art. If the gate tuning layer 922 is not provided, the gate contact 903 is formed directly on the dielectric layer 914. The result of step 1045 is shown in Figure 11i, a cross-sectional view taken along line SS in Figure 11t.

[0114] In step 1050, unwanted material is removed from the various formed layers to expose the underlying layers or features, as shown in Figure 11j, which is a cross-sectional view taken along line TT in Figure 11u. As illustrated, the drain contact 911, source-channel interface member 950, semiconductor layer 916, dielectric layer 914, gate tuning layer 922, and gate contact 903 are appropriately exposed. The method for removing unwanted material from the various layers is not particularly limited and can be achieved by various methods, including mechanical polishing, wet chemical etching, dry chemical etching, atomic layer etching, etc., as will be apparent to those skilled in the art.

[0115] In step 1055, the drain electrode 912 and the gate electrode 904 are formed. In the embodiment shown in Figure 11k, which is a cross-sectional view taken along line UU in Figure 11v, the drain electrode 912 and the gate electrode 904 are depositable and patternable using a masking approach. However, the method used to form the drain electrode 912 and the gate electrode 904 is not particularly limited, and various suitable methods will be apparent to those skilled in the art.

[0116] Figures 12a and 12b show flowcharts of a method 1100 for manufacturing or producing another embodiment of the TFT 1300, similar to the TFT 900b described above, according to the present invention. Method 1100 will be described with reference to Figures 13a to 13v.

[0117] Method 1100 begins with a substrate 920 on which an insulating layer 918 is formed. In step 1105, a source electrode 908 and a source contact 907 are formed on the insulating layer 918, as shown in Figure 13a, which is a cross-sectional view taken along the line BL-BL in Figure 13l. As will be apparent to those skilled in the art, the source electrode 908 and the source contact 907 may be the same part if they are formed from the same material. Step 1105 is analogous to step 1005 in Figure 10, and Figures 13a and 13l are analogous to Figures 11a and 11l, respectively.

[0118] In step 1110, a p-type semiconductor member 950 is formed on the source contact 907. As shown in Figure 13b, a cross-sectional view taken along the line BM-BM in Figure 13m, the source-channel interface member 950 is formed as a layer extending across the entire upper surface of the source contact 907. The source-channel interface member 950 can be formed in various ways, and in some embodiments it is deposited using atomic layer deposition techniques, but the method of forming the source-channel interface member 950 is not particularly limited and can be formed, for example, by forming a suitable metal oxide by catalytic action of the metal surface of the source contact 907, or by other suitable methods that will be apparent to those skilled in the art.

[0119] In step 1115, a second insulating layer 925 is formed on the source-channel interface member 950, as shown in Figure 13c, which is a cross-sectional view taken along the line BN-BN in Figure 13n. In some embodiments, the second insulating layer 925 is deposited using polymer spin coating, but the method of forming the second insulating layer 925 is not particularly limited, and the second insulating layer 925 can be deposited using, for example, chemical vapor deposition ("CVD") of a dielectric or any other suitable method that is apparent to those skilled in the art.

[0120] In step 1120, the drain contact 911 is formed. As shown in Figure 13d, a cross-sectional view taken along the line BO-BO in Figure 13o, the drain contact 911 is formed over the entire upper surface of the second insulating layer 925. Again, the method for forming the drain contact 911 is not particularly limited, and suitable methods will be obvious to those skilled in the art.

[0121] In step 1125, unwanted material is removed from the drain contact 911, as shown in Figure 13e, which is a cross-sectional view taken along the line BP-BP in Figure 13p. The method for removing the unwanted material from the drain contact 911 is not particularly limited. Furthermore, if desired, the unwanted material can be removed by etching or the like, thereby allowing the drain contact 911 to be formed in a predetermined pattern, such as the hexagonal pattern or stripe pattern (not shown) shown, in order to increase the packaging density of the resulting TFT.

[0122] In step 1130, the unwanted material is removed from the second insulating layer 925, as shown in Figure 13f, a cross-sectional view taken along line BQ-BQ in Figure 13q. As shown, the second insulating layer 925 has been removed up to the source-channel interface member 950.

[0123] Steps 1135 to 1155 of Method 1100 are analogous to steps 1035 to 1055 of Method 1000 described above. In step 1135, shown in Figure 13g, which is a cross-sectional view taken along the line BR-BR in Figure 13r, an n-type semiconductor layer 916 is formed above the source-channel interface member 950. The n-type semiconductor layer 205 can be formed by various methods, including atomic layer deposition techniques, as will be apparent to those skilled in the art.

[0124] In step 1140, a dielectric layer 914 is formed above the semiconductor layer 916. This is shown in Figure 13h, which is a cross-sectional view taken along the line BS-BS in Figure 13s. Here again, the dielectric layer 914 can be formed in various suitable ways as will be apparent to those skilled in the art.

[0125] In step 1145, a gate contact 903 is formed above the dielectric layer 914, as shown in Figure 13i, a cross-sectional view taken along the line BT-BT in Figure 13t. As shown, optionally, a gate tuning layer 922 can be formed on the dielectric layer 914 before the gate contact 903 is formed. The gate tuning layer 922 and the gate contact 903 can be formed by any suitable process conceivable to those skilled in the art, for example, by atomic layer deposition techniques.

[0126] In step 1150, the TFT 1300 is processed to remove unwanted material and expose the underlying layers and features, as shown in Figure 13j, which is a cross-sectional view taken along the line BU-BU in Figure 13u. The material removed to expose the layers and features in Figure 13j can be removed by any suitable method, for example, by mechanical polishing of the TFT 1300. In the illustrated embodiment, the underlying layers are exposed and a hexagonal pattern is formed.

[0127] In step 1155, the drain electrode 912 and gate electrode 904 are formed. As shown in Figure 13k, a cross-sectional view taken along line BV-BV in Figure 13v, the drain electrode 912 and gate electrode 904 can be patterned with a hexagonal pattern, a stripe pattern or other pattern by a masking process, if desired.

[0128] As is evident so far, the present invention includes various embodiments of novel semiconductor devices. In particular, the present invention discloses a TFT having improved performance even when fabricated with channel dimensions of less than 200 nm.

[0129] Another advantage of semiconductor devices according to embodiments of the present invention is that they can be fabricated in a back-end ("BEOL") process.

[0130] As is known to those skilled in the art, semiconductor manufacturing processes are often divided into front-end processes ("FEOL") and back-end processes. Conventionally, transistors, capacitors, resistors, and inductors of integrated circuits are first formed on a wafer by the FEOL process. Once these devices are fabricated on the wafer, they are then processed by the BEOL process, in which the metallization layer and bonding sites are formed.

[0131] Conventionally, once the FEOL process on a wafer (or other substrate) is completed, the wafer is exposed to the temperatures required for the fabrication of conventional semiconductor devices, which destroys the semiconductor structures and semiconductor devices already formed on the wafer by the FEOL process. Therefore, it has generally been impossible to add additional devices to a wafer during the BEOL process.

[0132] In recent years, attempts have been made to fabricate TFTs using indium gallium zinc oxide ("IGZO") as a BEOL process, either as a semiconductor material or channel material. While some success has been achieved with these devices, they generally tend to fail to perform as desired, exhibiting low threshold voltages, high leakage levels, or poor "off" characteristics. Furthermore, the processes used to fabricate IGZO devices have proven difficult to control, resulting in fragile devices that may not withstand other BEOL processes such as annealing.

[0133] In contrast, TFTs according to embodiments of the present invention can be fabricated by techniques and processes that have been shown to function well even with semiconductor or channel lengths of less than 200 nm without damaging previously fabricated FEOL devices or structures and without being damaged by other BEOL processes.

[0134] As detailed above, the TFTs according to embodiments of the present invention utilize six basic fabrication processes, namely, source formation, drain formation, gate formation, semiconductor formation, dielectric or insulator formation, and source-channel interface member formation, each typically achievable in multiple ways. The selection of one or more suitable alternative forms for each of these fabrication processes used in the fabrication of BEOL TFTs or FEOL or alternative TFTs is within the scope of the ordinary skill of those skilled in the art.

[0135] For example, in determining how to fabricate a TFT according to the present invention, if it is desired that the temperature not exceed 300°C during the fabrication process, source formation, drain formation, and gate formation are achieved by sputtering and patterning; semiconductor layer formation is achieved by atomic layer deposition; dielectric or insulator formation is achieved by atomic layer deposition; and source-channel interface member formation is achieved by oxidation of the source contact (if the material is an oxidizing metal) or by sputtering a degenerately doped single-atom semiconductor layer, such as sputtering of germanium or silicon. As is clear, each of these selected fabrication techniques is operable at temperatures below 300°C, so there is no impact on devices and structures previously fabricated in the FEOL process.

[0136] Furthermore, as is clear from the above, the present invention provides a novel thin-film semiconductor switching device that exhibits good performance even when manufactured with a semiconductor length or channel length of less than 1000 nm, and particularly less than 200 nm. Manufacturing techniques and methods for the novel device are also taught, and these techniques and methods make it possible to manufacture the novel device as a BEOL device.

[0137] The embodiments described above are intended to be examples of the present invention, and those skilled in the art should be able to modify and change them without departing from the scope of the present invention as defined solely by the appended claims.

Claims

1. It is a thin-film transistor, It is located on a substrate or insulating layer and includes a source contact, A drain disposed on the substrate or insulating layer and spaced apart from the source, An n-type semiconductor layer containing tin oxide extends between the source and the drain so as to form a carrier channel between the source and the drain, The channel interface member is located between the source contact and the n-type semiconductor layer and is in contact with the source contact and the n-type semiconductor layer. The channel interface member is operable to deplete the carrier channel in the region of the n-type semiconductor layer adjacent to the source contact in order to reduce leakage current when the thin-film transistor is in the off state. The drain includes a drain contact, The channel interface member is also positioned between the drain contact and the n-type semiconductor layer and is in contact with the drain contact and the n-type semiconductor layer, in a thin-film transistor.

2. The thin-film transistor according to claim 1, wherein the channel interface member includes a p-type semiconductor.

3. The thin-film transistor according to claim 1, wherein the channel interface member includes a p-type metal oxide.

4. The thin-film transistor according to claim 1, wherein the channel interface member includes the oxidation material of the source contact.

5. The thin-film transistor according to claim 1, wherein the channel interface member includes a layer of material deposited on the source contact.

6. The thin-film transistor according to claim 1, wherein the source contact contains ruthenium.

7. The thin-film transistor according to claim 6, wherein the channel interface member layer contains ruthenium oxide.

8. The thin-film transistor according to claim 1, wherein the source contact contains cobalt.

9. The thin-film transistor according to claim 8, wherein the channel interface member layer contains cobalt oxide.

10. The thin-film transistor according to claim 1, wherein the n-type semiconductor layer is formed by atomic layer deposition.

11. The gate dielectric layer above the n-type semiconductor layer, The thin-film transistor according to claim 1, further comprising a gate contact above the gate dielectric layer.

12. The thin-film transistor according to claim 11, wherein the gate dielectric layer contains hafnium oxide.

13. The thin-film transistor according to claim 1, wherein the channel interface member extends between the source contact and the drain contact.

14. The thin-film transistor according to claim 1, wherein the channel interface member is separated into a portion in contact with the source contact and the n-type semiconductor layer and a portion in contact with the drain contact and the n-type semiconductor layer.

15. A method for manufacturing thin-film transistors, A step of forming a source and a drain on a substrate or insulating layer, wherein the drain is spaced apart from the source, the source includes a source contact, and the drain includes a drain contact; The steps include forming a channel interface member that contacts the source contact in the source and the drain contact in the drain, The step includes forming an n-type semiconductor layer containing tin oxide between the source and the drain, in contact with the channel interface member, The channel interface member is operable to deplete a carrier channel in a region of the n-type semiconductor layer adjacent to the source contact in order to reduce leakage current when the thin-film transistor is in the off state.

16. The method according to claim 15, wherein the channel interface member includes a p-type semiconductor.

17. The method according to claim 15, wherein the channel interface member contains a p-type metal oxide.

18. The method according to claim 15, wherein the step of forming the channel interface member includes oxidizing the material of the source contact.

19. The method according to claim 15, wherein the step of forming the channel interface member includes forming a layer of material on the source contact.

20. The method according to claim 15, further comprising using atomic layer deposition to form the channel interface member on the source contact.

21. The source contact contains ruthenium, The method according to claim 15, wherein the channel interface member layer contains ruthenium oxide.

22. The source contact contains cobalt, The method according to claim 15, wherein the channel interface member layer contains cobalt oxide.

23. The method according to claim 15, wherein the step of forming the n-type semiconductor layer includes forming the n-type semiconductor layer using atomic layer deposition.

24. The steps include forming a gate dielectric layer above the n-type semiconductor layer, The method according to claim 15, further comprising the step of forming a gate contact above the gate dielectric layer.

25. The method according to claim 24, wherein the gate dielectric layer comprises hafnium oxide.

26. The method according to claim 15, wherein the step of forming the channel interface member is to form a channel interface member that extends from the source contact to the drain contact.

27. The method according to claim 15, wherein in the step of forming the channel interface member, the channel interface member that contacts the source contact and the channel interface member that contacts the drain contact are arranged separately.

28. A method for manufacturing thin-film transistors, The process includes using an atomic layer deposition (ATD) method to deposit tin oxide between the source and the drain to form an n-type semiconductor layer in contact with the channel interface member, using a wafer that includes a source and a drain located on a substrate or insulating layer, and a channel interface member formed in contact with the source contact of the source and the drain contact of the drain, The channel interface member is operable to deplete a carrier channel in a region of the n-type semiconductor layer adjacent to the source in order to reduce leakage current when the thin-film transistor is in the off state.

29. The method according to claim 28, further comprising using atomic layer deposition to form the channel interface member.

30. The method according to claim 28, further comprising using atomic layer deposition to deposit a gate dielectric layer above the n-type semiconductor layer.

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