Adaptive charge measurement circuit for data converter

Abstract

A data conversion circuit and a method of operating the data conversion circuit are disclosed. In some embodiments, the data conversion circuit includes a charge measurement circuit. In some embodiments, the charge measurement circuit is a capacitive transimpedance amplifier (CTIA). In some embodiments, the data conversion circuit includes a CTIA, a quantizer, a digital-to-analog converter, a summer, and a digital filter. In some embodiments, the data conversion circuit includes an analog-to-digital converter electrically coupled to the CTIA and the digital filter. In some embodiments, the method includes integrating an input signal with the CTIA, determining whether the CTIA output signal is greater than a threshold, and reducing or refraining from reducing the CTIA output signal based on a determination of whether the CTIA output signal is greater than a threshold. TIFF2024502327000011.tif207146

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims priority to U.S. Provisional Patent Application No. 63 / 132,309, filed Dec. 30, 2020, the entire disclosure of which is incorporated herein by reference for all purposes.

[0002] Field This disclosure generally relates to data converters. More specifically, this disclosure relates to data converters that include charge measurement circuits such as capacitive trans - impedance amplifiers (CTIA).

Background Art

[0003] Background Columns of sensor arrays (e.g., X - ray panels) may include large parasitic capacitances and / or large parasitic resistances. Depending on the distance from the pixel to the read - out circuit input and / or the pixel resistance, the parasitic resistance can range from a few ohms to 5 kilo - ohms. Variations in pixel and column parameters (e.g., of different sensor arrays) can affect the dynamics of charge movement (e.g., differences in transient waveforms associated with the same total charge).

[0004] A CTIA may be a charge measurement circuit used to convert charge from a sensor into a voltage value. The advantage of using a CTIA for this purpose is that the DC level of the CTIA output voltage is a function of the total input charge during the integration period. Although noise from circuit components adds noise to the CTIA output voltage, other than the offset noise of the CTIA, the DC level is not affected by the noise from circuit components. The column may be connected to a CTIA configured to move the charge of the selected sensor pixel from the column to the feedback capacitor of the CTIA.

[0005] In some cases, the capacitance of the feedback capacitor may need to be large enough to store the charge moved from the pixel. If this capacitance is large (e.g., in the pF range), it may be necessary for (one or more) feedback capacitors to occupy a large area of ​​the chip. If a CTIA is required for each column, the number of feedback capacitors is the number of columns in the sensor array (e.g., a 500-column array would require capacitors with an area of ​​500pF). Furthermore, because the capacitance value may be large, the corresponding output voltage may be low (due to the Q=CV relationship), requiring subsequent circuitry (e.g., analog-to-digital converter (ADC)) to have higher resolution or sensitivity. In some examples, the CTIA may be configured to obtain variable gain by including feedback capacitors of different values, which further increases the chip area.

[0006] In some examples, a specific feedback capacitor may be suitable for one sensor array size, one type of pixel, and / or one dynamic range, so different CTIA designs may be required for different sensor array sizes, different types of pixels, and / or different dynamic ranges, increasing the cost of designing specific readout circuits for different systems.

[0007] In addition, the charge integration time and the signal digitization time may not overlap. To reduce the time spent reading each row of the sensor, a sample-and-hold circuit may be included to allow simultaneous integration of the charge from the first row and digitization of the charge from the second row, requiring one or two additional capacitors (in addition to the feedback capacitor). The additional capacitors may be the same size as the feedback capacitor to reduce noise (e.g., Johnson noise). The additional capacitors further increase the chip area and limit the chip's ability to be used for different array sizes, different types of sensors, or different dynamic ranges. [Overview of the project]

[0008] overview A data conversion circuit and a method for operating the data conversion circuit are disclosed. In some embodiments, the data conversion circuit includes a charge measuring circuit. In some embodiments, the charge measuring circuit is a capacitive transimpedance amplifier (CTIA). In some embodiments, the data conversion circuit includes the CTIA, a quantizer, a digital-to-analog converter, an adder, and a digital filter. In some embodiments, the data conversion circuit includes an analog-to-digital converter electrically coupled to the CTIA and the digital filter. In some embodiments, the method includes the steps of integrating an input signal using the CTIA, determining whether the CTIA output signal is greater than a threshold, and reducing or stopping the reduction of the CTIA output signal based on the determination that the CTIA output signal is greater than a threshold.

[0009] In some embodiments, the circuit includes an analog input, a charge-transimpedance amplifier (CTIA) electrically coupled to the analog input, a quantizer electrically coupled to the output of the CTIA, a digital-to-analog converter (DAC) electrically coupled to the output of the quantizer, and an adder electrically coupled to the output of the DAC. The CTIA is electrically coupled to the output of the adder, a digital filter electrically coupled to the output of the quantizer, and a digital output electrically coupled to the digital filter. In some embodiments, the circuit allows the CTIA to be integrated adaptively favorably. As a result, a larger capacitor configured to store the entire sensor charge is no longer required, and the circuit may be used to read sensors from different array sizes, different types of sensors, or different dynamic ranges.

[0010] In some embodiments, the method includes the steps of: integrating an input signal using a CTIA of a circuit; determining whether the CTIA output signal at the output of the CTIA is greater than a threshold; reducing the CTIA output signal according to the determination that the CTIA output signal is greater than a threshold; and ceasing to reduce the CTIA output signal according to the determination that the CTIA output signal is less than or equal to a threshold. In some embodiments, a non-temporary computer-readable storage medium stores one or more programs, one or more programs include instructions, and when the instructions are executed by an electronic device having one or more processors and memory, the device causes the device to perform the method.

[0011] In some embodiments, the method allows the CTIA to be integrated adaptively favorably. As a result, a larger capacitor configured to store the entire sensor charge is no longer required in the circuit, and the circuit may be used to read sensors from different array sizes, different types of sensors, or different dynamic ranges. [Invention 1001] Analog input and, A charge transimpedance amplifier (CTIA) electrically coupled to the analog input, A quantizer electrically coupled to the output of the CTIA, A digital-to-analog converter (DAC) electrically coupled to the output of the quantizer, An adder electrically coupled to the output of the DAC, wherein the CTIA is electrically coupled to the output of the adder, A digital filter electrically coupled to the output of the quantizer, The digital output electrically coupled to the digital filter and A circuit that includes this. [Invention 1002] The CTIA includes a feedback capacitor, The aforementioned analog input is electrically coupled to the sensor. The capacitance of the feedback capacitor is smaller than the capacitance of the sensor. The circuit according to the present invention 1001. [Invention 1003] The circuit of the present invention 1001, wherein the adder is configured to reduce the CTIA output signal in response to receiving a high DAC output signal at the output of the DAC. [Invention 1004] The quantizer, Determine whether the CTIA output signal at the output of the CTIA is greater than the threshold, In accordance with the determination that the CTIA output signal is greater than the threshold, a first digital value is output to the DAC. A second digital value is output to the DAC according to the determination that the CTIA output signal is below the threshold. It is configured in such a way. The DAC in question In response to receiving the first digital value, the adder outputs a high DAC output signal. In response to receiving the second digital value, the adder stops outputting the high DAC output signal. It is structured in such a way. The circuit according to the present invention 1001. [Invention 1005] The CTIA further includes an analog-to-digital converter (ADC) electrically coupled to the output of the CTIA, The ADC, The output of the CTIA receives a voltage corresponding to the residual charge, Provides a digital value corresponding to the residual charge. It is configured in such a way, The digital output includes the digital value corresponding to the residual charge, The circuit according to the present invention 1001. [Invention 1006] The circuit of the present invention 1001 further includes an offset removal circuit configured to remove an offset from the CTIA output signal. [Invention 1007] The circuit of the present invention 1001, wherein the ADC is configured to convert an offset from the CTIA output signal into a digital value of the offset. [Invention 1008] The circuit of the present invention 1001, further comprising a low-pass filter included in the feedback of the CTIA. [Invention 1009] The sensitivity of the circuit is determined based on the operating frequency of the circuit. The operating frequency of the circuit is based on the integral time of the CTIA, The circuit according to the present invention 1001. [Invention 1010] The circuit of the present invention 1001, wherein the digital output signal in the digital output is the digital value of the charge in the analog input of the circuit. [Invention 1011] The circuit of the present invention 1001, wherein the digital output signal at the digital output is the digital value of the current at the analog input of the circuit. [Invention 1012] The circuit of the present invention 1001, wherein the digital output signal at the digital output is the digital value of the voltage at the analog input of the circuit. [Invention 1013] The circuit of the present invention 1001 further includes a variable resistor electrically coupled to the analog input, wherein the variable resistor is configured to reduce the signal level of the input signal at the analog input of the circuit. [Invention 1014] The digital filter includes a finite impulse response (FIR) decimator. The FIR decimator is configured to generate a digital output signal at the digital output based on the signal received from the output of the quantizer. The circuit according to the present invention 1001. [Invention 1015] The circuit of the present invention 1001, wherein the quantizer and the DAC are included in the combination of the quantizer and DAC of the circuit. [Invention 1016] A method including the following steps: The process of integrating the input signal using the CTIA of the circuit; A step of determining whether the CTIA output signal at the output of the CTIA is greater than a threshold; A step of reducing the CTIA output signal according to the determination that the CTIA output signal is greater than the threshold; and A step of stopping the reduction of the CTIA output signal in accordance with the determination that the CTIA output signal is below the threshold. [Invention 1017] A step of electrically coupling a sensor to the CTIA, The sensor provides the input signal, The CTIA includes a feedback capacitor, The capacitance of the feedback capacitor is smaller than the capacitance of the sensor. Process The method of the present invention 1016, further comprising: [Invention 1018] The method of the present invention 1016, further comprising the step of generating a digital output signal corresponding to the aforementioned input signal. [Invention 1019] The input signal is the charge at the analog input of the circuit. The digital output signal is the digital value of the charge. The method of the present invention 1018. [Invention 1020] A non-temporary computer-readable storage medium storing one or more programs, wherein the one or more programs include instructions, and when the instructions are executed by an electronic device having one or more processors and memory, the device... The process of integrating the input signal using the CTIA of the circuit; A step of determining whether the CTIA output signal at the output of the CTIA is greater than a threshold; A step of reducing the CTIA output signal according to the determination that the CTIA output signal is greater than the threshold; and A step of stopping the reduction of the CTIA output signal in accordance with the determination that the CTIA output signal is below the threshold. A non-temporary computer-readable storage medium that enables the execution of a method including the following. [Brief explanation of the drawing]

[0012] [Figure 1] This figure shows an exemplary circuit according to an aspect of the present disclosure. [Figure 2] This figure shows an exemplary waveform of a circuit according to an aspect of the present disclosure. [Figure 3] This figure shows an exemplary timing diagram according to the aspects of this disclosure. [Figure 4] This figure shows an exemplary circuit according to an aspect of the present disclosure. [Figure 5] This figure shows an exemplary circuit according to an aspect of the present disclosure. [Figure 6] This figure shows an exemplary circuit according to an aspect of the present disclosure. [Figure 7] This figure shows an exemplary method according to an aspect of the present disclosure. [Figure 8] This figure shows a method for manufacturing a MEMS system according to one embodiment. [Figure 9] This is a diagram illustrating an example sensor. [Modes for carrying out the invention]

[0013] Detailed description of exemplary embodiments In the following description of embodiments, references are made to the accompanying drawings, which illustrate specific embodiments that form part of this specification and can be implemented. It should be understood that other embodiments may be used and structurally modified without departing from the scope of the embodiments disclosed.

[0014] Figure 1 shows an exemplary circuit 100 according to an aspect of the present disclosure. In some aspects, the circuit 100 is a data converter and includes a CTIA 102, a quantizer 104 electrically coupled to the output of the CTIA, a digital-to-analog converter (DAC) 106 electrically coupled to the output of the quantizer, and an adder 108 electrically coupled to the outputs of the DAC and the CTIA. In some aspects, the circuit 100 is configured to generate a digital output signal 112 (provided, for example, by a digital output 128) corresponding to an input signal 110 at input 114 of the circuit. For example, input 114 is an analog input, and the digital output signal 112 is the converted digital value of the analog input.

[0015] Although the examples in this disclosure are described in relation to a CTIA, it should be understood that the circuits of the disclosure are not limited to processing inputs using a CTIA. For example, the circuits and methods of the disclosure may process inputs using different types of integral amplifiers or current-voltage converters. As another example, more generally, the circuits and methods of the disclosure may process inputs using different charge measuring circuits. In some embodiments, circuit 100 includes a charge measuring circuit (not shown) instead of a CTIA 102. For example, the charge measuring circuit receives a charge at its input (e.g., electrically coupled to input 114) and generates a signal at its output (e.g., electrically coupled to quantizer 104) that reflects the amount of charge.

[0016] For example, the input signal 110 is an analog signal, and the digital output signal 112 is a digital representation of the input signal 110. In some embodiments, the digital output signal 112 represents an analog sensor readout (e.g., sensor charge, sensor voltage, sensor current), and the digital output signal 112 is provided to another part of the sensor system for further processing.

[0017] In some embodiments, the digital output signal 112 is a digital value of the charge at the input 114 of the circuit (e.g., the circuit 100 is configured for charge detection). In some embodiments, the digital output signal 112 is a digital value of the current at the input 114 of the circuit (e.g., the circuit 100 is configured for current detection by measuring the input charge over a period of time or by integrating the input charge). In some embodiments, the digital output signal 112 is a digital value of the voltage at the input 114 of the circuit (e.g., the circuit 100 is configured for voltage detection). For example, to configure the circuit 100 for voltage detection, a voltage-to-current converter is electrically coupled to the CTIA 102. It is understood that the digital output signal 112 may also correspond to other electric quantities at the input 114 of the circuit 100.

[0018] In some embodiments, when circuit 100 is configured for current detection or voltage detection (e.g., to detect a steady current or a steady voltage), circuit 100 operates as a multi-stage noise shaping (MASH) modulator. For example, circuit 100 may operate as a MASH for measuring steady current (e.g., noise current, as opposed to shorter-duration transient or signal currents from a sensor, which may contain larger signal transitions). In some embodiments, while the circuit is operating as a MASH, the quantizer is turned off when the input signal is low enough not to saturate the feedback capacitor (e.g., the integral of the input signal does not saturate the feedback capacitor while the circuit is operating as a MASH) to prevent the accumulation of switching noise. Meanwhile, since the pixels remain connected, thermal noise can be reduced by the ADC (e.g., average noise is reduced).

[0019] In some embodiments, the CTIA 102 includes a feedback capacitor 116, and the input 114 of the circuit is configured to be electrically coupled to a sensor (e.g., a bolometer pixel, an X-ray sensor pixel, a visible image sensor pixel, an infrared image sensor pixel, a MEMS sensor pixel, a sensor pixel that converts environmental information into an electrical signal), and the capacitance of the feedback capacitor is smaller than the capacitance of the sensor. For example, the capacitance of the sensor pixel is 2.6 pF and the capacitance of the feedback capacitor 116 is 0.5 pF. In some embodiments, the capacitance of the feedback capacitor 116 is determined so that the feedback capacitor 116 does not saturate during integration, as will be described in more detail herein. Exemplary sensor readout methods can be referenced in International Publications WO2019204515 and WO2020033930, the disclosures thereof being incorporated herein by reference in their entirety for all purposes.

[0020] In some embodiments, the input signal 110 is integrated using circuit 100. That is, the CTIA 102 integrates portions of the signal 110 (e.g., the charge of a sensor electrically coupled to the CTIA) at different integration times using elements of circuit 100 and / or methods of operating the circuit as disclosed, which will be described in more detail herein. In some embodiments, if the output of the CTIA is greater than a threshold after a portion of the signal has been integrated, the charge on the CTIA is reduced by a certain value (e.g., by subtracting a fixed value 214 from the CTIA output signal). By integrating portions of the input signal at different times and reducing the CTIA output by a certain value after integrating a portion, the CTIA can be integrated in an adaptively favorable manner. As a result, a larger capacitor configured to store the entire sensor charge is no longer required. Furthermore, as will be explained in more detail below, CTIA can be integrated adaptively, so the integration timing (e.g., timing of quantizer decision time, timing of feedback time, number of quantizer decision times, number of feedback times) may be adjusted (e.g., for different input signal levels, for different sensitivities or resolutions, for different CTIA gains), which is advantageous as it allows circuit 100 to be used for a wider input range (e.g., different types of sensors, different sensor array configurations, different dynamic ranges).

[0021] As an exemplary advantage, the disclosed circuits and methods for operating them may allow for smaller feedback capacitance values ​​compared to conventional CTIAs. For example, the integration of output waveform 204 does not involve integrating portions of the input signal at different times and then reducing the CTIA output by a certain value after integrating a portion. CTIAs described herein with smaller feedback capacitors (e.g., CTIA102, CTIA402, Circuit 500, Circuit 600) can integrate the same input as conventional CTIAs but without the need for larger feedback capacitors. Thus, the corresponding output voltages of the CTIAs disclosed herein may be higher (e.g., due to the Q=CV relationship), easing the resolution or sensitivity requirements of subsequent circuits (e.g., ADCs). As another exemplary advantage, since CTIAs can integrate adaptively, the disclosed circuits and methods for operating them can accommodate readouts of different array sizes, different types of pixels, and / or different dynamic ranges. This reduces the need for different CTIA designs and lowers the cost of designing specific readout circuits.

[0022] For example, the circuit may have a maximum allowable analog voltage of 3V and a sensor pixel (e.g., an X-ray sensor pixel) with a maximum charge of 8pC and a capacitance of 2.6pF. Conventional CTIA may further require a correlated dusampler, which requires two additional capacitors with the same capacitance as the sensor pixel. In this exemplary system, the data conversion circuit using conventional CTIA would require approximately 8pF per channel (e.g., three times 2.6pF for the feedback capacitor and two capacitors for correlated dusampler).

[0023] In contrast, if a data conversion circuit using the disclosed CTIA (e.g., CTIA102, CTIA402, circuit 500, circuit 600) is used instead of this exemplary system, a 0.5pF feedback capacitor may be used for the CTIA, and a second 0.5pF capacitor (e.g., offset rejection capacitor 506, offset rejection capacitor 610) may be used for offset rejection, meaning that a capacitance of 1pF per channel is required. In this exemplary system, using a data conversion circuit including the disclosed CTIA can reduce the capacitor area to one-eighth.

[0024] Furthermore, since the CTIA feedback capacitors described herein may not saturate while being integrated, smaller 0.5pF feedback capacitors may be used to integrate charges beyond the capacitance of a conventional CTIA feedback capacitor of 2.6pF. In some embodiments, the effective capacitance of the CTIA feedback capacitors (e.g., feedback capacitor 116, feedback capacitor 416, feedback capacitor 516, feedback capacitor 616) (e.g., corresponding to the total number of charges that the CTIA feedback capacitors can integrate during the integration described herein) may be determined based on the clocks controlling the quantizers (e.g., quantizer 104, quantizer 404). For example, if N1 cycles are available for use by the CTIA (e.g., there are N1 quantizer determination times 210 during integration and N1 feedback times 212 during integration), the effective capacitance of the CTIA feedback capacitor is N1 × (capacitance of the CTIA feedback capacitor). In some embodiments, the number N1 is determined based on the total number N of oversampling rate (OSR) clock cycles, and how the N clock cycles are allocated between the integration time (e.g., integral 308) and the remainder transformation (e.g., remainder transformation and the remainder transformation portion of the FIR output 310). For example, if N1 = 16, the effective capacitance of the CTIA feedback capacitor is 16 × 0.5pF = 8pF, which means that a CTIA with a 0.5pF feedback capacitor can have three times the capacitance compared to a conventional CTIA with a 2.6pF feedback capacitor.

[0025] Furthermore, since CTIAs can be integrated adaptively, CTIAs (e.g., CTIA102, CTIA402, Circuit 500, Circuit 600) may be configured to obtain variable gain by varying the integration time, reducing the need for additional feedback capacitors for different gains. In addition, by integrating as described, the input portions may be transformed simultaneously (e.g., the first portion of the input is integrated and then transformed while the second portion of the input is being integrated), reducing the need for sample-and-hold circuits and additional capacitors without reducing the transformation speed.

[0026] The area efficiency and flexibility of the disclosed circuit may be advantageously suited to array sensors such as X-ray sensors, bolometers, visible image sensors, infrared image sensors, and MEMS sensors, where a set of signals can be read out and converted into a digital format. Without modifying the hardware, the disclosed circuit can be advantageously configured to convert data of different array sizes, different types of sensors, or different dynamic ranges while maintaining at least the accuracy of the corresponding data conversion circuit that integrates in a conventional manner (e.g., by adjusting the integration time).

[0027] As yet another exemplary advantage, the influence of thermal noise on the disclosed circuit (e.g., from parasitic capacitance of the sensor array) may be lower compared to a higher bandwidth sample-and-hold circuit used to capture the output of a conventional CTIA, due to the sigma-delta oversampling performed by the disclosed circuit (e.g., by integrating, i.e., by using a sigma-delta converter in the ADC118, as described herein).

[0028] In some embodiments, the CTIA 102 includes a reset switch 126 electrically coupled in parallel with the feedback capacitor 116. In some embodiments, before the sensor pixels begin transferring charge to the CTIA (e.g., during the feedback capacitor reset time 302), the feedback capacitor 116 is reset by the reset switch 126, and the reset switch 126 is closed (e.g., during the feedback capacitor reset time 302) to remove any residual charge on the feedback capacitor (e.g., to reset the output value of the CTIA (e.g., to leave the output at the offset value)).

[0029] In some embodiments, the quantizer 104 is configured to determine whether the CTIA output signal at the output of the CTIA is greater than a threshold. According to the determination that the CTIA output signal is greater than the threshold, the quantizer 104 outputs a first digital value (e.g., to the DAC 106, to the finite impulse response (FIR) decimator 122). According to the determination that the CTIA output signal is less than or equal to the threshold, the quantizer 104 outputs a second digital value (e.g., to the DAC 106, to the FIR decimator 122). In some embodiments, during integration, the output of the quantizer 104 outputs a binary sequence (e.g., quantizer output waveform 208) based on the quantizer comparison result.

[0030] In some embodiments, the threshold is set to provide a margin or headroom for the integrator output voltage. For example, the threshold prevents the CTIA102 from saturating while the amplifier's dynamic range is being effectively utilized (e.g., the threshold prevents premature reduction of the input signal).

[0031] In some embodiments, the threshold is set based on the capacitance of the feedback capacitor 116. For example, the threshold is less than the level corresponding to the charge storage capacitance of the feedback capacitor 116. In some embodiments, the threshold of the quantizer 104 is adjustable based on the input electrically coupled to the circuit 100, allowing the circuit 100 to be used with different sensor array sizes, different types of sensors, and / or different dynamic ranges.

[0032] In some embodiments, the quantizer 104 is a comparator. In some embodiments, the quantizer 104 compares the output of the CTIA with a threshold during the quantizer determination time of the integral, as will be described in more detail herein.

[0033] As an example, during the quantizer determination time, the quantizer 104 compares the output of CTIA102 with a threshold. If the output level of CTIA102 is greater than the threshold, the quantizer 104 outputs a "high" signal to DAC106; if the output level is less than or equal to the threshold, the quantizer 104 outputs a "low" signal to DAC106.

[0034] In some embodiments, DAC106 is configured to output a high DAC output signal to adder108 in response to receiving a first digital value from quantizer104 (for example, a signal that reduces the CTIA output signal by a certain value (e.g., a fixed value 214) during integration). In some embodiments, the high DAC output signal is this value (for example, the high DAC output signal is the charge corresponding to the value that reduces the charge from the feedback capacitor to reduce the CTIA output level by this value (e.g., the charge corresponding to the voltage being reduced)). In response to receiving a second digital value, DAC106 stops outputting the high DAC output signal to adder108. For example, if quantizer104 outputs a "high" signal to DAC106, DAC106 outputs a high DAC output signal to adder108. If quantizer104 outputs a "low" signal to DAC106, DAC106 stops outputting the high DAC output signal to adder108.

[0035] As an example, the CTIA output voltage is in the range of 0V to 3.3V (for example, the analog voltage rail is 3.3V). The quantizer threshold can be set to 2.8V, which is 2.3V. That is, according to the determination that the CTIA output voltage is greater than the threshold, the DAC outputs a high DAC output signal, and in response to the output of a high DAC output signal, the circuit reduces the output voltage by 2.3V. These values ​​are merely examples, and it should be understood that different output voltage values, quantizer thresholds, and DAC output values ​​may be set.

[0036] In some embodiments, when the quantizer 104 outputs a "low" signal to the DAC 106, the DAC 106 ceases to provide an output. As an exemplary advantage, by ceasing to provide an output when the quantizer 104 outputs a "low" signal to the DAC 106, noise charge (e.g., from charge injection) can be minimized when the quantizer 104 outputs a "low" signal to the DAC 106.

[0037] In some embodiments, the CTIA 102 includes a feedback capacitor 116, which is configured to store a total charge. The CTIA output signal is reduced by a value (e.g., a fixed value 214) corresponding to a charge smaller than the total charge configured to be stored by the feedback capacitor 116. For example, the value (e.g., a fixed value 214) by which the CTIA output signal is reduced is an amount less than the difference between the voltage level corresponding to the charge storage capacitance of the feedback capacitor 116 and the threshold level of the quantizer 104.

[0038] In some embodiments, the quantizer 104 and the DAC 106 are combined into a single component. For example, the combined quantizer and DAC are configured to output the result of comparing the CTIA output with a threshold and a high DAC output signal.

[0039] In some embodiments, the adder 108 is configured to reduce the output signal of the CTIA 102 by a value (e.g., a fixed value 214) corresponding to the high DAC output signal in response to receiving a high DAC output signal from the DAC 106. For example, after a portion of the input signal has been integrated (as shown by, for example, the CTIA waveform 206), an amount corresponding to this value (e.g., a fixed value 214) is reduced from the CTIA output. The portions of the input signal are integrated at different time intervals. An amount corresponding to this value is reduced each time the integrated portion (e.g., the CTIA output) exceeds the threshold of the quantizer 104, preventing the feedback capacitor 116 from saturating. As will be described in more detail below, the portions of the input signal are integrated, and the output of the CTIA is reduced in this way until the last portion of the input signal remains below the threshold level of the quantizer 104, which is the remainder of the CTIA 102 (e.g., residual charge, residual voltage, remainder 216).

[0040] In some embodiments, the adder 108 is electrically coupled to the terminals of a feedback capacitor 116 (e.g., at the input of the CTIA, at the output of the CTIA) to reduce the CTIA output signal by reducing the voltage at the terminals. In some embodiments, the adder 108 is electrically coupled to additional circuit components, and these additional circuit components reduce the CTIA output signal in response to receiving a signal from the adder 108 to reduce the CTIA output signal.

[0041] The adder 108 is illustrated as shown in Figure 1, but it should be understood that the figure is for illustrative purposes only. The adder 108 may be electrically coupled in a manner different from that shown. For example, the adder 108 may be electrically coupled to the output of the CTIA to subtract a value from the output of the CTIA.

[0042] In some embodiments, the circuit 100 includes an ADC 118 electrically coupled to the output of the CTIA 102. The ADC 118 is configured to receive a voltage corresponding to a residual voltage or residual charge at the output of the CTIA 102 and to generate a digital value corresponding to that residual voltage or residual charge. In some embodiments, the digital output signal 112 includes a digital value corresponding to the remainder (for example, the digital value of the residual voltage or residual charge and the binary sequence generated from the quantizer output are processed (for example, by an FIR decimator 122) to generate the digital output signal 112). In some embodiments, the ADC 118 is a sigma-delta ADC.

[0043] In some embodiments, the voltage corresponding to the residual charge (e.g., the voltage of the CTIA output 206 near the end of integration, residual voltage, remainder 216) is less than the threshold of the quantizer 104 (e.g., threshold 218). For example, a portion of the input signal is integrated and reduced in the manner described until a portion of the input signal remains below the threshold level of the quantizer 104 near the end of integration, and that portion is the residual voltage or residual charge of the CTIA 102. The ADC 118 receives the voltage corresponding to the residual charge, converts the residual voltage or residual charge into a digital signal, and the digital signal is provided to the input of the FIR decimator 122, which is described in more detail herein.

[0044] In some embodiments, circuit 100 includes an offset removal circuit 120, which is configured to remove the offset from the output of CTIA 102. For example, the offset removal circuit 120 takes in an offset value. The offset value is subtracted from the voltage corresponding to the residual charge or residual voltage before being provided to the ADC 118, removing the offset from the digital output signal 112 and improving the accuracy of the data conversion of circuit 100.

[0045] In some embodiments, the offset rejection circuit 120 is configured for correlated double sampling. Random noise may be sampled after the reset switch 126 resets the feedback capacitor 116 (e.g., after the feedback capacitor reset 302). In some embodiments, the capacitance of the sensor array may be large, and the noise may be thermal noise in the parasitic array elements, which can cause random charge values. The standard deviation of this random charge is It may be approximately equal to TIFF0007888218000001.tif6128.

[0046] In some embodiments, to remove this random noise, the output of the CTIA is measured by an offset rejection circuit 120, which measures the noise charge once at the start of integration or before integration begins, and once at the end of integration or after integration is complete (e.g., measured multiple times and averaged). The difference between these two measurements (e.g., the difference between these two measurements excludes the offset) is converted to a digital value using an ADC 118 (e.g., a sigma-delta converter). For example, without using the disclosed offset rejection circuits and methods, the offset is 4mV. When the disclosed offset rejection circuits and methods (e.g., offset rejection circuits 120, 400, 500, and 600) are used, the offset is reduced to 1.5mV.

[0047] In some embodiments, the CTIA can be adaptively integrated so that the sensitivity (e.g., resolution) of circuit 100 is based on the circuit's operating frequency, and the circuit's operating frequency is based on the integration time of the CTIA 102. Having sensitivity adjustability based on the operating frequency allows the circuit to be advantageously used for a wider range of applications (e.g., the circuit is suitable for both low-resolution and high-resolution systems).

[0048] For example, increasing the integration frequency (e.g., shortening the time between the integrations of the first and second parts of the input signal, or shortening the timing between the quantizer decision time 210 and the feedback time 212) improves the sensitivity (e.g., resolution) of circuit 100. Conversely, decreasing the integration frequency (e.g., lengthening the time between the integrations of the first and second parts of the input signal, or lengthening the timing between the quantizer decision time 210 and the feedback time 212) decreases the sensitivity (e.g., resolution) of circuit 100. The relationship between the integration time, frequency, and sensitivity of the disclosed circuit will be explained in more detail with reference to Figures 2 and 3.

[0049] In some embodiments, the circuit 100 includes a variable resistor (not shown) (e.g., a MOS transistor) electrically coupled to the input of the circuit, the variable resistor being configured to provide a reduced current level to the input of the circuit to prevent the feedback capacitor from saturating.

[0050] For example, a sensor that stores charge corresponding to data being read or detected begins to discharge. During this time (e.g., t=0), the resistance of the variable resistor is at its initial resistance (e.g., R0), and the sensor is electrically coupled to the variable resistor. As time progresses during this discharge time, the resistance of the variable resistor decreases from R0. By the end of the discharge time (e.g., t=T, when the sensor has completed its discharge), the resistance decreases linearly from R0 to 0. In some embodiments, T is the duration of the integral 308. In some embodiments, T is the duration of the sensor readout 306. In some embodiments, T is a portion of the duration of the sensor readout 306. In some embodiments, the discharge time window is several times longer than the rise time of the signal that turns on an equivalent MOS transistor. Thus, reducing the resistance of the variable resistor over the discharge time window may be different from simply turning on the transistor. For example, the discharge time window is in the range of microseconds, and the rise time of the signal that turns on the MOS transistor is in the range of nanoseconds. The resistance of the variable resistor can be calculated as follows: TIFF0007888218000002.tif9128

[0051] In some embodiments, to control the resistance, a control voltage is electrically coupled to the gate of the MOS variable resistor, increasing the drain-source transconductance from low to high (i.e., the resistance decreases from high to low) with each row time during readout (e.g., by increasing the gate voltage). As described in the above equation, the resistance of the variable resistor decreases linearly from t=0 to t=T, where the resistance at t=0 (e.g., R(0)) is R0, the initial resistance, and after t=0, the resistance decreases linearly as described with respect to the equation, with the resistance (e.g., R(T)) approaching substantially 0 at t=T.

[0052] Equation (1) shows that in the ideal case, R(t) reaches 0 at t=T, but it is understood that the components used to implement the variable resistor may not reach exactly 0 resistance at the end of the discharge time window. In some embodiments, this resistance is the minimum resistance of the variable resistor. For example, if the variable resistor is a MOS transistor, the minimum resistance is determined by the conductance of the transistor (e.g., the transistor's "on" resistance).

[0053] The capacitance of the sensor can be represented by C. The current entering the variable resistor can be calculated as follows: TIFF0007888218000003.tif10128

[0054] By solving for V(t), the voltage across the variable resistor can be calculated as a function of time. TIFF0007888218000004.tif12128

[0055] The current I(t) flowing through a variable resistor can be expressed as follows: TIFF0007888218000005.tif19128

[0056] As shown in equation (4), if the discharge time window T is set to be equal to the initial time constant (e.g., T = C × R0), the current output can be made substantially constant (e.g., I = V(0) / R0). Thus, in some embodiments, the R0 of the variable resistor is determined by the effective capacitance of the sensor (e.g., 1 to 5 pF) and the discharge time window (e.g., the time to read one row of sensors). By converting the discharge current to a constant current, the peak current associated with the transient sensor readout signal can be reduced, preventing the feedback capacitor 116 from saturating with high current.

[0057] In some embodiments, instead of linearly changing the resistance of the variable resistor over the sensor discharge time as described above, the resistor (e.g., a MOS transistor) is driven by a two-state voltage. When driven by a first voltage of two states, the resistor has low impedance, and when driven by a second voltage of two states, the resistor has high impedance. In some embodiments, when the signal associated with the input is at a high level (e.g., due to the transient characteristics of the input signal), the variable resistor is set to have high impedance by driving the variable resistor with a second voltage. The signal waveform can be advantageously reduced, slowing down the signal transmission rate (e.g., the rate at which the feedback capacitor is charged) and preventing the feedback capacitor from saturating (e.g., reducing the need for a larger feedback capacitor). After the signal amplitude has decreased to a lower level (e.g., due to the transient characteristics of the sensor discharge), the variable resistor is set to have low impedance by driving the variable resistor with a first voltage to increase the signal transmission rate (e.g., the rate at which the feedback capacitor is charged).

[0058] In some embodiments, the circuit 100 includes a digital filter. In some embodiments, the digital filter is electrically coupled to the output of the quantizer 104. It is understood that the digital filter may perform operations other than digital filtering. For example, the digital filter may be configured to decode a pulse code modulation (PCM) sequence from the quantizer output 104 and / or the ADC 118. As another example, the digital filter may be configured to combine the signals from the quantizer output 104 and the ADC 118 to produce a digital output signal 112 at the digital output 128.

[0059] In some embodiments, the digital filter includes an FIR decimator 122 (for example, the FIR decimator 122 is electrically coupled to the output of the quantizer 104), and the FIR decimator 122 is configured to receive a signal from the output of the quantizer 104. In some embodiments, the FIR decimator 122 is further configured to receive a digital value (for example, from the ADC 118) corresponding to the residual charge or residual voltage at the output of the CTIA 102. For example, the FIR decimator receives a signal from the output of the quantizer 104 (e.g., a binary sequence representing the input signal 110, obtained by integrating CTIA 102, the quantizer output waveform 208), or a digital value corresponding to the residual charge or residual voltage of the CTIA from the ADC 118, filters these inputs, and provides a digital output signal 112 (e.g., in digital output 128) that more accurately represents the input signal 110.

[0060] In some embodiments, the FIR decimator combines the output from CTIA102 (e.g., representing the integral result) with the output from ADC118 (e.g., representing the CTIA remainder). For example, a set of PCM sequences is created from CTIA102 (e.g., the PCM sequence is generated at the output of quantizer 104 based on the quantizer result (e.g., quantizer output waveform 208)), and ADC118 outputs to the level of possible input signal 110. A vector matrix equation (e.g., equations (5) and (6)) may be set. This equation associates the PCM sequence processed by the FIR tap coefficients with the corresponding analog input signal value. In some embodiments, the input signal is obtained from the outputs of CTIA102 and ADC118 using the following equations. In formula TIFF0007888218000006.tif5128, A1 is the PCM sequence of CTIA102. A2 is the PCM sequence of ADC118, C1 is the FIR filter coefficient of CTIA102, normalized to a sum of 1s. C2 is the FIR filter coefficient for the SD modulator, normalized to a sum of 1. g2 is the weight applied to the ADC's PCM sequence (which should be added to the CTIA's PCM sequence), g1 is the gain of the digital output signal 112 with respect to the input signal 110. μ0 is the offset of the digital output signal 112 relative to the input signal 110.

[0061] In some embodiments, μ is a quantity such as charge, current, or voltage. It is understood that the coefficient determination method of the disclosure is not limited to quantities that can be read by circuit 100. In some embodiments, depending on the specific application, μ is temperature, pressure, or X-ray dose, and the degrees of freedom incorporated into coefficients C1 and C2 may help to linearize other aspects of the system beyond the circuit of the disclosure.

[0062] In some embodiments, the coefficients associated with the FIR decimator 122 (e.g., the coefficients of the FIR filter) are determined using at least one of analytical determination, simulation-based numerical determination, and measurement-based numerical determination.

[0063] For example, C1 and C2 are linearly optimal FIR coefficients determined using at least one of analytical determination, simulation-based numerical determination, and measurement-based numerical determination. In some embodiments, the number of coefficients in C1 is the number of CTIA cycles (e.g., quantizer decision time and feedback time cycles), and the number of coefficients in C2 is the number of oversampling (OSR) cycles of the SD modulator. The constants C1 and the storage filter C2 may be determined using analytical determination (e.g., theoretical analysis). These filter coefficients may be used as default values. More optimal filter coefficients may be determined using simulation-based numerical determination and measurement-based numerical determination for more specific circuit implementations.

[0064] Using simulation-based numerical determination (e.g., numerical simulation), the coefficients will more closely reflect the circuit's structure. Using measurement-based numerical determination (e.g., experiment-based), it is also possible to find optimal coefficients for a particular chip incorporating noise and systematic errors (e.g., op-amp non-idealism, device mismatch). In some embodiments, these coefficients are determined before operating the circuit 100 (e.g., during the manufacturing of the circuit 100, before operating the system containing the circuit 100). In some embodiments, these coefficients are determined or updated while the circuit 100 is operating (e.g., calibration may be performed to determine more appropriate coefficients). In some embodiments, the circuit 100 is calibrated in wafer form, either as a packaged chip or using a probe card embedded in a sensing system, to yield an optimal decimation filter. In some embodiments, the variables in equation (5) (e.g., coefficient weights) are calibrated by operating the circuit 100 without an input signal (e.g., integrating with CTIA without an input signal).

[0065] In some embodiments, in numerical determination based on simulation and numerical determination based on measurement, the input analog values ​​(μ1, μ2, ..., μ N ) is output (A11, A12, ..., A1 N ), (A21, A22, ..., A2 N This is used to generate the following. The number N is greater than or equal to the number of parameters to be determined, which is the number of components in C1 + the number of components in C2 + 3 (for example, for g1, g2, μ0). Numerical methods such as least squares fitting are used to determine C1, C2, g1, g2, μ0 and the linear transformation from output to input. TIFF0007888218000007.tif18128

[0066] In some embodiments, depending on the parameters of chip manufacturing (e.g., fewer parameters), simulation-based numerical determination is advantageously a simpler method for determining coefficients. In some embodiments, simulation-based numerical determination sets the default coefficients for the system, and measurement-based numerical determination is used for more precise values.

[0067] In some embodiments, depending on the chip manufacturing parameters (e.g., more parameters), measurement-based numerical determinations are performed during wafer probe characterization of the ASIC with an on-chip test circuit, such as a stable reference voltage level. When the chip manufacturing parameters are more complex, using measurement-based numerical determinations can more accurately determine the coefficients.

[0068] In some embodiments, the FIR coefficients C1 and C2 are treated as independent variables, and in some examples, the number of independent variables is reduced. For example, in charge measurement, C1 is a constant and C2 is non-zero while the ADC118 is operating (e.g., while the remainder is being transformed). In some examples, further constraints, such as continuity, are applied to further reduce the number of independent variables and reduce the complexity of determining the optimal FIR coefficients.

[0069] In some embodiments, the circuit 100 includes a timing and control circuit 124 that provides timing and control signals for operating the elements of the circuit 100. For example, the timing and control circuit 124 is electrically coupled to the quantizer 104, ADC 118, offset rejection circuit 120, and FIR decimator 122 to control their respective timings. In another example, the timing and control circuit 124 generates timing and control signals for producing the waveforms and timing diagrams described with respect to Figures 2 and 3. The timing and control circuit 124 may also provide timing and control signals for other elements of the circuit 100 (e.g., CTIA 102, DAC 106, adder 108).

[0070] Circuit 100 is illustrated with its elements, but it should be understood that the diagram is for illustrative purposes only. Different or additional elements may be added or removed from Circuit 100 to form the disclosed data converter. The elements described may be electrically coupled or configured differently than those illustrated. For example, the offset rejection circuit 120 may be electrically coupled differently than shown in Figure 1. The offset rejection circuit may be included as part of the CTIA, as described with respect to Figures 5 and 6. As another example, Circuit 100 is shown as converting a single-ended signal, but it should be understood that Circuit 100 may convert a differential signal (for example, the elements of Circuit 100 may be configured for differential signaling). As yet another example, Circuit 100 may not include a digital filter or FIR decimator 122, and the output of the quantizer 104 and / or ADC 118 may provide a digital output signal 112, which is output to subsequent components for further processing.

[0071] As another example, while circuit 100 is shown to include a first-order CTIA in the first stage and an ADC (e.g., a second-order sigma-delta converter) in the second stage, other options for the order of CTIA or ADC and options for quantizers (e.g., single-bit vs. multi-bit) may be included in circuit 100. These options may be determined by system requirements (e.g., accuracy, area, sensor type, sensor array size). For example, the circuit 100 described with respect to Figure 1 may be a simpler architecture that may be advantageous for larger sensor arrays where area efficiency can be a significant constraint.

[0072] Figure 2 shows exemplary waveforms of circuits according to embodiments of the present disclosure. In some embodiments, Figure 2 shows exemplary waveforms of circuits 100, 400, 500, or 600. In some embodiments, the waveforms include an input waveform 202, a conventional CTIA output waveform 204, a CTIA output waveform 206, and a quantizer output waveform 208. In some embodiments, the input waveform 202 is the waveform of an input signal (e.g., input current, input signal 110, input signal 410), the CTIA output waveform 206 is the waveform of a CTIA (e.g., output voltage of CTIA 102, output voltage of CTIA 402, output voltage of circuit 500, output voltage of circuit 600), and the quantizer output waveform 208 is the waveform of a quantizer output (e.g., voltage output of quantizer 104, voltage output of quantizer 404). The conventional CTIA output waveform 204 is the output waveform (e.g., voltage output) of a CTIA without the integration described, which is used to integrate the signal corresponding to the input waveform 202, and is included for illustrative purposes to demonstrate the advantages of CTIA.

[0073] In some embodiments, the operation of circuit 100 is divided into a quantizer determination time 210 (shown by a lighter vertical dashed line) and a feedback time 212 (shown by a darker vertical dashed line). In some embodiments, timing and control circuits (e.g., timing and control circuits 124, 424) provide control signals for these times in the circuit. For example, the timing and control circuits generate a 50% duty cycle square wave clock signal whose rising edge is aligned with the quantizer determination time 210 to control the quantizer determination, and a complement of this clock whose rising edge is aligned with the feedback time 212 to control the feedback that reduces the value. It is understood that the clock signals may have different duty cycles and different shapes.

[0074] As shown in the figure, prior to the first quantizer determination time 210A, the inputs (e.g., corresponding to input waveform 202, CTIA input, input signal 110, and input signal 410) charge the feedback capacitors (e.g., feedback capacitor 116, feedback capacitor 416, feedback capacitor 516, and feedback capacitor 616) and increase the output of the CTIA. At the first quantizer determination time 210A, the value of the CTIA output waveform 206 is compared to a threshold 218 (e.g., the threshold of quantizer 104 or quantizer 404). In some embodiments, the quantizer compares the value of the CTIA output waveform 206 to the threshold 218. As shown in the figure, at the first quantizer determination time 210A, according to the determination that the CTIA output waveform 206 is less than or equal to the threshold 218, the quantizer output waveform 208 is a "low" value (e.g., 0, ground, low logic voltage level).

[0075] Between the first quantizer decision time 210A and the first feedback time 212A, the input continues to charge the feedback capacitor, causing the output of the CTIA to continue to increase. At the first feedback time 212A, as shown in the figure, the DACs (e.g., DAC106, DAC406) receive the quantizer decision and, in accordance with the quantizer decision that the CTIA output waveform 206 is less than or equal to the threshold 218, the DACs do not output a high DAC output signal to the adders (e.g., adder 108, adder 408) (for example, the circuit stops reducing the high DAC output signal from the output of the CTIA).

[0076] Between the first feedback time 212A and the second quantizer determination time 210B, the input continues to charge the feedback capacitor, causing the CTIA output to continue to rise. At the second quantizer determination time 210B, the value of the CTIA output waveform 206 is compared to a threshold 218 (e.g., the threshold of quantizer 104 or quantizer 404). As shown in the figure, at the second quantizer determination time 210B, according to the determination that the CTIA output waveform 206 is greater than the threshold 218, the quantizer output waveform 208 is a "high" value (e.g., 1, high supply value, high logic voltage level).

[0077] Between the second quantizer decision time 210B and the second feedback time 212B, the input continues to charge the feedback capacitor, causing the output of the CTIA to continue to increase. At the second feedback time 212B, as shown in the figure, the DAC receives the quantizer decision and, according to the quantizer decision that the CTIA output waveform 206 is greater than the threshold 218, the DAC outputs a high DAC output signal to the adder. A certain value (e.g., a fixed value 214) is reduced from the output of the CTIA. Thus, the value of the CTIA output waveform 206 is reduced by a fixed value 214 at the second feedback time 212B. Although the CTIA output signal is described as being reduced by a fixed value, it is understood that in some embodiments, during integration, the CTIA output signal may be reduced by different values ​​at different times of the integration.

[0078] Between the second feedback time 212B and the third quantizer determination time 210C, the value of the CTIA output waveform 206 is reduced by a fixed value 214, after which the input continues to charge the feedback capacitor and continue to increase the output of the CTIA. At the third quantizer determination time 210C, the value of the CTIA output waveform 206 is compared to a threshold 218 (e.g., the threshold of quantizer 104 or quantizer 404). As shown in the figure, at the third quantizer determination time 210C, according to the determination that the CTIA output waveform 206 is greater than the threshold 218, the quantizer output waveform 208 is a "high" value (e.g., 1, high supply value, high logic voltage level).

[0079] Between the third quantizer decision time 210C and the third feedback time 212C, the input continues to charge the feedback capacitor, causing the output of the CTIA to continue to increase. At the third feedback time 212C, as shown in the figure, the DAC receives the quantizer decision, and according to the quantizer decision that the CTIA output waveform 206 is greater than the threshold 218, the DAC 106 outputs a high DAC output signal to the adder. A value (e.g., a fixed value 214) is reduced from the output of the CTIA. As a result, the value of the CTIA output waveform 206 is reduced by a value of 214 at the third feedback time 212C.

[0080] As shown in the figure, the value of the input waveform 202 is the same between the second feedback time 212B and the fourth feedback time 212D. Therefore, the value of the CTIA output waveform 206 between the third feedback time and the fourth feedback time 212D changes in the same way as how the CTIA output waveform 206 changes between the second feedback time and the third feedback time 212C.

[0081] As shown in the figure, at the fourth feedback time 212D, the value of the input waveform 202 is reduced from its initial value. Therefore, between the fourth feedback time 212D and the fifth quantizer determination time 210E, after the value of the CTIA output waveform 206 is reduced by a fixed value 214, the input continues to charge the feedback capacitor and continue to increase the output of the CTIA, but at a slower rate compared to the previous rate (for example, because the initial value of the input is higher than this current value of the input). At the fifth quantizer determination time 210E, the value of the CTIA output waveform 206 is compared to a threshold 218 (for example, the threshold of quantizer 104 or quantizer 404). As shown in the figure, at the fifth quantizer determination time 210E, according to the determination that the CTIA output waveform 206 is greater than the threshold 218, the quantizer output waveform 208 is a "high" value (e.g., 1, high supply value, high logic voltage level).

[0082] Between the fifth quantizer decision time 210E and the fifth feedback time 212E, the input continues to charge the feedback capacitor, causing the output of the CTIA to continue to increase (at this slower rate). At the fifth feedback time 212E, as shown in the figure, the DAC receives the quantizer decision and, according to the quantizer decision that the CTIA output waveform 206 is greater than the threshold 218, the DAC outputs a high DAC output signal to the adder. A value (e.g., a fixed value 214) is reduced from the output of the CTIA. Thus, the value of the CTIA output waveform 206 is reduced by a fixed value 214 at the fifth feedback time 212E.

[0083] Between the fifth feedback time 212E and the sixth quantizer determination time 210F, the value of the CTIA output waveform 206 is reduced by a fixed value 214, after which the input continues to charge the feedback capacitor and continue to increase the output of the CTIA. At the sixth quantizer determination time 210F, the value of the CTIA output waveform 206 is compared to a threshold 218 (e.g., the threshold of quantizer 104 or quantizer 404). As shown in the figure, at the fifth quantizer determination time 210E, according to the determination that the CTIA output waveform 206 is less than or equal to the threshold 218, the quantizer output waveform 208 is a "low" value (e.g., 0, ground, low logic voltage level).

[0084] Between the sixth quantizer decision time 210F and the sixth feedback time 212F, the input continues to charge the feedback capacitor, causing the output of the CTIA to continue to increase. At the sixth feedback time 212F, as shown in the figure, the DAC receives the quantizer decision and, in accordance with the quantizer decision that the CTIA output waveform 206 is less than or equal to the threshold 218, the DAC does not output a high DAC output signal to the adder (for example, the circuit stops reducing the high DAC output signal from the output of the CTIA).

[0085] Between the sixth feedback time 212F and the seventh quantizer determination time 210G, the input continues to charge the feedback capacitor, causing the output of the CTIA to continue to rise. At the seventh quantizer determination time 210G, the value of the CTIA output waveform 206 is compared to a threshold 218 (e.g., the threshold of the quantizer 104). As shown in the figure, at the seventh quantizer determination time 210G, according to the determination that the CTIA output waveform 206 is greater than the threshold 218, the quantizer output waveform 208 is a "high" value (e.g., 1, high supply value, high logic voltage level).

[0086] Between the seventh quantizer decision time 210G and the seventh feedback time 212G, the input continues to charge the feedback capacitor, continuously increasing the output of the CTIA. At the seventh feedback time 212G, as shown in the figure, the DAC receives the quantizer decision and, according to the quantizer decision that the CTIA output waveform 206 is greater than the threshold 218, the DAC outputs a high DAC output signal to the adder. A value (e.g., a fixed value 214) is reduced from the output of the CTIA. As a result, the value of the CTIA output waveform 206 is reduced by a fixed value 214 at the seventh feedback time 212G.

[0087] Between the seventh feedback time 212G and the eighth quantizer determination time 210H, the value of the CTIA output waveform 206 is reduced by a fixed value 214, after which the input continues to charge the feedback capacitor and continue to increase the output of the CTIA. At the eighth quantizer determination time 210H, the value of the CTIA output waveform 206 is compared to a threshold 218 (e.g., the threshold of quantizer 104). As shown in the figure, at the eighth quantizer determination time 210H, according to the determination that the CTIA output waveform 206 is less than or equal to the threshold 218, the quantizer output waveform 208 is a "low" value (e.g., 0, ground, low logic voltage level).

[0088] Between the eighth quantizer decision time 210H and the eighth feedback time 212H, the input continues to charge the feedback capacitor, causing the output of the CTIA to continue to increase. At the eighth feedback time 212H, as shown in the figure, the DAC receives the quantizer decision and, in accordance with the quantizer decision that the CTIA output waveform 206 is less than or equal to the threshold 218, the DAC does not output a high DAC output signal to the adder (for example, the circuit stops reducing the high DAC output signal from the output of the CTIA).

[0089] As shown in the figure, at the eighth feedback time 212H, the value of the input waveform 202 is reduced to zero (for example, the electrically coupled sensor finishes discharging and the reading of the electrically coupled sensor is completed). Thus, after the eighth feedback time 212H, the feedback capacitor stops charging, causing the output of the CTIA to become constant. In some embodiments, this constant output of the CTIA 102 after the eighth feedback time 212H is the remainder (e.g., remainder 216, residual voltage, voltage corresponding to residual charge). In some embodiments, an ADC (e.g., ADC 118, ADC 418) receives the remainder, converts the remainder into a digital value, and provides the digital value of the remainder to an FIR decimator (e.g., FIR decimator 122, FIR decimator 422).

[0090] By integrating portions of the input signal at different times and then reducing the CTIA output by a certain value (e.g., a fixed value 214) after integrating a portion of it, the CTIA can integrate adaptively to a favorable degree. As an exemplary advantage, as shown by the difference between conventional CTIA output waveforms 204 and 206 (e.g., the feedback capacitor in a conventional CTIA continues to charge until the input becomes 0), the disclosed circuit and method of operating the circuit may allow for a smaller feedback capacitance value compared to the feedback capacitor of a conventional CTIA that integrates in a conventional manner. A CTIA with a smaller feedback capacitor may be able to integrate the same input as a conventional CTIA with a larger feedback capacitor. Therefore, the corresponding output voltage may be higher (e.g., due to the Q=CV relationship), easing the resolution or sensitivity requirements of subsequent circuitry (e.g., an ADC). As another exemplary advantage, because the CTIA can integrate adaptively, the disclosed circuit and method of operating the circuit may accommodate readouts of different array sizes, different types of pixels, and / or different dynamic ranges, reducing the need for different CTIAs and lowering the cost of designing specific readout circuits.

[0091] Furthermore, since CTIA can be adaptively integrated, it may be configured to obtain variable gain by varying the integration time (e.g., by changing the timing between the quantizer decision time 210 and the feedback time 212), reducing the need for additional feedback capacitors for different gains. In addition, by integrating as described, the input portions may be transformed simultaneously (e.g., the first portion of the input is integrated and then transformed while the second portion of the input is being integrated), reducing the need for sample-and-hold circuits and additional capacitors without reducing the transformation speed.

[0092] The area efficiency and flexibility of the disclosed circuit (e.g., made possible by operating the circuit using the disclosed method) may be advantageously suited to array sensors such as X-ray sensors, visible image sensors, infrared image sensors, and MEMS sensors, where a set of signals can be read out and converted into a digital format. Without modifying the hardware, the disclosed circuit can be advantageously configured to convert data of different array sizes, different types of sensors, or different dynamic ranges while maintaining the accuracy of the corresponding data conversion circuit that integrates in a conventional manner (e.g., by adjusting the timing between the quantizer decision time 210 and the feedback time 212).

[0093] While the waveforms in Figure 2 are shown as having specific relationships with time, it should be understood that the illustrated waveforms are illustrative. Waveforms may have relationships with time different from those illustrated. For example, input waveform 202 may have different relationships with time than those illustrated (e.g., exponential decay, constant values ​​(e.g., by using the disclosed variable resistors at the circuit input), relationships dependent on the electrical characteristics of the sensor pixels (e.g., sensor pixel capacitance, sensor pixel impedance) and / or the sensor array (e.g., sensor array capacitance, sensor array impedance), relationships dependent on the readout method). Based on input waveform 202 and the described integral, the CTIA output waveform 206 and quantizer output waveform 208 are appropriately generated. As another example, the timing of the integral (e.g., the timing of the quantizer decision time 210, the timing of the feedback time 212) may differ from those illustrated, based on system requirements (e.g., sensitivity, resolution, power consumption) and application (e.g., sensor array size, sensor type).

[0094] Figure 3 shows an exemplary timing diagram 300 according to an aspect of the present disclosure. In some aspects, the timing diagram 300 is an explanatory diagram of the operation of circuit 100, circuit 400, circuit 500, or circuit 600. In some aspects, the timing diagram 300 includes five parts: feedback capacitor reset 302, offset removal 304, sensor readout 306, integration 308, and remainder transformation and FIR output 310.

[0095] For example, in the case of a sensor array with 512 rows and a frame refresh rate of 30Hz, the corresponding row time is 65μs. In this example, the feedback capacitor reset time is 302 hours, the offset removal time is 304 hours, the integration time is 12μs, and the remainder transformation and FIR output time is 310 hours, which is 40μs. For example, with a 3.2MHz clock, the offset removal time is 10μs. 304This means that 32 samples are captured, and with a 40 μs remainder conversion and FIR output time, 128 samples are captured by the ADC (e.g., ADC118, ADC418).

[0096] In some embodiments, during the feedback capacitor reset 302, before the sensor pixels begin transferring charge to the CTIA, the feedback capacitors of the CTIA (e.g., feedback capacitor 116, feedback capacitor 416, feedback capacitor 516, feedback capacitor 616) are reset by the reset switches (e.g., reset switch 126, reset switch 426, reset switch 514, reset switch 620) by closing during the feedback capacitor reset 302 time to remove any residual charge on the feedback capacitors (e.g., resetting the output value of the CTIA (e.g., leaving the output at the offset value)).

[0097] In some embodiments, the CTIA offset is removed during offset removal 304. For example, during offset removal 304, an offset removal circuit (e.g., offset removal circuit 120, circuit 400) takes in the offset value, and the offset value is subtracted from the residual charge or residual voltage before being provided to the ADC (e.g., ADC 118, ADC 418) to remove the offset from the digital output signal (e.g., digital output signal 112, digital output signal 412) and improve the accuracy of the circuit's data conversion.

[0098] In some embodiments, correlation offset removal is performed during offset removal 304. For example, the offset removal circuit is configured for correlated double sampling. Random noise may be measured after the reset switch resets the feedback capacitor (e.g., after feedback capacitor reset 302). To remove this random noise, the output of the CTIA is measured by the offset removal circuit, which measures the noise charge once at the start of integration or before the start of integration, and once at the end of integration or after integration is complete (e.g., measured multiple times and averaged). The difference between these two measurements (e.g., the difference between these two measurements excludes the offset) is converted to a digital value using the ADC118 (e.g., a sigma-delta converter).

[0099] In some embodiments, during offset removal 304, the ADCs of the circuit (e.g., ADC118, ADC418) are configured to convert the CTIA offset (e.g., the average value of the offset across multiple samples) into a digital value. The value corresponding to the converted offset is removed from the output signal to better remove the offset component from the digital output signal. For example, before the start of integration, ADC418 converts the CTIA 402 offset into one or more digital values, and these (one or more) digital values ​​of the offset are used for offset removal from the digital output signal 412, as will be described in more detail with respect to Figure 4.

[0100] In some embodiments, the offset removal time 304 is set so that the low-pass filter (as described, for example, with respect to Figures 5 and 6) can sufficiently remove high-frequency noise from the offset signal. In some embodiments, the offset removal time 304 is set to be several times (e.g., 2 to 10 times) larger than the time constant of the low-pass filter (as described, for example, with respect to Figures 5 and 6).

[0101] In some embodiments, during sensor readout 306, sensor pixels are selectively electrically coupled to a circuit for readout (e.g., a row of sensor pixels is selectively electrically coupled to a corresponding number of circuits for readout). In some embodiments, during this time, the sensor pixel charge is transferred to the CTIA for integration (e.g., integration 308). In some embodiments, the transition for the selective coupling of a sensor pixel or a row of sensor pixels to the corresponding circuit is 0.1 μs. In some embodiments, as illustrated, sensor readout 306 takes place between integration 308 and the remainder transformation and FIR output 310. In some embodiments, sensor readout 306 takes place between integration 308 and the remainder transformation and FIR output 310. At the end of sensor readout 306, the sensor pixels are electrically isolated from the circuit. Exemplary methods of sensor readout can be referenced in international applications PCT / US2019 / 027982 and PCT / US2019 / 046066, which are incorporated herein by reference as a whole for all purposes.

[0102] In some embodiments, the integral 308 is performed as described with respect to Figures 1 and 2. The explanations and advantages associated with the integral described will not be repeated here.

[0103] In some embodiments, during the remainder transformation and FIR output 310, the remainder of CTIA is converted to a digital value by an ADC (e.g., ADC118, ADC418) as described with respect to Figures 1, 2, and 4. The digital value of the remainder and the output of the quantizer (e.g., quantizer 104, quantizer 404) (e.g., a sequence of pulses generated from the integral, quantizer output waveform 208) are received by an FIR decimator (e.g., FIR decimator 122, FIR decimator 422). The FIR decimator processes the output of the quantizer or the digital value of the quantizer output and remainder using coefficients determined using the methods described herein to obtain a digital representation of the input signal (e.g., input signal 110, input signal 410). 、Digital output signal ( for example, Digital output signal 112, digital output signal 412 ) Generates.

[0104] Although the timing diagram 300 is shown as containing four parts with a specific order, it is understood that the timing diagram 300 may contain parts with different orders and / or different timings. For example, parts of the timing diagram 300 may overlap (e.g., the integration 308 and the residue transformation and FIR output 310 steps may occur simultaneously). Another example is when the integration continues after the quantizer switching has stopped (e.g., in the case of MASH, the CTIA is electrically coupled to the ADC and the integration continues while the quantizer is turned off).

[0105] Figure 4 shows an exemplary circuit 400 according to an aspect of the present disclosure. In some aspects, the circuit 400 is a data converter (e.g., a sigma-delta converter). In some aspects, the circuit 400 includes the elements described with respect to the circuit 100 in Figure 1. For example, CTIA402 corresponds to CTIA102, quantizer 404 corresponds to quantizer 104, DAC406 corresponds to DAC106, adder 408 corresponds to adder 108, signal 410 at input 414 corresponds to signal 110 at input 114, feedback capacitor 416 corresponds to feedback capacitor 116, reset switch 426 corresponds to reset switch 126, ADC418 corresponds to ADC118 (e.g., sigma-delta converter), FIR decimator 422 corresponds to FIR decimator 122 included in the digital filter, timing and control circuit 424 corresponds to timing and control circuit 124, digital output signal 412 corresponds to digital output signal 112, and digital output 432 corresponds to digital output 128. Some explanations and benefits associated with these elements will not be repeated here.

[0106] In some embodiments, the ADC418 is configured to convert the remainder and offset of the CTIA402. For example, before the start of integration, the ADC418 converts the offset of the CTIA402 into one or more digital values ​​(e.g., the average value of the offset over multiple samples), and the digital value of the offset is used for offset removal from the digital output signal 412. A value corresponding to the converted offset is removed from the digital output signal 412 to better remove the offset component from the digital output signal 412 and to improve the accuracy of the digital output signal 412 (e.g., compared to the input 410).

[0107] In some embodiments, the offset of CTIA402 is smaller than the remainder of CTIA402 (e.g., about 20 times smaller). In some embodiments, the circuit 400 includes resistors 428 and 430. In some embodiments, the offset is scaled (e.g., amplified) by the configuration of resistors 428 and 430. For example, resistor 428 has a resistance 19 times greater than that of resistor 430. When ADC418 is used to convert the offset signal, resistors 428 and 430 are electrically coupled in parallel (e.g., controlled by timing and control circuit 424) and the current generated by the offset signal is amplified 20 times compared to when only resistor 428 is electrically coupled. When ADC418 is used to convert the remainder signal, resistor 428 is electrically coupled. As an illustrative advantage, by amplifying smaller offset signals, ADC418 may be used to convert both the offset and residue signals, potentially eliminating the need for a second, higher-resolution ADC to convert smaller offset signals (for example, a 10-bit resolution ADC may be required instead of a 14-bit resolution ADC that might be required without resistor 430).

[0108] In some embodiments, instead of resistors 428 and 430, the capacitance of the feedback capacitor 416 or the value of the CTIA output is reduced to decrease the required resolution of the ADC 418, thereby increasing the sensitivity at the ADC 418 input during offset rejection (e.g., offset rejection 304).

[0109] Figure 5 shows an exemplary circuit 500 according to an aspect of the present disclosure. In some aspects, the circuit 500 includes elements described with respect to the circuit 100 in Figure 1 and the circuit 400 in Figure 4. For example, the circuit 500 is CTIA102 or CTIA402, the reset switch 514 is reset switch 126 or reset switch 426, and the feedback capacitor 516 is feedback capacitor 116 or feedback capacitor 416. The capacitor 508 and resistor 510 represent the load at the input of the circuit 500 (e.g., the equivalent capacitance and resistance of a sensor and / or corresponding column electrically coupled to the input of the circuit, the equivalent capacitance and resistance of input 114 or input 414). Some descriptions and advantages associated with these elements are not repeated here.

[0110] In some embodiments, circuit 500 is a CTIA including a feedback capacitor 516 and an offset rejection circuit. In some embodiments, the offset rejection circuit is included in the feedback of the CTIA and includes a first switch 502 (shown as closed / conducting), a second switch 504, and an offset sampling capacitor 506. In some embodiments, the capacitance of the offset sampling capacitor 506 is the capacitance of the feedback capacitor 516.

[0111] For example, after the feedback capacitor 516 is reset (e.g., after the feedback capacitor reset 302), the first switch 502 is closed or conducts, causing the offset sampling capacitor 506 and the feedback capacitor 516 to sample the offset voltage of circuit 500 (e.g., the CTIA offset voltage). Since the capacitance of the offset sampling capacitor 506 is equal to the capacitance of the feedback capacitor 516, both capacitors sample the offset voltage. After sampling the offset voltage, the first switch 502 is opened or deconducted, and the second switch 504 is closed or conducts, moving the charge accumulated in the offset sampling capacitor 506 to the input of the amplifier. The moved charge cancels out the offset voltage accumulated in the feedback capacitor 516, eliminating the offset at the output of circuit 500.

[0112] In some embodiments, the time required to move the charge stored in the offset sampling capacitor 506 to the input of the amplifier is limited by the gain-bandwidth product of the amplifier. In some embodiments, the second switch 504 is opened again after the offset is removed at the output of the circuit 500. In some embodiments, the second switch 504 remains closed.

[0113] As an exemplary advantage, the disclosed CTIA may require only one feedback capacitor for different applications, thus simplifying the offset rejection circuitry for the CTIA compared to conventional CTIAs, which may require two or more feedback capacitors for different applications. The offset of the CTIA can be removed simply by adding a first switch 502 and a second switch 504 and an offset capacitor 516 to the CTIA feedback. Since additional offset rejection circuitry may not be required and offset rejection can be included in the CTIA feedback, the circuit area can be reduced compared to conventional CTIAs.

[0114] Figure 6 shows an exemplary circuit 600 according to an aspect of the present disclosure. In some aspects, the circuit 600 includes elements described with respect to the circuit 100 in Figure 1, the circuit 400 in Figure 4, or the circuit 500 in Figure 5. For example, the circuit 600 is CTIA102 or CTIA402, the reset switch 620 is reset switch 126, reset switch 426, or reset switch 514, and the feedback capacitor 616 is feedback capacitor 116, feedback capacitor 416, or feedback capacitor 516. 612 and resistors 614 This represents the load at the input of circuit 600 (e.g., the equivalent capacitance and resistance of the sensor and / or corresponding column electrically coupled to the input of the circuit, and the equivalent capacitance and resistance of input 114 or input 414). Some explanations and benefits associated with these elements will not be repeated here.

[0115] In some embodiments, circuit 600 is a CTIA including a feedback capacitor 616, an offset rejection circuit, and a low-pass filter. In some embodiments, the low-pass filter is included in the feedback of circuit 600. In some embodiments, the low-pass filter and the offset rejection circuit are included in the feedback of circuit 600.

[0116] In some embodiments, the first switch 602, the second switch 604, the capacitor 606, the third switch 608, and the offset sampling capacitor 610 function as a low-pass filter and an offset rejection circuit. In some embodiments, the capacitance of capacitor 606 is smaller than the capacitance of the offset sampling capacitor 610. In some embodiments, the first switch 602, the second switch 604, and the capacitor 606 function as a switch capacitor.

[0117] For example, after the feedback capacitor 616 is reset (e.g., after the feedback capacitor reset 302), the first switch 602 and the second switch 604 alternately switch between closed or conducting and open or non-conducting (e.g., the first and second switches are controlled by complementary clock signals) to cause capacitor 606 to sample a portion of the offset charge and transfer this sampled offset charge to the offset sampling capacitor 610. At the same time, the feedback capacitor 616 samples the offset voltage in the same way that the feedback capacitor 516 samples the offset voltage, as described with respect to Figure 5.

[0118] In some embodiments, f is the frequency of the clock that controls the first switch 602 and the second switch 604. The effective time constant of the low-pass filter is as follows: TIFF0007888218000008.tif10128

[0119] The first switch 602 and the second switch 604 alternately switch, moving the portion of the offset charge from capacitor 606 to the offset sampling capacitor 610. Since the capacitance of the offset sampling capacitor 610 is equal to that of the feedback capacitor 616, both capacitors sample the offset voltage. After sampling the offset voltage, the third switch 608 closes or conducts, moving the charge stored in the offset sampling capacitor 610 to the input of the amplifier. The moved charge cancels out the offset voltage stored in the feedback capacitor 616, eliminating the offset at the output of circuit 600.

[0120] In some embodiments, the time required to move the charge stored in the offset sampling capacitor 610 to the amplifier input is limited by the gain-bandwidth product of the amplifier. In some embodiments, the third switch 608 is opened again after the offset is removed at the output of circuit 600. In some embodiments, the third switch 608 remains closed.

[0121] As an exemplary advantage, the disclosed CTIA may require only one feedback capacitor for different applications, thus simplifying the offset rejection circuitry for the CTIA compared to conventional CTIAs that may require two or more feedback capacitors for different applications. Furthermore, a low-pass filter may be included in the CTIA feedback along with the offset rejection circuitry. By simply adding the first switch 602, the second switch 604, the capacitor 606, the third switch 608, and the offset sampling capacitor 610 to the CTIA feedback, the offset and noise of the CTIA can be removed, resulting in more accurate offset rejection. Since additional offset rejection and low-pass filtering circuits may not be required in the circuitry outside the CTIA, and offset rejection and low-pass filtering can be included in the CTIA feedback, the circuit area can be reduced.

[0122] In addition, a low-pass filter advantageously reduces Johnson noise or broadband noise (e.g., due to parasitic properties of the sensor array, the bandwidth of which is determined by the parasitic resistance and capacitance of the sensor array) before offset sampling, preventing these noises from being sampled during offset sampling and further improving the accuracy of offset rejection. For example, without the help of noise rejection, the accuracy of the data converter is approximately 1 × 10⁻⁶. -15 C (for example, the error between the output and the corresponding input) can be a parasitic capacitance of the sensor column, which can be caused by Johnson noise. In contrast, with the help of noise reduction using the circuits and methods described herein, the accuracy of the data converter with these help can be 1.4 × 10⁻⁶. -16 Improved accuracy of C (e.g., error between the output and the corresponding input) can be achieved. If the input is a 10pC input (e.g., the total amount of charge being integrated is 10pC), the improved data converter can achieve 16 effective bits (ENOB).

[0123] For example, without using the disclosed offset rejection circuit and method, the offset is 4mV. The low-pass filter and offset rejection circuit described with respect to Figure 6 are added to the CTIA feedback with the following parameters: C 610 =0.5pF, f=2MHz, C 606 =0.2pF, τ=1.25us. With the addition of a low-pass filter and offset rejection circuit, the offset is reduced to 1.5mV.

[0124] In some embodiments, resistors are used instead of a switched-capacitor circuit (e.g., a first switch 602, a second switch 604, and a capacitor 606) to create a low-pass filter having the same advantages as described above. For example, returning to the circuit 500 in Figure 5, a resistor with an appropriate resistance value (for example, to obtain a desired cutoff frequency) may be electrically coupled to the first switch 502 (not shown) to create a low-pass filter having the same advantages as described above.

[0125] Figure 7 shows an exemplary method 700 according to an aspect of the present disclosure. In some aspects, method 700 is a method for operating circuit 100, circuit 400, circuit 500, and / or circuit 600. Although method 700 is shown as including the steps described, it will be understood that different sequences of steps, additional steps, or fewer steps may be performed to operate the exemplary data converter without departing from the scope of the present disclosure. Some descriptions and advantages associated with the steps of method 700 have been described with respect to Figures 1 to 6 and will not be repeated here.

[0126] In some embodiments, method 700 includes a step (step 702) of integrating an input signal using a CTIA of a circuit. For example, a first portion of an input signal (e.g., input signal 110, input signal 410, input waveform 202) is integrated by a CTIA (e.g., CTIA 102, CTIA 402, circuit 500, circuit 600) such that it is shown by a CTIA output waveform 206 during adjacent feedback time 212.

[0127] In some embodiments, Method 700 includes the step of using a variable resistor to reduce the current level of an input signal. For example, as described with respect to Figure 1, a variable resistor (e.g., a MOS transistor controlled by a variable voltage to change the effective resistance of a transistor) is electrically coupled to the input of a circuit (e.g., circuit 100, circuit 400) in order to reduce the current level of an input signal (e.g., to reduce the rate at which a feedback capacitor is charged when a high current level causes a high charging rate, thereby preventing the feedback capacitor from saturating).

[0128] In some embodiments, Method 700 includes the step of electrically coupling a sensor to a CTIA. In some embodiments, the sensor provides an input signal, and the CTIA includes a feedback capacitor, the capacitance of which is smaller than that of the sensor. For example, during integration (e.g., integration 308), as described herein, a sensor pixel (e.g., a bolometer pixel, an X-ray sensor pixel, a visible image sensor pixel, an infrared image sensor pixel, a MEMS sensor pixel, a sensor pixel that converts information about the environment into an electrical signal) is electrically coupled to a CTIA (e.g., CTIA 102, CTIA 402, circuit 500, circuit 600). The sensor pixel provides an input signal (e.g., input signal 110, input signal 410, input waveform 202). The CTIA includes a feedback capacitor (e.g., feedback capacitor 116, feedback capacitor 416, feedback capacitor 516, feedback capacitor 616), the capacitance of which is smaller than that of the sensor (e.g., 0.5 pF in one example). Some of the explanations and advantages related to the CTIA feedback capacitor described in Figures 1-6 will not be repeated here.

[0129] In some embodiments, method 700 includes a step (step 704) of determining whether the CTIA output signal at the output of the CTIA is greater than a threshold. For example, a quantizer (e.g., quantizer 104, quantizer 404) determines whether the CTIA output signal is greater than a threshold (e.g., threshold 218) during the quantizer determination time (e.g., 210A to 210I).

[0130] In some embodiments, the method 700 includes a step (step 708) of reducing the CTIA output signal according to a determination that the CTIA output signal is greater than a threshold (step 706).

[0131] For example, a quantizer (e.g., quantizer 104, quantizer 404) determines that the CTIA output signal (e.g., CTIA output waveform 206) is greater than a threshold (e.g., threshold 218) during the quantizer decision time (e.g., 210B, 210C, 210D, 210E, 210G). In accordance with this determination, the quantizer (e.g., quantizer 104, quantizer 404) outputs a decision (e.g., a "high" value) to the DAC (e.g., DAC106, DAC406), and in response to receiving the quantizer decision, the DAC provides a high DAC output signal and, during the feedback time (e.g., 212B, 212C, 212D, 212E, 212G), reduces a certain value from the CTIA output signal (e.g., using adder 108 and adder 408) (e.g., subtracting a fixed value 214 from the CTIA output signal).

[0132] In some embodiments, method 700 includes the step of generating a high DAC output signal according to a determination that the CTIA output signal is greater than a threshold. The CTIA output signal is reduced by a certain value, which is generated based on the high DAC output value. For example, according to a determination that the CTIA output signal (e.g., output of CTIA102, output of CTIA402, output of circuit 500, output of circuit 600) is greater than a threshold (e.g., threshold of the quantizer, threshold 218), the DAC (e.g., DAC106, DAC406) generates a high DAC output signal.

[0133] In some embodiments, the CTIA includes feedback capacitors (e.g., feedback capacitor 116, feedback capacitor 416, feedback capacitor 516, feedback capacitor 616). The feedback capacitors are configured to store total charge, and the CTIA output signal is reduced by a value corresponding to a value less than the total charge. For example, a fixed value 214 corresponds to a value less than the total charge that the feedback capacitors can store (e.g., this value is less than or equal to the highest possible level of the CTIA output waveform 206).

[0134] In some embodiments, the method 700 includes a step (step 712) of stopping the reduction of the CTIA output signal in accordance with the determination that the CTIA output signal is below a threshold (step 710).

[0135] For example, a quantizer (e.g., quantizer 104, quantizer 404) determines that the CTIA output signal (e.g., CTIA output waveform 206) is less than or equal to a threshold (e.g., threshold 218) during the quantizer determination time (e.g., 210A, 210F, 210H). In accordance with this determination, the quantizer (e.g., quantizer 104, quantizer 404) outputs a determination (e.g., a "low" value) to the DAC (e.g., DAC106, DAC406), and in response to receiving the quantizer determination, the DAC stops providing a high DAC output signal at the circuit input (e.g., the DAC stops providing an output). The CTIA output signal is not reduced from the input signal during the feedback time (e.g., 212A, 212F) (e.g., a high DAC output signal is not provided to adder 108, a high DAC output signal is not provided to adder 408).

[0136] In some embodiments, the step of integrating the input signal includes the step of integrating a first portion of the input signal, and method 700 includes the step of integrating a second portion of the input signal using CTIA. For example, after the first portion has been integrated (e.g., a portion of the input signal is integrated between adjacent feedback time intervals), CTIA continues to integrate the second portion of the input signal (e.g., a subsequent portion of the input signal is integrated between the next adjacent feedback time intervals).

[0137] In some embodiments, whether the CTIA output signal at the CTIA output is greater than a threshold is determined while the first part is being integrated in a first time. For example, referring to Figure 2, whether the CTIA output signal at the CTIA output is greater than a threshold is determined during the quantizer decision time (e.g., quantizer Decision time It will be classified as 210A~210I).

[0138] In some embodiments, method 700 includes the step of reducing the CTIA output signal in a second time after a first time, according to the determination that the CTIA output signal is greater than a threshold. The integration of the second part begins in a third time after the second time, starting from the reduced CTIA output signal. For example, referring to Figure 2, according to the determination by the quantizers (e.g., quantizer 104, quantizer 404) that the CTIA output signal is greater than a threshold at quantizer time (e.g., quantizer times 210B, 210C, 210D, 210E, 210G), the CTIA output signal is reduced at the feedback time (e.g., the time between feedback times 212B, 212C, 212D, 212E, 212G), and the second part to be integrated starts from the reduced CTIA output signal at the third time (e.g., between feedback times 212B, 212C, between feedback times 212C, 212D, between feedback times 212D, 212E, and between feedback times 212G, 212H).

[0139] In some embodiments, method 700 includes the step of stopping the reduction of the CTIA output signal at a second time according to a determination that the CTIA output signal is below a threshold. The integration of the second portion begins at a third time from the CTIA output signal. For example, referring to Figure 2, the reduction of the CTIA output signal at the feedback time (e.g., feedback times 212A, 212F) is stopped according to a determination by the quantizer (e.g., quantizer 104, quantizer 404) that the CTIA output signal is below a threshold at the quantizer time (e.g., quantizer times 210A, 210F), and the second portion to be integrated begins at a third time (e.g., between feedback times 212A, 212B and between feedback times 212F, 212G).

[0140] In some embodiments, the operating frequency of a circuit is based on the time between integrals of an input signal, and the sensitivity of a circuit is based on the operating frequency of the circuit. For example, the operating frequency of a circuit (e.g., circuit 100, circuit 400) is based on the timing between the quantizer decision time (e.g., quantizer decision time 210A-210I) and / or the feedback time (e.g., feedback time 212A-212I). Based on the timing between the quantizer decision time and / or the feedback time, the sensitivity of the circuit is set (e.g., the size of the part being integrated is set, thereby setting the resolution of the integral). Having sensitivity adjustability based on the operating frequency allows the circuit to be used advantageously for a wider range of applications (e.g., the circuit is suitable for both low-resolution and high-resolution systems).

[0141] In some embodiments, when the CTIA output signal is below a threshold and the input signal level is 0, the CTIA output signal corresponds to a remainder. For example, near the end of the integration time (e.g., integration 308), the portion of the input signal being integrated (e.g., portion of the CTIA output waveform 206 after feedback time 212G) is a remainder.

[0142] In some embodiments, method 700 includes a step of removing the CTIA offset. For example, the CTIA offset is removed during offset removal 304. For example, offset removal circuit 120 captures the offset value. The offset value is reduced from residual charge or residual voltage before being provided to ADC 118, removing the offset from the digital output signal 112 and improving the accuracy of the data conversion of circuit 100.

[0143] In some embodiments, the offset rejection circuit 120 is configured for correlated double sampling. Random noise may be sampled after the reset switch 126 resets the feedback capacitor 116 (e.g., after the feedback capacitor reset 302). In some embodiments, the capacitance of the sensor array may be large, and the noise may be thermal noise in the parasitic array elements, which can cause random charge values. The standard deviation of this random charge is It may be approximately equal to TIFF0007888218000009.tif6128.

[0144] In some embodiments, to remove this random noise, the output of the CTIA is measured by an offset removal circuit 120, which measures the noise charge once at the start of integration or before integration begins, and once at the end of integration or after integration is complete (e.g., measured multiple times and averaged). The difference between these two measurements (e.g., the difference between these two measurements excludes the offset) is converted to a digital value using an ADC 118 (e.g., a sigma-delta converter).

[0145] In some embodiments, the offset is removed using an offset removal circuit included in the CTIA feedback. For example, an offset removal circuit included in circuit 500 or circuit 600 removes the CTIA offset using the method described with respect to Figures 5 and 6.

[0146] In some embodiments, method 700 includes the step of low-pass filtering the CTIA offset. In some embodiments, a low-pass filter is included in the feedback of the CTIA to low-pass filter the CTIA offset. For example, as described with respect to Figure 5, a resistor (not shown) having a desired resistance (e.g., to achieve a specific cutoff frequency of the filter) is electrically coupled to the first switch 502 in order to remove noise associated with the offset. As another example, as described with respect to Figure 6, a switched-capacitor circuit (e.g., a first switch 602, a second switch 604, and a capacitor 606) having a desired effective resistance (e.g., to achieve a specific cutoff frequency of the filter) is included in the feedback of circuit 600 in order to remove noise associated with the offset.

[0147] In some embodiments, the step of removing the CTIA offset further includes a step of converting the CTIA offset into a digital value of the offset. For example, as described with respect to Figure 4, the offset is converted into a digital value using the ADC 418, and the digital value of the offset is removed from the digital output signal 412 to eliminate the effect of the CTIA offset during the conversion of the input signal.

[0148] In some embodiments, the step of converting the CTIA offset further includes a step of scaling the CTIA offset. For example, as described with respect to Figure 4, the CTIA offset is scaled (e.g., amplified) using resistors 428, 430 to increase the current input to ADC 418 and reduce the sensitivity requirement of the ADC for converting the offset, before converting the offset to a digital value using ADC 418 and removing the digital value of the offset from the digital output signal 412.

[0149] In some embodiments, method 700 includes the step of generating a digital output signal corresponding to an input signal. For example, circuit 100 generates a digital output signal 112, or circuit 400 generates a digital output signal 412. The digital output signal is based on the output of a quantizer (e.g., a binary sequence based on the result of comparing the CTIA output with a quantizer threshold (e.g., quantizer output waveform 208)).

[0150] In some embodiments, the input signal is the charge at the input of the circuit, and the digital output signal is the digital value of the charge. In some embodiments, the input signal is the current at the input of the circuit, and the digital output signal is the digital value of the current. In some embodiments, the input signal is the voltage at the input of the circuit, and the digital output signal is the digital value of the voltage.

[0151] In some embodiments, method 700 includes a step of determining whether the reading of the input signal is complete based on the determination that the CTIA output signal is below a threshold. Method 700 includes a step of outputting the CTIA output signal as a remainder based on the determination that the reading of the input signal is complete. Method 700 includes a step of ceasing to output the CTIA output signal as a remainder based on the determination that the reading of the input signal is not complete.

[0152] For example, referring to Figure 2, at the eighth feedback time 212H, the value of the input waveform 202 is reduced to zero (for example, the electrically coupled sensor finishes discharging and the readout of the electrically coupled sensor is complete). Following the determination that the readout of the input signal is complete, after the eighth feedback time 212H, the feedback capacitor stops charging and causes the output of the CTIA to become constant. This constant output of the CTIA 102 after the eighth feedback time 212H is the remainder (for example, remainder 216, residual voltage, voltage corresponding to residual charge). Following the determination that the readout of the input signal is not complete before the eighth feedback time 212H, the circuit (for example, circuit 100, circuit 400) stops outputting the CTIA output signal as a remainder.

[0153] In some embodiments, the input signal is integrated in a first time interval. For example, referring to Figure 2, the input signal 202 is integrated in a time interval between two of the feedback times 212A to 212H. In some embodiments, it is determined in a second time interval after the first time interval whether the input signal readout is complete. In accordance with the determination that the input signal readout is complete, the CTIA output signal is output as a remainder in a third time interval after the second time interval. For example, referring to Figure 2, it is determined in feedback time 212H whether the input signal readout is complete. It is determined in feedback time 212H that the input signal readout is complete (e.g., the electrically coupled sensor has finished discharging and the readout of the electrically coupled sensor is complete). After feedback time 212H, the feedback capacitor stops charging, causing the CTIA output to become constant. This constant output of CTIA 102 after the eighth feedback time 212H is a remainder (e.g., remainder 216, residual voltage, voltage corresponding to residual charge).

[0154] In some embodiments, the output of the CTIA output signal as a remainder is discontinued based on the determination that the input signal readout is not yet complete. For example, referring to Figure 2, the determination of whether the input signal readout is complete is made before the feedback time 212H. Before the feedback time 212H, it is determined that the input signal readout is not yet complete (for example, an electrically coupled sensor is discharging and the reading of the electrically coupled sensor is being performed), and the circuit (e.g., circuit 100, circuit 400) discontinues outputting the CTIA output signal as a remainder.

[0155] In some embodiments, the digital output signal is further based on the remainder. For example, the digital output signal (e.g., digital output signal 112, digital output signal 412) is based on the remainder of the quantizer output and CTIA (e.g., CTIA 102, CTIA 402), and the remainder (or digital value of the remainder) of the quantizer output and CTIA is provided to an FIR decimator (e.g., FIR decimator 122, FIR decimator 422) to generate the digital output signal.

[0156] In some embodiments, method 700 includes the step of generating a binary sequence and providing the binary sequence to an FIR decimator. The digital output signal is generated by the FIR decimator, and the binary sequence is based on a determination of whether the CTIA output signal at the CTIA output is greater than a threshold. In some embodiments, the step of generating the binary sequence further includes the step of outputting a first binary value according to the determination that the CTIA output signal is greater than a threshold, and the step of outputting a second binary value according to the determination that the CTIA output signal is less than or equal to the threshold. For example, the digital output signals (e.g., digital output signal 112, digital output signal 412) are based on the output of the quantizer. In some embodiments, according to the determination that the CTIA output signal is greater than a threshold, the quantizer outputs a high digital value. According to the determination that the CTIA output signal is less than or equal to the threshold, the quantizer outputs a low digital value. The output of the quantizer is provided to an FIR decimator (e.g., FIR decimator 122, FIR decimator 422) to generate a digital output signal.

[0157] In some embodiments, Method 700 includes the step of providing a remainder digital value to an FIR decimator. The digital output signal is further based on the remainder digital value. For example, the digital output signals (e.g., digital output signal 112, digital output signal 412) are based on the quantizer output and the remainder of the CTIA (e.g., CTIA 102, CTIA 402), and the quantizer output and the remainder digital value are provided to an FIR decimator (e.g., FIR decimator 122, FIR decimator 422) to generate the digital output signal.

[0158] In some embodiments, Method 700 includes the step of generating a digital value of the remainder. For example, the CTIA output signal is the remainder, and an ADC (e.g., ADC118, ADC418) generates a digital value of the remainder (e.g., and provides the digital value of the remainder to an FIR decimator). In some embodiments, the digital value of the remainder is generated using a sigma-delta ADC (e.g., ADC118 is a sigma-delta ADC, and ADC418 is a sigma-delta ADC).

[0159] In some embodiments, Method 700 includes the step of determining a coefficient associated with an FIR decimator using at least one of analytical determination, simulation-based numerical determination, and measurement-based numerical determination. Examples of determining coefficients associated with FIR decimators (e.g., FIR decimator 122, FIR decimator 422) and their advantages are described with respect to Figure 1. These examples are not repeated here.

[0160] In some embodiments, method 700 includes the step of operating the circuit as a MASH modulator. In response to operating the circuit as a MASH modulator, the step of ceasing to determine whether the CTIA output signal at the CTIA output is greater than a threshold. For example, as described with respect to Figure 1, in response to operating the circuit as a MASH modulator, the quantizer 104 is turned off while the input signal continues to be integrated.

[0161] By integrating portions of the input signal at different times and then reducing the CTIA output by a certain value after integrating a portion, the CTIA can integrate adaptively to a favorable degree. As an exemplary advantage, the disclosed circuit and method of operating the circuit may allow for smaller feedback capacitance values ​​compared to the feedback capacitor of a conventional CTIA integrating in a conventional manner (e.g., associated with a conventional CTIA output waveform 204). A CTIA with a smaller feedback capacitor may be able to integrate the same input as a conventional CTIA with a larger feedback capacitor. Therefore, the corresponding output voltage may be higher (e.g., due to the Q=CV relationship), easing the resolution or sensitivity requirements of subsequent circuitry (e.g., an ADC). As another exemplary advantage, because the CTIA can integrate adaptively, the disclosed circuit and method of operating the circuit may accommodate readouts of different array sizes, different types of pixels, and / or different dynamic ranges, reducing the need for different CTIA designs and lowering the cost of designing specific readout circuits.

[0162] Furthermore, since the CTIA feedback capacitor does not saturate while being integrated as described (e.g., as a result of operating the circuit using the method disclosed), the CTIA feedback capacitor can be used to integrate charge beyond the storage capacitance of the conventional CTIA equivalent feedback capacitor. In some embodiments, the effective capacitance of the CTIA feedback capacitor (e.g., corresponding to the total amount of charge that the CTIA feedback capacitor can integrate during integration) may be determined based on the clock controlling the quantizers (e.g., quantizer 104, quantizer 404). For example, if N1 cycles are available for use by the CTIA (e.g., there are N1 quantizer determination times 210 during integration and N1 feedback times 212 during integration), the effective capacitance of the CTIA feedback capacitor is N1 × (capacitance of the CTIA feedback capacitor). In some embodiments, the number N1 is determined based on the total number N of oversampling rate (OSR) clock cycles, and how the N clock cycles are allocated between the integration time (e.g., integral 308) and the remainder transformation (e.g., remainder transformation and the remainder transformation portion of the FIR output 310). For example, if N1 = 16 and the capacitance of the CTIA feedback capacitor is 0.5 pF, the effective capacitance of the CTIA feedback capacitor is 16 × 0.5 pF = 8 pF, which means that a CTIA with a 0.5 pF feedback capacitor can have three times the capacitance compared to a conventional CTIA with a 2.6 pF feedback capacitor.

[0163] Furthermore, since CTIAs can be integrated adaptively, CTIAs (e.g., CTIA102, CTIA402, Circuit 500, Circuit 600) may be configured to obtain variable gain by varying the integration time, reducing the need for additional feedback capacitors for different gains. In addition, by integrating as described, the input portions may be transformed simultaneously (e.g., the first portion of the input is integrated and then transformed while the second portion of the input is being integrated), reducing the need for sample-and-hold circuits and additional capacitors without reducing the transformation speed.

[0164] The area efficiency and flexibility of the disclosed circuit (e.g., made possible by operating the circuit using the disclosed method) may be advantageously suited to array sensors such as X-ray sensors, visible imaging sensors, infrared imaging sensors, and MEMS sensors, where a set of signals can be read out and converted into a digital format. Without modifying the hardware, the disclosed circuit can be advantageously configured to convert data of different array sizes, different types of sensors, or different dynamic ranges while maintaining the accuracy of the corresponding data conversion circuit that integrates in a conventional manner (e.g., by adjusting the integration time).

[0165] As yet another exemplary advantage, the influence of thermal noise on the disclosed circuit (e.g., from parasitic capacitance of the sensor array) may be lower compared to a higher bandwidth sample-and-hold circuit used to capture the output of a conventional CTIA, due to the sigma-delta oversampling performed by the disclosed circuit (e.g., by integrating, i.e., by using a sigma-delta converter in the ADC118, as described herein).

[0166] In some embodiments, a non-temporary computer-readable storage medium stores one or more programs, one or more of which include instructions. When an instruction is executed by an electronic device having one or more processors and memory (for example, an electronic device including the circuits described herein), the instruction causes the electronic device to perform the actions described with respect to Figures 1 to 7.

[0167] While the disclosed circuit is illustrated with the elements shown, it should be understood that the diagram is for illustrative purposes only. Different or additional elements may be added or removed from the disclosed circuit to form the disclosed data converter. The elements described may be electrically coupled or configured differently from those illustrated. For example, while a portion of the circuit is shown as a single-ended circuit, it should be understood that the disclosed circuit may be configured for differential signaling.

[0168] Figure 8 shows a method 800 for manufacturing an electromechanical system according to one embodiment. In a non-limiting example, the electromechanical system may be associated with circuits 100, 400, 500, or 600 (and / or related methods) (for example, circuits 100, 400, 500, or 600 are included in the readout circuit of the electromechanical system). To manufacture the electromechanical system, all or some of the process steps in method 800 may be used and used in a different order. In a non-limiting example, step 814 may be performed before step 812.

[0169] Method 800 includes step 802, the step of providing a substrate. In some embodiments, the substrate is made of glass. In some embodiments, the substrate is low-temperature polycrystalline silicon. In some embodiments, the substrate is a borosilicate containing additional elements for fine-tuning of properties. An example of a borosilicate is provided by Corning Eagle™, which manufactures alkaline earth boroaluminosilicate (a silicate containing boron, aluminum, and various alkaline earth elements). Other variations are available from Asahi Glass™ or Schott™.

[0170] In some embodiments, a flat panel glass process is used to manufacture electromechanical systems. In some embodiments, a liquid crystal display (LCD) process is used to manufacture electromechanical systems. In some embodiments, an OLED display process or an X-ray panel process is used. By using a flat panel glass process, it is possible to increase the substrate size, thereby increasing the number of electromechanical systems per substrate and reducing processing costs. "Panel-level" sizes can include 300mm×400mm, 360mm×465mm, 400mm×500mm, 550mm×650mm, 620mm×750mm, 680mm×880mm, 730mm×920mm, 1100mm×1300mm, 1300mm×1500mm, 1500mm×1850mm, 1950mm×2250mm, 2200mm×2500mm, and 2840mm×3370mm. Furthermore, the cost of thin-film transistors (TFTs) in panel-level manufacturing can also be reduced, which is why, for example, the LCD-TFT process can be beneficial.

[0171] Some embodiments may include mounting of readout integrated circuits (ROICs) which may include circuits 100, 400, 500, and / or 600, as well as flex / PCB mounting. The processes and devices described herein may have the further advantage that the area required for signal processing can be made much smaller than the sensing area defined by sensing physics. Typically, sensors are integrated on top of CMOS circuits, and the area-driving cost leads to technology nodes that are not optimal for signal processing tasks. The processes described herein can free sensors from arbitrary area constraints by using more suitable CMOS and reducing the area required for signal processing, thereby taking advantage of the low cost of FPD (flat panel display) manufacturing. In some embodiments, the ROIC is specifically designed to meet the requirements for sensing specific electromagnetic wavelengths (X-rays, THz, LWIR, etc.).

[0172] In some embodiments, the MEMS device manufactured by the process described herein is a bolometer comprising a glass substrate and bolometer pixels coupled to a structure, respectively. In some embodiments, the bolometer includes a MEMS or NEMS device manufactured by an LCD-TFT manufacturing process.

[0173] Bolometers can be used in a variety of applications. For example, far-infrared (LWIR, wavelengths of approximately 8-14 μm) bolometers can be used in the automotive and commercial security industries. For example, LWIR bolometers have QVGA, VGA, and other resolutions. Terahertz (THz, wavelengths of approximately 0.1-1.0 mm) bolometers can be used in security (such as airport passenger security screening) and medical (medical imaging). For example, THz bolometers can have QVGA resolution (320 x 240) or other resolutions. Some electromechanical systems can include X-ray sensors or camera systems. Similarly, LWIR and THz sensors are used in camera systems. Several electromechanical systems, such as endoscopes and exoscopies, are applied to medical imaging.

[0174] Other electromechanical systems include scanners for light detection and ranging (LIDAR) systems, such as optical scanners that can shape the spatial characteristics of a laser beam (for example, for beam pointing). Electromechanical systems also include inertial sensors (for example, when the input stimulus is linear or angular motion). Some systems can be used in biosensing and biotherapeutic platforms (for example, when biochemical drugs are detected).

[0175] As used herein, the term "MEMS" can be understood to include electromechanical systems having a size of approximately 1 mm or less. For example, the term "MEMS" can be understood to include nanoelectromechanical systems ("NEMS").

[0176] While the aspects of the disclosure are fully illustrated with reference to the accompanying drawings, it should be noted that various changes and modifications will become apparent to those skilled in the art. Such changes and modifications should be understood to fall within the scope of the aspects of the disclosure as defined by the accompanying claims. For example, while this disclosure primarily describes glass MEMS plates / panels, those skilled in the art will recognize that other MEMS plates / panels can also be used without departing from the scope of this disclosure. Such other MEMS plates may include, but are not limited to, organic materials (plastics, polymers) and metals (such as stainless steel). As used herein, the terms “plate” and “panel” are synonymous.

[0177] Method 800 includes step 804, the step of adding a MEMS to a substrate. While MEMS is used to illustrate the addition of a structure, it should be understood that other structures can also be added without departing from the scope of this disclosure. In some embodiments using panel-level processing, the MEMS structure may be added using an LCD-TFT process.

[0178] Step 804 may be followed by an optional step 816, subplating. Step 816 may be used if the substrate is larger than the processing equipment used in subsequent steps. For example, when using a panel-level process (such as an LCD), some embodiments include a step (in step 804) to cut the panel to wafer size for further processing (e.g., using a CMOS manufacturing apparatus). In other embodiments, the same size substrate is used throughout method 800 (i.e., step 816 is not used).

[0179] Method 800 includes step 806, a step of removing the MEMS from the substrate.

[0180] Method 800 includes step 808, a post-removal treatment. Such post-removal treatment may prepare the MEMS structure for further process steps, such as planarization. In wafer-level processing, planarization may include chemomechanical planarization. In some embodiments, the further process step includes etch-back, in which a photoresist is rotatably coated onto the topography to produce a flatter surface, which is then etched. More precise control of the etching time can yield a smoother surface profile. In some embodiments, the further process step includes "spin-on glass," in which an organic binder containing glass is rotatably coated onto the topography, the result is calcined to remove the organic solvent, leaving a smoother surface.

[0181] Method 800 may optionally include step 810, vacuum sealing of the MEMS structure. Vacuum sealing may be beneficial for extending the device lifespan.

[0182] Method 800 includes step 812, framing. Some embodiments may include calibration and chip programming (for example, of circuits 100, 400, 500, and / or 600), and the calibration and chip programming may take into account the characteristics of the sensor. The methods described herein may be advantageous in the glass substrate manufacturing process because the uniformity of the glass lithography capability is limited. As a further advantage, glass has a lower thermal conductivity, so the glass substrate can be a better insulator, and by manufacturing a thin structure that separates the bolometer pixels from the glass substrate, embodiments herein may work better to thermally isolate the glass bolometer pixels from the packaging environment.

[0183] Method 800 includes mounting of a readout integrated circuit (ROIC), which may include steps 814, circuits 100, 400, 500, and / or 600, as well as flex / PCB mounting. The processes and devices described herein may have the further advantage that the area required for signal processing can be made much smaller than the sensing area defined by sensing physics. Typically, sensors are integrated on top of CMOS circuits, and the area-driving cost leads to technology nodes that are not optimal for signal processing tasks. The processes described herein can free sensors from arbitrary area constraints by using more suitable CMOS and reducing the area required for signal processing, thereby taking advantage of the low cost of FPD (flat panel display) manufacturing. In some embodiments, the ROIC is specifically designed to sense a particular electromagnetic wavelength (X-rays, THz, LWIR, etc.).

[0184] Figure 9 shows an exemplary sensor. In some embodiments, the sensor 900 is manufactured using method 800. In some embodiments, the sensor 900 is read using circuits 100, 400, 500, and / or 600.

[0185] In some embodiments, the sensor includes a glass substrate, a structure manufactured from one of the methods described herein and bonded to the glass substrate, and sensor pixels bonded to the structure.

[0186] In some embodiments, the sensor includes a MEMS or NEMS device manufactured by an LCD-TFT manufacturing process and a structure manufactured by one of the methods described herein.

[0187] For example, sensors can include resistance sensors and capacitive sensors. Bolometers can be used in a variety of applications. For example, far-infrared (LWIR, wavelengths of approximately 8-14 μm) bolometers can be used in the automotive and commercial security industries. For example, LWIR bolometers with QVGA, VGA, and other resolutions. Terahertz (THz, wavelengths of approximately 0.1-3 mm) bolometers can be used in security (such as security screening of airport passengers) and medical (medical imaging). For example, THz bolometers with QVGA resolution and other resolutions. Some electromechanical systems can include X-ray sensor or camera sensor systems. Similarly, LWIR and THz sensors are used in camera sensor systems. Several electromechanical systems, such as endoscopes and exoscopy, are applied to medical imaging. X-ray sensors include direct and indirect sensing configurations.

[0188] Other electromechanical systems include scanners for light detection and ranging (LIDAR) systems, such as optical scanners that can shape the spatial characteristics of a laser beam (for example, for beam pointing). Electromechanical systems also include inertial sensors (for example, when the input stimulus is linear or angular motion). Some systems can be used in biosensing and biotherapeutic platforms (for example, when biochemical drugs are detected).

[0189] In one aspect, the circuit includes an analog input, a charge-transimpedance amplifier (CTIA) electrically coupled to the analog input, a quantizer electrically coupled to the output of the CTIA, a digital-to-analog converter (DAC) electrically coupled to the output of the quantizer, and an adder electrically coupled to the output of the DAC. The CTIA is electrically coupled to the output of the adder, a digital filter electrically coupled to the output of the quantizer, and a digital output electrically coupled to the digital filter.

[0190] In some aspects of the above circuit, the CTIA includes a feedback capacitor, the analog input is electrically coupled to the sensor, and the capacitance of the feedback capacitor is smaller than the capacitance of the sensor.

[0191] In some aspects of the above circuit, the adder is configured to reduce the CTIA output signal in response to receiving a high DAC output signal at the DAC output.

[0192] In some aspects of the above circuit, the adder is further configured to reduce the CTIA output signal by a certain value in response to receiving a high DAC output signal at the output of the DAC.

[0193] In some aspects of the above circuit, the CTIA includes a feedback capacitor, which is configured to store total charge, and the value corresponds to a charge less than the total charge.

[0194] In some aspects of the above circuit, the quantizer is configured to determine whether the CTIA output signal at the output of the CTIA is greater than a threshold, to output a first digital value to the DAC according to the determination that the CTIA output signal is greater than the threshold, and to output a second digital value to the DAC according to the determination that the CTIA output signal is less than or equal to the threshold, and the DAC is configured to output a high DAC output signal to the adder in response to receiving the first digital value, and to stop outputting a high DAC output signal to the adder in response to receiving the second digital value.

[0195] In some aspects of the above circuit, the circuit further includes an analog-to-digital converter (ADC) electrically coupled to the output of the CTIA. The ADC is configured to receive a voltage corresponding to the residual charge at the output of the CTIA and to provide a digital value corresponding to the residual charge. The digital output includes a digital value corresponding to the residual charge.

[0196] In some aspects of the above circuit, the voltage corresponding to the residual charge is below the threshold of the quantizer.

[0197] In some aspects of the above circuit, the ADC is a sigma-delta ADC.

[0198] In some aspects of the above circuit, the circuit further includes an offset removal circuit. The offset removal circuit is configured to remove the offset from the CTIA output signal.

[0199] In some aspects of the above circuit, the offset removal circuit is included in the feedback of the CTIA.

[0200] In some aspects of the above circuit, the ADC is configured to convert the offset from the CTIA output signal into a digital value of the offset.

[0201] In some aspects of the above circuit, the offset from the CTIA output signal is scaled, and the scaled offset is provided to the ADC.

[0202] In some aspects of the above circuit, the circuit further includes a low-pass filter that is part of the CTIA feedback.

[0203] In some aspects of the above circuit, the sensitivity of the circuit is based on the operating frequency of the circuit, and the operating frequency of the circuit is based on the integral time of CTIA.

[0204] In some aspects of the above circuit, the digital output signal at the digital output is the digital value of the charge at the analog input of the circuit.

[0205] In some aspects of the above circuit, the digital output signal at the digital output is the digital value of the current at the analog input of the circuit.

[0206] In some aspects of the above circuit, the digital output signal at the digital output is the digital value of the voltage at the analog input of the circuit.

[0207] In some aspects of the above circuit, the circuit further includes a variable resistor electrically coupled to the analog input. The variable resistor is configured to reduce the signal level of the input signal at the analog input of the circuit.

[0208] In some aspects of the above circuit, the digital filter includes a finite impulse response (FIR) decimator. The FIR decimator is configured to generate a digital output signal at the digital output based on the signal received from the output of the quantizer.

[0209] In some aspects of the above circuit, the FIR decimator is configured to further receive a digital value corresponding to the residual charge at the output of the CTIA, and the FIR decimator is configured to further generate a digital output signal based on the digital value corresponding to the residual charge at the output of the CTIA.

[0210] In some aspects of the above circuit, the coefficients associated with the FIR decimator are determined using at least one of the following methods: analytical determination, simulation-based numerical determination, and measurement-based numerical determination.

[0211] In some aspects of the above circuit, the quantizer and DAC are included in the combination of the quantizer and DAC of the circuit.

[0212] In one aspect, the method includes the steps of: integrating the input signal using the CTIA of the circuit; determining whether the CTIA output signal at the output of the CTIA is greater than a threshold; reducing the CTIA output signal according to the determination that the CTIA output signal is greater than the threshold; and ceasing to reduce the CTIA output signal according to the determination that the CTIA output signal is less than or equal to the threshold.

[0213] In some aspects of the above method, the method further includes the step of electrically coupling a sensor to a CTIA. The sensor provides an input signal, and the CTIA includes a feedback capacitor, the capacitance of which is less than that of the sensor.

[0214] In some aspects of the above method, the method further includes the step of generating a digital output signal corresponding to an input signal.

[0215] In some aspects of the above method, the input signal is the charge at the analog input of the circuit, and the digital output signal is the digital value of the charge.

[0216] In some aspects of the above method, the input signal is the current at the analog input of the circuit, and the digital output signal is the digital value of the current.

[0217] In some aspects of the above method, the input signal is the voltage at the analog input of the circuit, and the digital output signal is the digital value of the voltage.

[0218] In some aspects of the above method, the digital output signal is further based on the remainder.

[0219] In some aspects of the above method, the digital output signal is generated by a digital filter.

[0220] In some aspects of the above method, the digital output signal is generated by an FIR decimator. The method further includes the steps of generating a binary sequence and providing the binary sequence to an FIR decimator. The step of generating a binary sequence further includes the steps of outputting a first binary value according to the determination that the CTIA output signal is greater than a threshold, and outputting a second binary value according to the determination that the CTIA output signal is less than or equal to a threshold.

[0221] In some aspects of the above method, the method further includes providing the remaining digital values to a FIR decimator. The digital output signal is further based on the remaining digital values.

[0222] In some aspects of the above method, the method further includes determining coefficients associated with the FIR decimator using at least one of an analytical determination, a numerical determination based on simulation, and a numerical determination based on measurement.

[0223] In some aspects of the above method, the step of integrating the input signal includes integrating a first portion of the input signal, and the method further includes integrating a second portion of the input signal using a CTIA.

[0224] In some aspects of the above method, whether the CTIA output signal at the output of the CTIA is greater than a threshold is determined while the first portion is being integrated at a first time. The method includes reducing the CTIA output signal at a second time after the first time and starting to integrate the second portion at a third time after the second time in accordance with a determination that the CTIA output signal is greater than the threshold, and stopping reducing the CTIA output signal at the second time and starting to integrate the second portion at the third time in accordance with a determination that the CTIA output signal is below the threshold.​​​​​​​​​​​​​​​In some aspects of the above method, the digital value of the remainder is generated using a sigma-delta ADC.

[0229] In some aspects of the above method, the method further includes a step of generating a high DAC output signal according to the determination that the CTIA output signal is greater than a threshold. The CTIA output signal is reduced by a certain value, which is generated based on the high DAC output value.

[0230] In some aspects of the above method, the method further includes the step of stopping the generation of a high DAC output signal in accordance with the determination that the CTIA output signal is below a threshold.

[0231] In some aspects of the above method, the CTIA includes a feedback capacitor, which is configured to accumulate total charge, and the CTIA output signal is reduced by a value less than the total charge.

[0232] In some aspects of the above method, the method further includes a step of removing the CTIA offset.

[0233] In some aspects of the above method, the offset is removed before integrating the input signal.

[0234] In some aspects of the above method, the offset is removed using an offset removal circuit included in the CTIA feedback.

[0235] In some aspects of the above method, the step of removing the CTIA offset further includes the step of converting the CTIA offset into a digital value of the offset.

[0236] In some aspects of the above method, the step of converting the CTIA offset further includes the step of scaling the CTIA offset.

[0237] In some aspects of the above method, the method further includes the step of low-pass filtering the CTIA offset.

[0238] In some aspects of the above method, the low-pass filter included in the CTIA feedback filters out the CTIA offset.

[0239] In some aspects of the above method, the method further includes the step of using a variable resistor to reduce the current level of the input signal.

[0240] In some aspects of the above method, the method further includes the steps of: determining whether the reading of the input signal is complete based on the determination that the CTIA output signal is below a threshold; outputting the CTIA output signal as a remainder based on the determination that the reading of the input signal is complete; and ceasing to output the CTIA output signal as a remainder based on the determination that the reading of the input signal is not complete.

[0241] In some aspects of the above method, the input signal is integrated in a first time period, and it is determined in a second time period (after the first time period) whether the reading of the input signal is complete. If it is determined that the reading of the input signal is complete, the CTIA output signal is output as a remainder in a third time period (after the second time period). If it is determined that the reading of the input signal is not complete, the output of the CTIA output signal as a remainder is canceled.

[0242] In some aspects of the above method, the method further includes the step of resetting the feedback capacitor of the CTIA before integrating the input signal.

[0243] In some aspects of the above method, the method further includes the steps of operating the circuit as a multi-stage noise shaping (MASH) modulator, and, in response to operating the circuit as a MASH modulator, ceasing to determine whether the CTIA output signal at the CTIA output is greater than a threshold.

[0244] In one aspect, a non-transitory computer-readable storage medium stores one or more programs, the one or more programs including instructions that, when executed by an electronic device having one or more processors and a memory, cause the device to perform any of the above methods.

[0245] In the present disclosure, "electrically coupled" and "coupled" are used to describe an electrical connection between two elements of a circuit, but it is understood that an electrical connection does not necessarily require a direct connection between the terminals of the components being coupled to each other. Different combinations and connections of the recited components can achieve electrical coupling without departing from the scope of the present disclosure. For example, an electrical routing connects between the terminals of components that are electrically coupled to each other. In another example, a closed (conductive) switch is connected between the terminals of components that are coupled to each other. In yet another example, additional elements connect between the terminals of components that are coupled to each other without affecting the characteristics of the circuit. For example, buffers, amplifiers, and passive circuit elements can be added without affecting the characteristics of a read circuit and without departing from the scope of the present disclosure.

[0246] Similarly, when it is described in the present disclosure that two elements of a circuit are electrically disconnected, it is understood that the electrical disconnection does not necessarily require physically opening between the terminals of the components being switched. It is also understood that the disconnection is not limited to meaning preventing the transfer of electrical energy between two elements. For example, a high-impedance element is connected between the terminals of separated components. In another example, an open (non-conductive) switch is connected between the terminals of separated components, substantially separating the components.

[0247] While some elements or quantities are described in an absolute sense without using the term "substantially," it is understood that these elements and quantities may have a quality that is functionally equivalent to their absolute descriptions. For example, in some embodiments, a coefficient is described as 3. However, it is understood that this coefficient may be greater than or less than 3, as long as the ratio falls within the system's tolerance (e.g., the system's accuracy requirements).

[0248] The manner of disclosure is fully described with reference to the accompanying drawings, but it should be noted that various changes and modifications will become apparent to those skilled in the art. Such changes and modifications should be understood to fall within the scope of the manner of disclosure as defined by the accompanying claims.

[0249] The terms used in the descriptions of the various aspects of this specification are intended to describe, and not to limit, a particular aspect. Where used in the descriptions of the various aspects of this specification and in the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural form unless the context makes it clear otherwise. The terms “and / or” as used herein will be understood to refer to and encompass one or any possible combination of the related items. The terms “includes,” “including,” “comprises,” and / or “comprising,” where used herein, specify the presence of a described feature, integer, process, operation, element, and / or component, but will not exclude the presence or addition of one or more other features, integers, processes, operations, elements, components, and / or groups thereof.

Claims

1. An analog input electrically coupled to a sensor, A charge transimpedance amplifier (CTIA) electrically coupled to the analog input, the CTIA including a feedback capacitor, wherein the capacitance of the feedback capacitor is smaller than the capacitance of the sensor, A quantizer electrically coupled to the output of the CTIA, A digital-to-analog converter (DAC) electrically coupled to the output of the quantizer, An adder electrically coupled to the output of the DAC, wherein the CTIA is electrically coupled to the output of the adder, A digital filter electrically coupled to the output of the quantizer, The digital output electrically coupled to the digital filter and A circuit that includes this.

2. The circuit according to claim 1, wherein the adder is configured to reduce the CTIA output signal in response to receiving a high DAC output signal at the output of the DAC.

3. The quantizer, Determine whether the CTIA output signal at the output of the CTIA is greater than the threshold, In accordance with the determination that the CTIA output signal is greater than the threshold, a first digital value is output to the DAC. A second digital value is output to the DAC according to the determination that the CTIA output signal is below the threshold. It is configured in such a way. The DAC in question In response to receiving the first digital value, the adder outputs a high DAC output signal. In response to receiving the second digital value, the adder stops outputting the high DAC output signal. It is structured in such a way. The circuit according to claim 1.

4. The CTIA further includes an analog-to-digital converter (ADC) electrically coupled to the output of the CTIA, The ADC, The output of the CTIA receives a voltage corresponding to the residual charge, Provides a digital value corresponding to the residual charge. It is configured in such a way, The digital output includes the digital value corresponding to the residual charge, The circuit according to claim 1.

5. The circuit according to claim 1, further comprising an offset removal circuit configured to remove an offset from a CTIA output signal.

6. The circuit according to claim 1, wherein the ADC is configured to convert an offset from the CTIA output signal into a digital value of the offset.

7. The circuit according to claim 1, further comprising a low-pass filter included in the feedback of the CTIA.

8. The sensitivity of the circuit is determined based on the operating frequency of the circuit. The operating frequency of the circuit is based on the integral time of the CTIA, The circuit according to claim 1.

9. The circuit according to claim 1, wherein the digital output signal at the digital output is the digital value of the charge at the analog input of the circuit.

10. The circuit according to claim 1, wherein the digital output signal at the digital output is the digital value of the current at the analog input of the circuit.

11. The circuit according to claim 1, wherein the digital output signal at the digital output is the digital value of the voltage at the analog input of the circuit.

12. The circuit according to claim 1, further comprising a variable resistor electrically coupled to the analog input, wherein the variable resistor is configured to reduce the signal level of the input signal at the analog input of the circuit.

13. The digital filter includes a finite impulse response (FIR) decimator. The FIR decimator is configured to generate a digital output signal at the digital output based on the signal received from the output of the quantizer. The circuit according to claim 1.

14. The circuit according to claim 1, wherein the quantizer and the DAC are included in the combination of the quantizer and the DAC of the circuit.

15. A step of integrating an input signal through a capacitive transimpedance amplifier (CTIA) of the circuit; A step of determining whether the CTIA output signal at the output of the CTIA is greater than a threshold value via the quantizer of the circuit; A step of reducing the CTIA output signal via the digital-to-analog converter (DAC) of the circuit and an adder electrically coupled to the DAC, in accordance with the determination that the CTIA output signal is greater than the threshold; and A step of stopping the reduction of the CTIA output signal via the DAC and adder of the circuit, in accordance with the determination that the CTIA output signal is below the threshold. A method including, The CTIA is electrically coupled to the sensor that provides the input signal and includes a feedback capacitor. The capacitance of the feedback capacitor is smaller than the capacitance of the sensor, and The CTIA includes a reset switch, and the feedback capacitor is reset before the integrating step. The method.

16. The method according to claim 15, further comprising the step of generating a digital output signal corresponding to the input signal via a digital filter of the circuit.

17. The input signal is the charge at the analog input of the circuit. The digital output signal is the digital value of the charge. The method according to claim 16.

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