Analog-to-digital converters and analog-to-digital conversion systems

Abstract

To provide a system, a device, and a method that implement analog / digital conversion that initiates the conversion of a sampling input from a sampling circuit when or after sampling is stopped.SOLUTION: In an analog / digital conversion device 500 including a sampling circuit 520 that samples an input signal and an analog / digital conversion circuit 550, the sampling circuit stops sampling in response to the acquisition of a trigger signal. The analog / digital conversion circuit includes an analog / digital converter (ADC) that converts the sampling input supplied from the sampling circuit into a digital output. The ADC starts converting the sampling input from the sampling circuit when or after the sampling circuit has stopped sampling.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] Various embodiments generally relate to systems, apparatus, and methods for implementing analog-to-digital conversion. [Background technology]

[0002] Many applications that rely on analog input measurements implement analog-to-digital conversion using an analog-to-digital converter (ADC) to control the control loop. For conversion, a trigger signal can be used to detect the analog value. To give a few examples, the trigger signal can arrive from application software, other hardware peripherals such as peripherals within a system-on-a-chip (SoC), or other electronic or electrical components such as an ASIC or integrated circuit.

[0003] In conventional trigger-based conversion, sampling starts when a trigger is received. To achieve fast results, users can set a short sampling time. A short sampling time results in charge transfer occurring in a short time, so that the input current is defined by the relationship I(current) = dq / dt, where q is the charge. For example, if the charge is consumed at 3 pC, then with a sampling time of 100 ns, I = 30 μA.

[0004] In applications where an external blocking capacitor is used, almost all of the input charge is taken out by the external capacitor. To avoid gain errors in this situation, the external capacitor must be at least 2^(x+1) times the sampling capacitor, where x is the ADC resolution. For example, if a 1pF input sampling capacitor provides 12-bit resolution, the external capacitor must be at least 8192pF or about 8.1nF, which leads to increased costs.

[0005] Furthermore, as the trend moves towards faster and higher-performance SoCs, there is a demand for smaller technology nodes. At smaller technology nodes (e.g., 28nm), capacitors tend to exhibit a memory effect that impacts the performance of ADCs utilizing sample-and-hold (S / H) circuits.

[0006] Conventional approaches in analog-to-digital conversion result in increased component costs, higher power consumption, larger PCB space, and greater complexity in PCB and system design. Furthermore, dielectric absorption effects can sometimes occur, leading to performance degradation.

[0007] In the figures, similar reference numerals generally refer to the same parts across different drawings. The drawings are not necessarily to actual size and proportions, but rather generally focus on illustrating the principles of the present invention. The following description will explain various embodiments of the present invention with reference to the following drawings. [Brief explanation of the drawing]

[0008] [Figure 1] This is a diagram showing a conventional analog-to-digital converter. [Figure 2] This figure shows the input signal, trigger signal, and sampling circuit response for a conventional analog-to-digital converter. [Figure 3] This figure shows a circuit model for a sampling capacitor that includes a simplified dielectric absorption model. [Figure 4] This figure shows the exemplary conversion results of a constant input voltage for various combinations of sample-and-hold times for conventional sampling and conversion processes. [Figure 5] This figure shows an analog-to-digital converter according to at least one exemplary embodiment of the present disclosure. [Figure 6] Figure 5 is a graph showing the input signal, trigger signal, and sampling circuit response on the time axis for the analog / digital conversion device. [Figure 7] It is a diagram showing conversion results of an exemplary constant input voltage for various combinations of sample & hold times, for the conventional sampling process and conversion process in the case of the apparatus of FIG. 5. [Figure 8] It is a diagram showing a method according to at least one exemplary embodiment of the present disclosure.

Mode for Carrying Out the Invention

[0009] The following detailed description refers to the accompanying drawings which illustrate specific details and embodiments in which the invention can be implemented.

[0010] Note that throughout the drawings, like reference numerals and reference signs are used to indicate the same or similar elements, features and structures.

[0011] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration". It should not necessarily be construed that any embodiment or design described herein as "exemplary" is more preferable or advantageous than other embodiments or designs.

[0012] The terms "at least one" and "one or more" can be understood to include one or more quantities (e.g., 1, 2, 3, 4, [...], etc.). The term "plural" can be understood to include quantities of two or more (e.g., 2, 3, 4, 5, [...], etc.).

[0013] The phrase "at least one" in relation to element groups can be used herein to mean at least one element from a group consisting of multiple elements. For example, the phrase "at least one" in relation to element groups can be used herein to mean the following selections: one of the enumerated elements, multiple of the enumerated elements, multiple of the individual enumerated elements, or multiple of the many enumerated elements.

[0014] In the detailed description and claims, the terms “multiple” and “many” explicitly refer to a quantity greater than one. Therefore, any expression that explicitly calls the above terms referring to a quantity of objects (e.g., “multiple [objects],” “many [objects]”) explicitly refers to two or more of those objects. In the specification and claims, terms such as “(of) a group,” “(of) a set,” “(of) a collection,” “(of) a series,” “(of) a sequence,” and “(of) a grouping,” if any, refer to a quantity greater than one, i.e., one or more. The terms “appropriate subset,” “reduced subset,” and “smaller subset” refer to a subset of a set that is not equal to that set, i.e., a subset of a set that contains fewer elements than that set.

[0015] As used herein, the term “data” can be understood to include information in any appropriate analog or digital format, for example, as a file, a portion of a file, a set of files, a signal or stream, a portion of a signal or stream, a set of signals or streams, and similar entities. Furthermore, the term “data” may also be used to mean, for example, a reference to information in the form of a pointer. However, the term “data” is not limited to the examples given above and can take various forms to represent any information understood in the art.

[0016] For example, the terms “processor” or “controller” as used herein can be understood as any kind of entity that enables the processing of data, signals, etc. Data, signals, etc. can be processed according to one or more specific functions performed by the processor or controller.

[0017] Therefore, a processor or controller can be an analog circuit, a digital circuit, a mixed-signal circuit, a logic circuit, a processor, a microprocessor, a central processing unit (CPU), a neuromorphic computer unit (NCU), a graphics processing unit (GPU), a digital signal processor (DSP), a field-programmable gate array (FPGA), an integrated circuit, an application-specific integrated circuit (ASIC), etc., or any combination thereof, or a processor or controller may include these. Any other type of implementation of the individual functions described in more detail below can be understood as a processor, controller, or logic circuit. Obviously, any two (or more) of the processors, controllers, or logic circuits detailed herein can be realized as a single entity having equivalent functions, etc., and conversely, any single processor, controller, or logic circuit detailed herein can be realized as two (or more) separate entities having equivalent functions, etc.

[0018] The term “system” as described in detail herein (e.g., drive system, position detection system, etc.) can be understood as a set of multiple interacting elements, which may include, but are not limited to, one or more mechanical parts, one or more electrical or electronic components, one or more instructions (e.g., coded on a storage medium), one or more controllers, etc.

[0019] In this specification, "circuit" as a user is understood to mean any kind of logic implementation entity, which may include processors that run dedicated hardware or software. Thus, a circuit can be an analog circuit, a digital circuit, a mixed-signal circuit, a logic circuit, a processor, a microprocessor, a signal processor, a central processing unit ("CPU"), a graphics processing unit ("GPU"), a neuromorphic computer unit (NCU), a digital signal processor ("DSP"), a field-programmable gate array ("FPGA"), an integrated circuit, an application-specific integrated circuit ("ASIC"), etc., or any combination thereof. Any other kind of implementation of the individual functions described in more detail below may be understood as a "circuit." Obviously, any two (or more) of the circuits detailed herein can be implemented as a single circuit with substantially equivalent functionality, and conversely, any single circuit detailed herein can be implemented as two (or more) separate circuits with substantially equivalent functionality. In addition, the expression "circuit" can refer to two or more circuits that collectively form a single circuit.

[0020] As used herein, the terms “module,” “component,” “system,” “circuit,” “element,” “slice,” “circuit system,” and similar terms are intended to refer to a set of one or more electronic components, computer-related entities, hardware, software (e.g., running), and / or firmware. For example, a circuit system or similar term may refer to a computer comprising a processor, processes running on the processor, controllers, objects, executable programs, storage devices, and / or processing units. As an example, an application running on a server and the server itself may also be considered a circuit system. One or more circuits may reside within the same circuit system, a circuit system may be located locally on one computer, and / or distributed across two or more computers. Although this specification may describe a set of multiple elements or a set of multiple other circuits, the term “set” here can be interpreted as “one or more.”

[0021] As used herein, a signal is something that can be transmitted or transmitted through a signal chain, in which the signal is processed to change its characteristics such as phase, amplitude, and frequency. Signals may be referred to as the same signal even if such characteristics have been adapted. Generally, a signal can be considered the same signal as long as it continues to encode the same information. For example, a transmitted signal can be considered to refer to a transmitted signal at baseband frequency, intermediate frequency, and radio frequency.

[0022] As used herein, “memory” can be understood as a non-temporary, computer-readable medium capable of storing data or information for retrieval. Therefore, the term “memory” as used herein can be understood to refer to volatile or non-volatile memory, including random-access memory ("RAM"), read-only memory ("ROM"), flash memory, solid-state storage, magnetic tape, hard disk drives, optical drives, etc., or any combination thereof. Furthermore, as is obvious, registers, shift registers, processor registers, data buffers, etc., are also included in the term “memory” as used herein. As is obvious, a single component or “one memory” referred to as “memory” can consist of two or more different types of memory, and thus can refer to a collective component containing one or more types of memory. It is easily understood here that any single memory component can be separated into multiple collectively equivalent memory components, and vice versa. Furthermore, although memory may be depicted separately from one or more other components (in drawings, etc.), as is obvious, memory can be integrated within other components, such as on a common integrated chip. In the context of dielectric absorption, "memory" or "memory effect" can refer to the effect caused by dielectric absorption or dielectric relaxation in which a capacitor recognizes or attempts to achieve a previous or past voltage through experience.

[0023] Figure 1 shows a conventional analog-to-digital converter 100 that utilizes a trigger approach. The analog-to-digital converter 100 includes a sampling circuit 110 and an analog-to-digital converter (ADC) circuit 150. The sampling circuit 110 can sample an analog signal and supply the sampled input to the ADC circuit 150. The sampling circuit 110 includes, or may include, an input capacitor C4 coupled between an input source 115 and a reference potential. The input source 115 and the input capacitor C4 are coupled to a switch S1. The circuit shows an exemplary resistor 120 between the input source and the switch S1.

[0024] This switch S1 controls the sampling performed by the sampling circuit 110. Sampling is performed when switch S1 is closed, and sampling ends, stops, or pauses when switch S1 is open. In Figure 1, a sampling capacitor C2 is placed between switch S1 and the ADC circuit 150. As shown in the figure, the sampling capacitor C2 is coupled to a reference potential (e.g., earth) and can hold the value of the sampling input, e.g., the sampling voltage.

[0025] Switch S1 can be any suitable switch, for example, an electronic switch configured to selectively close to sample the input in response to an acquired trigger or trigger signal. When switch S1 acquires or receives a trigger signal, switch S1 closes to start sampling. When a trigger signal is received, the sampling circuit 110 enters a period t sample The sampling circuit 110 can be configured to perform sampling over a specified period. After this period, switch S1 is opened (again). Once switch S1 is open, A / D conversion can be started.

[0026] The ADC circuit 150 can convert an input, for example, a sampling input, into a digital output or digital signal. In the embodiment shown in Figure 1, the ADC circuit 150 is an ADC in the form of a successive approximation register (SAR). An ADC circuit like the ADC circuit 150 may include a holding circuit to hold a value or input. According to one embodiment, the ADC circuit 150 may include one or more switches, comparators, a capacitive DAC (digital-to-analog converter), and connections to a reference trough.

[0027] The ADC circuit 150 can begin conversion or holding when it receives a sampling input from the sampling circuit 110. In other words, the conversion process can start after a trigger signal is transmitted or received.

[0028] FIG. 2 shows a graph representing an exemplary input signal 210 that may be input to the apparatus 100 on the time (t) axis. The graph 200 shows the received exemplary trigger signal 215 f trigger and the response 220 of the sampling capacitor. This graph also shows the timing of a particular event. For example, at 230, in response to the received trigger signal 215a, the sampling circuit 110 closes, thereby starting sampling (sampling start). As shown, the sampling circuit 110 samples over a sampling period t sample . At the end of the sampling period (“sampling end” or “EoS”), digital conversion of the sampling input begins, which is referred to as “conversion start” or “SoC”. The conversion period t conv corresponds to the time from when the sampling input is converted or held until it is converted by the ADC circuit 150. The end of the conversion period is referred to as “conversion end” or “EoC”. Sampling is not resumed until a new trigger signal 215b is received.

[0029] Thus, for this apparatus 100, the total trigger period (t trigger ) is a function of the sampling time (t sample ) and the conversion time (t conv ). Further, the conversion time t conv is a function of the desired resolution and the operating frequency of the ADC circuit 150. The sampling time t sample is a function of the sampling capacitor C2, the voltage change, and the input current (I in ). The sampling time t sample can be approximated using the following equation, which ignores or does not consider the minimum settling time that depends on the resolution of the ADC. t sample = C2 × (dV / I in )

[0030] This equation assumes a constant input current, and thus the I in the equation inThe average input current is used. The voltage dV can be kept constant for specific applications, such as powertrains (for example, dV = 5V) or radar applications (for example, dV = 3.3V).

[0031] The sampling capacitor C2 can also be selected or defined by specific technical applications based on particular requirements such as gain error, total usable error (TUE), and offset error. The value of C2 may be considered constant. TUE can be measured in terms of deviations from the ideal conversion result, for example, as an accumulation of errors of the types of gain, offset, and linearity, and / or errors related to crosstalk, relaxation, and / or noise.

[0032] Figure 3 shows a model of a sampling capacitor that takes dielectric absorption (DA) effects into account. The DA model is based on the capacitor C da and a sampling capacitor in parallel with the resistor. During the idle phase when no input sampling is performed, capacitor C2 and capacitor C da It can be charged. However, if the subsequent sampling time is insufficient, the sampled input voltage will be C da The residual delta voltage above is not sufficiently or completely overwritten or erased. Therefore, the voltage sampled by capacitor C2 is altered during the holding and conversion phases, resulting in an incorrect conversion value. Capacitor C da This memory effect worsens as the sampling time is shortened and the difference between the input voltage of the sampling circuit and the reference voltage is reduced. Moreover, as the holding time by the sampling circuit increases, C da As the charge is redistributed to the C2 capacitor, more charge is generated, which may therefore alter the sampling value.

[0033] Figure 4 shows exemplary conversion results of a constant input voltage for various combinations of sample-and-hold times for conventional sampling and conversion processes. Since this graph is intended solely to illustrate the characteristics of the converted output for extended sample-and-hold times, no values ​​are assigned to any of the axes.

[0034] Generally, to achieve higher conversion throughput and / or reduced conversion latency, the sampling time t is increased. sample This needs to be made as short as possible. However, in order to minimize the dielectric absorption effect, the sampling time must be long while the holding and conversion times must be short. Solutions involving the use of a larger input current to alleviate some of the above problems require more expensive sensors and higher system design costs. Furthermore, using a larger blocking capacitor to alleviate the above drawbacks also presents problems. For example, referring to apparatus 100 in Figure 1, capacitor C2 takes charge from blocking capacitor C4, thereby causing a voltage drop in capacitor C4 and resulting in a gain error. As the capacitance of capacitor C4 increases or becomes larger, the cost increases due to the cost of system design and printed circuit board (PCB).

[0035] Figure 5 shows an analog-to-digital converter 500 according to at least one exemplary embodiment of the present disclosure. The converter 500 includes a sampling circuit 520 and an analog-to-digital converter (ADC) circuit 550. The converter 500 can be trigger-based. According to at least one embodiment, the converter 500 can be configured to sample an analog signal and then, in response to a trigger signal, convert the sampled input to a digital output.

[0036] The sampling circuit 520 has R representing the input resistance. extIt is coupled to an input source 505 which has [a certain feature]. The input source 505 can supply an analog signal as an input to be sampled by the sampling circuit 520.

[0037] The sampling circuit 520 includes an input capacitor C4 coupled to the input section 510 of the sampling circuit 520. The sampling circuit 520 can be configured to perform sampling until the sampling circuit is triggered, or to perform sampling. The sampling circuit 520 samples the signal supplied from the input source 505 and can then stop or pause sampling in response to a received or acquired trigger signal. The stopping or pausing of sampling by the sampling circuit 520 can occur immediately after the trigger signal is transmitted or received. In other cases, sampling can be stopped or paused after a predetermined or configurable period. The trigger signal may be generated from one or more components of the converter 500, or it may be generated and transmitted from a component or circuit system outside of the converter 500.

[0038] As shown in the embodiment of Figure 5, the sampling circuit 520 includes a sampling switch S1 and a sampling capacitor C2. The sampling switch S1 can be coupled between the input unit 510 and the sampling capacitor C2. The sampling switch S1 can control the sampling operation performed by the sampling circuit 520. The sampling switch S1 can be configured to control when sampling should be performed. When the sampling switch S1 is closed or in a closed state, the sampling capacitor C2 is electrically coupled to the input source of the sampling circuit 520 and can therefore obtain a sampled value from the input signal. Continuous closing of the sampling switch S1 allows or enables continuous sampling of the input signal.

[0039] The sampling circuit 520 stops sampling in response to the sampling switch S1 being opened or in an open state. As described above, the sampling circuit 520 stops sampling when the sampling switch S1 is opened. This opening of switch S1 to stop sampling occurs immediately after the trigger, or after the trigger, after a set or predetermined period of time. In response to the trigger operation, the sampling circuit 520 can be configured as a holding circuit that holds the current sampled value or voltage in the sampling capacitor C2, and the ADC circuit 550 can acquire the held value. In other words, the sampling circuit 520 can also be configured as a holding circuit. According to one or more embodiments, the holding time, or the time during which the sampling circuit 520 is required to hold the sampled value, can be defined as the time from the end of sampling (EoS) to the start of conversion (SoC) when the sampled value is acquired from the sampling circuit 520.

[0040] According to various embodiments, the sampling switch S1 is used as a trigger or trigger signal (f trigger ) can be configured to be opened by a trigger or trigger signal, which terminates sampling by interrupting, blocking, or opening the electrical connection between the input source 505 and the sampling capacitor C2.

[0041] According to one embodiment, the sampling switch S1 may be closed by default. For example, when power is supplied to the converter 500 or the sampling circuit 520, the sampling switch S1 may be closed to enable or permit sampling. In other words, the sampling switch S1 can be considered a normally closed switch that transitions to an open state only in response to a received or acquired trigger signal.

[0042] In response to a trigger signal, the sampling switch S1 can be kept open for a certain period of time. For example, the switch S1 can be configured to remain open at least as long as the ADC circuit 550 is performing the conversion process. The switch S1 can also be configured to close at or after the end of the conversion process by the ADC circuit. The period during which the switch S1 is open may be predetermined or fixed, or in other cases, undefined beforehand. According to at least one embodiment, the switch S1 can be configured to close in response to another trigger, for example, a trigger sent to the sampling circuit 520. This second trigger can be coincided with the end of conversion (EoC) by the ADC circuit 550. Such a signal can be generated by the ADC circuit 550 or by an external component not shown.

[0043] The sampling circuit 520 may further include switches S2 and S5, each of which is coupled between a predetermined potential and the sampling capacitor C2. For example, as shown in Figure 5, switch S5 can be coupled between the input side of the sampling capacitor C2 and a reference potential (e.g., ground). Switch S2 is coupled between the output side of the sampling capacitor C2 and a voltage potential (V cm ) can be coupled between these. These switches can be configured to transition between an open state and a closed state, for example, in response to a trigger signal that opens the sampling switch S1. Switch S2 can be closed during sampling and opened during the digital conversion process performed by the ADC550. Switch S5 can be opened during sampling and closed during the digital conversion process performed by the ADC550. In other words, switches S2 and S5 can be configured to facilitate holding the sampling input.

[0044] The ADC circuit 550 in Figure 5 is configured to perform a conversion operation on a sampling input acquired from the sampling circuit 520. The ADC circuit 550 can be configured to hold the received sampling input and to convert the acquired sampling input into a digital output. The ADC circuit 550 can include any type of ADC circuit suitable for achieving or performing such functions. According to the embodiment in Figure 5, the ADC circuit can be a successive approximation register (SAR) ADC 550 circuit. For example, the ADC circuit 550 may include a comparator and further include one or more switches coupled between this comparator and a voltage or reference potential. The ADC circuit 550 may also include internal digital logic (e.g., digital logic or hardware components) for receiving the signal output from the comparator, for the purpose of implementing the known successive approximation register function for supplying a digitized output.

[0045] The device 500 can initiate a stop to the sampling period (EoS or End of Sampling) in response to a trigger operation, for example, in response to an acquired or received trigger signal that terminates sampling by the sampling circuit 520. The sampling capacitor C2 holds the sampling voltage or sampling value for a holding period corresponding to the conversion start (SoC) from the trigger operation.

[0046] Furthermore, this trigger action can initiate or start the conversion process by the ADC circuit 550. Specifically, at the end of sampling (EoS) or after the end of sampling (EoS) (for example, when the sampling switch S1 is open), the ADC circuit 550 can acquire a sampling input from the sampling circuit 520 (for example, from the sampling capacitor C2), and then hold and / or convert the sampling input. The ADC circuit 550 can be configured to control one or more switches in response to a trigger signal for acquiring a sampling input from the sampling circuit 520, for example, by closing a switch. For example, by closing a switch in the ADC circuit 550, the current sampling input can be received from the sampling circuit, and the current input value or sampling voltage can be acquired, for example, from the sampling capacitor C2 of the sampling circuit 520. In other words, such a switch can be configured to close in response to a trigger signal, such as the same trigger signal that opens the sampling switch S1. In another case, the switch can be configured to close when another trigger signal corresponding to the end of sampling or the start of conversion is generated.

[0047] During conversion by the ADC circuit 550, the ADC circuit 550 holds the acquired sampling input and / or converts it to a digital output. The ADC circuit 550 can be implemented or configured as a holding circuit for holding the sampling input. This held sampling input can be held for subsequent digital conversion. In other cases, the ADC circuit 550 can convert the acquired sampling input to a digital output immediately, for example, without an intermediate holding time. Therefore, the conversion process may include the step of holding the sampling input and / or the step of converting the sampling input to a digital output.

[0048] According to this embodiment, after or at the end of conversion (EoC), the sampling switch S1 is configured to close again and continue sampling until another trigger occurs (for example, a trigger that opens the sampling switch S1 and stops sampling). A trigger signal can be transmitted to selectively convert the sampling input at a specific point in time.

[0049] The conversion device 500 continuously or always when not performing conversion. For example, the device 500 can be configured to continuously sample the input until a trigger operation occurs. Sampling time (e.g., dt trigger ~dt sample If the holding time and conversion time are negligible compared to the average input current, then the average input current is I in =C2 × (dV / dt trigger It can be approximated as ).

[0050] Furthermore, as a result of this continuous sampling before the trigger operation event, the input current to the device is approximately t trigger / t sample It can be made smaller by the ratio of t. sample This refers to the sampling time or minimum sampling time of a conventional device, t trigger This refers to the sampling time of device 500.

[0051] For example, the trigger period can be set to 10 μs, and the minimum sampling time can be set to 100 ns. Thus, the input current I in This can be reduced to 1 / 100th (10 μs / 100 ns). The reduced current eliminates the need for an external capacitor C4, or allows for a significant reduction in the value of the external capacitor C4.

[0052] Figure 6 shows a graph 600 representing an exemplary input signal 610 that can be input to a converter such as the converter 500 in Figure 5 on the time (t) axis. Graph 600 also shows an exemplary trigger signal ftrigger Includes 615. The lower half of graph 600 shows an exemplary response 620 of the sampling capacitor of the sampling circuit or converter 500. When the input signal is input to the converter, the sampling capacitor is charged by the sampling voltage from the input signal. Then, the trigger (f trigger In response to the trigger, the sampling switch opens and the device moves to the conversion phase (EoS / SoC), during which the ADC circuit 550 starts holding and / or converting the current sampling input (e.g., the current sampling voltage) held by the sampling circuit 520. As previously described, EoS can occur immediately after the trigger is acquired or after a predetermined or configurable period. Although not shown, a hold time can exist between EoS and SoC, during which the sampling circuit 520 holds the sampled value for the ADC circuit 550.

[0053] Conversion period (t conv During this time, the sampling voltage remains constant. Subsequently, at the end of conversion and at the start of sampling (EoC / SoS), the sampling capacitor is recharged in response to the input signal until the conversion process is restarted by a trigger signal.

[0054] Until the sampling circuit is triggered (for example, until a trigger signal is acquired), the sampling circuit continuously samples during the period corresponding to the start of sampling. The sampled value or sampling voltage of the sampling capacitor detected at the time of trigger can be supplied to the ADC circuit 550 for conversion. Continuous sampling until the trigger prevents the sampling voltage, for example the voltage at the sampling capacitor, from reaching or returning to a fixed or configurable reference potential. In other words, the sampling circuit 520 immediately samples the input without reset to mitigate or reduce the memory effect at the sampling capacitor due to dielectric absorption. In other words, referring again to Figure 3, the continuous sampling period reduces the C of the dielectric absorption model. da This allows the voltage across the capacitor to closely track the sampling voltage. Consequently, the variation in the sampling voltage across capacitor C2 when the sampling circuit 520 is triggered is reduced, resulting in a reduction in the error in the output of the converter 550. This approach allows the sampling time to be increased or extended to its maximum extent, for example, allowing for weaker input sources to be tolerated.

[0055] Figure 7 shows the conversion results of a constant input voltage for various combinations of sample-and-hold times, for the conventional sampling and conversion processes in the apparatus of Figure 5. This graph is intended only to illustrate the characteristics of the converted output for extended sample-and-hold times using an apparatus like the one in Figure 5, and therefore, no values ​​are assigned to any of the axes. Compared to the graph in Figure 4, the average output code does not have sample-and-hold time-dependent errors due to dielectric absorption, and instead remains much closer to the ideal converted value.

[0056] Figure 8 shows a method according to at least one exemplary embodiment of the present disclosure. The apparatus can implement a method or technique similar to that of the converter 500 shown in Figure 5. This method may include, in step 810, sampling an analog input signal by the sampling circuit of the converter. This method includes, in step 820, acquiring a trigger signal. If the trigger signal has been acquired, then in step 830, this method includes pausing sampling of the analog input signal by the sampling circuit.

[0057] For example, if no trigger signal is acquired, this method includes a step in which the sampling circuit continues sampling. Otherwise, if a trigger signal is acquired, the sampling circuit that was performing the sampling stops the sampling process and holds the current sampling input or sampling voltage.

[0058] After a pause in sampling, the method includes, in step 840, the steps of converting the sampling input acquired from the sampling circuit to a digital output by an analog-to-digital converter (ADC), and / or holding the sampling input acquired from the sampling circuit. In other words, according to at least one embodiment, the ADC circuit may include an ADC and a holding circuit. After a pause in sampling due to a trigger signal, the ADC circuit may be configured to acquire the sampling input and decide to hold the sampling input and convert it to digital later. Depending on the environment, the ADC circuit may be configured to acquire the sampling input and to immediately convert the sampling input to a digital output or digital signal. After the conversion process is complete, for example, after the holding and / or conversion is completed or terminated by the ADC circuit, the method can be started from step 810 to perform sampling again.

[0059] This method can be implemented by a converter such as apparatus 500 or a similar concept. This method can be implemented to reduce the input current, because if the input power is not reduced, a large input could result in a more expensive sensor and a more expensive system design. Furthermore, the apparatus and method described herein do not require a larger blocking capacitor, which would introduce gain errors and increase costs due to system design and PCB requirements. In addition, the dielectric absorption effect is reduced due to continuous sampling, resulting in improved performance, specifically the performance of the ADC.

[0060] The following examples relate to further exemplary implementation forms.

[0061] Embodiment 1 is a system comprising a sampling circuit and an analog-to-digital converter, the sampling circuit being configured to sample an input signal, wherein the sampling circuit is configured to stop sampling in response to the acquisition of a trigger signal, and the analog-to-digital converter has an analog-to-digital converter (ADC) that converts a sampling input supplied from the sampling circuit to a digital output, the ADC being configured to start converting the sampling input from the sampling circuit when the sampling circuit stops sampling or after it has stopped sampling.

[0062] Embodiment 2 is a protected object of Embodiment 1, and the analog-to-digital conversion circuit may further include a holding circuit configured to hold the sampling input from the sampling circuit when the sampling circuit stops sampling or after it has stopped sampling.

[0063] Example 3 is a protected object of Example 1 or 2, and the sampling circuit can be configured to start sampling when the system is powered on.

[0064] Embodiment 4 is a protected embodiment of any one of Embodiments 1 to 3, wherein the sampling circuit may further include a sampling switch coupled between the input of the sampling circuit and the input to the analog-to-digital conversion circuit, and the sampling circuit is configured to stop sampling by opening the sampling switch in response to the acquisition of a trigger signal.

[0065] Example 5 is a protected object of Example 4, and the sampling switch can be configured as a normally closed switch, and the sampling switch can be configured to be closed during sampling.

[0066] Example 6 is a protected embodiment of any one of Examples 1 to 5, and the sampling circuit can be configured to stop sampling for a predetermined period of time in response to the acquisition of a trigger signal.

[0067] Example 7 is a protected object of Example 6, and the ADC can be configured to terminate the conversion of the sampling input after a predetermined period or at the end of the predetermined period.

[0068] Example 8 is the protected subject of Example 6 or 7, and the predetermined period can be a predetermined period.

[0069] Example 9 is a protected embodiment of any one of Examples 1 to 8, wherein the sampling circuit can be configured to resume sampling after or when the ADC has finished converting the sampling input.

[0070] Example 10 is a protected embodiment of any one of Examples 4 to 9, and the sampling circuit may further include an input capacitor coupled between the reference potential and the input of the sampling circuit.

[0071] Example 11 is a protected object of any one of Examples 1 to 10, and the ADC can be a successive approximation register (SAR) ADC.

[0072] Example 12 is a protected embodiment of any one of Examples 1 to 11, wherein the ADC can be configured to begin converting the sampling input in response to an ADC circuit that acquires a second trigger signal different from a first trigger signal.

[0073] Example 13 is a protected embodiment of any one of Examples 1 to 12, and the sampling circuit can be further configured to hold a sampling input detected when a trigger signal is acquired.

[0074] Example 14 is a protected object from any one of Examples 1 to 13, wherein the sampling circuit can be further configured to continuously sample the input signal before and until the trigger signal is acquired.

[0075] Example 15 is a protected embodiment of any one of Examples 1 to 14, and the sampling circuit can be configured to stop sampling immediately after acquiring a trigger signal.

[0076] Example 16 is a protected embodiment of any one of Examples 1 to 14, and the sampling circuit can be configured to stop sampling after a predetermined period of time has elapsed since the acquisition of a trigger signal.

[0077] Example 17 is a method comprising the following steps: sampling an analog input signal with a sampling circuit; acquiring a trigger signal; pausing sampling of the analog input signal by the sampling circuit in response to acquiring the trigger signal; and, during the sampling pause, converting the sampling input acquired from the sampling circuit into a digital output by an analog-to-digital converter (ADC) and / or holding the sampling input acquired from the sampling circuit.

[0078] Example 18 is protected under Example 17, and the step of pausing sampling of the analog input signal may include a step of pausing sampling for a predetermined period of time.

[0079] Example 19 is a protected object of Example 17 or 18, which further includes the step of restarting sampling of the analog input signal at or after the completion of the conversion by the ADC.

[0080] Example 20 is a protected subject of Example 18 or 19, and a predetermined period can be specified in advance.

[0081] Example 21 is a protected object of any one of Examples 17 to 20, which further includes the step of suspending the conversion or retention of the sampling input after or at the end of a predetermined period.

[0082] Example 22 is protected under any one of Examples 17 to 21, wherein the step of pausing sampling of the analog input signal may include the step of opening a sampling switch of the sampling circuit, the sampling switch being coupled between the input of the sampling circuit and the input to the ADC.

[0083] Example 23 is a protected embodiment of any one of Examples 17 to 22, wherein the ADC can be a successive approximation register (SAR) ADC.

[0084] Example 24 is protected under any one of Examples 17 to 23, and the step of pausing sampling may include the step of pausing sampling immediately after acquiring the trigger signal.

[0085] Example 25 is protected under any one of Examples 17 to 23, and the step of pausing sampling may include pausing sampling after a predetermined period of time has elapsed since the acquisition of the trigger signal.

[0086] Example 26 is an analog-to-digital converter (ADC) system comprising the following means: the system comprises means for sampling an analog input signal, the sampling means having means for pausing sampling of the analog input signal in response to the acquisition of a trigger signal; the system comprises means for holding a sampling input obtained from the sampling means, the holding means having means for initiating the holding of the sampling input during a sampling pause; and the system further comprises means for converting the sampling input to a digital output, the conversion means having means for initiating the conversion of the sampling input during a sampling pause.

[0087] Example 27 is the protected object of Example 26, and this protected object may further include means for generating a trigger signal.

[0088] Example 28 is a protected object of Example 26 or 27, and the means for pausing sampling of the analog input signal may include means for pausing sampling for a predetermined period of time.

[0089] Example 29 is protected under any one of Examples 26 to 28, and the sampling means may include means for resuming sampling after a predetermined period of time has elapsed.

[0090] Example 30 is protected under Example 26, and the means for converting the sampling input may include means for stopping the conversion of the sampling input before the sampling means resumes sampling.

[0091] Example 31 is a protected subject of Example 29 or 30, and a predetermined period can be specified in advance.

[0092] It should be noted that one or more features of any of the above embodiments can be combined with any one of the other embodiments. It is obvious that the implementations of the methods detailed herein are illustrative in nature and are therefore understood to be implementable in corresponding apparatuses. Similarly, it is obvious that the implementations of the apparatuses detailed herein are understood to be implementable as corresponding methods. Therefore, it is obvious that apparatuses corresponding to the methods detailed herein may include one or more components configured to carry out each of the relevant aspects of the methods.

[0093] Although the present invention has been described in detail with reference to specific embodiments, those skilled in the art will understand that various modifications in form and detail can be made without departing from the idea and scope of the invention as defined by the appended claims. Therefore, the scope of the invention is expressed by the appended claims, and is therefore intended to encompass all modifications that fall within the spirit and scope of the equivalents of the claims.

Claims

1. A system including a sampling circuit configured such that the sampling of an input signal and the accumulation of a sampling voltage in a sampling capacitor are started at a first time point, and an analog-to-digital conversion circuit, The sampling circuit is configured to stop sampling at a second time point in response to the acquisition of a trigger signal, in order to maintain the sampling voltage in the sampling capacitor. The analog-to-digital conversion circuit includes an analog-to-digital converter (ADC) that converts the sampling input supplied from the sampling circuit into a digital output. The ADC is configured to begin converting the sampling input from the sampling circuit when the sampling circuit stops sampling or after it has stopped, and to complete the conversion of the sampling input to the digital output at a third point in time. The sampling circuit restarts sampling of the input signal at the third time point. system.

2. The sampling circuit restarts the sampling of the input signal at the third time point without resetting the sampling capacitor, thereby keeping the voltage on the sampling capacitor lower than the reference potential between the first and second time points. The system according to claim 1.

3. The sampling circuit is configured to start sampling when the system is powered on. The system according to claim 1.

4. The sampling circuit has a sampling switch coupled between the input section of the sampling circuit and the sampling capacitor. The sampling circuit is configured to stop sampling by opening the sampling switch in response to the acquisition of the trigger signal. The system according to any one of claims 1 to 3.

5. The sampling switch is configured as a normally closed switch, and is configured to be closed during sampling. The system according to claim 4.

6. The sampling circuit is configured to stop sampling for a predetermined period of time in response to the acquisition of the trigger signal. The system according to any one of claims 1 to 5.

7. The ADC is configured to terminate the conversion of the sampling input after a predetermined period or at the end of the predetermined period. The system according to claim 6.

8. The aforementioned period is a predetermined period. The system according to claim 6 or 7.

9. The sampling circuit is configured to resume sampling after the ADC has finished or has finished converting the sampling input. The system according to any one of claims 1 to 8.

10. The sampling circuit further includes an input capacitor coupled between a reference potential and the input section of the sampling circuit. The system according to any one of claims 4 to 9.

11. The ADC is a successive approximation register (SAR) ADC. The system according to any one of claims 1 to 10.

12. The ADC is configured to start converting the sampling input in response to an ADC circuit that acquires a second trigger signal different from the first trigger signal. The system according to any one of claims 1 to 11.

13. The sampling circuit is further configured to continuously sample the input signal before and until the trigger signal is acquired. The system according to any one of claims 1 to 12.

14. The sampling circuit is configured to stop sampling immediately after acquiring the trigger signal. The system according to any one of claims 1 to 13.

15. The sampling circuit is configured to stop sampling after a predetermined period of time has elapsed since the acquisition of the trigger signal. The system according to any one of claims 1 to 13.

16. A method that includes the following steps, In performing sampling of an analog input signal using a sampling circuit including a sampling switch and a sampling capacitor, the steps include: closing the sampling switch at a first time point to start accumulating the sampling voltage in the sampling capacitor due to the sampling; Steps to acquire a trigger signal, In response to the acquisition of the trigger signal, the sampling switch is opened at a second time point, and the sampling of the analog input signal by the sampling circuit is paused. During the pause of the sampling, The steps include converting the sampling voltage obtained from the sampling circuit into a digital output using an analog-to-digital converter (ADC) so as to be completed at a third point in time, The third step is to restart the sampling of the analog input signal at the third time point, A method that includes this.

17. The step of pausing sampling of the analog input signal includes a step of pausing sampling for a predetermined period of time. The method according to claim 16.

18. The sampling switch is coupled between the input section of the sampling circuit and the input section to the ADC. The method according to claim 16 or 17.

19. comprising a sampling circuit and an analog-to-digital converter (ADC), The sampling circuit has a sampling switch coupled to a sampling capacitor, and the sampling circuit is configured to start the sampling of the input signal and the accumulation of the sampling voltage in the sampling capacitor by closing the sampling switch at a first time point, and the sampling circuit is configured to stop the sampling at a second time point by opening the sampling switch in response to the acquisition of a trigger signal in order to hold the sampling voltage in the sampling capacitor. The analog-to-digital converter (ADC) is configured to convert the sampling voltage supplied from the sampling circuit into a digital output while the sampling switch is open, and to complete the conversion of the sampling voltage to the digital output at a third time point. The sampling circuit restarts the sampling of the input signal at the third time point without resetting the sampling capacitor to a fixed reference potential. system.

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