Display device, display panel, and method for manufacturing the same

Abstract

The present invention provides a display device, a display panel and a manufacturing method thereof, the display panel including a substrate (101), a wiring layer (103), a conductive shielding layer (4), a flat layer (104), a first electrode layer (2), a pixel definition layer (3), a light-emitting layer (5) and a second electrode (6), the wiring layer (103) being provided on one side of the substrate (101), the conductive shielding layer (4) being provided on the same side of the wiring layer (103) and the substrate (101), the flat layer (104) being provided on the wiring layer (102), and the flat layer (102) being provided on the same side of the wiring layer (102). the first electrode layer (2) is provided on the flat layer (104) and includes a first electrode (21), the first electrode (21) is connected to the wiring layer (103) via a first conductor (D1); the pixel definition layer (3) covers the flat layer (104); the light-emitting layer (5) covers the pixel definition layer (3) and the first electrode (21) and is connected to the conductive shielding layer (4) via a second conductor (D2); and the second electrode (6) covers the light-emitting layer (5).

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and more particularly, to a display device, a display panel, and a method for manufacturing a display panel.

Background Art

[0002] With the development of display technologies, display panels have been widely applied to various electronic devices such as mobile phones and are used to achieve image display and touch operations. Here, OLED (Organic Light-Emitting Diode) display panels are relatively common. However, the color gamut of existing display panels needs to be improved.

[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure and may include information that does not constitute prior art known to those skilled in the art.

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present disclosure is to provide a display device, a display panel, and a method for manufacturing a display panel.

Means for Solving the Problems

[0005] One aspect of the present disclosure provides a display panel including a substrate, at least one wiring layer, a conductive shielding layer, a planarization layer, a first electrode layer, a pixel definition layer, a light-emitting layer, and a second electrode. At least one wiring layer is provided on one side of the substrate. The conductive shielding layer is provided on the same side of the wiring layer and the substrate and is provided insulated from the wiring layer. The planarization layer covers the wiring layer and the conductive shielding layer. The first electrode layer is provided on the surface where the flat layer is separated from the substrate and includes a plurality of first electrodes distributed at intervals, the first electrodes being connected to the wiring layer via a first conductor located within the flat layer. The pixel definition layer covers the flat layer and exposes each of the first electrodes. The light-emitting layer covers the pixel definition layer and the first electrode, and is connected to the conductive shielding layer via a second conductor, at least a portion of which is located within the flat layer, and the orthographic projection of the second conductor onto the substrate is located apart from the orthographic projection of the first electrode onto the substrate. The second electrode covers the light-emitting layer.

[0006] In exemplary embodiments of the present disclosure, the pixel definition layer is provided with a partition groove recessed in the substrate, the orthographic projection of the partition groove onto the substrate is located elsewhere than the orthographic projection of the first electrode onto the substrate, and the light-emitting layer is recessed in the partition groove. The second conductor is inserted into the partition groove along the direction away from the substrate and embedded in the light-emitting layer.

[0007] In exemplary embodiments of the present disclosure, the flat layer is provided with a recess, and the orthographic projection of the recess onto the substrate is located other than the orthographic projection of the first electrode onto the substrate. The pixel definition layer extends to the side walls and bottom surface of the recess, forming the partition groove.

[0008] In exemplary embodiments of the present disclosure, the pixel definition layer covers the surface on which the second conductor is separated from the substrate and is intermittently provided on the sidewalls of the second conductor.

[0009] In exemplary embodiments of the present disclosure, the flat layer is provided with a recess, and the orthographic projection of the recess onto the substrate is located other than the orthographic projection of the first electrode onto the substrate. The orthographic projection of the pixel definition layer onto the substrate is located outside the orthographic projection of the recess onto the substrate, and the light-emitting layer is recessed in the recess. The second conductor is inserted into the recess along the direction away from the substrate and embedded within the light-emitting layer.

[0010] In exemplary embodiments of the present disclosure, the conductive shielding layer is provided in the same layer as one of the wiring layers.

[0011] In exemplary embodiments of the present disclosure, the wiring layers are of a number and are sequentially distributed along the direction away from the substrate, and two adjacent wiring layers are connected. The wiring layer that is furthest from the substrate is the target wiring layer, and the target wiring layer is connected to the first electrode via the first conductor. The conductive shielding layer is provided in the same layer as the target wiring layer.

[0012] In exemplary embodiments of the present disclosure, the length of the first conductor is greater than the length of the second conductor in a direction perpendicular to the substrate.

[0013] In exemplary embodiments of the present disclosure, the length of the portion of the second conductor located within the recess in a direction perpendicular to the substrate is less than the depth of the recess.

[0014] In exemplary embodiments of the present disclosure, the distance between the surface of the first conductor away from the substrate and the bottom surface of the recess, in a direction perpendicular to the substrate, is greater than the length of the portion of the second conductor located in the recess.

[0015] In exemplary embodiments of the present disclosure, the bottom surface of the recess has an opening region and a peripheral region located outside the opening region, the second conductor passes through the opening region, and the peripheral region protrudes toward the side away from the substrate from the opening region.

[0016] In exemplary embodiments of the present disclosure, the height to which the peripheral region protrudes into the opening region in a direction perpendicular to the substrate is less than the length of the portion of the second conductor that protrudes from the flat layer.

[0017] In an exemplary embodiment of the present disclosure, the number of the second conductors is plural, and each of them is connected to the shielding layer of the conductor.

[0018] In an exemplary embodiment of the present disclosure, the area of the surface of the second conductor away from the substrate is smaller than the area of the surface of the first conductor away from the substrate.

[0019] In an exemplary embodiment of the present disclosure, in the direction perpendicular to the substrate, the length of the first conductor is equal to the length of the second conductor.

[0020] In an exemplary embodiment of the present disclosure, the conductive shielding layer is connected to the second electrode.

[0021] In an exemplary embodiment of the present disclosure, the conductive shielding layer includes a first conductive layer, a second conductive layer, and a third conductive layer sequentially laminated in a direction away from the substrate.

[0022] In an exemplary embodiment of the present disclosure, the materials of the first conductive layer and the third conductive layer are both titanium metal, and the material of the second conductive layer is aluminum metal.

[0023] In an exemplary embodiment of the present disclosure, the light-emitting layer includes a plurality of light-emitting sub-layers connected in series, and at least one of the light-emitting sub-layers is connected in series with an adjacent light-emitting sub-layer through a charge generation layer.

[0024] In an exemplary embodiment of the present disclosure, the light-emitting layer is recessed as a first recessed region in a region corresponding to the recess, and a region where the bottom surface of the first recessed region corresponds to the second conductor protrudes as a first protruding region. The second electrode is recessed as a second recessed region in a region corresponding to the first recess, and a region where the bottom surface of the second recessed region corresponds to the first protrusion protrudes as a second protruding region.

[0025] One aspect of the present disclosure provides a method for manufacturing a display panel. Forming a substrate, A conductive shielding layer, at least one wiring layer, a flat layer covering the wiring layer and the conductive shielding layer, a first conductor, and a second conductor are formed on one side of the substrate, the conductive shielding layer is provided insulated from the wiring layer, the first conductor is located within the flat layer and connected to the wiring layer, and the second conductor enters the flat layer from the side of the flat layer away from the substrate and is connected to the conductive shielding layer. A first electrode layer is formed on the surface of the flat layer that is separated from the substrate, the first electrode layer includes a plurality of first electrodes distributed at intervals, the orthographic projection of the conductive shielding layer onto the substrate and the orthographic projection of the first electrodes onto the substrate are distributed at intervals, and the first electrodes are connected to the first conductor. A pixel definition layer is formed that covers the flat layer and exposes each of the aforementioned first electrodes. A light-emitting layer is formed to cover the pixel definition layer and the first electrode, and the light-emitting layer is connected to the second conductor. This includes forming a second electrode that covers the light-emitting layer.

[0026] In exemplary embodiments of the present disclosure, after forming the first electrode layer and before forming the pixel definition layer, the manufacturing method further: A recess is formed in the flat layer, the orthographic projection of the recess onto the substrate is located elsewhere than the orthographic projection of the first electrode onto the substrate, and the second conductor is inserted into the recess in a direction away from the substrate. The pixel definition layer extends to the side walls and bottom surface of the recess to form a partition groove, and the light-emitting layer is recessed into the partition groove.

[0027] In exemplary embodiments of the present disclosure, after forming the first electrode layer and before forming the pixel definition layer, the manufacturing method further: A recess is formed in the flat layer, the orthographic projection of the recess onto the substrate is located elsewhere than the orthographic projection of the first electrode onto the substrate, and the second conductor is inserted into the recess in a direction away from the substrate. The orthographic projection of the pixel definition layer onto the substrate is located outside the orthographic projection of the recess onto the substrate, and the light-emitting layer is recessed into the recess.

[0028] In exemplary embodiments of the present disclosure, a conductive shielding layer, at least one wiring layer, and a flat layer covering the wiring layer, a first conductor, a second conductor, and the conductive shielding layer are formed on one side of the substrate. A conductive shielding layer, at least one wiring layer, and a first flat insulating layer covering the conductive shielding layer and the wiring layer are formed on one side of the substrate. A first via and a second via are formed in the first flat insulating layer, extending to the substrate, the wiring layer is exposed in the first via, and the conductive shielding layer is exposed in the second via. A first conductive portion is formed in the first via, and a second conductor is formed in the second via. A second flat insulating layer is formed covering the first flat insulating layer, and the flat layer includes the first flat insulating layer and the second flat insulating layer. A third via is formed in the second flat insulating layer that penetrates the first via, The third via forms a second conductive portion connected to the first conductive portion, and the first conductor includes the first conductive portion and the second conductive portion.

[0029] In exemplary embodiments of the present disclosure, a conductive shielding layer, at least one wiring layer, and a flat layer covering the wiring layer, a first conductor, a second conductor, and the conductive shielding layer are formed on one side of the substrate. A conductive shielding layer, at least one wiring layer, and a flat layer covering the conductive shielding layer and the wiring layer are formed on one side of the substrate. A first via and a second via are formed in the flat layer, extending to the substrate, the wiring layer is exposed in the first via, and the conductive shielding layer is exposed in the second via. This includes forming a first conductor in the first via and forming a second conductor in the second via.

[0030] In exemplary embodiments of this disclosure, the conductive shielding layer and one of the wiring layers are formed simultaneously.

[0031] In exemplary embodiments of the present disclosure, the wiring layers are of a number and are sequentially distributed along the direction away from the substrate, and two adjacent wiring layers are connected. The wiring layer that is furthest from the substrate is the target wiring layer, and the target wiring layer is connected to the first electrode via the first conductor. The conductive shielding layer and the target wiring layer are formed simultaneously.

[0032] One aspect of this disclosure provides a display device including a display panel as described above.

[0033] The above general explanation and the detailed explanation below are illustrative and interpretive and do not limit this disclosure.

[0034] The drawings are incorporated herein by reference to embodiments conforming to the Disclosure and are used together with the Specification to illustrate the principles of the Disclosure. Clearly, the drawings in the following description are only a few embodiments of the Disclosure, and those skilled in the art can obtain other drawings based on these without any creative effort. [Brief explanation of the drawing]

[0035] [Figure 1] This is a schematic diagram illustrating the principle of leakage current in a conventional light-emitting unit circuit. [Figure 2] This is a diagram illustrating the principle of leakage current structure in a conventional light-emitting unit. [Figure 3] This is a spectral diagram of a conventional light-emitting unit. [Figure 4] This is a schematic diagram of one embodiment of the display panel of the present disclosure. [Figure 5] This is a schematic diagram of one embodiment of the display panel of the present disclosure. [Figure 6] This is a schematic diagram of one embodiment of the display panel of the present disclosure. [Figure 7] Figure 6 is a schematic diagram of a partial film layer in the embodiment shown. [Figure 8] This is a schematic diagram of one embodiment of the display panel of the present disclosure. [Figure 9] This is a plan view of a drive backplate in one embodiment of the display panel of the present disclosure. [Figure 10] A schematic diagram of the light-emitting layer in one embodiment of the display panel of this disclosure. [Figure 11] This is a schematic diagram of the leakage protection circuit for the display panel of this disclosure. [Figure 12] This is a spectral diagram of one embodiment of the display panel of the present disclosure. [Figure 13] A schematic diagram of voltage-luminance in one embodiment of the display panel of the present disclosure. [Figure 14] This is a schematic diagram of the voltage-color coordinates of a red subpixel in one embodiment of the display panel of the present disclosure. [Figure 15] This is a schematic diagram of the voltage-color coordinates of a blue subpixel in one embodiment of the display panel of the present disclosure. [Figure 16] This is a schematic diagram of the voltage-color coordinates of a green subpixel in one embodiment of the display panel of the present disclosure. [Figure 17] This is a schematic diagram illustrating the configuration of several steps in one embodiment of the manufacturing method for the display panel disclosed herein. [Figure 18] This is a schematic diagram illustrating the configuration of several steps in one embodiment of the manufacturing method for the display panel disclosed herein. [Figure 19] This is a schematic diagram illustrating the configuration of several steps in one embodiment of the manufacturing method for the display panel disclosed herein. [Figure 20] This is a schematic diagram illustrating the configuration of several steps in one embodiment of the manufacturing method for the display panel disclosed herein. [Figure 21] This is a schematic diagram illustrating the configuration of several steps in one embodiment of the manufacturing method for the display panel disclosed herein. [Figure 22] This is a schematic diagram illustrating the configuration of several steps in one embodiment of the manufacturing method for the display panel disclosed herein. [Modes for carrying out the invention]

[0036] Next, exemplary embodiments will be described in more detail with reference to the drawings. However, exemplary embodiments can be carried out in various forms and should not be understood as being limited to the embodiments described herein. In contrast, these embodiments are provided to ensure that this disclosure is comprehensive and complete and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures and therefore no further detailed description is given. Also, the drawings are merely schematic illustrations of this disclosure and are not necessarily drawn proportionally.

[0037] The terms “one,” “one,” “the said,” and “at least one” are used to indicate the presence of one or more elements / components / etc. The terms “including” and “having” are used to mean open inclusion and mean elements / components / etc. that may exist in addition to the listed elements / components / etc. The terms “first,” “second,” “third,” etc. are used only as markers and do not imply a quantitative limitation of the subject.

[0038] In related technologies, Micro OLED display panels (Micro Organic Light-Emitting Diodes) are a display panel that has developed in recent years, and the Micro OLED light-emitting elements contained within them are typically less than 100 μm in size. Silicon-based OLED display panels are a relatively common type, and silicon-based OLEDs not only enable active addressing of pixels, but also allow for the fabrication of CMOS circuits, including pixel circuits, timing control (TCON) circuits, and overcurrent protection (OCP) circuits, on a silicon substrate using semiconductor manufacturing processes, which is advantageous for reducing system volume and achieving weight reduction.

[0039] Taking a silicon-based OLED display panel as an example, it may include a drive backplate and an emissive layer, where the emissive functional layer is provided on one side of the drive backplate and may include multiple light-emitting elements. This emissive unit includes one or more OLED light-emitting elements connected in series, and each light-emitting element includes a first electrode (anode), an emissive layer, and a second electrode (cathode) sequentially stacked in the direction away from the drive backplate. By applying electrical signals to the first and second electrodes, the emissive layer can be driven to emit light. The specific light emission principle of the OLED light-emitting elements is omitted here.

[0040] Furthermore, the light-emitting layer of each light-emitting element can be formed by direct deposition of a fine mask plate (FMM), and the light-emitting layers of each light-emitting element are distributed at intervals, emitting light independently and enabling color display. However, due to the limitations of the manufacturing process of the fine mask plate, it is difficult to achieve a high PPI (pixel density). Therefore, color display can also be achieved by a color film mixed with monochromatic or white light. That is, each light-emitting element shares the same continuous light-emitting layer, the light-emitting layer can generate white light or other monochromatic light, the color film layer has multiple filter regions that correspond one-to-one with the light-emitting units, one filter region and the corresponding light-emitting unit can constitute one subpixel, multiple subpixels constitute one pixel, the colors of light that can be transmitted by different filter regions can be different, thereby making the emitted colors of different subpixels different, the same pixel can contain multiple subpixels of different colors, for example, one pixel can contain three subpixels each having the emitted colors red (R), green (G), and blue (B). This enables color display using multiple pixels.

[0041] However, if the light-emitting layer is a continuous, all-layer structure, leakage current is more likely to occur between one light-emitting unit and surrounding light-emitting units, causing color transfer. Therefore, the following diagrams are combined to analyze the cause of color transfer.

[0042] As shown in Figure 1, each light-emitting unit includes two series-connected light-emitting elements, the two light-emitting elements sharing a first electrode 2a and a second electrode 3a, and having two light-emitting sublayers 1a between the first electrode 2a and the second electrode 3a, the two light-emitting sublayers 1a are connected in series via a charge generation layer 4a to form a light-emitting layer. As can be seen from Figures 1 and 2, positive charges (holes) move between two adjacent light-emitting units via the charge generation layer 4a, but as can be seen from Figure 2, when the light-emitting unit corresponding to the red filter region R in the color film layer 5a emits light, the light-emitting unit corresponding to the green filter region G in the color film layer 5a also emits light due to the effect of leakage current, reducing the light emission purity of a single pixel and reducing the color gamut of the entire display panel.

[0043] As shown in Figure 3, Figure 3 shows the spectral diagram when three subpixels—red (R), green (G), and blue (B)—are lit simultaneously in the same pixel (shown in Figure 3a), and the spectral diagrams when each subpixel is lit individually (shown in Figure 3bc). As can be seen from the wavelengths, when the three subpixels are lit, different colored light is emitted from adjacent subpixels. For example, as shown in Figure 3a, when the R subpixel emits red light, there are peaks emitted by blue and green light at wavelengths corresponding to blue and green light. This reduces the overall color gamut of the display panel. According to calculations, the display panel's color gamut index (NTSC) is only 30%.

[0044] Embodiments of this disclosure provide a display panel, as shown in Figures 4 to 9, which includes a drive backplate 1, a first electrode layer 2, a pixel definition layer 3, a light-emitting layer 5, a second electrode 6, and a color film layer 7, where, The drive backplate 1 includes a substrate 101, a conductive shielding layer 4, at least one wiring layer 103 located on one side of the substrate 101, and a flat layer 104 covering the wiring layer 103 and the conductive shielding layer 4. The conductive shielding layer 4 is provided insulated from each wiring layer 103.

[0045] The first electrode layer 2 is provided on the surface of the flat layer 104 away from the substrate 101 and includes a plurality of first electrodes 21 distributed at intervals, the orthographic projection of the first electrodes 21 onto the substrate 101 and the orthographic projection of the conductive shielding layer 4 onto the substrate 101 are distributed at intervals, and the first electrodes 21 are connected to the wiring layer 103 via a first conductor D1 located within the flat layer 104.

[0046] The pixel definition layer 3 covers the flat layer 104, exposing each first electrode 21. The light-emitting layer 5 covers the pixel definition layer 3 and the first electrodes 21, and is connected to the conductive shielding layer 4 via a second conductor D2, at least a portion of which is located in the flat layer 104. The second electrode 6 covers the light-emitting layer 5.

[0047] In the embodiment of the present disclosure, the display panel can be configured as a light-emitting unit 001, comprising either a first electrode 21, a corresponding light-emitting layer 5, and a second electrode 6. The orthographic projection of the conductive shielding layer 4 onto the substrate 101 is located outside the orthographic projection of the wiring layer 103 onto the substrate 101 and is connected to the light-emitting layer 5 via the second conductor D2. Therefore, carriers (e.g., holes) moving in the distribution direction of the first electrode 21 generated in the light-emitting layer 5 can be absorbed through the conductive shielding layer 4, thereby preventing mutual leakage between the light-emitting units 001 and improving color transfer.

[0048] Next, we will describe in detail the configuration by which the display panel of this disclosure realizes the display function.

[0049] As shown in Figures 4 to 9, the drive backplate 1 includes a pixel region 110 and a peripheral region 120, where the peripheral region 120 is located outside the pixel region 110 and is arranged around the pixel region 110. The drive backplate 1 is used to form a drive circuit that drives the light emission of the light emission unit 001, and the drive circuit may include a pixel circuit and a peripheral circuit, where, The number of pixel circuits and light-emitting units 001 may be multiple, the pixel circuits are located within the pixel region 110, and the pixel circuits may be 2T1C, 4T2C, 6T1C, or 7T1C, and as long as they can drive the light-emitting units 001 to emit light, their structure is not particularly limited here. The number of pixel circuits is the same as the number of first electrodes 21, and they are connected to the first electrodes 21 in a one-to-one correspondence to control the light emission of each light-emitting unit 001. Here, nTmC indicates that one pixel circuit contains n transistors (represented by the letter "T") and m capacitors (represented by the letter "C").

[0050] The peripheral circuit is located in the peripheral region 120 and is connected to the pixel circuit. The peripheral circuit may include at least one of a light emission control circuit, a gate 102 drive circuit, a source drive circuit, and a power supply circuit, and may also include other circuits that can drive the light emission unit 001 to emit light via the pixel circuit. The peripheral circuit may also include a power supply circuit connected to the second electrode 6 for inputting a power supply signal to the second electrode 6. The peripheral circuit can input a drive signal to the first electrode 21 via the pixel circuit and a power supply signal to the second electrode 6 to cause the light emission unit 001 to emit light.

[0051] In some embodiments of this disclosure, as shown in Figures 4 to 8, the substrate 101 may be a silicon substrate, and the above-described drive circuit may be formed on the silicon substrate by a semiconductor process. For example, both the pixel circuit and the peripheral circuit may include multiple transistors, and a well region 1011 may be formed on the silicon substrate by a doping process, and the well region 1011 has two spaced-apart doping regions 1012. Taking one well region 1011 as an example, a gate 102 is provided on one side of the drive backplate 1, that is, the orthogonal projection of the gate 102 onto the substrate 101 is located between the two doping regions 1012. At least one wiring layer 103 is connected to the doping region 1012, and one wiring layer 103 may include a source 1031S and a drain 1031D connected to two doping regions 1012 of the same well region 1011.

[0052] For example, the number of wiring layers 103 is two, located within the flat layer 104, and for example, the wiring layer 103 includes a first wiring layer 1031 provided on one side of the substrate 101, with a portion of the flat layer 104 between it and the substrate 101, and a second wiring layer 1032. The first wiring layer 1031 includes a source 1031S and a drain 1031D, and the source 1031S and drain 1031D of the same transistor are respectively connected to two doping regions 1012 of the same well region 1011, and a transistor can be formed via the well region 1011 and its corresponding gate 102, source 1031S and drain 1031D. The second wiring layer 1032 is provided on the side away from the substrate 101 from the first wiring layer 1031, separated from the first wiring layer 1031 by a portion of the flat layer 104, and at least a portion of the second wiring layer 1032 is connected to the first wiring layer 1031. By connecting transistors via each wiring layer 103, a drive circuit can be formed. The specific connection circuit and wiring pattern will vary depending on the circuit configuration and are not particularly limited here.

[0053] Each wiring layer 103 can be formed by a sputtering process. The material for the flat layer 104 can be silicon oxide, silicon nitride, or silicon nitride, and each layer can be formed by multiple deposition and polishing processes; that is, the flat layer 104 can be laminated from multiple insulating film layers.

[0054] As shown in Figures 4 to 8, each array of light-emitting units 001 of the display panel is distributed on one side of the drive backplate 1. For example, each light-emitting unit 001 is provided on the surface where the flat layer 104 is separated from the substrate 101. Each light-emitting unit 001 may include a first electrode 21, a second electrode 6, and a light-emitting layer 5 located between the first electrode 21 and the second electrode 6. Both the first electrode 21 and the second electrode 6 are connected to the wiring layer 103. A drive signal is applied to the first electrode 21 and a power signal is applied to the second electrode 6 via the drive backplate 1, driving the light-emitting layer 5 to emit light.

[0055] To achieve color display, each light-emitting unit 001 emits light of the same color, and color display can be achieved by aligning the second electrode 6 with the color film layer 7 located on the side away from the substrate 101. The embodiments of this disclosure will be described using this form of color display as an example. Of course, each light-emitting unit 001 may be made to emit light independently, and the emitted colors of different light-emitting units 001 may be different.

[0056] In some embodiments of this disclosure, as shown in Figures 4-9, a plurality of light-emitting units 001 can be formed by a first electrode layer 2, a pixel definition layer 3, a light-emitting layer 5, and a second electrode 6, where, The first electrode layer 2 is provided on the surface where the flat layer 104 is separated from the substrate 101. The first electrode layer 2 may include a plurality of first electrodes 21 with a spacing distribution, and the orthogonal projection of each first electrode 21 onto the substrate 101 is located in the pixel region 110 and connected to the pixel circuit, with one first electrode 21 connected to one pixel circuit.

[0057] The first electrode 21 can be connected to the wiring layer 103 that is the furthest from the substrate 101 from among multiple wiring layers 103. For example, a first via can be opened in a flat layer 104 in which the wiring layer 103 is exposed, and a first conductor D1 can be formed on the first via. The first electrode 21 covers the first via and is connected to this wiring layer 103 via the first conductor D1, thereby connecting the first electrode 21 to the pixel circuit.

[0058] In some embodiments of the present disclosure, as described above, the wiring layer 103 includes a first wiring layer 1031 and a second wiring layer 1032, and the first electrode 21 can be connected to the second wiring layer 1032 via a first conductor D1 located in the first via.

[0059] The first electrode layer 2 may be a single layer or a multilayer structure, and its material is not particularly limited here. For example, the first electrode layer 2 may include a first layer 201, a second layer 202, a third layer 203, and a fourth layer 204 that are sequentially stacked away from the substrate 101, where the first layer 201 and the third layer 203 may be made of the same metallic material, such as titanium, and the fourth layer 204 may be made of a transparent conductive material such as ITO (indium tin oxide). The second layer 202 may be made of a different metallic material than the first layer 201, the third layer 203, and the fourth layer 204, and may have a lower resistivity than the first layer 201 and the third layer 203. For example, the material of the second layer 202 may be aluminum.

[0060] As shown in Figures 4 to 8, the pixel definition layer 3 covers the flat layer 104 and exposes each first electrode 21. Specifically, the pixel definition layer 3 is provided with an opening 31 that exposes the first electrode 21, and the pixel definition layer 3 and its opening 31 can limit the range of each light-emitting unit 001. The material of the pixel definition layer 3 may be an insulating material such as silicon oxide or silicon nitride, and is not particularly limited here.

[0061] The orthographic projection of any of the apertures 31 onto the substrate 101 is located within the exposed first electrode 21, i.e., the aperture 31 is not larger than the exposed first electrode 21. In some embodiments of this disclosure, the pixel definition layer 3 is located on the surface away from the substrate 101 and has an extended portion that covers and extends over the edge of the first electrode 21, the aperture 31 is provided in the extended portion, and the extended portion has an annular structure having the aperture 31. The shape of the aperture 31 may be a polygon such as a rectangle, pentagon, or hexagon, but is not necessarily a regular polygon, and the shape of the aperture 31 may be other shapes such as an ellipse, and is not particularly limited herein.

[0062] As shown in Figures 4 and 10, the light-emitting layer 5 covers the pixel definition layer 3 and the first electrode 21, and the light-emitting layer 5 is located within the aperture 31. The region stacked with the first electrode layer 2 is used to form a light-emitting unit 001. That is, each light-emitting unit 001 can share the same light-emitting layer 5, meaning that portions of the light-emitting layer 5 located within different apertures 31 belong to different light-emitting units 001. Also, since each light-emitting unit 001 shares the light-emitting layer 5, the light-emitting color of different light-emitting units 001 will be the same.

[0063] In some embodiments of the present disclosure, as shown in Figure 10, the light-emitting unit 001 may include a plurality of light-emitting elements, each including a first electrode 21, a second electrode 6, and a plurality of light-emitting sublayers 51 between the first electrode 21 and the second electrode 6, where each light-emitting element of the same light-emitting unit 001 shares the same first electrode 21 and the same second electrode 6, that is, the same light-emitting unit 001 may have only one first electrode 21 and one second electrode 6.

[0064] For example, as shown in Figure 10, the light-emitting layer 5 may include a plurality of light-emitting sublayers 51 connected sequentially in series away from the substrate 101, with at least one light-emitting sublayer 51 connected in series with an adjacent light-emitting sublayer 51 via a charge-generating layer 52. When an electrical signal is applied to the first electrode 21 and the second electrode 6, each light-emitting sublayer 51 can emit light, and different light-emitting sublayers 51 can be used to emit light rays of different colors.

[0065] Furthermore, as shown in Figure 10, each light-emitting sublayer 51 can include a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting material layer (EL), an electron transport layer (ETL), and an electron injection layer (EIL) distributed away from the substrate 101. A detailed explanation of the specific light emission principle is omitted here. The number of hole injection layers, hole transport layers, electron transport layers, and electron injection layers is not particularly limited here, and each light-emitting sublayer 51 can share one or more of the hole injection layers, hole transport layers, electron transport layers, and electron injection layers. At the same time, a charge generation layer 52 can be provided between at least two adjacent light-emitting sublayers 51 to connect two light-emitting sublayers 51 in series.

[0066] In some embodiments of this disclosure, as shown in Figure 10, the light-emitting layer 5 may include three light-emitting sublayers 51 of different colors: a first light-emitting sublayer 51 that emits red light, a second light-emitting sublayer 51 that emits green light, and a third light-emitting sublayer 51 that emits blue light. When the first, second, and third light-emitting sublayers 51 emit light simultaneously, the light-emitting layer 5 can emit white light. Here, the first and second light-emitting sublayers 51 share a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. The light-emitting material layer of the second light-emitting sublayer 51 is provided on the surface away from the substrate 101 from the light-emitting material layer of the first light-emitting sublayer 51, thereby directly connecting the first and second light-emitting sublayers 51 in series. A charge generation layer 52 may be provided on the surface of the second light-emitting sublayer 51 away from the substrate 101. The third light-emitting sublayer 51 shares an electron injection layer with the first light-emitting sublayer 51 and the second light-emitting sublayer 51. The hole injection layer of the third light-emitting sublayer 51 is provided on the surface away from the substrate 101, and the third light-emitting sublayer 51 and the second light-emitting sublayer 51 can be connected in series.

[0067] As shown in Figures 4 to 8, the second electrode 6 covers the light-emitting layer 5, and the orthographic projection of the second electrode 6 onto the substrate 101 covers the pixel area 110 and can extend into the peripheral area 120. Each light-emitting unit 001 can share the same second electrode 6. When the voltage difference between the second electrode 6 and the first electrode 21 reaches a differential pressure that can cause the light-emitting layer 5 to emit light, the light-emitting layer 5 can be made to emit light. Therefore, the emission of light from the light-emitting layer 5 can be controlled by controlling the voltage of the power supply signal input to the second electrode 6 and the drive signal input to the first electrode 21.

[0068] As shown in Figures 4 to 8, in order to achieve color display, the display panel is provided with the second electrode 6 on the side away from the substrate 101, and includes a color film layer 7 containing a plurality of filter sections 71, with each first electrode 21 and each filter section 71 arranged one-to-one opposite each other in a direction perpendicular to the substrate 101, that is, the orthographic projection of the filter section 71 onto the flat layer 104 overlaps with at least a portion of the first electrode 21. Each filter section 71 includes at least three color filter sections 71, for example, a filter section 71 that can transmit red light, a filter section 71 that can transmit green light, and a filter section 71 that can transmit blue light. The light rays emitted by each light-emitting unit 001 pass through the filtering action of the filter unit 71 to obtain monochromatic light of different colors, thereby realizing color display. Here, one filter unit 71 and its corresponding light-emitting unit 0011 can constitute one subpixel, and the color emitted by any subpixel is the color of the light rays transmitted through that filter unit 71. Multiple subpixels can constitute one pixel, and the emitted colors of each subpixel of the same pixel are different.

[0069] The orthographic projection of the filter section 71 onto the substrate 101 may be the same as the shape of the aperture 31 of the pixel definition layer 3, and the orthographic projection of each aperture 31 onto the substrate 101 may be located in a one-to-one correspondence within the orthographic projection of each filter section 71 onto the substrate 101.

[0070] As shown in Figures 4 to 8, the color film layer 7 further includes a light-shielding portion 72 that shields the filter portion 71 from light, and the light-shielding portion 72 does not transmit light and can shield the area between the two light-emitting units 001. The filter portion 71 can be provided directly with a light-shielding material at a distance from the filter portion 71, or, in some embodiments of this disclosure, adjacent filter portions 71 may be stacked in corresponding areas between two adjacent light-emitting units 001, and the colors of light transmitted by each may be different so that the stacked area does not transmit light.

[0071] Furthermore, in some embodiments of this disclosure, in order to enhance screen brightness when the light-emitting layer 5 emits white light, the color film layer 7 may further include a transparent portion positioned opposite the light-emitting unit 001 in a direction perpendicular to the substrate 101, so that the color film layer 7 can also transmit white light and increase brightness with white light.

[0072] To improve the efficiency of light transmission, the light extraction layer 11 can be applied to the side of the second electrode 6 that is away from the substrate 101 to increase brightness. Furthermore, the light extraction layer 11 can directly cover the surface of the second electrode 6 that is away from the substrate 101.

[0073] To facilitate connection between the second electrode 6 and the drive circuit, in some embodiments of the present disclosure, the first electrode layer 2 further includes an adapter ring whose orthogonal projection onto the substrate 101 is located in the peripheral region 120, which can be connected to the peripheral circuit and surrounds the outside of the pixel region 110. The second electrode 6 can be connected to the adapter ring so that the second electrode 6 and the peripheral circuit can be connected via the adapter ring in order to apply a drive signal from the peripheral circuit to the second electrode 6. The pattern of the adapter ring may be the same as the pattern of the first electrode 21 in the pixel region 110 in order to improve the uniformity of the pattern of the first electrode layer 2.

[0074] As shown in Figures 4 to 8, in some embodiments of the present disclosure, the display panel of the present disclosure may further include a first encapsulation layer 8 located between the color film layer 7 and the second electrode 6, where the second electrode 6 is provided on the side away from the substrate 101, and to block external water and oxygen erosion. The first encapsulation layer 8 may be a single layer or a multilayer structure, for example, the first encapsulation layer 8 may include a first encapsulation sublayer 81, a second encapsulation sublayer 82, and a third encapsulation sublayer 83 stacked in order away from the substrate 101, where the material of the first encapsulation sublayer 81 and the second encapsulation sublayer 82 may be an inorganic insulating material such as silicon nitride or silicon oxide, and the second encapsulation sublayer 82 may be formed using an ALD (Atomic Layer Deposition) process, and the material of the third encapsulation sublayer 83 may be an organic material that can be formed using an MLD (Molecular Layer Deposition) process. Of course, the first encapsulation layer 8 can employ other structures, and the structure of the first encapsulation layer 8 is not particularly limited here.

[0075] Furthermore, in some embodiments of the present disclosure, the display panel of the present disclosure may include a transparent cover plate 10 on which the color film layer 7 is covered on the side away from the substrate 101, the transparent cover plate 10 may be single-layer or multi-layer, and its material is not particularly limited herein.

[0076] In some embodiments of the present disclosure, the display panel of the present disclosure may further include a second encapsulation layer 9 that can cover the surface of the color film layer 7 away from the substrate 101 in order to achieve planarization for easy covering of the transparent cover plate 10, and which can enhance the packaging effect and further block water and oxygen. The second encapsulation layer 9 may be a single layer or a multilayer structure, may contain an inorganic material such as silicon nitride or silicon oxide, or an organic material, and the structure of the second encapsulation layer 9 is not particularly limited here.

[0077] Next, we will describe in detail how to resolve the color transfer problem caused by the display panel of this disclosure.

[0078] In line with the analysis of the related technologies described above, since each light-emitting unit 001 shares the light-emitting layer 5, carriers (e.g., holes) from one light-emitting unit 001 can move to other light-emitting units 001 via film layers such as the charge generation layer 52, and in particular to adjacent light-emitting units 001, i.e., leakage current can occur, potentially affecting the purity of light emission. Therefore, as shown in Figures 4 to 8, a conductive shielding layer 4 is provided on the drive backplate 1, and the conductive shielding layer 4 is conductive, although it is insulated from the wiring layer 103. Simultaneously, a second via can be formed in the flat layer 104 to expose the conductive shielding layer 4, and a second conductor D2 is formed within the second via. The orthographic projection of the second conductor D2 onto the substrate 101 is located elsewhere than the orthographic projection of the first electrode 21 onto the substrate 101. The light-emitting layer 5 covers the second conductor D2, and the conductive shielding layer 4 is connected to the light-emitting layer 5 via the second conductor D2. This allows the conductive shielding layer 4 to absorb carriers during transmission by the second conductor D2, preventing carrier movement between the light-emitting units 001 and avoiding color transfer due to leakage current.

[0079] The conductive shielding layer 4 can be connected to a peripheral circuit to lead out carriers. For example, although the light-emitting layer 5 is also present between the conductive shielding layer 4 and the second electrode 6, the conductive shielding layer 4 does not drive the light-emitting layer 5 to emit light because it is connected to the second electrode 6. Of course, the conductive shielding layer 4 may be grounded directly via a peripheral circuit, or other signals may be introduced, as long as it is possible to lead out carriers in a way that avoids leakage current between adjacent light-emitting units 001 and prevents the light-emitting layer 5 from emitting light in the region corresponding to the conductive shielding layer 4.

[0080] As shown in Figures 4 to 8, the conductive shielding layer 4 may be a single layer or a multilayer structure. For example, in some embodiments of the present disclosure, the conductive shielding layer 4 includes a first conductive layer 41, a second conductive layer 42, and a third conductive layer 43 that are sequentially stacked in the direction away from the substrate 101. The materials of the first conductive layer 41 and the third conductive layer 43 may be the same as those of the first layer 201 and the third layer 203 of the first electrode layer 2. For example, the materials of the first conductive layer 41 and the third conductive layer 43 may both be metallic titanium, and the material of the second conductive layer 42 may be the same as that of the second layer 202 of the first electrode layer 2. For example, the material of the second conductive layer 42 may be metallic aluminum. This allows the conductive shielding layer 4 to be formed using at least part of the process for forming the first electrode layer 2, thereby saving costs. At the same time, the conductive performance of the conductive shielding layer 4 can be made similar to that of the first electrode layer 2, and it is possible to avoid the absorption of too many or too few carriers, which would affect normal light emission.

[0081] As shown in Figures 4 to 8, in order to simplify the process, the conductive shielding layer 4 can be placed in the same layer as one wiring layer 103, that is, the conductive shielding layer 4 can be formed simultaneously with one wiring layer 103, in some embodiments of the present disclosure there are multiple wiring layers 103, which are distributed sequentially along the direction away from the substrate 101, and the wiring layer 103 that is furthest from the substrate 101 is the target wiring layer, which is connected to the first electrode 21 via the first conductor D1, and the conductive shielding layer 4 is provided in the same layer as the target wiring layer. Furthermore, with respect to the first wiring layer 1031 and the second wiring layer 1032 described above, the target wiring layer is the second wiring layer 1032.

[0082] As shown in Figures 4 to 8, in some embodiments of the present disclosure, the pixel definition layer 3 can be made to correspond to an area other than the light-emitting unit 001, i.e., an area other than the aperture 31, and a partition groove 32 can be formed, and the orthogonal projection of the partition groove 32 onto the substrate 101 is located other than the orthogonal projection of the first electrode 21 onto the substrate 101. The light-emitting layer 5 can be recessed into the partition groove 32, which is advantageous for thinning and also cuts the charge generation layer 52 and at least some of the light-emitting sublayer 51 in the light-emitting layer 5, and the partition groove 32 of the pixel definition layer 3 can separate each light-emitting unit 001, and the light-emitting layer 5 can be recessed into the partition groove 32, so that the light-emitting layer 5 does not need to climb a slope on the side wall of the partition groove 32, which is advantageous for thinning or cutting the light-emitting layer 5 in the partition groove 32, further preventing mutual leakage between adjacent light-emitting units 001 and improving color transfer.

[0083] In order to form the partition groove 32, in some embodiments of the present disclosure, as shown in Figures 4 and 20, a recess 1041 can be provided in the flat layer 104 of the drive backplate 1, the thickness of the pixel definition layer 3 is less than the depth of the recess 1041, and the partition groove 32 is recessed in the recess 1041, i.e., the pixel definition layer 3 extends into the recess 1041, covering the side walls and bottom surface of the recess 1041 to form the partition groove 32, i.e., the partition groove 32 does not penetrate the pixel definition layer 3 in the depth direction. In order to prevent the recess 1041 from exposing the wiring layer 103, each wiring layer 103 can be located on the side of the bottom surface of the recess 1041 closer to the substrate 101 so as not to be exposed in the recess 1041.

[0084] As shown in Figures 4 and 21, the depth of the partition groove 32 can be set to 800 μm to 1000 μm, for example, 800 μm, 900 μm, or 1000 μm, in order to allow the partition groove 32 to recess the light-emitting layer 5. The bottom surface of the partition groove 32 is not limited to a flat surface, but may be a curved or irregular surface, and the depth of the partition groove 32 refers to the distance between the point where the bottom surface of the partition groove 32 is closest to the substrate 101 and the substrate 101.

[0085] The orthographic projection of the second conductor D2 onto the substrate 101 can be located within the orthographic projection of the partition groove 32 onto the substrate 101, and the second conductor D2 includes not only the portion located within the second via but also the portion located outside the second via and within the partition groove 32, so that the second conductor D2 contacts the light-emitting layer 5, i.e., is embedded within the light-emitting layer 5. In other words, the second conductor D2 can penetrate the bottom of the partition groove 32 and enter into the partition groove 32. Since the partition groove 32 is located within the recess 1041, it is natural that the second conductor D2 that penetrates the partition groove 32 is also inserted into the recess 1041.

[0086] As shown in Figure 5, in other embodiments of the present disclosure, the pixel definition layer 3 is not recessed into the recess 1041 but is cut at the location of the recess 1041 to expose the recess 1041, i.e., the orthographic projection of the pixel definition layer 3 onto the substrate 101 is located outside the orthographic projection of the recess 1041 onto the substrate 101. The light-emitting layer 5 can be recessed into the recess 1041, and the light-emitting layer 5 can also be thinned or cut within the recess 1041, further preventing mutual leakage between adjacent light-emitting units 001 and improving color transfer. The second conductor D2 is inserted into the recess 1041 in a direction away from the substrate 101 and is embedded in the light-emitting layer 5 to connect with the light-emitting layer 5.

[0087] In some embodiments of this disclosure, as shown in Figure 4, a portion of the second conductor D2 is located within the recess 1041 and does not need to be connected to the first electrode 21. Therefore, the length of the portion of the second conductor D2 located within the recess 1041 in the direction perpendicular to the substrate 101 is smaller than the depth of the recess 1041. That is, the second conductor D2 does not protrude from the recess 1041, and it is sufficient that the second conductor D2 can be brought into contact with the light-emitting layer 5. Furthermore, in the direction perpendicular to the substrate 101, the length of the second conductor D2 can be made smaller than the length of the first conductor D1 to avoid the second conductor D2 located within the recess 1041 being too long and prone to breakage.

[0088] Furthermore, as shown in Figure 4, in a direction perpendicular to the substrate 101, the distance between the surface of the first conductor D1 away from the substrate 101 and the bottom surface of the recess 1041 is greater than the length of the portion of the second conductor D2 located within the recess 1041.

[0089] Furthermore, if the pixel definition layer 3 has a partition groove 32 recessed into the recess 1041, in order for the second conductor D2 to penetrate the pixel definition layer 3 and enter the partition groove 32, the length of the portion of the second conductor D2 located within the recess 1041 in the direction perpendicular to the substrate 101 should be greater than the thickness of the pixel definition layer 3.

[0090] Furthermore, since the length of the second conductor D2 is shorter than the length of the first conductor D1, and it is difficult to form both simultaneously in a primary process, in some embodiments of this disclosure, the first conductor D1 is divided into a first conductive portion D11 and a second conductive portion D12, and the flat layer 104 is divided into a first flat insulating layer P1 and a second flat insulating layer P2, the first flat insulating layer P1 covers each wiring layer 103 and conductive shielding layer 4, the first conductive portion D11 and the second conductor D2 of the first conductor D1 are located in the first flat insulating layer P1, and the second conductive portion D12 of the first conductor D1 is located in the second flat insulating layer P2, thereby obtaining a first conductor D1 and a second conductor D2 of different lengths. The recess 1041 is provided in the second flat insulating layer P2 and can extend into the first flat insulating layer P1.

[0091] As shown in Figures 4 to 8, the first via and the second via housing the first conductor D1 and the second conductor D2 may both have a tapered structure. Therefore, the first conductor D1 and the second conductor D2 also have a tapered structure, meaning that the surface area closer to the substrate 101 is smaller than the surface area further away from the substrate 101. However, since the first conductive portion D11 of the first conductor D1 and the second conductor D2 are provided in the same layer, the surface area of ​​the second conductor D2 further away from the substrate 101 and the surface area of ​​the first conductive portion D11 further away from the substrate 101 are the same, but the surface area of ​​the second conductive portion D12 further away from the substrate 101 is smaller. That is, the surface area of ​​the second conductor D2 further away from the substrate 101 is smaller than the surface area of ​​the first conductive portion D11 further away from the substrate 101.

[0092] Furthermore, the flat layer 104 may be a multilayer structure using the same material. For example, since silicon nitride is used in both the first flat insulating layer P1 and the second flat insulating layer P2, the flat layer 104 can be considered as the whole. However, it is not limited to being formed in a single process, and may be formed in multiple stages.

[0093] As shown in Figure 8, in other embodiments of the present disclosure, the lengths of the first conductor D1 and the second conductor D2 in the direction perpendicular to the substrate 101 may be the same and they may be formed simultaneously. For example, after forming a flat layer 104, a first via and a second via of the same depth may be formed simultaneously, with the first conductor D1 formed in the first via and the second conductor D2 formed in the second via.

[0094] In some embodiments of this disclosure, when forming the pixel definition layer 3, the surface of the second conductor D2 that is away from the substrate 101 can be covered, but the light-emitting layer 5 can be in contact with the second conductor D2, exposing at least the sidewall of the second conductor D2. Of course, in order to increase the contact area between the second conductor D2 and the light-emitting layer 5, after forming the pixel definition layer 3, the pixel definition layer 3 covering the second conductor D2 can be removed, allowing the surface of the second conductor D2 that is away from the substrate 101 to be in contact with the light-emitting layer 5.

[0095] As shown in Figures 6 and 7, in some embodiments of the present disclosure, the bottom surface of the recess 1041 may have an opening region H1 and a peripheral region H2 located outside the opening region H1, the second conductor D2 passing through the opening region H1, the peripheral region H2 protruding toward the side away from the substrate 101, and the contour of the peripheral region H2 may be arc-shaped or other smooth curve. Furthermore, in order to ensure that the second conductor D2 can contact the light-emitting layer 5, the height of the peripheral region H2 protruding from the opening region H1 in a direction perpendicular to the substrate 101 may be made smaller than the length of the portion of the second conductor D2 protruding from the flat layer 104, that is, the surface of the second conductor D2 away from the substrate 101 may be positioned toward the side of the peripheral region H2 away from the substrate 101. Therefore, if the pixel definition layer 3 extends to the sidewall and bottom surface of the recess 1041, the pixel definition layer 3 may protrude into the region corresponding to the peripheral region H2.

[0096] Furthermore, due to the presence of the recess 1041 and the second conductor D2, the light-emitting layer 5 can be recessed as a first recessed region A1 in the area corresponding to the recess 1041. The bottom surface of the first recessed region A1 is convex as a first convex region T1 in the area corresponding to the second conductor D2.

[0097] Therefore, the second electrode 6 is recessed as the second recessed region A2 in the region corresponding to the first recessed region A1. The bottom surface of the second recessed region A2 is convex as the second convex region T2 in the region corresponding to the first convex region T1.

[0098] The materials of the first conductor D1 and the second conductor D2 described above may be metals such as tungsten, gold, or copper, or conductive nonmetallic materials, and there are no particular limitations on the materials here.

[0099] Next, the effects of the display panel of this disclosure will be described.

[0100] As shown in Figure 11, Figure 11 illustrates the circuit principle in which the conductive shielding layer 4 absorbs carriers, and it can be seen that carriers (holes) between two adjacent light-emitting units 001 are absorbed by the conductive shielding layer 4, thus preventing leakage current between the two light-emitting units 001.

[0101] As shown in Figure 12, Figure 12 shows the spectral diagram when the three subpixels red (R), green (G), and blue (B) are lit simultaneously, and the spectral diagram when each subpixel is lit individually. Compared with the spectral diagram of related technology shown in Figure 3, it can be seen that in the display panel of this disclosure, when the three subpixels are lit individually, the light of different colors is significantly reduced, and the overall color gamut of the display panel is improved. According to calculations, the color gamut index (NTSC) of this display panel can reach 80%.

[0102] As shown in Figure 13, Figure 13 shows the voltage-luminance curves of three types of subpixels: red (R), green (G), and blue (B), where the R, G, and B curves are the curves of the three types of subpixels in one embodiment of the present disclosure, and R-071, G-071, and B-071 are the curves of the three types of subpixels in the related art. Figures 14 to 16 show the voltage-color coordinate curves of three types of pixels: red (R), green (G), and blue (B), where the sample Rx, Ry, Gx, Gy, Bx, and By curves are the color coordinate curves of the three types of pixels in one embodiment of the present disclosure, and the Rx, Ry, Gx, Gy, Bx, and By curves are the color coordinate curves of the three types of pixels in the related art.

[0103] As can be seen from Figures 14 to 16, in related technologies, display panels exhibit clear changes in brightness and color coordinates under low voltage (to the left of the dashed line), and are accompanied by jump and inversion problems with voltage changes, making Gamma adjustment difficult at low gradation levels and prone to color bar problems. The display panel of the embodiment of this disclosure clearly reduces the amplitude of each monochromatic coordinate with voltage changes, is advantageous for Gamma adjustment, and does not suffer from excessive smoothing of curves or jump problems.

[0104] From the above, it can be seen that some embodiments of the display panels of this disclosure can prevent electrical leakage and thereby avoid the problem of color transfer.

[0105] This disclosure also provides a method for manufacturing a display panel according to any of the above embodiments, the configuration and effects of which are not described in detail here.

[0106] As shown in Figures 4 to 8 and Figures 17 to 22, the manufacturing method includes steps S110 to S170.

[0107] In step S110, a substrate is formed.

[0108] In step S120, a conductive shielding layer, at least one wiring layer, a flat layer covering the wiring layer and the conductive shielding layer, a first conductor, and a second conductor are formed on one side of the substrate, wherein the conductive shielding layer is provided insulated from the wiring layer, the first conductor is located within the flat layer and connected to the wiring layer, and the second conductor enters the flat layer from the side of the flat layer away from the substrate and is connected to the conductive shielding layer. This is shown in Figures 18 and 19.

[0109] In step S130, a first electrode layer is formed on the surface of the flat layer that is separated from the substrate, the first electrode layer includes a plurality of first electrodes distributed at intervals, the orthographic projection of the conductive shielding layer onto the substrate and the orthographic projection of the first electrodes onto the substrate are distributed at intervals, and the first electrodes are connected to the first conductor. This is shown in Figure 20.

[0110] In step S140, a pixel definition layer is formed that covers the flat layer and exposes each of the first electrodes. This is shown in Figure 21.

[0111] In step S150, a light-emitting layer is formed to cover the pixel definition layer and the first electrode, and the light-emitting layer is connected to the second conductor. This is shown in Figure 22.

[0112] In step S160, a second electrode covering the light-emitting layer is formed. This is shown in Figure 4.

[0113] In some embodiments of this disclosure, as shown in Figures 17 to 19, step S120 includes steps S1210 to S1260.

[0114] In step S1210, a conductive shielding layer, at least one wiring layer, and a first flat insulating layer covering the conductive shielding layer and the wiring layer are formed on one side of the substrate.

[0115] The first flat insulating layer P1, each wiring layer 103, and the conductive shielding layer 4 can be formed in multiple processes, and the first flat insulating layer P1 may be an integral structure formed from the same material, but is not limited to primary formation.

[0116] In step S1220, a first via and a second via extending to the substrate are opened in the first flat insulating layer, the wiring layer is exposed in the first via and the conductive shielding layer is exposed in the second via.

[0117] For example, the second wiring layer 1032 may be exposed on the first via.

[0118] In step S1230, a first conductive portion is formed in the first via, and a second conductor is formed in the second via. This is shown in Figure 14.

[0119] The second conductor D2 and a portion of the first conductor D1, i.e., the first conductive portion D11, can be formed simultaneously.

[0120] In step S1240, a second flat insulating layer is formed covering the first flat insulating layer, and the flat layer includes the first flat insulating layer and the second flat insulating layer. This is shown in Figure 18.

[0121] The second flat insulating layer P2 can be made of the same material as the first flat insulating layer P1, so that the flat layer 104 has the same integral structure as the material. The thickness of the second flat insulating layer P2 may be smaller than that of the first flat insulating layer P1, but is not limited to this.

[0122] Note that Figure 14 shows the boundary line between the second flat insulating layer P2 and the first flat insulating layer P1 for the convenience of explaining the formation order of the second flat insulating layer P2 and the first flat insulating layer P1. However, if the second flat insulating layer P2 uses the same material as the first flat insulating layer P1, even if the two are not formed at the same time, the second flat insulating layer P2 and the first flat insulating layer P1 can be made into an integrated structure after the second flat insulating layer P2 is formed. Therefore, in Figure 15, the second flat insulating layer P2 and the first flat insulating layer P1 are depicted as an integrated structure, and in Figure 14, the boundary line between the second flat insulating layer P2 and the first flat insulating layer P1 is omitted. In substance, both embodiments in Figures 14 and 15 include the second flat insulating layer P2 and the first flat insulating layer P1.

[0123] In step S1250, a third via is formed in the second flat insulating layer, which penetrates the first via.

[0124] The third via and the first via share a common via for housing the first conductor D1, and the hole diameters of the third via and the first via may be the same or different.

[0125] In step S1260, a second conductive portion is formed in the third via and connected to the first conductive portion, and the first conductor includes the first conductive portion and the second conductive portion. This is shown in Figure 18.

[0126] The first conductive part D11 and the second conductive part D12 can be made of the same material in order to match their conductive properties.

[0127] In other embodiments of this disclosure, as shown in Figure 8, step S120 includes steps S1210 to S1230.

[0128] In step S1210, a conductive shielding layer, at least one wiring layer, and a flat layer covering the conductive shielding layer and the wiring layer are formed on one side of the substrate.

[0129] The method for forming the flat layer 104 may be the same as the method for forming the first flat insulating layer P1 in the above embodiment.

[0130] In step S1220, a first via and a second via extending to the substrate are opened in the flat layer, the wiring layer is exposed in the first via and the conductive shielding layer is exposed in the second via.

[0131] The depths of the first via and the second via may be the same, and the wiring layer 103 exposed on the first via is provided on the same layer as the conductive shielding layer 4 exposed on the second via.

[0132] In step S1230, a first conductor is formed in the first via, and a second conductor is formed in the second via.

[0133] The first conductor D1 and the second conductor D2 can be formed simultaneously, and both have the same length in the direction perpendicular to the substrate 101.

[0134] In some embodiments of the present disclosure, after forming the first electrode layer and before forming the pixel definition layer, i.e., after step S130 and before step S140, the manufacturing method of the present disclosure further includes step S180.

[0135] In step S180, a recess is formed in the flat layer, the orthographic projection of the recess onto the substrate is located outside the orthographic projection of the first electrode onto the substrate, and the second conductor is inserted into the recess along the direction away from the substrate. This is shown in Figure 5.

[0136] The recess 1041 causes the pixel definition layer 3 to be recessed, forming a partition groove 32. The pixel definition layer 3 extends to the side walls and bottom surface of the recess 1041, forming the partition groove. Therefore, the light-emitting layer 5 can be recessed into the partition groove 32.

[0137] In response to this, step S140 includes steps S1410 and S1420, where, In step S1410, a pixel definition layer is formed covering the second flat insulating layer, the pixel definition layer is recessed in the recess as a partition groove, and the second conductor is inserted into the partition groove in a direction away from the substrate.

[0138] The orthographic projection of the partition groove 32 onto the substrate 101 is located in a position other than the orthographic projection of the first electrode 21 onto the substrate 101.

[0139] Furthermore, based on some embodiments of the display panel described above, the conductive shielding layer 4 can be placed in the same layer as the second wiring layer 1032, that is, the conductive shielding layer 4 can be formed simultaneously with the second wiring layer 1032. For example, if the conductive shielding layer 4 includes the first conductive layer 41, the second conductive layer 42, and the third conductive layer 43, the second wiring layer 1032 can include three conductive film layers formed simultaneously with the first conductive layer 41, the second conductive layer 42, and the third conductive layer 43, respectively. Alternatively, the second wiring layer 1032 may be a single-layer structure including one conductive film layer, but this conductive film layer may be formed simultaneously with one of the first conductive layer 41, the second conductive layer 42, and the third conductive layer 43. Here, the process is not specifically limited to the simultaneous formation of the conductive shielding layer 4 and the second wiring layer 1032.

[0140] In other embodiments of this disclosure, the pixel definition layer 3 can be exposed to the recess 1041, i.e., the orthogonal projection of the pixel definition layer 3 onto the substrate 101 is located outside the orthogonal projection of the recess 1041 onto the substrate 101, thereby allowing the light-emitting layer 5 to be recessed into the recess 1041. These are shown in Figures 18 and 20.

[0141] Furthermore, after step S160, the manufacturing method of the present disclosure further includes step S170. A color film layer including multiple filter portions is formed on one side of the second electrode that is away from the substrate, and each of the first electrodes is provided in a one-to-one pair facing direction perpendicular to each of the filter portions and the substrate. This is shown in Figures 4 to 8.

[0142] The configurations in each step of the manufacturing method of the embodiments of this disclosure have been described in detail in the embodiment of the display panel described above, and will not be described in detail here.

[0143] Although the drawings illustrate the steps of the manufacturing method in this disclosure in a specific order, this does not require or imply that these steps must be performed in that specific order, or that all steps must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be merged into a single step execution, or a single step may be broken down into multiple step executions.

[0144] Embodiments of this disclosure provide a display device comprising a display panel of any of the above embodiments, the configuration of the display panel can be described by referring to the embodiments of the display surface described above, and will not be described here. The display device of this disclosure may also be an electronic device having an image display function, such as a mobile phone or tablet, and will not be listed here individually.

[0145] Those skilled in the art will readily conceive of other embodiments of the Disclosure after considering the specification and practicing the inventions disclosed herein. This application aims to cover any variations, uses, or adaptability changes of the Disclosure, including common or conventional means known in the art but not disclosed herein, in accordance with the general principles of the Disclosure. The specification and embodiments are merely illustrative, and the true scope and spirit of the Disclosure are indicated by the appended claims. [Explanation of symbols]

[0146] 1 Drive backplate 110 pixel area 120 Peripheral area 101 circuit board 1011 well area 1012 Doping Area 102 Gate 103 Wiring Layer 1031 First wiring layer 1031S Source 1031D Drain 1032 Second wiring layer 104 Flat layer P1 First flat insulating layer P2 Second flat insulating layer 1041 Recess H1 opening area H2 surrounding region 2. First electrode layer 21 First electrode 201 Layer 1 202 Second Layer 203 The third layer 204 The fourth layer 3 Pixel Definition Layer 31 Aperture 32 partition grooves 4. Conductive shielding layer 41 First conductive layer 42 Second conductive layer 43 Third conductive layer 5. Emitting layer 51 Emitting sublayer 52 Charge generation layer 001 Light-emitting unit A1 First recessed area T1 First convex region 6. Second electrode A2 Second recessed area T2 Second convex region 7 Color film layers 71 Filter section 72 Light-shielding part 8. First encapsulation layer 81. First encapsulation sublayer 82 Second encapsulation sublayer 83. Third encapsulation sublayer 9. Second encapsulation layer 10 Transparent cover plate 11 Light extraction layer

Claims

1. A display panel comprising a substrate, at least one wiring layer, a conductive shielding layer, a flat layer, a first electrode layer, a pixel definition layer, a light-emitting layer, and a second electrode, The at least one wiring layer is provided on one side of the substrate, The conductive shielding layer is provided on the same side as the wiring layer and the substrate, and is provided insulated from the wiring layer. The flat layer covers the wiring layer and the conductive shielding layer, and is provided with a first conductor and a second conductor. The first electrode layer is provided on the surface of the flat layer away from the substrate and includes a plurality of first electrodes distributed at intervals, the first electrodes being connected to the wiring layer via the first conductor located within the flat layer, The pixel definition layer covers the flat layer and exposes each of the first electrodes. The light-emitting layer covers the pixel definition layer and the first electrode, and is connected to the conductive shielding layer via a second conductor located at least a portion of the flat layer, wherein the orthographic projection of the second conductor onto the substrate is located other than the orthographic projection of the first electrode onto the substrate. The second electrode covers the light-emitting layer, The side of the second conductor away from the substrate is in contact with the light-emitting layer. The flat layer is provided with a recess, and the orthographic projection of the recess onto the substrate is located in a position other than the orthographic projection of the first electrode onto the substrate. The light-emitting layer is recessed as a first recess region in the region corresponding to the recess, and the bottom surface of the first recess region protrudes as a first convex region in the region corresponding to the second conductor. The second electrode is recessed as a second recessed region in the region corresponding to the first recessed region, and the bottom surface of the second recessed region protrudes as a second convex region in the region corresponding to the first convex region. A display panel characterized by the following features.

2. The pixel definition layer is provided with partition grooves recessed into the substrate, the orthographic projection of the partition grooves onto the substrate is located elsewhere than the orthographic projection of the first electrode onto the substrate, and the light-emitting layer is recessed into the partition grooves. The second conductor is inserted into the partition groove along the direction away from the substrate and embedded in the light-emitting layer. The display panel according to feature 1.

3. The pixel definition layer extends to the side walls and bottom surface of the recess to form the partition groove. The display panel according to feature 2.

4. The orthographic projection of the pixel definition layer onto the substrate is located other than the orthographic projection of the recess onto the substrate, and the light-emitting layer is recessed in the recess, The second conductor is inserted into the recess along the direction away from the substrate and embedded within the light-emitting layer. The display panel according to feature 1.

5. The conductive shielding layer is provided in the same layer as one of the wiring layers. The display panel according to feature 1.

6. The aforementioned wiring layers are numerous, distributed sequentially along the direction away from the substrate, and two adjacent wiring layers are connected. The wiring layer that is furthest from the substrate is the target wiring layer, and the target wiring layer is connected to the first electrode via the first conductor. The conductive shielding layer is provided in the same layer as the target wiring layer. The display panel according to feature 5.

7. In the direction perpendicular to the substrate, the length of the first conductor is greater than the length of the second conductor. The display panel according to feature 6.

8. In a direction perpendicular to the substrate, the length of the portion of the second conductor located within the recess is less than the depth of the recess. The display panel according to any one of claims 3 to 4.

9. In a direction perpendicular to the substrate, the distance between the surface of the first conductor away from the substrate and the bottom surface of the recess is greater than the length of the portion of the second conductor located in the recess. The display panel according to feature 8.

10. The bottom surface of the recess has an opening region and a peripheral region located outside the opening region, the second conductor passes through the opening region, and the peripheral region protrudes from the edge of the opening region toward the substrate. The display panel according to any one of claims 3 to 4.

11. In a direction perpendicular to the substrate, the height to which the peripheral region protrudes into the opening region is smaller than the length of the portion of the second conductor that protrudes from the flat layer. The display panel according to feature 10.

12. The second conductors consist of multiple conductors, all of which are connected to the conductive shielding layer. The display panel according to feature 1.

13. The surface area of ​​the second conductor that is separated from the substrate is smaller than the surface area of ​​the first conductor that is separated from the substrate. The display panel according to feature 1.

14. In a direction perpendicular to the substrate, the length of the first conductor is equal to the length of the second conductor. The display panel according to feature 6.

15. The conductive shielding layer is connected to the second electrode. The display panel according to feature 1.

16. The conductive shielding layer includes a first conductive layer, a second conductive layer, and a third conductive layer, which are sequentially laminated in a direction away from the substrate. The display panel according to feature 1.

17. The materials of the first conductive layer and the third conductive layer are both metallic titanium, and the material of the second conductive layer is metallic aluminum. The display panel according to feature 16.

18. The light-emitting layer includes a plurality of light-emitting sublayers connected in series, and at least one of the light-emitting sublayers is connected in series with an adjacent light-emitting sublayer via a charge generation layer. The display panel according to feature 1.

19. A method for manufacturing a display panel, Forming a substrate and A conductive shielding layer, at least one wiring layer, a flat layer covering the wiring layer and the conductive shielding layer, a first conductor, and a second conductor are formed on one side of the substrate, the conductive shielding layer is provided insulated from the wiring layer, the first conductor is located within the flat layer and connected to the wiring layer, and the second conductor is inserted into the flat layer from the side of the flat layer away from the substrate and connected to the conductive shielding layer. A first electrode layer is formed on the surface of the flat layer that is separated from the substrate, the first electrode layer includes a plurality of first electrodes distributed at intervals, the orthographic projection of the conductive shielding layer onto the substrate and the orthographic projection of the first electrodes onto the substrate are distributed at intervals, and the first electrodes are connected to the first conductor. A pixel definition layer is formed that covers the flat layer and exposes each of the first electrodes. A light-emitting layer is formed to cover the pixel definition layer and the first electrode, and the light-emitting layer is connected to the second conductor. This includes forming a second electrode that covers the light-emitting layer, The side of the second conductor away from the substrate is in contact with the light-emitting layer. After forming the first electrode layer and before forming the pixel definition layer, the manufacturing method further: The flat layer is formed with a recess, the orthographic projection of the recess onto the substrate is located elsewhere than the orthographic projection of the first electrode onto the substrate, and the second conductor is inserted into the recess along a direction away from the substrate. The light-emitting layer is recessed as a first recess region in the region corresponding to the recess, and the bottom surface of the first recess region protrudes as a first convex region in the region corresponding to the second conductor. The second electrode is recessed as a second recessed region in the region corresponding to the first recessed region, and the bottom surface of the second recessed region protrudes as a second convex region in the region corresponding to the first convex region. A method for manufacturing a display panel, characterized by the following:

20. After forming the first electrode layer and before forming the pixel definition layer, the manufacturing method further: The pixel definition layer extends to the side walls and bottom surface of the recess to form a partition groove, and the light-emitting layer is recessed into the partition groove. A method for manufacturing a display panel according to claim 19.

21. After forming the first electrode layer and before forming the pixel definition layer, the manufacturing method further: The orthographic projection of the pixel definition layer onto the substrate is located outside the orthographic projection of the recess onto the substrate, and the light-emitting layer is recessed into the recess. A method for manufacturing a display panel according to claim 19.

22. Forming a conductive shielding layer, at least one wiring layer, and a flat layer covering the wiring layer, the first conductor, the second conductor, and the conductive shielding layer on one side of the substrate is: The conductive shielding layer, at least one wiring layer, and a first flat insulating layer covering the conductive shielding layer and the wiring layer are formed on one side of the substrate. A first via and a second via are formed in the first flat insulating layer, extending to the substrate, the wiring layer is exposed in the first via, and the conductive shielding layer is exposed in the second via. A first conductive portion is formed in the first via, and a second conductor is formed in the second via, A second flat insulating layer is formed covering the first flat insulating layer, and the flat layer includes the first flat insulating layer and the second flat insulating layer. A third via is formed in the second flat insulating layer that penetrates the first via, A second conductive portion is formed within the third via and connected to the first conductive portion, and the first conductor includes the first conductive portion and the second conductive portion. A method for manufacturing a display panel according to claim 20 or 21, characterized in that it is the method for manufacturing a display panel according to claim 20 or 21.

23. Forming a conductive shielding layer, at least one wiring layer, and a flat layer covering the wiring layer, the first conductor, the second conductor, and the conductive shielding layer on one side of the substrate is: The conductive shielding layer, at least one wiring layer, and a flat layer covering the conductive shielding layer and the wiring layer are formed on one side of the substrate. A first via and a second via are formed in the flat layer, extending to the substrate, the wiring layer is exposed in the first via, and the conductive shielding layer is exposed in the second via. This includes forming a first conductor in the first via and forming a second conductor in the second via. A method for manufacturing a display panel according to claim 20 or 21, characterized in that it is the method for manufacturing a display panel according to claim 20 or 21.

24. The conductive shielding layer and one of the wiring layers are formed simultaneously. A method for manufacturing a display panel according to claim 19.

25. The aforementioned wiring layers are numerous, distributed sequentially along the direction away from the substrate, and two adjacent wiring layers are connected. The wiring layer that is furthest from the substrate is the target wiring layer, and the target wiring layer is connected to the first electrode via the first conductor. The conductive shielding layer and the target wiring layer are formed simultaneously. The method for manufacturing a display panel according to the feature described in 24.

26. Includes a display panel according to any one of claims 1 to 18 A display device characterized by the following features.

Images