Rail-to-rail nMOS amplifier

The amplifier assembly addresses the challenge of rail-to-rail operation with low power and minimal area by using parallel-connected auxiliary control transistor elements and clamp circuits, enhancing linearity and reducing input offset voltage, thus achieving efficient rail-to-rail operation with reduced complexity and cost.

JP7888666B2Inactive Publication Date: 2026-07-13RENESAS DESIGN (UK) LTD
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Patent Information

Application Number
JP2024134009
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Priority Date
2023-08-18
Filing Date
2024-08-09
Publication Date
2026-07-13
Estimated Expiration
Not applicable · inactive patent

AI Technical Summary

Technical Problem

Existing signal buffers struggle to achieve rail-to-rail operation with low power consumption and minimal die area, often requiring complex circuitry and increased quiescent current due to the use of constant transconductance gm circuits and folded cascade stages.

Method used

An amplifier assembly with parallel-connected auxiliary control transistor elements and clamp circuits that enhance linearity and reduce input voltage offset, allowing for rail-to-rail operation with low power consumption and reduced die area, using nMOS and pMOS transistor elements.

Benefits of technology

The amplifier assembly achieves high linearity and accuracy with a small die area, reducing input offset voltage and trimming costs while expanding the rail-to-rail input voltage range without complex circuitry, enabling low-signal quiescent current operation.

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Patent Text Reader

Abstract

To provide a rail-to-rail amplifier assembly with high linearity within a complete / large rail-to-rail range.SOLUTION: An amplifier assembly 10 includes a first input circuit 20 connected to a first signal input node 12 for a first input level range, a second input circuit 30 connected to a second signal input node 14 for a second input level range, and a load circuit coupled to the first input circuit, the second input circuit, and an output node 16 of the amplifier assembly. The first input circuit includes a first auxiliary control transistor element 26 and a first control transistor element 24. The first signal input node is coupled to a control terminal of the first control transistor element and a control terminal of the first auxiliary control transistor element. A path connected in parallel to the first control transistor element includes the first auxiliary control transistor element.SELECTED DRAWING: Figure 1
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Citation Information

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