Photoelectric converter, photoelectric converter system, mobile device, semiconductor substrate, method for driving a photoelectric converter

Abstract

To solve a problem in which: a power supply voltage varies when a gain of AD conversion is switched.SOLUTION: There is provided a photoelectric conversion device having a plurality of pixels arranged in array, and the photoelectric conversion device has a first pixel group arranged in a first direction among the plurality of pixels and a first output line to which the first pixel group is connected, and a second pixel group in which pixels not included in the first pixel group among the plurality of pixels are arranged in the first direction and a second output line to which the second pixel group is connected. The first output line is connected with a first current source. The second output line is connected with a second current source. The photoelectric conversion device has a control unit that, in accordance with control to reduce a current flowing in the first current source, performs control to increase a current flowing in the second current source.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device, a photoelectric conversion system including the photoelectric conversion device, a moving body, a semiconductor substrate, and a driving method for the photoelectric conversion device.

Background Art

[0002] A solid-state imaging device that switches the current value of a comparator arranged for each pixel column according to the AD conversion gain of the comparator is disclosed in Patent Document 1.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] [[ID= 35]]In the solid-state imaging device described in Patent Document 1, there is a problem that the accuracy of the output signal of the solid-state imaging device decreases due to fluctuations in the power supply voltage.

[0005] The present case has been made in view of the above problems, suppresses fluctuations in the power supply voltage of the photoelectric conversion device, and improves the accuracy of the output signal of the photoelectric conversion device.

Means for Solving the Problems

[0006] One aspect of the present disclosure is a photoelectric converter having a plurality of pixels arranged in an array, wherein the plurality of pixels comprises a first pixel group arranged in a first direction, a first output line to which the first pixel group is connected, a second pixel group of pixels not included in the first pixel group arranged in the first direction, and a second output line to which the second pixel group is connected, wherein the first output line is connected to a first current source, the second output line is connected to a second current source, and the converter has a control unit that performs control to increase the current flowing through the second current source in response to control to decrease the current flowing through the first current source.

[0007] Another aspect of the present disclosure is a photoelectric converter having a plurality of pixels arranged in an array, wherein the plurality of pixels comprises a first pixel group arranged in a first direction, a first output line to which the first pixel group is connected, a second pixel group of pixels not included in the first pixel group arranged in the first direction, and a second output line to which the second pixel group is connected, the first output line being connected to a first current source, the second output line being connected to a second current source, and a control unit that suppresses fluctuations in the total amount of current flowing by changing the current flowing through the second current source in response to changes in the current flowing through the first current source.

[0008] Further aspects of the present disclosure are photoelectric converters having a plurality of output lines, a plurality of pixels, each connected to one of the plurality of output lines, a plurality of current sources, each connected to one of the plurality of output lines, and a plurality of comparators, each connected to one of the plurality of output lines, wherein the plurality of current sources include a first current source and a second current source, the plurality of comparators include a first comparator and a second comparator, the second current source is disposed between the first current source and the first comparator, and the first comparator is disposed between the second current source and the second comparator.

[0009] Further aspects of this disclosure are semiconductor substrates for stacking on other semiconductor substrates, characterized by having a first output line connected to a first current source, a second output line connected to a second current source, and a control unit that performs control to increase the current flowing through the second current source in response to control to decrease the current flowing through the first current source.

[0010] Further aspects of this disclosure are methods for driving a photoelectric converter having a plurality of pixels arranged in an array, wherein the plurality of pixels include a first group of pixels arranged in a first direction, a first output line to which the first group of pixels is connected, a second group of pixels not included in the first group of pixels are arranged in the first direction, and a second output line to which the second group of pixels is connected, the first output line being connected to a first current source, and the second output line being connected to a second current source, characterized in that the current flowing through the second current source is increased during a period in which the current flowing through the first current source is decreased. [Effects of the Invention]

[0011] According to this disclosure, the accuracy of the output signal of the photoelectric converter can be improved. [Brief explanation of the drawing]

[0012] [Figure 1] This is a schematic diagram of a photoelectric conversion device according to the first embodiment. [Figure 2] This is a schematic diagram of a photoelectric conversion device according to the first embodiment. [Figure 3] This is a schematic diagram of a photoelectric conversion device according to the first embodiment. [Figure 4] This is a timing chart according to the first embodiment. [Figure 5] This is a schematic diagram of a photoelectric conversion device according to the second embodiment. [Figure 6] This is a timing chart according to the second embodiment. [Figure 7] This is a schematic diagram of a photoelectric conversion device according to the third embodiment. [Figure 8] It is a timing chart according to the third embodiment. [Figure 9] It is a timing chart according to the third embodiment. [Figure 10] It is a schematic diagram of a photoelectric conversion device according to the fourth embodiment. [Figure 11] It is a schematic diagram of a photoelectric conversion device according to the fourth embodiment. [Figure 12] It is a modified example of a photoelectric conversion device according to the fourth embodiment. [Figure 13] It is a schematic diagram of a photoelectric conversion device according to the fifth embodiment. [Figure 14] It is a schematic diagram of a photoelectric conversion device according to the fifth embodiment. [Figure 15] It is a timing chart according to the fifth embodiment. [Figure 16] It is a timing chart according to the fifth embodiment. [Figure 17] It is a diagram showing the configuration of a photoelectric conversion system according to the sixth embodiment. [Figure 18] It is a diagram showing the configuration and operation of a moving body according to the seventh embodiment.

Embodiments for Carrying Out the Invention

[0013] Hereinafter, each embodiment will be described with reference to the drawings.

[0014] In each of the embodiments described below, as an example of a photoelectric conversion device, an imaging device will be mainly described. However, each embodiment is not limited to an imaging device and is also applicable to other examples of photoelectric conversion devices. For example, there are ranging devices (devices for distance measurement using focus detection or TOF (Time Of Flight)), photometry devices (devices for measuring the amount of incident light), and the like.

[0015] (First Embodiment) FIGS. 1 to 3 are schematic diagrams of a photoelectric conversion device according to the present embodiment. [[ID=​The photoelectric converter shown in Figure 1 includes a pixel array 110, vertical output lines 130 and 131, current source transistors 140 and 141, switches 150 and 151, a GND pad 160, and a power supply pad 161. It also has control signal lines PWR1 and PWR2, a bias line BS, and resistors 170 and 171 are parasitic resistors.

[0017] Multiple pixels 100 are arranged in an array-like manner across multiple rows and columns in the pixel array 110.

[0018] Each column of the pixel array 110 has vertical output lines 130 and 131 extending in the column direction (vertical direction in Figure 1). These vertical output lines are connected to the pixels 100 arranged in the column direction and form a common signal line for these pixels 100.

[0019] The number of pixels 100 that make up the pixel array 110 is not particularly limited. For example, the pixel array 110 may be composed of thousands of rows x thousands of columns of pixels 100, as in a typical digital camera, or it may be composed of multiple pixels 100 arranged in a single row.

[0020] The pixel signal read from pixel 100 is input to a column signal processing circuit (not shown) via a vertical output line. The column signal processing circuit may include a memory or the like to hold the pixel signal read from pixel 100. The pixel signals output from the column signal processing circuit are output sequentially for each column via a signal processing circuit.

[0021] The power supply voltage is supplied to the pixel array 110 via the power pad 161 and resistor 171.

[0022] GND pad 160 is connected to ground, which is at the ground potential. Hereafter, ground will also be referred to as GND.

[0023] The current source transistors 140 and 141 are supplied with a reference potential (GND potential) via the GND pad 160 and resistor 170, and a bias voltage is input to the gates of the current source transistors 140 and 141 from the bias line BS. The bias source that supplies the bias voltage to the bias line BS takes the form of a current source and a variable transistor, for example, as shown in Figure 2. A bias voltage corresponding to the size of the variable transistor is output to the bias line BS.

[0024] Current is supplied to the vertical output line 130 in accordance with the on / off state of switch 150 connected to control signal line PWR1. Similarly, current is supplied to the vertical output line 131 in accordance with the on / off state of switch 151 connected to control signal line PWR2.

[0025] The control unit, the timing generator 190, controls the signals output to the control signal lines PWR1 and PWR2. In this way, the timing generator 190 controls the operation of switches 150 and 151. The timing generator 190 also controls the readout operation of signals from the pixels of the pixel array 110 and the driving of the signal processing operations of the column signal processing circuit and the signal processing circuit.

[0026] (Pixel composition) The configuration of the pixel 100 according to this embodiment will be described below.

[0027] Figure 3 shows an equivalent circuit diagram of a pixel circuit. One of the pixels connected to the vertical output line 130 is taken as an example. Each of the pixels 100 has a photodiode 400, a transfer transistor 410, a floating diffusion 420, a source follower transistor 430, a selection transistor 440, a GND node 450, a reset transistor 455, and a power node 460.

[0028] Photodiode 400 is grounded at GND node 450. Photodiode 400 is connected to transfer transistor 410. The control signal TX is input to the gate of transfer transistor 410. Transfer transistor 410 has a common node with reset transistor 455 and source follower transistor 430, which is the floating diffusion 420. Both reset transistor 455 and source follower transistor 430 are connected to power node 460. The reset signal RES is input to the gate of reset transistor 455. Source follower transistor 430 is connected to select transistor 440, and the select signal is input to the gate of select transistor 440 from select signal line SEL. Select transistor 440 is connected to vertical output line 130.

[0029] (Function of each element of a pixel) This section explains the function of each element in pixel 100.

[0030] The photodiode 400 converts incident light into photoelectric energy, generating an electric charge.

[0031] The charge photoelectrically converted by the photodiode 400 is transferred to the floating diffusion 420 via the transfer transistor 410, and converted into a signal voltage by the parasitic capacitance associated with the floating diffusion 420. This signal voltage is input to the gate of the source follower transistor 430 and output to the vertical output line 130 via the selection transistor 440. The source follower transistor 430, together with the current source transistor 140 in Figure 1, constitutes a source follower, and the signal voltage on the floating diffusion 420 is output to the vertical output line 130 via the source follower.

[0032] (Driving the photoelectric converter) In the photoelectric converter according to this embodiment, a full-pixel readout mode with high resolution and normal signal-to-noise ratio is used, and a column decimation mode with low resolution and high signal-to-noise ratio is used by switching between them. By making the current consumption of both modes approximately the same, fluctuations in the power supply and the reference voltage source GND can be suppressed, and the accuracy of the output signal can be improved.

[0033] The specific operation will be explained below.

[0034] In the photoelectric converter shown in Figure 1, increasing the bias voltage supplied from the bias line BS to the current source transistors 140 and 141 increases the current supplied to the vertical output lines 130 and 131, respectively. This reduces the 1 / f noise generated in the source follower transistor 430 in the pixel 100 and improves the signal-to-noise ratio.

[0035] In this case, either switch 150 or switch 151 can be turned off by setting either the control line PWR1 that controls switch 150 or the control signal line PWR2 that controls switch 151 to a low level. Let's take the example of when switch 151 is turned off while switch 150 is turned on. At this time, no current is supplied to the vertical output line 131 (power saving state), and a column-decimation readout mode is entered in which the signal of the pixel group consisting of pixels 100 connected to the vertical output line 131 is not read out. In this column-decimation mode, the resolution of the image due to the output signal is reduced, but the amount of data output from the pixel array 110 is reduced, thereby reducing the load on subsequent data processing and reducing power consumption.

[0036] When changing the readout mode in this way, the current consumption of each pixel row changes, causing fluctuations in the power supply voltage. If a signal is read out while these fluctuations are occurring, the fluctuations are superimposed on the signal as noise, and the signal-to-noise ratio of the output signal decreases.

[0037] Therefore, in this embodiment, when the column thinning mode is activated, the current supplied from the current source transistor 140 to the vertical output line 130 is increased. Specifically, in response to the switching of the signal level of the control signal line PWR, which determines the amount of current supplied to the vertical output line by the control unit, the control unit changes the transistor size of the variable transistor connected to the bias source and changes the bias voltage supplied to the current source transistor. By suppressing fluctuations in the total amount of current and suppressing voltage fluctuations of the power supply and GND when changing the readout mode, it is possible to suppress deterioration of image quality.

[0038] The operation of the photoelectric converter will be explained below using the timing chart shown in Figure 4.

[0039] First, at time t0, the control signals PWR1 and PWR2 are at a high level. A bias voltage is supplied to the gates of current source transistors 140 and 141 from a common bias line BS. The current flowing through current source transistor 140 and the current flowing through current source transistor 141 are approximately equal.

[0040] Between times t0 and t1, the signals of pixels 100 in the pixel array 110 are read out sequentially, one row at a time.

[0041] After reading all the signals for all rows, at time t1, the control signal PWR2 is set to a low level, and switch 151 is turned off, transitioning to column thinning mode. At the same time, the bias voltage supplied from the bias line BS to the gates of current source transistors 140 and 141 is increased. This suppresses fluctuations in the total amount of current and reduces power supply voltage fluctuations when transitioning to column thinning mode.

[0042] In other words, it suppresses fluctuations in the current flowing through the path from power pad 161 to resistor 171 to pixel array 110 to vertical output line 130 to current source transistor 140 to resistor 170 to GND pad 160.

[0043] This suppression of current fluctuations can suppress fluctuations in the power supply voltage of the power supply node 460 of the pixel 100, as well as fluctuations in the source node potential of the current source transistors 140 and 141. This suppresses image quality degradation caused by the potential fluctuation of the power supply node 460 interfering with the floating diffusion 420 via the drain-gate capacitance of the source follower transistor 430. In this case, in order to prevent fluctuations in the total amount of current, it is desirable that the increase in the current flowing through the current source transistor 140 and the decrease in the current flowing through the current source transistor 141 be as close as possible, but the balance between the increase and decrease in current can be determined according to the acceptable image quality.

[0044] Furthermore, by suppressing fluctuations in the potential of the source nodes of the current source transistors 140 and 141, it is possible to suppress fluctuations in the current of the current source transistors 140 and 141 and the degradation of the signals on the vertical output lines 130 and 131. In addition, since the current source transistors 140 and 141 are identical circuit elements located adjacent to each other, and the impedance from their respective source nodes to the GND pad 160 is almost identical and common, the effect of suppressing fluctuations in the source nodes by suppressing current fluctuations can be enhanced.

[0045] Thus, in the photoelectric converter according to this embodiment, it is possible to suppress fluctuations in the power supply during mode switching. Furthermore, by suppressing fluctuations in the power supply voltage, the signal-to-noise ratio is improved, and image quality degradation can be suppressed.

[0046] In Figure 1, the bias wires for the gates of current source transistors 140 and 141 are shared, and the control wires for switches 150 and 151 are separate, illustrating an example where one of them is put into a power-saving state. However, the configuration is not limited to this. The bias wires for the gates of current source transistors 140 and 141 can be separate, and one of them can be put into a power-saving state. In this case, the power-saving state can also be defined as a state where a very weak current, for example, about 0.1 μA, is left flowing without cutting off the current. By allowing a weak current to flow even in the power-saving state, the time required to recover can be shortened.

[0047] In this embodiment, the timing generator 190 of the photoelectric converter controlled the current flow of the current source transistors 140 and 141. As another example, a control unit located outside the photoelectric converter may control the current source transistors 140 and 141. For example, the overall control and calculation unit 1009 of the photoelectric converter system in Figure 17, which will be described later in the sixth embodiment, may control them. Alternatively, the current source transistors 140 and 141 may be controlled from outside the photoelectric converter system in Figure 17.

[0048] (Second Embodiment) Figure 5 shows a schematic diagram of the photoelectric converter according to the second embodiment. Explanations that overlap with the first embodiment will be omitted, and the differences from the first embodiment will be explained primarily.

[0049] In this embodiment, the photoelectric converter is used by switching between a high-speed mode with a normal signal-to-noise ratio and a high-SN mode that is slow but has a high signal-to-noise ratio.

[0050] In this embodiment, the vertical output line 130 of the photoelectric converter has a switch 180, and the vertical output line 131 has a switch 181. The vertical output line 130 is connected to a group of pixels in the even-numbered rows of the pixel array 110, and the vertical output line 131 is connected to a group of pixels in the odd-numbered rows of the pixel array 110. The switch 180 is controlled by a signal input from the control signal line VLON1, and the switch 180 is controlled by a signal input from the control signal line VLON2.

[0051] The operation of the photoelectric converter will be explained below using the timing chart in Figure 6.

[0052] The operation from time t0 to t1 is the same as in Figure 4. At time t0, control signal VLON1 is at a high level and switch 180 is ON, and control signal VLON2 is at a low level and switch 181 is OFF. Also, control signals PWR1 and PWR2 are at a high level and switches 150 and 151 are ON. The currents from current source transistors 140 and 141 are approximately equal and flow to the GND pad 160 via vertical output lines 130 and 131, respectively. In this state, the signals of pixels 100 in the pixel array 110 are read out one row at a time.

[0053] At time t1, the control signal PWR2 is set to a low level, turning off switch 151 and transitioning the read mode from high-speed mode to high-SNR mode. At the same time, the bias voltage supplied from bias line BS to the gates of each current source transistor is increased. This suppresses fluctuations in the total amount of current and power supply voltage fluctuations during the transition of read modes.

[0054] Between times t1 and t2, the control signal VLON1 is at a high level, and switch 180 is in the ON state. The control signal VLON2 is at a low level, and switch 181 is in the OFF state. Current from the current source transistor 140 flows through the vertical output line 130. In this state, the signals of the even-numbered rows of pixels 100 in the pixel array 110 are read out via the vertical output line 130.

[0055] At time t2, the control signal VLON1 becomes low level, and switch 180 turns off. The control signal VLON2 becomes high level, and switch 181 turns on. The current from the current source transistor 141 flows through the vertical output line 131. In this state, the signals of the odd-numbered pixels 100 of the pixel array 110 are read out via the vertical output line 131.

[0056] Thus, in high signal-to-noise ratio mode, the signals of 100 pixels in one row are read out in two separate steps between time t1 and t3: the signals of 100 pixels in odd-numbered columns and the signals of 100 pixels in even-numbered columns.

[0057] Between times t3 and t5, a similar operation is performed to read the signal from pixel 100 of the next row. This drive mechanism allows for signal reading without reducing resolution in high-S / N mode in this embodiment. Furthermore, it suppresses power supply voltage fluctuations when transitioning from high-speed mode to high-S / N mode, thereby suppressing image quality degradation associated with power supply voltage fluctuations.

[0058] (Third embodiment) Figure 7 shows a schematic diagram of a photoelectric converter according to the third embodiment.

[0059] Similar to the second embodiment, the photoelectric converter in this embodiment also switches between a high-speed mode with a normal signal-to-noise ratio and a high-SN mode with a low speed but a high signal-to-noise ratio. The differences from the second embodiment will be explained below.

[0060] The photoelectric converter according to this embodiment, shown in Figure 7, has a comparator 200 as a signal processing circuit after the vertical output line 130 and a comparator 201 as a signal processing circuit after the vertical output line 131. Also shown are a GND pad 210 and a resistor 220 connected to comparator 200, and a GND pad 211 and a resistor 221 connected to comparator 201. Furthermore, it has a ramp signal line RAMP, a bias signal line CBS, control lines CPWR1 and CPWR2.

[0061] In the photoelectric converter shown in Figure 7, in addition to fluctuations in the power supply voltage of the wiring, fluctuations in the power supply voltage and GND of the comparator can also be suppressed. The bias current values ​​of comparator 200 and comparator 201 are driven by the bias voltage supplied from bias line CBS. The lamp signal supplied from lamp signal line RAMP is input as a reference signal to the input terminal. Furthermore, the current flowing through each of the vertical output lines is controlled by control lines PWR1 and PWR2.

[0062] As an example of operation, the timing chart in Figure 8 is shown. The timing chart in Figure 8 is the same as the timing chart in Figure 6, except that it shows that the control lines CPWR1, CPWR2, and bias line CBS are controlled in the same way as the control lines PWR1, PWR2, and bias line BS, respectively.

[0063] Between times t0 and t1, control lines CPWR1 and CPWR2 are both at a high level, and comparators 200 and 201 process the signals output via vertical output lines 130 and 131, respectively.

[0064] At time t1, when the readout mode is switched from high-speed mode to high-SN mode and the bias voltage CBS is increased, the current supply to comparator 201 is stopped by setting the control line CPWR2 to a low level. This suppresses fluctuations in the total amount of current in comparators 200 and 201, and suppresses fluctuations in power supply voltage and GND. Comparators 200 and 201 each have a differential stage and an amplification stage, and each of the differential stage and amplification stage has a current source, but when switching modes, it does not matter whether the current supply to the differential stage or the amplification stage is changed.

[0065] Between times t1 and t2, AD conversion is performed by comparing the signal output from the vertical output line 130 with the ramp signal using the comparator 200.

[0066] Between times t2 and t3, AD conversion is performed on the signal output from the vertical output line 131 by comparing it with the ramp signal using the comparator 201.

[0067] Here, the operation of AD conversion of the signal on the vertical output line will be explained using the vertical output line 130 and comparator 200 as examples, with reference to the timing chart in Figure 9. Note that the symbols t0 to t5 in Figure 8 and the symbols t0 to t8 in Figure 9 are unrelated.

[0068] Between times t0 and t1, the control signal RES in Figure 3 becomes high, turning on the reset transistor 455 and resetting the floating diffusion 420. Accordingly, the potential of the vertical output line 130 becomes the reset level.

[0069] At time t2, a slope operation is initiated to change the potential of the ramp signal over time. The diagram shows a case where the potential decreases uniformly, but the ramp signal can also be a signal whose potential continuously increases over time, or a signal whose potential changes in a sawtooth pattern.

[0070] At time t3, the relative magnitudes of the ramp signal input to comparator 200 and the output signal of vertical output line 130 are reversed, and the output of comparator 200 is reversed. The time until this reversal of the comparator output is measured by a counter (not shown), and the AD conversion of the reset level is performed.

[0071] At time t4, the lamp signal is reset.

[0072] Between times t5 and t6, the control signal TX in Figure 3 becomes high level, and the transfer transistor 410 turns on, transferring photocharge from the photodiode 400 to the floating diffusion 420. The potential of the floating diffusion 420 decreases in proportion to the amount of charge, and accordingly, the potential of the vertical output line 130 becomes the signal level.

[0073] The ramp signal will begin its slope operation again from time t7.

[0074] At time t8, the relative magnitudes of the ramp signal input to comparator 200 and the output of vertical output line 130 are reversed, causing the comparator output to change. The time until the comparator output changes is measured by a counter (not shown), and AD conversion of the signal level is performed. Then, in the subsequent processing circuit, so-called CDS processing is performed by taking the difference between the reset level and the AD conversion result of the signal level.

[0075] The above operations are performed between times t1 and t2 in Figure 8 to perform AD conversion of the signal on vertical output line 130. Similarly, AD conversion of the signal on vertical output line 131 is performed between times t2 and t3 in Figure 8. This process is then repeated.

[0076] As described above, in this embodiment, fluctuations in the comparator's power supply voltage and GND due to mode switching can be suppressed.

[0077] In order to prevent fluctuations in the total amount of current, it is desirable that the increase in current flowing through current source transistor 140 and the decrease in current flowing through current source transistor 141 be as close as possible. However, the balance between the increase and decrease in current can be determined according to the acceptable image quality. For example, a photoelectric converter can be considered that has a mode in which current flows through all comparators and a mode in which current is reduced or not supplied to 1 / 3 of the comparators, and current is increased to the remaining 2 / 3 of the comparators. In other words, a balance between the increase and decrease in current may be maintained between the current source group including current source transistor 140 and the current source group including current source transistor 141.

[0078] In Figure 9, the AD conversion gain (V / LSB) can be switched by changing the slope of the ramp signal. When transitioning to the high SN mode at time t1 in Figure 8, the AD conversion gain may be switched simultaneously, or the AD conversion may be performed without switching the AD conversion gain.

[0079] Furthermore, Figure 7 illustrates an example where the bias lines of the gates of current source transistors 140 and 141 are common, and the control lines of switches 150 and 151 are separate, allowing one of them to be in a power-saving state. However, the configuration is not limited to this. The bias lines of the gates of current source transistors 140 and 141 can be provided individually, and one of the current source transistors can be put into a power-saving state. In this case, the power-saving state can also be defined as a state where a weak current, for example, of about 0.1 μA, is left flowing without cutting off the current. By allowing a weak current to flow even in the power-saving state, the time required to recover can be shortened.

[0080] (Fourth embodiment) Figures 10 and 11 show schematic diagrams of the photoelectric converter according to the fourth embodiment. The differences from the third embodiment will be explained below.

[0081] Figure 10 is a block diagram of a photoelectric converter according to the fourth embodiment, and includes a circuit 700 containing a first current source, a circuit 701 containing a second current source, a circuit 710 containing a first comparator, and a circuit 711 containing a second comparator. Figure 11 shows a specific example of the circuit of the photoelectric converter shown in Figure 10. In the photoelectric converter shown in Figure 11, the vertical output lines 130 and 131 are capable of reading signals from different pixel rows in parallel within the same pixel column. In other words, high-speed (simultaneous reading of multiple rows) is possible.

[0082] In the third embodiment, as shown in the timing chart in Figure 8, the pixel signals were read out one row at a time from time t0 to t1, and in the high SN mode from time t1 onward, the pixel signals corresponding to odd and even rows were read out alternately.

[0083] In the photoelectric converter shown in Figure 11, the pixel signals are read out two rows at a time in parallel from time t0 to t1, using a timing chart similar to that in Figure 8. After time t1, in high signal-to-noise ratio mode, the pixel signals are read out one row at a time. In this case as well, it is possible to suppress power supply voltage fluctuations when transitioning the readout mode at time t1.

[0084] Furthermore, as shown in Figure 10, the circuit 700 including the first current source and the circuit 701 including the second current source are located in close proximity, and the circuit 710 including the first comparator and the circuit 711 including the second comparator are also located in close proximity.

[0085] In Figure 11, which shows the circuit arrangement of Figure 10 in a circuit diagram, current source transistors 140 and 141 are placed adjacent to each other, and comparators 200 and 201 are also placed adjacent to each other. In other words, circuit 701 is placed between circuits 700 and 710, and circuit 710 is placed between circuits 701 and 711. It is also acceptable to arrange the current source transistor 140, comparator 200, current source transistor 141, and comparator 201 in the order from the pixel side to the power pad side, but it is preferable to arrange the same circuit elements adjacent to each other as in Figure 11. This arrangement makes it possible to increase the suppression effect of power supply and GND fluctuations by making the common impedance from comparators 200 and 201 to the GND pad 210 and power pad 211 almost equal.

[0086] Furthermore, the photoelectric conversion device in each embodiment may have a stacked configuration as shown in Figure 12.

[0087] The photoelectric converter with a stacked structure shown in Figure 12 has a pixel substrate 800 and a circuit board 810. Let's consider the case where current source transistors 140 and 141, comparators 200 and 201 are arranged on the circuit board 810.

[0088] When increasing the unit current of current source transistors 140, 141, comparator 200, and 201 during a transition to readout mode, reducing the number of operating circuits makes it possible to suppress current fluctuations and reduce the increase in heat generation and its unevenness. This makes it possible to suppress the increase in dark current of the photodiode 400 and the degradation of image quality due to its unevenness in the pixel 100 within the pixel substrate 800. Furthermore, by suppressing current fluctuations between adjacent circuits, the effect of suppressing uneven heat generation can be enhanced.

[0089] For example, you could use the mode with the lower comparator current as the video mode and the mode with the higher current as the still image mode.

[0090] (Fifth embodiment) Figures 13 and 14 show schematic diagrams of a photoelectric converter and comparator according to the fifth embodiment.

[0091] In the photoelectric converter according to this embodiment, a global shutter mode is used, which performs signal readout using a global shutter, and a rolling shutter mode is used, which performs signal readout using a rolling shutter.

[0092] In Figures 13 and 14, unit 500 (hereinafter also referred to as pixel AD) consists of a pixel and a comparator, with each pixel having one comparator. 505 is a control circuit.

[0093] The pixel AD500 shown in Figure 14 includes a photodiode 510, an overflow transistor 520, a transfer transistor 530, a reset transistor 540, and a floating diffusion transistor 550. Transistors 560 and 570 form a differential pair. Transistor 580 operates as a current source. Transistors 590 and 600 form a current mirror. 610 is a switch.

[0094] The global shutter operation will be explained using Figure 15.

[0095] In Figure 15, OFG1 is the OFG corresponding to pixel AD500 located in the first row of Figure 13, while OFG2, OFG3, and OFD4 correspond to the second, third, and fourth rows, respectively. Similarly, RES1 is the RES corresponding to pixel AD500 located in the first row of Figure 13, TX1 is the TX corresponding to pixel AD500 located in the first row of Figure 13, and PWR1 is the PWR corresponding to pixel AD500 located in the first row of Figure 13.

[0096] At times t1-t2, the control signals OFG1-t4 are set to a high level, which turns on the overflow transistor 520 in all pixels AD500 in Figure 13 and resets the charge of the photodiode 510.

[0097] By setting the control signals RES1-4 to a high level at times t3-t4, the reset transistors 540 of all pixel AD500s are turned on, and the floating diffusion 550s are reset.

[0098] The reset level of the floating diffusion 550 is converted AD by applying a slope to the ramp signal at times t5-t6.

[0099] At times t7-t8, the control signals TX1-t4 are set to high levels to transfer photocharge from the photodiode 510 to the floating diffusion 550. The charge accumulation time is the same for all pixels in all rows, from time t2 to t8. The potential of the floating diffusion 550 decreases to the signal level in proportion to the amount of photocharge.

[0100] At times t9-10, the ramp signal is again subjected to slope operation to perform AD conversion on the signal level of the floating diffusion 550.

[0101] Furthermore, from time t0 to t11, all control signals PWR1 to 4 are at a high level, and all pixel AD500s are in operation. The reason that control signals PWR1 to 4 are set to a high level from time t0, before time t3 when the read operation begins, is that it takes a predetermined amount of time for the power supply voltage fluctuations caused by current fluctuations to subside.

[0102] Next, we will explain the rolling shutter operation using Figure 16.

[0103] Similar to Figure 15, OFG1 is the OFG corresponding to pixel AD500 located in the first row of Figure 13, while OFG2, OFG3, and OFD4 correspond to the second, third, and fourth rows, respectively. Similarly, RES1 is the RES corresponding to pixel AD500 located in the first row of Figure 13, TX1 is the TX corresponding to pixel AD500 located in the first row of Figure 13, and PWR1 is the PWR corresponding to pixel AD500 located in the first row of Figure 13.

[0104] As shown in Figure 15, each pixel AD performs a so-called global shutter operation, where charge accumulation occurs at the same timing for all rows.

[0105] Between times t0 and t1, the control signal OFG1 is set to a high level, which turns on the overflow transistor 520 at pixel AD500 in the first row of Figure 13 and resets the charge of the photodiode 510.

[0106] At times t2-t3, the control signal OFG2 is set to a high level, which turns on the overflow transistor 520 at pixel AD500 in the second row of Figure 13 and resets the charge of the photodiode 510.

[0107] At times t4-t5, the control signal OFG3 is set to a high level, which turns on the overflow transistor 520 at pixel AD500 in the third row of Figure 13, resetting the charge of the photodiode 510.

[0108] At times t7-t8, the control signal OFG4 is set to a high level, which turns on the overflow transistor 520 at pixel AD500 in the fourth row of Figure 13, resetting the charge of the photodiode 510.

[0109] By setting the control signal RES1 to a high level at time t9-10, the reset transistor 540 is turned on and the floating diffusion 550 is reset in the first row of pixel AD500 in Figure 13.

[0110] At times t11-t2, the ramp signal is operated in a slope manner to perform AD conversion on the reset level of the floating diffusion 550. At this time, control signal PWR1 is at a high level, and PWR2-4 are at low levels. Switch 610 is turned on only at the first row of pixels AD500 in Figure 13, allowing current to flow and enabling AD conversion. The reason control signal PWR1 is set to a high level from time t6, before the read operation begins at time t9, is that it takes a certain amount of time for the power supply voltage fluctuations caused by current fluctuations to subside.

[0111] At times t13-t14, the control signal TX1 is set to a high level, transferring photocharge from the photodiode 510 to the floating diffusion 550. At this time, the accumulation time of the pixels AD in the first row of Figure 13 is from time t1 to t14.

[0112] Between times t15 and t16, the ramp signal is operated in a slope manner to perform AD conversion on the signal level of the floating diffusion 550.

[0113] Between times t17 and t19, AD conversion between the reset level and the signal level is similarly performed at pixel AD500 in the second row of Figure 13. The charge accumulation time is from time t3 to t18.

[0114] Similarly, for pixel AD500 in the third row of Figure 13, the storage time is from time t5 to t20, and for pixel AD500 in the fourth row of Figure 13, the storage time is from time t8 to t22.

[0115] As shown in Figure 16, each pixel AD accumulates at a staggered timing for each row, resulting in a so-called rolling shutter operation.

[0116] In rolling shutter mode, at time t17, control signal PWR1 goes to a low level while control signal PWR2 goes to a high level, thereby maintaining current consumption and suppressing power supply voltage fluctuations. The same operation is performed at times t19 and t21.

[0117] Here, we consider the case where the readout mode is switched from the rolling shutter mode, which performs the rolling shutter operation shown in Figure 16, to the global shutter mode, which performs the global shutter operation shown in Figure 15.

[0118] At time t23 in Figure 16, only control signal PWR4 is at a high level, while control signals PWR1-3 are at a low level. On the other hand, at time t0 in Figure 15, control signals PWR1-4 are all at a high level. By lowering the bias voltage supplied from bias line BS to transistor 580 at the timing of the readout mode transition, and reducing the current consumption per pixel AD500, the total amount of current can be kept approximately constant, thereby suppressing power supply voltage fluctuations during the transition.

[0119] In this embodiment, the example described is the transition from a rolling shutter mode, which performs row-by-row reading, to a global shutter mode. However, the reading operation is not limited to this. For example, it is also possible to transition from column-by-column reading to global shutter operation. Furthermore, it is also possible to transition from a global shutter operation with a reduced number of operating pixels (AD500) to a global shutter operation without reduction.

[0120] Furthermore, although the example given was that of a pixel AD, where a comparator is provided for each pixel, the method can also be applied to a block AD, where a comparator is provided for multiple pixels (pixel blocks) in a matrix.

[0121] (Sixth Embodiment) The photoelectric conversion system according to this embodiment will be described with reference to Figure 17. Figure 17 is a block diagram showing the schematic configuration of the photoelectric conversion system according to this embodiment.

[0122] The photoelectric conversion devices described in the first to fifth embodiments above are applicable to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, photocopiers, fax machines, mobile phones, in-vehicle cameras, and observation satellites. Camera modules, which include optical systems such as lenses and imaging devices, are also included in photoelectric conversion systems. Figure 15 shows a block diagram of a digital still camera as an example of these.

[0123] The photoelectric conversion system illustrated in Figure 17 includes an imaging device 1004, which is an example of a photoelectric conversion device, and a lens 1002 that forms an optical image of a subject onto the imaging device 1004. Furthermore, it includes an aperture 1003 for varying the amount of light passing through the lens 1002, and a barrier 1001 for protecting the lens 1002. The lens 1002 and aperture 1003 form an optical system that focuses light onto the imaging device 1004. The imaging device 1004 is a photoelectric conversion device of any of the above embodiments, which converts the optical image formed by the lens 1002 into an electrical signal.

[0124] The photoelectric conversion system also includes a signal processing unit 1007, which is an image generation unit that generates an image by processing the output signal output from the imaging device 1004. The signal processing unit 1007 performs various corrections and compressions as needed and outputs the image data. The signal processing unit 1007 may be formed on the semiconductor substrate on which the imaging device 1004 is mounted, or it may be formed on a semiconductor substrate separate from the imaging device 1004.

[0125] The photoelectric conversion system further includes a memory unit 1010 for temporarily storing image data, and an external interface unit (external I / F unit) 1013 for communicating with an external computer or the like. Furthermore, the photoelectric conversion system includes a recording medium 1012 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1011 for recording or reading data from the recording medium 1012. The recording medium 1012 may be built into the photoelectric conversion system or may be detachable.

[0126] Furthermore, the photoelectric conversion system includes an overall control / calculation unit 1009 that controls various calculations and the entire digital still camera, and a timing generation unit 1008 that outputs various timing signals to the imaging device 1004 and the signal processing unit 1007. Here, the timing signals and the like may be input from an external source, and the photoelectric conversion system only needs to have at least the imaging device 1004 and the signal processing unit 1007 that processes the output signals output from the imaging device 1004.

[0127] The imaging device 1004 outputs an imaging signal to the signal processing unit 1007. The signal processing unit 1007 performs predetermined signal processing on the imaging signal output from the imaging device 1004 and outputs image data. The photoelectric conversion system uses this image data to generate an image.

[0128] Thus, according to this embodiment, a photoelectric conversion system can be realized by applying a photoelectric conversion device (imaging device) of any of the above embodiments.

[0129] (Seventh Embodiment) The photoelectric conversion system and mobile unit of this embodiment will be described with reference to Figure 18. Figure 18 is a diagram showing the configuration of the photoelectric conversion system and mobile unit of this embodiment.

[0130] Figure 18(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 300 has an imaging device 310. The imaging device 310 is a photoelectric conversion device (imaging device) as described in any of the embodiments above. The photoelectric conversion system 300 has an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by the photoelectric conversion system 300. The photoelectric conversion system 300 also has a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 318 may use any of this distance information to determine the possibility of collision. The means for acquiring distance information may be implemented by specially designed hardware, or by a software module. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof.

[0131] The photoelectric conversion system 300 is connected to the vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 300 is also connected to a control ECU 330, which is a control unit that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 318. The photoelectric conversion system 300 is also connected to a warning device 340 that issues a warning to the driver based on the judgment result of the collision judgment unit 318. For example, if the collision judgment result of the collision judgment unit 318 indicates a high probability of collision, the control ECU 330 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 340 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0132] In this embodiment, the photoelectric conversion system 300 images the area around the vehicle, for example, the front or rear. Figure 18(b) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the photoelectric conversion system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0133] The above example illustrates control to prevent collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles or automatically drive to prevent vehicles from straying from their lanes. Furthermore, the photoelectric conversion system can be applied not only to vehicles such as the vehicle itself, but also to mobile objects (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to mobile objects but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0134] [Modified Embodiment] The present invention is not limited to the embodiments described above and can be modified in various ways.

[0135] For example, examples in which some configurations of one embodiment are added to other embodiments, or in which some configurations of other embodiments are replaced, are also included as embodiments of the present invention.

[0136] Furthermore, the photoelectric conversion systems shown in the sixth and seventh embodiments above are examples of photoelectric conversion systems to which the photoelectric conversion device can be applied, and the photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 15 and 16.

[0137] It should be noted that the above embodiments are merely examples of how the present invention can be implemented, and the technical scope of the present invention should not be interpreted as being limited by them. In other words, the present invention can be implemented in various forms without departing from its technical concept or its main features. [Explanation of symbols]

[0138] 100 pixels 130 Vertical output lines 131 Vertical output line 140 Current source 141 Current source

Claims

1. Multiple output lines, Each of the multiple pixels is connected to one of the multiple output lines, Each of the multiple current sources is connected to one of the multiple output lines, Multiple comparators, each connected to one of the multiple output lines, A photoelectric converter having a first pad connected to the plurality of comparators and supplying voltage to the plurality of comparators, The plurality of current sources include a first current source and a second current source, The aforementioned plurality of comparators include a first comparator and a second comparator, The second current source is positioned between the first current source and the first comparator. The first comparator is positioned between the second current source and the second comparator. The plurality of pixels include a first pixel and a second pixel that are included in the same pixel sequence. The plurality of output lines include a first output line connected to the first pixel and a second output line connected to the second pixel. The first current source is connected to the first output line, The second current source is connected to the second output line, The first comparator is connected to the first output line, The photoelectric converter is characterized in that the second comparator is connected to the second output line.

2. The photoelectric conversion apparatus according to claim 1, further comprising a control unit that performs control to increase the current flowing through the second current source while control is being performed to decrease the current flowing through the first current source from a state in which current is flowing through the first current source and the second current source.

3. The photoelectric conversion device according to claim 1, further comprising a control unit that performs control to suppress fluctuations in the total amount of current flowing by changing the current flowing through the second current source in accordance with the change in the current flowing through the first current source, from a state in which current flows through the first current source and the second current source.

4. The plurality of pixels include a third pixel and a fourth pixel that are included in a different pixel sequence from the first pixel, The plurality of output lines include a third output line connected to the third pixel and a fourth output line connected to the fourth pixel. The aforementioned plurality of current sources include a third current source and a fourth current source. The aforementioned plurality of comparators include a third comparator and a fourth comparator. The fourth current source is positioned between the third current source and the third comparator. The third comparator is positioned between the fourth current source and the fourth comparator. The third current source is connected to the third output line, The fourth current source is connected to the fourth output line, The third comparator is connected to the third output line, The photoelectric converter according to claim 1, characterized in that the fourth comparator is connected to the fourth output line.

5. The photoelectric converter according to any one of claims 1 to 4, characterized by having a first readout mode in which a first pixel signal output from the first pixel and a second pixel signal output from the second pixel are read out in parallel, and a second readout mode in which a first pixel signal output from the first pixel and a second pixel signal output from the second pixel are read out sequentially.

6. The system includes a first readout mode in which a first pixel signal output from the first pixel and a second pixel signal output from the second pixel are read out in parallel, and a second readout mode in which a first pixel signal output from the first pixel and a second pixel signal output from the second pixel are read out sequentially. In the first readout mode, the third pixel signal output from the third pixel and the fourth pixel signal output from the fourth pixel are read out in parallel. The photoelectric converter according to claim 4, characterized in that, in the second readout mode, the third pixel signal output from the third pixel and the fourth pixel signal output from the fourth pixel are read out in order.

7. The photoelectric conversion device according to claim 5 or 6, characterized in that the first readout mode is a video mode and the second readout mode is a still image mode.

8. The plurality of pixels are formed on a first semiconductor substrate, The first current source and the second current source are formed on the second semiconductor substrate. The photoelectric conversion device according to any one of claims 1 to 7, characterized in that it is constructed by stacking a plurality of semiconductor substrates, including the first semiconductor substrate and the second semiconductor substrate.

9. The photoelectric conversion device according to any one of claims 1 to 8, characterized in that the first pad supplies ground potential to the plurality of comparators.

10. The photoelectric conversion device according to any one of claims 1 to 8, characterized in that the first pad supplies power voltage to the plurality of comparators.

11. The present invention further comprises a second pad connected to the plurality of comparators, The photoelectric conversion device according to any one of claims 1 to 9, characterized in that the second pad supplies power voltage to the plurality of comparators.

12. The photoelectric conversion apparatus according to any one of claims 1 to 11, characterized in that the first current source is disposed between the pixel array including the plurality of pixels and the first comparator.

13. The photoelectric conversion device according to any one of claims 1 to 12, characterized in that the wiring resistance between the first comparator and the first pad is substantially equal to the wiring resistance between the second comparator and the first pad.

14. A photoelectric conversion device according to any one of claims 1 to 13, A photoelectric conversion system characterized by having a signal processing unit that generates an image using the signal output by the aforementioned photoelectric conversion device.

15. A mobile body comprising a photoelectric converter according to any one of claims 1 to 13, A mobile body characterized by having a control unit that controls the movement of the mobile body using a signal output by the photoelectric converter.

Images