Wiring board

Abstract

This wiring board comprises: an insulating layer made of a ceramic material; and a conductor layer extending in a planar direction within the insulating layer. The conductor layer is constituted by a plurality of sintered crystallites consisting mainly of a metal. If a specific range of the conductor layer is specified in a cross-sectional view, and the linear length in the planar direction of the conductor layer is noted as L0, and the length of the outline of the conductor layer is noted as L1, L1 / L0 falls within the range from 1.04 to 1.40.

Description

Technical Field

[0001] The disclosed embodiments relate to a wiring board.

Background Art

[0002] Conventionally, a wiring board having an insulating layer mainly composed of ceramics and a conductor layer mainly composed of metal has been known. Such a wiring board can be obtained, for example, by simultaneously firing a conductor material in which a metal oxide is added to copper powder and a glass ceramic as an insulating layer material (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] The wiring board of the present disclosure includes an insulating layer made of ceramics and a conductor layer extending in a planar direction inside the insulating layer. The conductor layer is composed of a sintered body of a plurality of crystallites mainly composed of metal. When a specific range of the conductor layer is specified in a cross-sectional view, and the linear length in the planar direction is L0 and the length of the contour of the conductor layer is L1, L1 / L0 is in the range of 1.04 to 1.40.

Brief Description of the Drawings

[0005] [Figure 1] FIG. 1 is an enlarged cross-sectional view showing an example of the configuration of a wiring board according to an embodiment. [Figure 2] FIG. 2 is an enlarged view of region A shown in FIG. 1. [Figure 3] FIG. 3 is a diagram showing a SEM observation photograph of a conductor layer according to Example 1.

Modes for Carrying Out the Invention

[0006] The embodiments of the wiring board disclosed herein will be described below with reference to the attached drawings. However, the embodiments described below do not limit this disclosure. Furthermore, each embodiment can be combined as appropriate, provided that the processing content is not inconsistent. Also, the same parts are denoted by the same reference numerals in each of the embodiments below, and redundant descriptions are omitted.

[0007] Furthermore, in the embodiments described below, expressions such as "parallel" may be used, but these expressions do not require strict parallelism. In other words, the expressions described above allow for deviations such as manufacturing accuracy and installation accuracy.

[0008] Conventionally, wiring substrates having an insulating layer mainly composed of ceramics and a conductive layer mainly composed of metal are known. Such wiring substrates can be obtained, for example, by simultaneously firing a conductive material obtained by adding a metal oxide to copper powder and glass ceramics as the insulating layer material.

[0009] However, conventional technology still had room for improvement in terms of increasing the interfacial conductivity of the conductor layer. Therefore, there is a need for a technology that can overcome the aforementioned problems and increase the interfacial conductivity of the conductor layer in a wiring board.

[0010] Figure 1 is an enlarged cross-sectional view showing an example of a wiring board 1 according to the embodiment, and Figure 2 is an enlarged view of region A shown in Figure 1. As shown in Figures 1 and 2, the wiring board 1 according to the embodiment comprises an insulating layer 10 and a conductor layer 20.

[0011] The insulating layer 10 can be, for example, a glass-ceramic sintered body. The glass-ceramic sintered body may contain ceramics such as aluminum oxide, aluminum nitride, silicon carbide, silicon nitride, or mullite as fillers.

[0012] The insulating layer 10 may be made of, for example, glass ceramics. This allows the wiring board 1 to be manufactured by simultaneously firing the green sheet, which is the raw material for the insulating layer 10, and the conductive paste, which is the raw material for the conductor layer 20. Therefore, according to this embodiment, the manufacturing cost of the wiring board 1 can be reduced.

[0013] The insulating layer 10 may have a first layer 11 and a second layer 12 facing each other with the conductor layer 20 in between. The first layer 11 and the second layer 12 are positioned, for example, to sandwich both sides of the conductor layer 20 in the thickness direction.

[0014] The conductive layer 20 is electrically conductive and extends in a planar direction (lateral direction in Figure 1) within the insulating layer 10. The conductive layer 20 is arranged in a predetermined pattern shape, for example, between the first layer 11 and the second layer 12. In this disclosure, the conductive layer 20 may be located exposed on the surface of the wiring board 1.

[0015] As shown in Figure 2, the conductive layer 20 is composed of a sintered body of multiple crystallites 21. These crystallites 21 are composed of metallic materials such as copper, silver, palladium, gold, platinum-tungsten, molybdenum, or manganese, or alloy materials or mixed materials mainly composed of these metallic materials.

[0016] Here, "metallic material" or "primarily composed of metal (e.g., copper)" means that metal accounts for 70% or more by volume in the conductive layer 20. If the conductive layer 20 contains voids, the volume percentage of metal excluding the voids should be 80% or more as a guideline. The upper limit for the volume percentage of metal (e.g., copper) contained in the conductive layer 20 may be 99%.

[0017] The reason for setting the upper limit of the volume percentage of metal (e.g., copper) contained in the conductive layer 20 to 99% is that, since the wiring substrate 1 of this disclosure is formed by the simultaneous firing of a ceramic insulating layer and a metal, elements contained in the insulating layer 10 inevitably enter the conductive layer 20.

[0018] The volume ratio of the metal in the conductor layer 20 is determined, for example, by the following method. In this case, the area ratio of the metal determined by the following method is used as the volume ratio. First, the wiring board 1 is cut or crushed to expose the internal cross-section.

[0019] Next, one layer of the conductor layer 20 visible in the cross-section of the exposed wiring board 1 is selected. At this time, when the length of the conductor layer 20 is long enough to correspond to the width of the wiring board 1, a specific length is specified.

[0020] The specified length only needs to be such that the portion of the conductor layer 20 to be evaluated falls within the range that can be included in one photograph or screen in the observation and photography by a scanning electron microscope (SEM) described later. As the length, it is better that the size is larger than the thickness of the conductor layer 20. As a guideline for the length, it is preferably 1 (μm) or more and 100 (μm) or less.

[0021] In the cross-section of the wiring board 1, the range of the target conductor layer 20 is preferably, for example, the range that appears as a contour when observed using a scanning electron microscope. The contour of the conductor layer 20 is preferably obtained from a reflected electron image, which is one of the analysis methods using a scanning electron microscope, but may also be obtained by mapping analysis using an elemental analyzer attached to the scanning electron microscope.

[0022] Also, the electron backscattered diffraction (EBSD) method may be used to measure the volume ratio of the metal. According to the electron backscattered diffraction method, while obtaining the volume ratio (area ratio) of the conductor layer 20, it is possible to confirm that the metal constituting the conductor layer 20 is formed by a plurality of crystallites.

[0023] When voids (including pores) are present in the conductor layer 20, the area of all voids included in the observed range may be removed from the area of the conductor layer 20 in advance. As a guideline for the size of the voids to be counted as voids, those with a maximum diameter of 0.1 (μm) or more are used.

[0024] Here, in the embodiment, a specific range (for example, region A) of the conductor layer 20 is specified in a cross-sectional view. When the linear length in the planar direction (the horizontal direction in FIG. 2) is L0 and the length of the contour 20a of the conductor layer 20 (that is, the interface length between the conductor layer 20 and the insulating layer 10) is L1, L1 / L0 is in the range of 1.04 to 1.40.

[0025] Here, the specific range is such that the width in the longitudinal direction of the conductor layer 20 is 10 (μm) or more and 100 (μm) or less. The width in the longitudinal direction within this specific range can be any width selected within the range of 10 μm (or more) and 100 (μm) or less. Such an arbitrary width is determined in consideration of the thickness of the conductor layer 20, the size of the crystallites 21 contained in the conductor layer 20, and the like.

[0026] For example, as the specific range, it may be the range where one layer of the conductor layer 20 is sandwiched between the upper and lower insulating layers 10. The specific range may specify a plurality of locations in the photographed photograph. As a specific area, it may be any area that is 100 (μm 2 ) or more and 10000 (μm 2 ) or less.

[0027] Thus, in the embodiment, by making the unevenness of the contour 20a of the conductor layer 20 relatively small, the interfacial conductivity of the conductor layer 20 can be increased.

[0028] Also, in the embodiment, the sintered body constituting the conductor layer 20 contains nano-sized silica particles 22 (see FIG. 3), and such silica particles 22 may be located on the surface of the crystallites 21. In other words, in this wiring board 1, silica may be present on the surface of the conductor layer 20 in a particulate state.

[0029] Here, the "surface of the conductor layer 20" means, when the conductor layer 20 is formed on the surface of the insulating layer 10, the vicinity of the interface between the insulating layer 10 and the conductor layer 20. This "vicinity of the interface" includes the range from the surface of the conductor layer 20 to a slight width range inside the conductor layer 20. This "slight width" is, for example, a range within 1 (μm) from the surface of the conductor layer 20.

[0030] The conductive layer 20 is such that, when silica particles 22 are present on the surface of the conductive layer 20, the distance from the silica particles 22 is within 1 μm, and there are no voids in the area within 1 μm from the surface of the conductive layer 20. In this case, a void refers to a space with a size greater than or equal to the maximum diameter of the silica particles 22.

[0031] The reason the conductive layer 20 has such a dense region around the silica particles 22 is thought to be that, as will be described later, the presence of silica particles 22 at the interface with the insulating layer 10 reduces the diffusion of components from the insulating layer 10 into the copper powder, thereby controlling the sintering behavior of the copper powder and resulting in gradual sintering.

[0032] The presence of silica particles 22 near the interface with the insulating layer 10 partially reduces the diffusion of glass components from the insulating layer 10 of the glass ceramic. In this way, the surface of the insulating layer 10 can maintain a gentle shape during firing, and the surface shape of the conductive layer 20 can be maintained flat. The silica particles 22 are less likely to react excessively with the insulating layer 10.

[0033] The conductive layer 20 has a microstructure formed by fine copper crystallites 21. In this case, some of the crystallites 21 have polygonal shapes with straight edges, and these edges are in contact with each other as grain boundaries. The longest diameter of the crystallites 21 is preferably 1 μm or more and 10 μm or less. It is preferable that 70% or more of the crystallites 21 have two or more edges.

[0034] In this embodiment, the presence of silica particles 22 on the surface of the conductive layer 20 enhances the adhesion between the conductive layer 20 and the insulating layer 10. The silica particles 22 may be present over the entire surface of the conductive layer 20 facing the insulating layer 10, or they may be present only on a portion of the surface of the conductive layer 20. If multiple silica particles 22 are present on the surface of the conductive layer 20, these silica particles 22 may exist in isolation from each other.

[0035] The reason why the presence of silica particles 22 on the surface of the conductive layer 20, or near the interface between the insulating layer 10 and the conductive layer 20, increases the adhesion between the insulating layer 10 and the conductive layer 20 is thought to be partly because the shrinkage behavior of the metal material (for example, copper) used in the conductive layer 20 during firing is similar to that of the silica particles 22.

[0036] Furthermore, the reason why the shrinkage behavior of the metal material used in the conductive layer 20 during firing is similar to that of the silica particles 22 is thought to be due to the minute size (nano-size) of the silica particles 22.

[0037] If silica particles larger than nanoscale 22 are used, there will be an expansion of the particle size distribution based on size, and an increase in heat capacity due to size. These factors will then change the sintering behavior and adhesion.

[0038] Furthermore, if composite oxide glass powder is used instead of nano-sized silica particles 22, the temperature range in which the glass powder melts will be wider than that of nano-sized silica particles 22, because the glass powder contains multiple components.

[0039] For example, glass powder may have a lower melting temperature compared to nano-sized silica particles 22. Also, glass powder often has a wide particle size distribution. When glass powder with these properties is used, aggregation and migration due to sintering are more likely to occur within the printed pattern that becomes the conductive layer 20 during firing.

[0040] As a result, when forming the conductive layer 20, metal particles tend to grow larger, and voids tend to form within the conductive layer 20. This is because the glass powder tends to diffuse from the printed pattern area to the area that becomes the insulating layer 10.

[0041] On the other hand, when nano-sized silica particles 22 are used, the range of temperatures at which they melt is narrower than that of glass powder, due to their single composition. As a result, the conductive layer 20 becomes denser, and gently shaped recesses are more easily formed on the surface along the insulating layer 10.

[0042] The particle size of the silica particles 22 according to this embodiment is preferably 1 nm to 50 nm. Here, particle size refers to diameter. Diameter refers to the maximum diameter obtained when observing the silica particles 22. Among these, the silica particles 22 are preferably those with an average particle size of 20 nm. Furthermore, the silica particles 22 are preferably such that the cumulative amount ratio of particles with a lower limit of 10 nm and an upper limit of 30 nm is 70% or more.

[0043] Furthermore, in this embodiment, the area ratio of silica particles 22 in the conductive layer 20 may be 0.002% to 0.067%. This can increase the interfacial conductivity of the conductive layer 20. The method for determining the area ratio of silica particles 22 in the conductive layer 20 will be described later.

[0044] Furthermore, in this embodiment, the content of silica particles 22 in the conductive layer 20 may be 0.099 (wt%) to 2.912 (wt%). This can increase the interfacial conductivity of the conductive layer 20. Here, the content of silica particles 22 refers to the ratio obtained by dividing the amount of added silica particles 22 by the total amount of copper powder and silica particles 22.

[0045] Furthermore, in this embodiment, the crystallite 21 may be composed mainly of copper, and the copper content in the conductive layer 20 may be 80 wt% to 99 wt%. This can further increase the interfacial conductivity of the conductive layer 20.

[0046] Furthermore, in this embodiment, as shown in Figure 2, the crystallite 21 may have a polygonal shape. This reduces the decrease in interfacial conductivity in the high-frequency range (for example, 1 GHz to 49 GHz), thereby increasing the interfacial conductivity of the conductor layer 20 in the high-frequency range. [Examples]

[0047] The embodiments of this disclosure will be described below in detail. In the embodiments described below, a wiring substrate having an insulating layer made of glass ceramics and a conductive layer mainly composed of copper will be shown, but this disclosure is not limited to the embodiments described below.

[0048] <Example 1> First, a mixture of 40 wt% alumina particles and 60 wt% borosilicate glass was prepared as the material for the insulating layer. This mixture is a glass ceramic raw material with a firing temperature of 900°C to 1000°C.

[0049] Furthermore, as an organic binder, 20 parts by mass of isobutyl methacrylate resin and dibutyl phthalate were used per 100 parts by mass of glass ceramic raw material, and a green sheet with a thickness of 100 μm was produced by doctor blade molding.

[0050] Furthermore, copper powder with an average particle size of 2 μm (purity 99.9 wt%) and silica particles with an average particle size of 20 nm were prepared as raw materials for the conductive layer. The silica particles had a cumulative amount ratio of 70% or more between a lower limit of 10 nm and an upper limit of 30 nm. The amount of silica particles added was 0.1 parts by mass per 100 parts by mass of copper powder.

[0051] Furthermore, an organic binder was used, consisting of isobutyl methacrylate resin and a mixed solvent of butyl carbitol acetate and dibutyl phthalate. Then, isobutyl methacrylate resin was added at a ratio of 5 parts by mass per 100 parts by mass of copper powder, and the mixed solvent of butyl carbitol acetate and dibutyl phthalate was further added to prepare a conductive paste containing copper powder and silica particles.

[0052] Next, conductive paste was printed onto both surfaces of the fabricated green sheet in a predetermined area and then fired. The firing was performed in a reducing atmosphere using a hydrogen-nitrogen mixed gas, with a maximum temperature of 930°C and a holding time of 2 hours. Multiple green sheets were stacked to a thickness of 500 μm. This obtained the wiring board 1 of Example 1.

[0053] <Examples 2-7> Except for the amount of silica particles added in the conductive paste manufacturing process, the wiring boards 1 of Examples 2 to 7 were obtained using the same methods and conditions as in Example 1 described above.

[0054] In Examples 2 to 7, during the preparation process for the conductive paste, the amounts of copper powder were 0.3 parts by mass, 0.5 parts by mass, 1 part by mass, 1.5 parts by mass, 2 parts by mass, and 3 parts by mass, respectively, per 100 parts by mass of copper powder.

[0055] <Example 8> Except for the conductive paste preparation process, the wiring board 1 of Example 8 was obtained using the same method and conditions as in Example 1 described above. In Example 8, copper powder with an average particle size of 2 μm (purity 99.9 wt%) and borosilicate glass powder with an average particle size of 2 μm were prepared as raw materials for the conductive layer. The amount of glass powder added was 6 parts by mass per 100 parts by mass of copper powder.

[0056] Furthermore, an organic binder consisting of isobutyl methacrylate resin and a mixed solvent of butyl carbitol acetate and dibutyl phthalate was used. Isobutyl methacrylate resin was added at a ratio of 5 parts by mass to 100 parts by mass of copper powder, and then the mixed solvent of butyl carbitol acetate and dibutyl phthalate was added to prepare a conductive paste containing copper powder and glass powder.

[0057] <Various evaluations> Next, the wiring boards 1 of Examples 1 to 8 obtained above were cut, the cut surfaces were mirror-polished, and the cross-sections were observed with a scanning electron microscope. Figure 3 shows an SEM observation image of the conductor layer 20 according to Example 1.

[0058] As shown in Figure 3, in the embodiment, silica particles 22 were observed between adjacent copper crystallites 21 (i.e., on the surface of the crystallites 21). The volume percentage of metal (copper) contained in the conductive layer 20 of the fabricated wiring substrate 1 was 90% or more and 98% or less in all samples, excluding the void portion.

[0059] Furthermore, using the SEM observation images obtained above, the ratio L1 / L0 of the length L1 of the contour 20a of the conductive layer 20 to the straight length L0 in the planar direction was measured for each of the Examples 1 to 8.

[0060] Specifically, first, points A and B were marked at both ends of a contour 20a of the conductive layer 20 as seen in the cross-sectional photograph, and a straight line was drawn between points A and B, with the length of this straight line being defined as L0. Next, the length of the contour 20a from point A to point B was determined using an image processing device, and this length was defined as L1. Finally, the ratio of the two lengths, L1 / L0, was calculated.

[0061] Furthermore, the area ratio of silica particles 22 in Examples 1 to 8 was measured using the SEM observation images obtained above. Specifically, first, several square areas with a length of 1 / 10 to 1 / 2 of the thickness of the conductive layer 20 were designated in the cross-sectional image. For example, 8 to 10 such square areas were designated so that they were continuously aligned in the direction in which the conductive layer 20 extends (planar direction).

[0062] Next, the area of ​​the metallic portion (corresponding to crystallite 21) in the region demarcated by the square was defined as A0. The area of ​​the black-colored portion shown in Figure 3 (corresponding to silica particles 22) was defined as A1.

[0063] Then, the ratio A1 / A0 of the two areas was taken as the area ratio of silica particles 22 in one square region. Finally, the average of the area ratios of silica particles 22 in multiple square regions was taken as the area ratio of silica particles 22 in that sample.

[0064] Furthermore, the interfacial conductivity of the wiring boards 1 of Examples 1 to 8 obtained above was measured. The interfacial conductivity was measured using the dielectric cylindrical resonator method shown below. For the measurement, a sample with a diameter of 50 mm and a conductive layer 20 formed on almost the entire surface of both sides was used.

[0065] The dielectric cylinder resonator method is a method for measuring interfacial conductivity by forming a dielectric resonator by attaching an insulating layer with a conductor formed inside to one or both ends of a dielectric cylinder made of a dielectric material with known relative permittivity and dielectric loss, in a predetermined relationship, thereby measuring the conductivity at the interface between the conductor and the insulating layer, i.e., the conductor interface.

[0066] The principle of this measurement method is that when an electromagnetic field resonator is constructed by sandwiching a dielectric cylinder having a predetermined dimensional ratio (height h / diameter d) between two sufficiently large conducting plates (usually conducting plates with a diameter D about three times the diameter d of the dielectric cylinder) positioned parallel to each other, the high-frequency current flowing through the conducting plates due to the TEomn resonant mode (hereinafter referred to as the TEomn mode) is distributed only on the short-circuit surface, i.e., the surface facing the dielectric and the conductor.

[0067] In a dielectric resonator, the high-frequency current flowing through a conductor due to TEomn modes (m=1,2,3..., n=1,2,3...) is distributed only at the interface between the conductor and the dielectric substrate in contact with the dielectric cylinder. This allows for the calculation of the interface conductivity from the measured resonant frequencies f0 of the TEomn modes (m=1,2,3..., n=1,2,3...), and the unloaded Q and Qu. The interface conductivity was measured at a frequency of 10 GHz.

[0068] Furthermore, the presence or absence of conductor delamination in the wiring boards 1 of Examples 1 to 8 obtained above was evaluated. For evaluation, a conductor layer 20 with sides of 10 mm to 50 mm was used, with insulating layers 10 superimposed on both sides.

[0069] Furthermore, to evaluate conductor delamination, the evaluation sample was first cut at a point approximately half the length in one direction, and both the interface between the insulating layer 10 and the conductive layer 20 at the cross-section was observed. If delamination was observed in even one location, it was determined to be "delamination present," and if no delamination was observed at any interface, it was determined to be "no delamination."

[0070] In the above determination, the condition "delamination present" was defined as a state where the length of the region where the insulating layer 10 and the conductive layer 20 are separated by 0.1 mm or more is 1 mm or more.

[0071] Table 1 shows the amounts of silica particles and glass powder added to the conductive layer 20, the L1 / L0 value in the conductive layer 20, the area ratio of silica particles in the conductive layer 20, the measurement results of the interfacial conductivity at a frequency of 10 GHz, and the evaluation results of whether or not conductor delamination occurred for Examples 1 to 8. Note that the measurement results of the interfacial conductivity at a frequency of 10 GHz are relative values ​​when the interfacial conductivity at DC is set to 100%.

[0072] [Table 1]

[0073] As shown in Table 1, it can be seen that the interfacial conductivity of the conductor layer 20 can be increased by setting the L1 / L0 value in the conductor layer 20 to the range of 1.04 to 1.40. Furthermore, it can be seen that the interfacial conductivity of the conductor layer 20 can be increased even further by setting the L1 / L0 value in the conductor layer 20 to the range of 1.04 to 1.18.

[0074] Furthermore, it can be seen that the interfacial conductivity of the conductor layer 20 can be further increased by setting the L1 / L0 value in the conductor layer 20 to a range of 1.04 to 1.14. It can also be seen that the interfacial conductivity of the conductor layer 20 can be further increased by setting the L1 / L0 value in the conductor layer 20 to a range of 1.04 to 1.11.

[0075] Although not shown in Table 1, in a printed circuit board (so-called printed circuit board) that comprises an insulating layer made of a resin such as epoxy resin and a conductive layer made of copper foil, the adhesion between the resin (insulating layer) and the copper foil (conductor layer) is low. Therefore, adhesion can only be ensured by increasing the irregularities of the contour of the conductive layer to create an anchoring effect.

[0076] Therefore, in this printed circuit board, the L1 / L0 value in the conductive layer becomes 2 or greater. In addition, in this printed circuit board, the unevenness of the contour of the conductive layer is large, which reduces the interfacial conductivity of the conductive layer.

[0077] Furthermore, expressing the results in Table 1 in other terms, it can be seen that the interfacial conductivity of the conductor layer 20 can be increased in the samples (Examples 1-7) prepared using a conductive paste in which the amount of silica particles 22 added per 100 parts by mass of copper powder is 0.1 to 3 parts by mass. In addition, it can be seen that the conductive delamination of the conductor layer 20 can be reduced in the samples (Examples 2-7) prepared using a conductive paste in which the amount of silica particles 22 added is 0.3 to 3 parts by mass.

[0078] Furthermore, it can be seen that when samples (Examples 2 to 6) are prepared using a conductive paste in which the amount of silica particles 22 added per 100 parts by mass of copper powder is 0.3 to 2 parts by mass, the interfacial conductivity of the conductive layer 20 can be increased, and the conductive peeling of the conductive layer 20 can be reduced.

[0079] Furthermore, it can be seen that when samples are prepared using a conductive paste in which the amount of silica particles 22 added per 100 parts by mass of copper powder is 0.3 to 1.5 parts by mass (Examples 2 to 5), the interfacial conductivity of the conductive layer 20 can be further increased, and the conductive peeling of the conductive layer 20 can be reduced.

[0080] Furthermore, as shown in Table 1, it can be seen that the interfacial conductivity of the conductive layer 20 can be increased by setting the area ratio of silica particles 22 in the conductive layer 20 to the range of 0.002 (%) to 0.067 (%). In addition, it can be seen that the conductive delamination of the conductive layer 20 can be reduced by setting the area ratio of silica particles 22 in the conductive layer 20 to the range of 0.005 (%) to 0.067 (%).

[0081] Furthermore, it can be seen that by setting the area ratio of silica particles 22 in the conductive layer 20 to a range of 0.005% to 0.042%, the interfacial conductivity of the conductive layer 20 can be increased, and the delamination of the conductive layer 20 can be reduced.

[0082] Furthermore, it can be seen that by setting the area ratio of silica particles 22 in the conductive layer 20 to a range of 0.005% to 0.033%, the interfacial conductivity of the conductive layer 20 can be further increased, and the delamination of the conductive layer 20 can be reduced.

[0083] While embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments, and various modifications are possible without departing from its spirit. For example, the above embodiments show an example in which fine silica particle powder is added to the conductive paste, which is the raw material for the conductive layer 20, but the present disclosure is not limited to such examples.

[0084] For example, ceramic fine powders other than silica (such as alumina fine powder) may be added to the conductive paste. This will also provide the same effects as those in the above embodiment.

[0085] Further effects and other embodiments can be readily derived by those skilled in the art. Therefore, broader embodiments of this disclosure are not limited to the specific details and representative embodiments expressed and described above. Accordingly, various modifications are possible without departing from the spirit or scope of the overall concept of the invention as defined by the appended claims and their equivalents. [Explanation of symbols]

[0086] 1 Wiring board 10 Insulating layer 20 Conductor layer 20a Contour 21 crystallites 22 Silica particles

Claims

1. An insulating layer made of ceramics, A conductive layer extending in the planar direction within the insulating layer, Equipped with, The conductive layer is composed of a sintered body of multiple crystallites, with metal as the main component. When a specific range of the conductor layer is designated in a cross-sectional view, and the straight-line length in the planar direction is L0 and the contour length of the conductor layer is L1, then L1 / L0 is in the range of 1.04 to 1.40, and the specified range is the range where L0 is 10 (μm) or more and 100 (μm) or less. The sintered body contains silica particles with a diameter of 1 nm to 50 nm. The silica particles are located on the surface of the crystallite, The area ratio of the silica particles in the conductive layer is 0.002% to 0.067%. Wiring board.

2. The content of silica particles in the conductive layer is between 0.099 (wt%) and 2.912 (wt%). The wiring board according to claim 1.

3. The aforementioned crystallite is composed mainly of copper, The copper content in the conductive layer is 80 (wt%) to 99 (wt%). A wiring board according to claim 1 or 2.

4. The aforementioned crystallites have a polygonal shape. A wiring board according to claim 1 or 2.

Images