Photoelectric converter, photoelectric converter system, and mobile body

Abstract

To provide a photoelectric conversion device including a stack of a plurality of semiconductor element layers, in which the heat radiation unevenness can be reduced.SOLUTION: A photoelectric conversion device according to one embodiment includes a first chip including a first semiconductor element layer including a pixel region where a plurality of pixel circuits are disposed, and a second chip including a second semiconductor element layer. The first chip and the second chip are bonded to each other with a plurality of metal bonding parts between the first semiconductor element layer and the second semiconductor element layer. The metal bonding parts include a first metal bonding part and a second metal bonding part disposed in a region overlapping with the pixel region in a plan view. The first metal bonding part connects at least one pixel circuit among the pixel circuits, and the second semiconductor element layer. The second metal bonding part is connected to at least one pixel circuit among the pixel circuits and is not connected to the second semiconductor element layer in the region overlapping with the pixel region in the plan view.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device.

Background Art

[0002] A photoelectric conversion device in which a chip including a pixel circuit and a chip including an electric circuit for processing signals from the pixel circuit are stacked is known. Patent Document 1 discloses a photoelectric conversion device in which a chip having a plurality of pixel circuits and a chip having a plurality of electric circuits are stacked.

[0003] In the photoelectric conversion device shown in Patent Document 1, there is a conductive portion that electrically connects the pixel circuit and the electric circuit and joins the chip having the pixel circuit and the chip having the electric circuit. In Patent Document 1, the number of conductive portions is less than the number of pixel circuits. Specifically, in a pixel region where pixel circuits are arranged in an array, the conductive portions are selectively arranged at a ratio of one for a plurality of pixel circuits. Therefore, there are pixel circuits provided with conductive portions and pixel circuits not provided with conductive portions.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The conductive portion connects the pixel circuit and the electric circuit via a metal wiring. Generally, since the metal wiring has a high thermal conductivity with respect to the interlayer insulating film, heat transfer is large in the conductive portion. On the other hand, in pixel circuits where no conductive portion is provided, heat transfer generated in at least one of the photoelectric conversion element and the signal processing circuit is less likely to occur than in pixels provided with the conductive portion. Therefore, heat dissipation unevenness occurs between pixel circuits provided with conductive portions and pixel circuits not provided with conductive portions.

[0006] The present invention aims to reduce uneven heat dissipation in a photoelectric conversion device in which multiple semiconductor element layers are stacked. [Means for solving the problem]

[0007] A photoelectric converter according to one embodiment comprises a first chip having a first semiconductor element layer including a pixel region on which a plurality of pixel circuits are arranged, a second chip having a second semiconductor element layer on which a signal processing circuit for processing signals output by the plurality of pixel circuits is arranged, and a first wiring pattern, wherein the first chip and the second chip are joined by a plurality of metal joints at the junction surface between the first semiconductor element layer and the second semiconductor element layer, and the plurality of metal joints include a plurality of first metal joints and a plurality of second metal joints arranged in a region that overlaps with the pixel region in a plan view, and the plurality of first metal Each of the metal junctions connects at least one pixel circuit among the plurality of pixel circuits to the second semiconductor element layer, each of the plurality of second metal junctions is not included in the electrical path connecting the plurality of pixel circuits to the signal processing circuit, the first wiring pattern is provided in the layer between the plurality of metal junctions and one of the first semiconductor element layer and the second semiconductor element layer, each of the plurality of second metal junctions is commonly connected to the first wiring pattern, and an insulating material is provided between the plurality of second metal junctions in contact with the junction surface. Furthermore, the plurality of metal junctions include a third metal junction that is not connected to the first semiconductor element layer and the second semiconductor element layer. This is a photoelectric conversion device characterized by the following features. Another embodiment of the photoelectric converter comprises a first chip having a first semiconductor element layer including a pixel region on which a plurality of pixel circuits are arranged, a second chip having a second semiconductor element layer on which a signal processing circuit for processing signals output by the plurality of pixel circuits is arranged, and a first wiring pattern, wherein the first chip and the second chip are joined by a plurality of metal junctions at the junction surface between the first semiconductor element layer and the second semiconductor element layer, and the plurality of metal junctions include a plurality of first metal junctions and a plurality of second metal junctions arranged in a region overlapping the pixel region in a plan view, each of the plurality of first metal junctions connects at least one pixel circuit among the plurality of pixel circuits and the second semiconductor element layer, and the plurality of second metal junctions Each of the above is not included in the electrical path connecting the plurality of pixel circuits and the signal processing circuit, the first wiring pattern is provided in the layer between the plurality of metal junctions and one of the first semiconductor element layer and the second semiconductor element layer, each of the plurality of second metal junctions is commonly connected to the first wiring pattern, an insulating material is provided between the plurality of second metal junctions that contacts the junction surface, each of the plurality of second metal junctions has a first surface on the first semiconductor element layer side and a second surface on the second semiconductor element layer side, the first surface is not connected to the wiring connected to the pixel circuit, and the second surface is connected to the wiring connected to the signal processing circuit, characterized in that the photoelectric conversion device is such that. Another embodiment of the photoelectric converter comprises a first chip having a first semiconductor element layer including a pixel region on which a plurality of pixel circuits are arranged, a second chip having a second semiconductor element layer on which a signal processing circuit for processing signals output by the plurality of pixel circuits is arranged, and a first wiring pattern, wherein the first chip and the second chip are joined by a plurality of metal junctions at the junction surface between the first semiconductor element layer and the second semiconductor element layer, the plurality of metal junctions include a plurality of first metal junctions and a plurality of second metal junctions arranged in a region overlapping the pixel region in a plan view, and each of the plurality of first metal junctions includes at least one pixel circuit from the plurality of pixel circuits and the second semiconductor element The photoelectric conversion device is characterized in that layers are connected, each of the plurality of second metal junctions is not included in the electrical path connecting the plurality of pixel circuits and the signal processing circuit, the first wiring pattern is provided in the layer between the plurality of metal junctions and one of the first semiconductor element layer and the second semiconductor element layer, each of the plurality of second metal junctions is commonly connected to the first wiring pattern, an insulating material is provided between the plurality of second metal junctions that is in contact with the junction surface, each of the plurality of pixel circuits includes a photoelectric conversion element, and the plurality of metal junctions are arranged such that one metal junction corresponds to one of the photoelectric conversion elements. Another embodiment of the photoelectric converter comprises a first chip having a first semiconductor element layer including a pixel region on which a plurality of pixel circuits are arranged, a second chip having a second semiconductor element layer on which a signal processing circuit for processing signals output by the plurality of pixel circuits is arranged, and a first wiring pattern, wherein the first chip and the second chip are joined by a plurality of metal junctions at the junction surface between the first semiconductor element layer and the second semiconductor element layer, the plurality of metal junctions include a plurality of first metal junctions and a plurality of second metal junctions arranged in a region overlapping the pixel region in a plan view, each of the plurality of first metal junctions connects at least one pixel circuit among the plurality of pixel circuits and the second semiconductor element layer, and each of the plurality of second metal junctions The photoelectric conversion device is characterized in that the above are not included in the electrical path connecting the plurality of pixel circuits and the signal processing circuit, the first wiring pattern is provided in the layer between the plurality of metal junctions and one of the first semiconductor element layer and the second semiconductor element layer, each of the plurality of second metal junctions is commonly connected to the first wiring pattern, an insulating material is provided between the plurality of second metal junctions that is in contact with the junction surface, and when viewing a 1000 μm × 1000 μm area including the pixel region, the area of ​​the first wiring pattern connected to the plurality of second metal junctions is 10 times or more the area of ​​the wiring pattern arranged in the same layer as the first wiring pattern and connected to the first metal junction. Furthermore, a photoelectric converter according to another embodiment comprises a first chip having a first semiconductor element layer including a pixel region on which a plurality of pixel circuits are arranged, a second chip having a second semiconductor element layer on which a signal processing circuit for processing signals output by the plurality of pixel circuits is arranged, and a first wiring pattern, wherein the first chip and the second chip are joined by a plurality of metal junctions at the junction surface between the first semiconductor element layer and the second semiconductor element layer, and the plurality of metal junctions include a plurality of first metal junctions and a plurality of second metal junctions arranged in a region overlapping the pixel region in a plan view, and each of the plurality of first metal junctions includes at least one pixel circuit from the plurality of pixel circuits and the second semiconductor element layer, The photoelectric conversion device is characterized in that each of the plurality of second metal junctions is not included in the electrical path connecting the plurality of pixel circuits and the signal processing circuit, the first wiring pattern is provided in the layer between the plurality of metal junctions and one of the first semiconductor element layer and the second semiconductor element layer, each of the plurality of second metal junctions is commonly connected to the first wiring pattern, an insulating material is provided between the plurality of second metal junctions that is in contact with the junction surface, and each of the plurality of second metal junctions is connected to one of the first semiconductor element layer and the second semiconductor element layer, but not to the other of the first semiconductor element layer and the second semiconductor element layer. Another embodiment of the photoelectric converter comprises a first chip having a first semiconductor element layer including a pixel region on which a plurality of pixel circuits are arranged, a second chip having a second semiconductor element layer on which a signal processing circuit for processing signals output by the plurality of pixel circuits is arranged, a first wiring pattern, and a plurality of via plugs, wherein the first chip and the second chip are joined by a plurality of metal junctions at the junction surface between the first semiconductor element layer and the second semiconductor element layer, the plurality of metal junctions include a plurality of first metal junctions and a plurality of second metal junctions arranged in a region overlapping the pixel region in a plan view, each of the plurality of first metal junctions connects at least one pixel circuit among the plurality of pixel circuits and the second semiconductor element layer, and each of the plurality of second metal junctions connects the plurality of pixel circuits and the signal processing circuit The photoelectric conversion device is characterized in that the first wiring pattern is provided in the layer between the plurality of metal junctions and the first semiconductor element layer, each of the plurality of second metal junctions is commonly connected to the first wiring pattern, an insulating material is provided between the plurality of second metal junctions that is in contact with the junction surface, each of the plurality of second metal junctions has a first surface facing the first semiconductor element layer and a second surface facing the second semiconductor element layer and located between the first surface and the second semiconductor element layer, the first surface of each of the plurality of second metal junctions and the first wiring pattern are connected via a corresponding via plug from the plurality of via plugs, and the entire second surface of each of the plurality of second metal junctions is in contact with the insulating material. Another embodiment of the photoelectric converter comprises a first chip having a first semiconductor element layer including a pixel region on which a plurality of pixel circuits are arranged, a second chip having a second semiconductor element layer on which a signal processing circuit for processing signals output by the plurality of pixel circuits is arranged, a first wiring pattern, and a plurality of via plugs, wherein the first chip and the second chip are joined by a plurality of metal junctions at the junction surface between the first semiconductor element layer and the second semiconductor element layer, the plurality of metal junctions include a plurality of first metal junctions and a plurality of second metal junctions arranged in a region overlapping the pixel region in a plan view, each of the plurality of first metal junctions connects at least one pixel circuit among the plurality of pixel circuits and the second semiconductor element layer, and each of the plurality of second metal junctions connects the plurality of pixel circuits and the signal processing circuit The photoelectric conversion device is characterized in that the first wiring pattern is not included in the electrical path, is provided in the layer between the plurality of metal junctions and the second semiconductor element layer, each of the plurality of second metal junctions is commonly connected to the first wiring pattern, an insulating material is provided between the plurality of second metal junctions that is in contact with the junction surface, each of the plurality of second metal junctions has a first surface facing the first semiconductor element layer and a second surface facing the second semiconductor element layer and located between the first surface and the second semiconductor element layer, the second surface of each of the plurality of second metal junctions and the first wiring pattern are connected via a corresponding via plug from the plurality of via plugs, and the entire first surface of each of the plurality of second metal junctions is in contact with the insulating material. [Effects of the Invention]

[0011] According to the present invention, in a photoelectric conversion device in which multiple semiconductor element layers are stacked, uneven heat dissipation can be reduced. [Brief explanation of the drawing]

[0012] [Figure 1] Perspective view schematically showing the configuration of the photoelectric conversion device. [Figure 2] Circuit diagram of the pixel. [Figure 3] Schematic cross-sectional view of the photoelectric conversion device. [Figure 4] Schematic plan view showing the arrangement of the metal joints in Embodiment 1. [Figure 5A] Schematic plan view and schematic cross-sectional view in Embodiment 1. [Figure 5B] Schematic plan view and schematic cross-sectional view in Embodiment 1. [Figure 5C] Schematic plan view and schematic cross-sectional view in Embodiment 1. [Figure 5D] Schematic plan view and schematic cross-sectional view in Embodiment 1. [Figure 6] Pixel arrangement pattern in Embodiment 1. [Figure 7] Schematic plan view showing the arrangement of the metal joints in the comparative example. [Figure 8A] Schematic plan view and schematic cross-sectional view in the comparative example. [Figure 8B] Schematic plan view and schematic cross-sectional view in the comparative example. [Figure 8C] Schematic plan view and schematic cross-sectional view in the comparative example. [Figure 9A] Schematic plan view and schematic cross-sectional view in Embodiment 2. [Figure 9B] Schematic plan view and schematic cross-sectional view in Embodiment 2. [Figure 9C] Schematic plan view and schematic cross-sectional view in Embodiment 2. [Figure 10A] Schematic plan view and schematic cross-sectional view in Embodiment 3. [Figure 10B] Schematic plan view and schematic cross-sectional view in Embodiment 3. [Figure 10C] Schematic plan view and schematic cross-sectional view in Embodiment 3. [Figure 11] Schematic cross-sectional view in Embodiment 4. [Figure 12A] Schematic plan view and schematic cross-sectional view in Embodiment 5. [Figure 12B] A schematic plan view and a schematic cross-sectional view of Embodiment 5. [Figure 13] Schematic cross-sectional view of a modified example. [Figure 14] Comparison photos of images taken in low light. [Figure 15] Block diagram of the photoelectric conversion system in Embodiment 6. [Figure 16] Conceptual diagram of the photoelectric conversion system and mobile body in Embodiment 7. [Figure 17] A schematic top view of the photoelectric converter in Embodiment 8. [Figure 18] Schematic diagram of the X-X' section in Embodiment 8. [Figure 19A] A schematic plan view of the wiring layer in Embodiment 9. [Figure 19B] A schematic plan view of the wiring layer in Embodiment 9. [Figure 19C] A schematic plan view of the wiring layer in Embodiment 9. [Figure 19D] A schematic plan view of the wiring layer in Embodiment 9. [Figure 19E] A schematic plan view of the wiring layer in Embodiment 9. [Figure 19F] A schematic plan view of the polysilicon and semiconductor regions of the wiring layer in Embodiment 9. [Figure 20] Another example of a wiring layer in Embodiment 9. [Figure 21] Circuit diagram of a pixel in Embodiment 9. [Modes for carrying out the invention]

[0013] The embodiments shown below are intended to embody the technical concept of the present invention and do not limit it. The size and positional relationships of the components shown in each drawing may be exaggerated for clarity of explanation. In the following description, identical components may be given the same number and their explanation may be omitted.

[0014] Figure 1 shows the photoelectric converter in each embodiment. The photoelectric converter is a semiconductor device that can be used, for example, as an image sensor, a photometric sensor, or a distance measuring sensor.

[0015] The photoelectric converter is a stack of chip 1 and chip 2. Chip 1 has a semiconductor element layer 11 (first semiconductor element layer) containing a pixel circuit included in a pixel 10, and a wiring structure 12 (first wiring structure). In this specification, "semiconductor element layer" includes not only the semiconductor layer but also the semiconductor layer and the gate of the transistor formed on the semiconductor layer. The wiring layer of the wiring structure is not included in the "semiconductor element layer". Chip 2 has a wiring structure 24 (second wiring structure) and a semiconductor element layer 23 (second semiconductor element layer) containing an electrical circuit. As will be described later, the wiring structure 12 of chip 1 and the wiring structure 24 of chip 2 are joined by a metal joint formed by joining the wiring layers included in each wiring structure. A metal joint is a structure in which the metal constituting the wiring layer and the metal constituting the wiring layer are directly joined.

[0016] As will be described in detail later, the elements constituting the pixel 10 are arranged in the semiconductor element layer 11. Note that some of the components of the pixel 10 may be arranged in the semiconductor element layer 11, and other components may be arranged in the semiconductor element layer 23. In this case, the components of the pixel circuit arranged in the semiconductor element layer 11 of the pixel 10 include photoelectric conversion elements such as photodiodes. The pixel circuit including the photoelectric conversion elements is arranged in a two-dimensional array in a planar view on the semiconductor element layer 11. In this specification, "planar view" refers to viewing from a direction perpendicular to the junction surface between chip 1 and chip 2. The semiconductor element layer 11 has a pixel region in which multiple pixel circuits are arranged in a two-dimensional array. In Figure 1, multiple photoelectric conversion elements constituting multiple pixel circuits are arranged in a two-dimensional array in the row and column directions on the semiconductor element layer 11.

[0017] The wiring structure 12 includes M (where M is an integer greater than or equal to 1) layers of wiring and an interlayer insulating material. The wiring structure 24 includes N (where N is an integer greater than or equal to 1) layers of wiring and an interlayer insulating material.

[0018] The semiconductor element layer 23 includes electrical circuits. For the sake of explanation, the configuration shown on the top surface of the chip 2 in Figure 1 is a configuration arranged on the semiconductor element layer 23. An electrical circuit is, for example, one of the transistors that make up the row scanning circuit 20, column scanning circuit 21, signal processing circuit 22, etc., as shown in Figure 1. The signal processing circuit 22 is, for example, a combination of at least one of the following: a part of the configuration of the pixel 10 such as an amplification transistor, selection transistor, reset transistor, etc., an amplification circuit, a selection circuit, a logic operation circuit, an AD conversion circuit, a memory, a circuit that performs compression processing or synthesis processing, etc.

[0019] Pixel 10 may refer to the smallest unit of circuitry that is repeatedly arranged to constitute an image. Furthermore, the pixel circuit included in the pixel 10 and arranged on the semiconductor element layer 11 only needs to include at least a photoelectric conversion element. The pixel circuit may also include components other than the photoelectric conversion element. For example, the pixel circuit may further include at least one of the following: a transfer transistor, a floppy disk, a reset transistor, an amplification transistor, a capacitive addition transistor, or a selection transistor. Typically, a selection transistor and a group of elements connected to the signal line via the selection transistor constitute the pixel 10. That is, the selection transistor may be the outer edge of the pixel circuit. Alternatively, a pair of a photoelectric conversion element and a transfer transistor may constitute the pixel 10. In addition, a pair of one or more photoelectric conversion elements and one amplification circuit or one AD conversion circuit may constitute the pixel 10.

[0020] In Figure 2, the pixel circuit is composed of photoelectric conversion elements 101A, 101B, transfer transistors 102A, 102B, FD103, reset transistor 104, amplification transistor 105, selection transistors 106A, 106B, and capacitive addition transistors 107A, 107B. As shown in Figure 2, a single pixel circuit may contain multiple photoelectric conversion elements, or a single pixel circuit may contain one photoelectric conversion element.

[0021] The following describes each component included in the pixel circuit. In the following explanation, subscripts such as A, B, etc., will be omitted when the explanation is common to all components.

[0022] The photoelectric conversion element 101 is an element that generates electrons and holes through photoelectric conversion. For example, a photodiode can be used as the photoelectric conversion element 101. The transfer transistor 102 controls whether or not to transfer the signal charge generated in the photoelectric conversion element 101 to the floating diffusion (FD) 103. The reset transistor 104 controls whether or not to set the potential of the FD 103 and the potential of the photoelectric conversion element 101 to a reference potential. The capacitive addition transistor 107 controls whether or not to add capacitance to the FD 103. The amplification transistor 105 amplifies and outputs a signal based on the signal charge transferred to the FD. The selection transistor 106 is connected to the amplification transistor 105 and the output line 17. When the selection transistor 106 is turned on, the signal output from the amplification transistor 105 is transmitted to the output line 17. If the pixel circuit does not include a selection transistor, the on / off control of the amplification transistor controls whether or not to output a signal to the signal line. The output line 17 is connected to the signal processing circuit 22 in Figure 1. Furthermore, signals from the row scanning circuit 20 shown in Figure 1 are supplied to the gates of the transfer transistor 102, reset transistor 104, amplification transistor 105, selection transistor 106, and capacitive addition transistor 107. This controls the on / off state of each transistor.

[0023] The device may be equipped with a rolling shutter function that sequentially reads out rows from one side of the pixel area to the opposite side, or it may be equipped with a global shutter function that simultaneously transfers and accumulates charge throughout the entire pixel area. Furthermore, within the pixel area, the exposure time may differ for each block containing multiple pixels. In this case, it is preferable that the number of metal joints 30B within a single block is greater than the number of metal joints 30A.

[0024] In the following embodiments, the pixel circuit shown in Figure 2 is assumed to be arranged on chip 1. However, since the area of ​​the photoelectric conversion element 201 can be secured without increasing the area of ​​chip 1, the components of the pixel other than the photoelectric conversion element may be arranged on chip 2.

[0025] Figure 3 is a schematic cross-sectional diagram illustrating the conceptual structure of a photoelectric converter. Chip 1 and Chip 2 are laminated together by bonding at a bonding surface 3. The wiring structure 12 of Chip 1 and the wiring structure 24 of Chip 2 are located between the semiconductor element layer 11 of Chip 1 and the semiconductor element layer 23 of Chip 2. In Figure 3, the wiring structure 12 has three wiring layers: wiring layers 121, 122, and 123, and the wiring structure 24 has three wiring layers: wiring layers 241, 242, and 243. Insulating materials 124 and 244 are placed between each wiring layer.

[0026] Each wiring layer comprises one or more wiring patterns and insulating material placed between the wiring patterns. For example, wiring layer 122 includes wiring pattern 122A (first wiring pattern) and wiring pattern 122B (second wiring pattern). The wiring patterns included in each wiring layer are wiring patterns on the same layer. In this specification, two separate wiring patterns on the same layer may be referred to as wiring pattern XA and wiring pattern XB. From one perspective, wiring pattern XA and wiring pattern XB may be wirings that transmit different potentials. From another perspective, wiring pattern XA and wiring pattern XB may be wirings that are separated from each other in the plane of the wiring layer on which they are arranged. For example, wiring pattern XA and wiring pattern XB are separated from each other by insulating material placed between them. In this case, wiring pattern XA and wiring pattern XB may constitute a single wiring. In other words, separated wiring pattern XA and wiring pattern XB on one wiring layer may be electrically connected via wiring patterns on another wiring layer.

[0027] In this embodiment, wiring pattern 122A is electrically connected to the gate of an amplifying transistor in a pixel circuit. Wiring pattern 122B is electrically connected to components other than the gate of the amplifying transistor in a pixel circuit arranged on the semiconductor element layer 11. Wiring pattern 122B is, for example, wiring that supplies the power supply voltage to a reset transistor or an amplifying transistor. Alternatively, wiring pattern 122B may be wiring that supplies a ground voltage to a photoelectric conversion element.

[0028] Each wiring pattern in wiring layers 121, 122, 123, 241, 242, and 243 is composed of a metallic material. Preferably, the main component of each wiring pattern in wiring layers 121, 122, 123, 241, 242, and 243 is copper. Having copper as the main component means that more than 50% of the total components are copper. Preferably, each wiring pattern in wiring layers 121, 122, 123, 241, 242, and 243 has more than 90% of its total components as copper. Note that each wiring layer may be composed of a metal such as aluminum or tungsten. Furthermore, wiring layers 123 and 243, which include the wiring patterns constituting the metal joint, may be composed primarily of copper, while wiring layers other than wiring layers 123 and 243 may be composed primarily of a metal such as aluminum or tungsten. The via plugs that connect each wiring layer, and the contact plugs that connect the wiring layer to the transistor gate or the wiring layer to the semiconductor element layer, are also made of metals such as copper, aluminum, and tungsten.

[0029] Each wiring pattern of wiring layers 123 and 243 is embedded in a recess formed in the interlayer insulating layer. Each wiring pattern of wiring layers 123 and 243 can be formed by a damascene process. The wiring patterns of wiring layer 123 and wiring patterns of wiring layer 243 are joined together to form a metal joint 30.

[0030] In this embodiment, some or all of the multiple metal joints 30 are classified into one of the following types: metal joint 30A (first metal joint), metal joint 30B (second metal joint), or metal joint 30C (third metal joint). Of course, the multiple metal joints 30 may include types different from these classifications.

[0031] The metal junction 30A is positioned in a region that overlaps with the pixel region in a plan view. The metal junction 30A connects the pixel circuit, which is located on the semiconductor element layer 11, to the semiconductor element layer 23. In Figure 3, the source or drain of the selection transistor 106 of the pixel circuit is connected to the electrical circuit located on the semiconductor element layer 23. Signals from the photoelectric conversion element are transmitted to the electrical circuit of the semiconductor element layer 23 via the metal junction 30A. In Figure 3, the metal junction 30A is connected to the wiring layers 122 and 242 via via plugs 15 and 25, but the metal junction 30A may be connected to the wiring layers 122 and 242 without via plugs. In other words, the metal junction 30A may be directly connected to at least one of the wiring layers 122 and 242. Furthermore, the via plug 15 may be formed integrally with the wiring pattern of the wiring layer 123 that constitutes the metal junction 30A. The via plug 25 may be formed integrally with the wiring pattern of the wiring layer 243 that constitutes the metal joint 30A. By using a dual damascene process, the wiring pattern and the via plug can be formed integrally. The dual damascene process can also be applied to metal joints other than the metal joint 30A.

[0032] The metal junction 30B is electrically connected to one of the semiconductor element layer 11 and the semiconductor element layer 23 in the region that overlaps with the pixel region in a plan view. Note that the contact plug that connects the metal junction 30B to one of the semiconductor element layer 11 and the semiconductor element layer 23 is not shown in Figure 3. Furthermore, the metal junction 30B is not connected to the other semiconductor element layer 11 and the semiconductor element layer 23, at least in the region that overlaps with the pixel region in a plan view. Not being electrically connected to the other semiconductor element layer 11 and the semiconductor element layer 23 in the pixel region means that the metal junction 30B is not connected to the other semiconductor element layer 11 and the semiconductor element layer 23 in the region that overlaps with the pixel region in a plan view. In other words, in the region that overlaps with the pixel region in a plan view, none of the contact plugs that are in contact with the other semiconductor element layer 11 and the semiconductor element layer 23 are electrically conductive to the metal junction 30B. On the other hand, this includes cases where the metal junction 30B is connected to the other semiconductor element layer 11 and semiconductor element layer 23 in a region that does not overlap with the pixel region in a planar view. For example, in Figure 3, a configuration in which a ground voltage is supplied to the wiring pattern 122B via a wiring pattern from a region of the semiconductor element layer 23 that does not overlap with the pixel region is included in the present invention. In Figure 3, the metal junction 30B is connected to the semiconductor element layer 11 in the region that overlaps with the pixel region in a plan view, but is not connected to the semiconductor element layer 23. In addition, the metal junction 30B may be connected to both the wiring layer 122 and the wiring layer 242, as long as it is not connected to either the semiconductor element layer 11 or the semiconductor element layer 23 in the region that overlaps with the pixel region in a plan view.

[0033] From another perspective, the metal junction 30B is connected to a via plug on the semiconductor element layer 11 side, or to the wiring pattern of the wiring layer 122 via a via plug, and the entire surface of the semiconductor element layer 23 side is in contact with an insulating material. Alternatively, for example, in the case of a metal junction 30B formed by the dual damascene method, a protrusion is provided on the surface of the semiconductor element layer 11 for connection to the wiring pattern of the wiring layer 122, and the entire surface of the semiconductor element layer 23 side is in contact with an insulating material. In other words, one side of the metal junction 30B, either the semiconductor element layer 11 or the semiconductor element layer 23, is connected to the wiring pattern, while the other side is not connected to the wiring pattern. The via plug and the metal junction 30B may be made of the same material or different materials.

[0034] Furthermore, if the metal joint 30B is configured under this viewpoint, the metal joint 30B may be connected to both the semiconductor element layer 11 and the semiconductor element layer 23 in the region that overlaps with the pixel region in a plan view.

[0035] As will be explained in detail later, the connection between the metal junction 30B and the pixel circuit or semiconductor element layer 23 reduces uneven heat dissipation in the photoelectric converter. Even if there is only one metal junction 30B, the effect of reducing uneven heat dissipation can be obtained compared to the case where there is no metal junction 30B. Therefore, the number and position of the metal junction 30B are not limited to those described below.

[0036] The metal joints 30A and 30B may be connected to one or both of the wiring layers 122 and 243 via via plugs, or they may be connected by direct contact to at least one of the wiring layers 122 and 243.

[0037] The metal joint 30C in Figure 3 is a metal joint that is not electrically connected to either the semiconductor element layer 11 or the semiconductor element layer 23. The metal joint 30C is used to ensure the bonding strength of each chip, etc. Note that the metal joint 30C is not required. In other words, even if each of the multiple metal joints 30 is composed of only one of the metal joints 30A and the metal joint 30B, the effect of reducing uneven heat dissipation can be obtained.

[0038] (Embodiment 1) The photoelectric conversion device according to Embodiment 1 will be described with reference to Figures 4 to 6. The photoelectric conversion device according to Embodiment 1 includes all the configurations shown in Figures 1 to 3.

[0039] Figure 4 is a schematic plan view showing the arrangement of the metal junctions. For simplicity, consider a pixel region where each pixel 10 is corresponding to two row scan lines 16 and one vertical output line 17, with the pixels 10 arranged in a 5x5 grid. Two of the control lines connected to the gates of each transistor in Figure 2 are shown as the row scan lines 16 in Figure 4. One of the output lines 17A and 17B in Figure 2 is shown as the vertical output line 17 in Figure 4. Additionally, wiring 19 is arranged for each column. The wiring 19 may be, for example, a wire to which a fixed voltage is supplied, or it may be floating. Wiring to which a fixed voltage is supplied includes, for example, a wire to which the power supply voltage (e.g., VDD) is supplied, or a wire to which the ground voltage (e.g., GND) is supplied. The reset line VDD in Figure 2 is shown as the wiring 19 in Figure 4.

[0040] The connection of the metal joint 30B to any wiring can be appropriately set according to the arrangement of the wiring pattern. Figure 4 shows an example in which the metal joint 30B is connected to wiring 19. However, the metal joint 30B may also be connected to the row scan line 16 or the vertical output line 17, as in the embodiment described later. Furthermore, if a metal joint 30C is provided, a portion of the metal joint 30B can be left unconnected to any wiring pattern and replaced with the metal joint 30C.

[0041] In a pixel region arranged in a 5x5 grid, at least two metal junctions 30A are provided in each row to electrically connect two row scan lines 16 to the row scan circuit 20. Additionally, at least one metal junction 30A is provided in each column to electrically connect one vertical output line 17 to the signal processing circuit 22. In a plan view, the metal junctions 30 (30A, 30B) are arranged to overlap the configuration (e.g., pixel circuit) of the pixels 10 arranged on the chip 1. In other words, in a plan view, multiple metal junctions 30 are arranged in multiple rows and multiple columns. For convenience, a pixel 10 with a metal junction 30A electrically connecting the row scan lines 16 to the row scan circuit 20 is referred to as pixel 10A. Similarly, a pixel with a metal junction 30A electrically connecting the vertical output line 17 to the signal processing circuit 22 is referred to as pixel 10B. Furthermore, a pixel having a metal junction 30B that is connected to the semiconductor element layer 11 but not connected to the semiconductor element layer 23 in the pixel region is called a pixel 10C.

[0042] Figure 5A shows a schematic plan view of the wiring layer 122 of chip 1, showing the 7th row and 7th column of pixels 10 within the pixel area. In Figure 5A, in addition to the wiring patterns arranged on the wiring layer 122, namely the vertical output lines 17 and wiring 19, the positions of the metal joints 30A, 30B, and via plugs 15 in a plan view are shown. In Figure 5A, the metal joint 30A is shown by a long dashed line, and the metal joint 30B is shown by a dotted line. Note that the metal joint 30 is not limited to a rectangular shape in a plan view, but may have rounded corners or be circular. The via plugs 15 connect the wiring pattern of the wiring layer 122 to the metal joint 30.

[0043] Figure 5B shows a schematic plan view of the wiring layer 121 of chip 1, showing the row scan lines 16 and via plugs 18.

[0044] Figure 5C is a cross-sectional view of the line X-X' in Figures 5A and 5B, and Figure 5D is a cross-sectional view of the line Y-Y' in Figures 5A and 5B. As shown in Figure 5D, pixels 10A and 10B have a metal junction 30A, and pixel 10C has a metal junction 30B. In Figure 5C, the metal junction 30A connects the semiconductor element layer 11 and the semiconductor element layer 23. Also, in Figure 5C, as mentioned above, the metal junction 30B is not connected to the semiconductor element layer 23 in the region that overlaps with the pixel region in a plan view. In other words, the metal junction 30B does not connect the semiconductor element layer 11 and the semiconductor element layer 23 in the region that overlaps with the pixel region in a plan view, but it is connected to the semiconductor element layer 11 via the wiring layer 122.

[0045] As shown in Figures 5A to 5D, two or more metal joints 30B are connected to the wiring pattern 122B of the wiring layer 122. In this embodiment, the wiring pattern refers to a wiring layer separated in a plan view. It is preferable that four or more metal joints 30B are connected to the wiring pattern 122B. By connecting multiple metal joints 30B to a single continuous wiring pattern 122B in this way, the volume of the wiring pattern 122B can be secured compared to the case where each metal joint 30B is connected to a separate wiring pattern. This makes it easier to dissipate heat from the semiconductor element layer 11.

[0046] In a plan view, it is preferable that the wiring pattern 122B has a larger area than the wiring pattern 122A. This ensures a heat dissipation path. The areas of wiring pattern 122A and wiring pattern 122B can be compared, for example, by comparing the wiring patterns corresponding to pixels in a 5x5 grid.

[0047] Furthermore, in chip 1, the area of ​​the wiring pattern 122B when viewing a 1000 μm × 1000 μm region is preferably 10 times or more the area of ​​the wiring pattern 122A, and more preferably 20 times or more the area of ​​the wiring pattern 122A.

[0048] Figure 6 shows an example of the arrangement pattern of pixels 10A, 10B, and 10C in a pixel region where pixels are arranged in 25 rows and 25 columns, relating to the photoelectric conversion device according to this embodiment. In the pixel region, there are two pixels 10A with metal bonding portions 30A in each row, and one pixel 10B with a metal bonding portion 30A in each column. The remaining pixels 10C are equipped with metal bonding portions 30B.

[0049] As will be explained in detail later, as shown in Figure 6, in this embodiment, when looking at at least one of the rows and columns, metal joints 30B are provided to pixels (pixels 10C) other than those (pixels 10A and 10B) where metal joints 30A are provided. In other words, there are more metal joints 30B than metal joints 30A. This makes it possible to increase the area in which the pixel area and metal joint are connected, rather than the area in which the pixel area and metal joint are connected locally. Therefore, compared to the case where metal joints 30B are not provided, the presence of metal joints 30B can reduce uneven heat dissipation.

[0050] Furthermore, as shown in Figure 6, since one metal joint 30A or 30B is provided for each pixel 10, the distance between the metal joints 30 can be kept constant. This further reduces uneven heat dissipation. Note that multiple metal joints 30 may be provided for a single pixel 10. Also, the number of metal joints 30 provided may differ depending on the pixel 10. On the other hand, metal joints 30 may not be provided for some pixels. For example, a metal joint 30B may be provided for only one of the pixels 10C in Figure 6, while the other pixels 10C may not have a metal joint 30, or may have a metal joint 30C.

[0051] Next, the effects of this embodiment will be explained with reference to the comparative examples in Figures 7 and 8. First, the configuration in the comparative example will be described.

[0052] Figure 7 is a schematic plan view showing the arrangement of the metal joints in the comparative example. The difference from Embodiment 1 is that the metal joint 30B is not present. Figure 8A is a plan view of the wiring layer 122 in the comparative example. In Figure 8A, the metal joint 30A is shown by a long dashed line, and the metal joint 30C is shown by a long dashed line. Although not shown, the wiring corresponding to the wiring layer 121 is the same as in Figure 5B of Embodiment 1. Figure 8B is a cross-sectional view of the position corresponding to X-X' in Figure 8A, and Figure 8C is a cross-sectional view of the position corresponding to Y-Y' in Figure 8A.

[0053] As shown in Figures 8A, 8B, and 8C, the comparative example does not have a metal junction 30B. In other words, the multiple metal junctions 30 are composed of either a metal junction 30A or a metal junction 30C that is not connected to either the semiconductor element layer 11 or the semiconductor element layer 23.

[0054] Figure 14 shows a dark image captured by the photoelectric converter according to the comparative example and a dark image captured by the photoelectric converter according to Embodiment 1 under the same conditions. In Figures 14(a) and 14(b), the color changes according to the output; the lower the output, the closer the color is to black, and the higher the output, the closer the color is to white.

[0055] In Figure 14(a), the area near the pixel electrically connected via the metal junction 30A is black. On the other hand, the area near the pixel where the metal junction 30C, which is not connected to the wiring layer 122, is located is white. Thus, in the comparative example, output unevenness occurs from pixel to pixel. In contrast, in Figure 14(b), the overall color is close to black. In other words, the output unevenness from pixel to pixel is reduced. Thus, it was confirmed that output unevenness is reduced in Embodiment 1 compared to the comparative example.

[0056] The mechanism of output unevenness in the comparative example and the mechanism of output unevenness reduction according to this embodiment are described below. It should be noted that the mechanism described below is a speculation by the inventors and does not limit the effects of the present invention to those obtained by this mechanism.

[0057] The thermal conductivity of copper wiring, a common wiring layer, is approximately 400-410 [W / mK], while the thermal conductivity of silicon oxide, a common interlayer insulating material, is 5-15 [W / mK]. In pixels 10A and 10B, the heat generated near the pixel is dissipated to the surroundings through the wiring layer and the metal junction 30A. In other words, in pixels 10A and 10B, heat can be dissipated not only through wiring layers 121 and 122, but also through wiring layers 123 and 243. Therefore, the heat generated near the photoelectric conversion element of pixel 10A and pixel 10B is dissipated more efficiently than the heat generated by the photoelectric conversion element of pixel 10D. On the other hand, pixel 10D does not have a metal junction connected to the semiconductor element layer 11. In other words, the heat generated near the photoelectric conversion element of pixel 10D can only be dissipated through wiring layers 121 and 122 connected to pixel 10. Therefore, the photoelectric conversion element of pixel 10A and pixel 10B, which have high heat dissipation, will have lower dark currents compared to pixel 10D, which has low heat dissipation. Thus, it is presumed that output unevenness arises from uneven dark current due to heat.

[0058] On the other hand, in this embodiment, as shown in Figures 5A to 5D, the metal junction 30B and the wiring layer 122 are electrically connected. In other words, pixel 10C can dissipate heat not only from wiring layers 121 and 122, but also from wiring layers 123 and 243 (metal junction 30B). Therefore, compared to the comparative example, the dark current can be reduced in pixels other than pixels 10A and 10B. Consequently, since the degree of heat dissipation in pixels 10A, 10B, and 10C is uniform, it is considered that output unevenness due to dark current in dark images is reduced.

[0059] Thus, in the comparative example, only the metal junction 30A served as a heat dissipation path, resulting in a localized temperature drop. However, in this embodiment, the heat dissipation paths for the heat generated by the photoelectric conversion element can be increased within the pixel region. Therefore, heat can be dissipated more evenly, reducing or eliminating dark current unevenness.

[0060] Furthermore, the effect of increasing the heat dissipation path can be obtained even if there is only one metal joint 30B. In the case of one metal joint 30B, for example, the power supply wiring can be connected to the metal joint 30B. Various variations are possible, such as one metal joint 30B being provided for m × n pixels, or one metal joint 30B being provided for each column. Even in these cases, the effect of increasing the heat dissipation path can be obtained.

[0061] In this embodiment, all metal joints 30 are composed of either metal joints 30A or metal joints 30B, but are not limited to this. For example, metal joints 30B may be arranged discretely. As an example, a configuration in which metal joints 30C are arranged between metal joints 30B is given. Even in this case, it is clear that dark current unevenness is reduced compared to Figure 14(a). For example, a configuration in which metal joints 30C are arranged between metal joints 30B is also included in the present invention. Furthermore, even when metal joints 30C are arranged between metal joints 30B, dark current unevenness can be reduced compared to the comparative example. In this case, it is preferable that the metal joints 30B are arranged at predetermined intervals. This further reduces dark current unevenness.

[0062] It is sufficient for the wiring pattern of wiring layer 123 and the wiring pattern of wiring layer 243 to be in contact and joined, but in order to ensure joint strength, it is preferable that the interlayer insulating material 124 of wiring layer 123 and the interlayer insulating material 244 of wiring layer 243 are also joined.

[0063] As described above, the configuration of Embodiment 1 can reduce output unevenness due to dark current compared to the comparative example.

[0064] (Embodiment 2) The photoelectric converter according to Embodiment 2 will be described with reference to Figure 9. The photoelectric converter according to Embodiment 2 differs from Embodiment 1 in that a wiring layer 125 is arranged between wiring layer 121 and wiring layer 122, and the wiring pattern of wiring layer 122 is different. Other configurations are the same as those in Embodiment 1 and may be omitted from the description below. The photoelectric converter according to Embodiment 2 also includes all the configurations shown in Figures 1 to 3.

[0065] Figure 9A is a plan view of the wiring layer 122 of the photoelectric converter according to Embodiment 2, Figure 9B is a cross-sectional view of the position corresponding to X-X' in Figure 9A, and Figure 9C is a cross-sectional view of the position corresponding to Y-Y' in Figure 9A.

[0066] Figure 9A shows wiring patterns 122A, 122B, 122C, metal joints 30A and 30B, and via plugs 15. Wiring patterns 122B and 122C are VDD wiring to which the power supply voltage is supplied, or GND wiring to which the ground voltage is supplied. In this embodiment, the vertical output lines 17 are not arranged in wiring layer 122. Wiring layer 125 is arranged between wiring layer 121 and wiring layer 122. The vertical output lines 17 are included in wiring layer 125. As a result, the vertical output lines 17 are not restricted in their arrangement in the plan view of wiring patterns 122B and 122C. Therefore, it is possible to arrange multiple vertical output lines 17 in pixel 10. Consequently, the readout speed can be improved by simultaneously reading signals from multiple vertical output lines 17 in the signal processing circuit 22.

[0067] Furthermore, since wiring patterns 122B and 122C are power supply or ground wiring, they can be arranged with thicker wires than the output lines without constraints on wiring capacity. As a result, the area of ​​wiring patterns 122B and 122C increases, making it easier to connect to multiple metal junctions 30B. Heat dissipation at metal junction 30B increases and becomes more aligned with heat dissipation at metal junction 30A. Consequently, output unevenness due to dark current can be further reduced.

[0068] The area of ​​wiring patterns 122B and 122C connected to the metal joint 30B via the via plug 15 in a plan view is larger than the area of ​​wiring pattern 122A connected to the metal joint 30A via the via plug 15 in a plan view. In addition, two or more metal joints 30B are connected to wiring patterns 122B and 122C.

[0069] (Embodiment 3) The photoelectric converter according to Embodiment 3 will be described with reference to Figure 10. The photoelectric converter according to Embodiment 3 differs from Embodiments 1 and 2 in that the electrical circuit of chip 2 is connected to the metal junction 30B, while the metal junction 30B is not connected to the semiconductor element layer 11 of chip 1. Other configurations are the same as those in Embodiments 1 or 2 and may be omitted from description. The photoelectric converter according to Embodiment 3 includes all the configurations shown in Figures 1 to 3.

[0070] Figure 10A shows a plan view of the wiring layer 122 of the chip 1 in Embodiment 3, Figure 10B is a cross-section at the position corresponding to X-X' in Figure 10A, and Figure 10C is a cross-section at the position corresponding to Y-Y' in Figure 10A.

[0071] Figure 10A shows wiring patterns 122A, 122B, 122C, a metal junction 30B, and a via plug 15. This embodiment differs from Embodiment 2 in that wiring patterns 122B and 122C, which are power supply or GND wiring, are not electrically connected to the metal junction 30B. It also differs from Embodiment 2 in that a wiring layer 245 is placed between wiring layers 242 and 243. Furthermore, in Embodiment 3, a pixel 10E is arranged with the metal junction 30B and the wiring layer 245 connected via a via plug 25. In addition, two or more metal junctions 30B are connected to the wiring patterns of the wiring layer 245.

[0072] In Embodiment 3, the metal junction 30B located on pixel 10E is connected to the wiring layer 245 by a via plug 25. This means that heat dissipation from the chip 2 located on pixel 10E can be achieved not only through the connected wiring layers 241, 242, and 245, but also through wiring layers 243 and 123, similar to pixels 10A and 10B. As a result, heat can be dissipated from pixel 10E as well, reducing the likelihood of uneven heat dissipation. Furthermore, because the degree of heat dissipation at pixels 10A and 10E is consistent, unevenness due to dark current is reduced in dark images.

[0073] According to this embodiment, when an electrical circuit that is prone to generating heat is arranged in the semiconductor element layer 23, uneven heat dissipation can be reduced.

[0074] (Embodiment 4) The photoelectric conversion device according to Embodiment 4 differs from Embodiment 1 in that the metal junction 30B is physically connected to the semiconductor element layer 23, but not electrically. Other configurations are the same as those in Embodiment 1 and may therefore be omitted from description. Furthermore, the photoelectric conversion device according to Embodiment 4 includes all the configurations shown in Figures 1 to 3.

[0075] Figure 11 shows a cross-sectional view of the photoelectric conversion device according to this embodiment.

[0076] As shown in Figure 11, the metal junction 30B in this embodiment is connected to the pixel circuit of the semiconductor element layer 11 and to the semiconductor element layer 23, but it is not connected to the signal processing circuit of the semiconductor element layer 23. In other words, signals passing through the metal junction 30B are not output as signals from the pixels.

[0077] In other words, in this embodiment, the metal junction 30B is a metal junction that is not connected to the signal processing circuit of the semiconductor element layer 23. Four or more metal junctions 30B are connected to one metal layer.

[0078] The junction between the metal junction 30B and the semiconductor element layer 23 is preferably located away from electrical circuits to prevent noise from interfering with the signal from the pixel.

[0079] According to this embodiment, similar to Embodiment 1, heat generated in the pixel circuit can be dissipated to the metal junction 30B, thereby reducing uneven heat dissipation. Furthermore, according to this embodiment, heat can be dissipated from the metal junction 30B to the semiconductor element layer 23, which may further reduce uneven heat dissipation.

[0080] (Embodiment 5) The photoelectric converter according to Embodiment 5 differs from Embodiment 1 in that the metal junction 30B is connected to the same wiring pattern as the wiring pattern connected to the metal junction 30A, but is not electrically connected to the signal processing circuit of the semiconductor element layer 23. Other configurations are the same as those in Embodiment 1 and may be omitted from description. Furthermore, the photoelectric converter according to Embodiment 5 includes all the configurations shown in Figures 1 to 3.

[0081] Figure 12 shows a schematic plan view and a schematic cross-sectional view of the arrangement of the metal junctions 30A and 30B of the photoelectric converter according to this embodiment. Metal junction 30A is a metal junction that connects the semiconductor element layer 11 and the semiconductor element layer 23. Metal junction 30B is connected to the semiconductor element layer 11, but is not connected to the semiconductor element layer 23 in a position that overlaps with the pixel area in a plan view.

[0082] The metal junction 30B is connected to the same wiring pattern 122C as the metal junction 30A. Wiring pattern 122C is, for example, a wire that supplies a fixed potential. For example, wiring pattern 123C is a wire that is connected to the source or drain of a reset transistor.

[0083] The side of the metal junction 30B facing the semiconductor element layer 23 is in contact with an insulating material. In other words, it is not electrically connected to the wiring pattern arranged in the wiring structure 24.

[0084] According to this embodiment, similar to Embodiment 1, heat dissipation unevenness can be reduced compared to the case where the metal joint portion 30B is not provided, that is, the case where the metal joint portion and the wiring layer are not connected.

[0085] (modified version) In embodiments 1 to 5, the metal junction 30B is connected to one of the wiring layers arranged above and below it, but not to the other. However, as shown in Figure 13, the metal junction 30B may be connected to both of the wiring layers arranged above and below it. Specifically, the metal junction 30B does not need to be electrically connected to the semiconductor element layer 11 or the semiconductor element layer 23 in the pixel region, and may be electrically connected to the wiring layer 122 or the wiring layer 241 via via plugs. In this case, although the number of steps required to form the via plugs increases, the wiring area can be increased, thus further reducing dark current.

[0086] (Embodiment 6) Figure 15 is a block diagram showing the configuration of the photoelectric conversion system 500 according to this embodiment. The photoelectric conversion system 500 of this embodiment includes a photoelectric conversion device 2000 to which any of the above-described configurations of the photoelectric conversion device are applied. In Figure 15, an imaging system is shown as the photoelectric conversion system 500. Specific examples of the imaging system include a digital still camera, a digital camcorder, a surveillance camera, etc. The photoelectric conversion system 500 includes a photoelectric conversion device 2000, a lens 5020, an aperture 504, and a barrier 506 for protecting the lens 5020. The photoelectric conversion system 500 includes a signal processing unit 5080 (image signal generation unit) that processes the output signal output from the photoelectric conversion device 2000. The signal processing unit 5080 performs signal processing operations that perform various corrections and compressions on the input signal as needed before outputting it. The signal processing unit 5080 may also have a function to perform AD conversion processing on the output signal output from the photoelectric conversion device 2000. The photoelectric conversion system 500 further includes a buffer memory unit 510 for temporarily storing image data, and an external interface unit (external I / F unit) 512 for communicating with an external computer or the like. Furthermore, the photoelectric conversion system 500 includes a recording medium 514 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 516 for recording or reading data from the recording medium 514.

[0087] Furthermore, the photoelectric conversion system 500 includes an overall control and calculation unit 518 that performs various calculations and controls the entire digital still camera, and a timing generation unit 520 that outputs various timing signals to the photoelectric conversion device 2000 and the signal processing unit 5080. The photoelectric conversion device 2000 outputs an image signal to the signal processing unit 5080. The signal processing unit 5080 performs predetermined signal processing on the image signal output from the photoelectric conversion device 2000 and outputs image data. The signal processing unit 5080 also generates an image using the image signal.

[0088] By configuring a photoelectric conversion system using the photoelectric conversion devices of each embodiment described above, an imaging system capable of acquiring higher quality images can be realized.

[0089] (Embodiment 7) The photoelectric conversion system and mobile device of this embodiment will be described with reference to Figure 16. This embodiment shows an example of an imaging system related to an in-vehicle camera. Figure 16 shows an example of a vehicle system and an imaging system mounted thereon. The photoelectric conversion system 701 includes a photoelectric converter 702, an image preprocessing unit 715, an integrated circuit 703, and an optical system 714. The optical system 714 forms an optical image of the subject on the photoelectric converter 702. The photoelectric converter 702 converts the optical image of the subject formed by the optical system 714 into an electrical signal. The photoelectric converter 702 is one of the photoelectric converters of each embodiment described above. The image preprocessing unit 715 performs predetermined signal processing on the signal output from the photoelectric converter 702. The photoelectric conversion system 701 is provided with at least two sets of optical system 714, photoelectric converter 702, and image preprocessing unit 715, and the output from each set of image preprocessing unit 715 is input to the integrated circuit 703.

[0090] The integrated circuit 703 is an integrated circuit for photoelectric conversion system applications and includes an image processing unit 704 including a memory 705, an optical distance measuring unit 706, a parallax calculation unit 707, an object recognition unit 708, and an anomaly detection unit 709. The image processing unit 704 performs image processing such as development and defect correction on the output signal of the image preprocessing unit 715. The memory 705 stores the primary storage of the captured image and the location of defects in the captured pixels. The optical distance measuring unit 706 focuses on the subject and measures the distance. The parallax calculation unit 707 calculates the parallax (phase difference of the parallax image) from multiple image data acquired by multiple photoelectric conversion devices 702. The object recognition unit 708 recognizes subjects such as cars, roads, signs, and people. When the anomaly detection unit 709 detects an anomaly in the photoelectric conversion device 702, it alerts the main control unit 713 to the anomaly.

[0091] The integrated circuit 703 may be implemented by specially designed hardware, by a software module, or by a combination of these. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination of these.

[0092] The main control unit 713 coordinates and controls the operation of the photoelectric conversion system 701, vehicle sensor 710, control unit 720, etc. Alternatively, there may be no main control unit 713, and the photoelectric conversion system 701, vehicle sensor 710, and control unit 720 may each have their own communication interfaces and send and receive control signals via a communication network (e.g., CAN standard).

[0093] The integrated circuit 703 has the function of receiving control signals from the main control unit 713 or transmitting control signals and setting values ​​to the photoelectric converter 702 via its own control unit. For example, the integrated circuit 703 transmits settings for signal driving of the voltage switches in the photoelectric converter 702, and settings for switching the voltage switches for each frame.

[0094] The photoelectric conversion system 701 is connected to the vehicle sensor 710 and can detect the vehicle's driving conditions, such as vehicle speed, yaw rate, and steering angle, as well as the external environment and the state of other vehicles and obstacles. The vehicle sensor 710 also serves as a distance information acquisition means, which acquires distance information to an object from a parallax image. Furthermore, the photoelectric conversion system 701 is connected to the driver assistance control unit 711, which performs various driving assistance functions such as automatic steering, automatic cruising, and collision avoidance. In particular, regarding the collision judgment function, it determines whether a collision with another vehicle or obstacle has occurred and estimates a collision based on the detection results of the photoelectric conversion system 701 and the vehicle sensor 710. This enables avoidance control when a collision is estimated and activation of safety devices in the event of a collision.

[0095] Furthermore, the photoelectric conversion system 701 is also connected to a warning device 712 that issues a warning to the driver based on the judgment result of the collision judgment unit. For example, if the collision judgment unit determines that there is a high probability of collision, the main control unit 713 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 712 warns the user by sounding an alarm, displaying warning information on a display screen such as the car navigation system or instrument panel, or vibrating the seat belt or steering wheel.

[0096] In this embodiment, the photoelectric conversion system 701 captures images of the area around the vehicle, for example, the front or rear. Figure 16(b) shows an example of the arrangement of the photoelectric conversion system 701 when it captures images of the front of the vehicle.

[0097] Furthermore, although this embodiment describes control to avoid collisions with other vehicles, it can also be applied to control that automatically follows other vehicles or control that automatically drives without deviating from the lane. Moreover, the photoelectric conversion system 701 can be applied not only to vehicles such as the vehicle itself, but also to mobile objects (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to mobile objects, but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0098] (Embodiment 8) The photoelectric converter according to Embodiment 8 will be described with reference to Figures 17 and 18. The photoelectric converter according to Embodiment 8 differs from Embodiment 1 in that some of the pixels among the plurality of pixels 10 arranged in the pixel region 100 are shielded from light. In addition, a pad region 27 with pads 28 is arranged in the semiconductor element layer 11. These points and other configurations not described below are the same as in Embodiment 1, and therefore may be omitted from the description.

[0099] Figure 17 shows a schematic plan view of the corner of the semiconductor element layer 11, and Figure 18 shows a cross-sectional view of Figure 17 along the line X-X'. As shown in Figure 17, in a plan view, a pad region 27 with multiple pads 28 is arranged around the outer periphery of the pixel region 100. Each pad 28 conducts power to the photoelectric converter and a signal processing device located outside the photoelectric converter. The multiple pads 28 include pads that output signals from the photoelectric converter to the outside and pads that input power supply voltage to the photoelectric converter. The pads that input power supply voltage and the pads that output signals can be placed at any position. For example, the pads that input power supply voltage and the pads that output signals may be arranged alternately, or the pads that output signals may be arranged at predetermined intervals with the pads that input power supply voltage placed in between. Alternatively, the output pads may be grouped together, and the input pads may be placed in other areas.

[0100] A power supply region 26 is located between the pad region 27 and the pixel region 100. The boundary between the pad region 27 and the power supply region 26 can be defined, for example, by a light-shielding film 13. The region where no photoelectric conversion elements are located and where the light-shielding film 13 is located can be designated as the power supply region 26, and the area from the edge of the light-shielding film 13 to the edge of the semiconductor element layer 11 can be designated as the pad region 27.

[0101] The light-shielding film 13 is positioned so as to overlap, in a plan view, with a plurality of pixels 10 located near the power supply area 26 and the pad area 27. Pixels that overlap the light-shielding film 13 in a plan view can function as optical black pixels (OB pixels) that detect a reference value for the black level. As shown in Figure 17, the pixel area 100 has an OB pixel area 100B in which a plurality of OB pixels are arranged, and an effective pixel area 100A in which pixels to which light is incident are arranged and the light-shielding film 13 is not present.

[0102] As shown in Figure 18, the pad 28 includes a trench that penetrates the semiconductor element layer 11. The trench is formed in the depth direction from the light incident surface of the semiconductor element layer 11 to a depth that reaches the wiring pattern of the wiring layer 242 of the chip 2. The pad 28 is electrically connected to the wiring layer 242 formed on the chip 2 by wire bonding.

[0103] A metal junction 30A is provided in the OB pixel region 100B. In Figure 18, the metal junction 30A is connected to the semiconductor element layer 11 and the semiconductor element layer 23. The metal junction 30A provided in the OB pixel region 100B in Figure 18 outputs the signal of the OB pixel to the semiconductor element layer 23. Alternatively, the OB pixel region 100B may also contain a metal junction connected to one of the semiconductor element layer 11 and the semiconductor element layer 23, but not to the other.

[0104] A metal junction 30D is provided in the power supply area 26, which inputs the power supply voltage from the pad 28 to the semiconductor element layer 11 and the semiconductor element layer 23. The metal junction 30D is located in an area that does not overlap with the pixel area 100 in a plan view, and is a metal junction that connects the semiconductor element layer 11 and the semiconductor element layer 23. The power supply voltage is input to the pixels of the semiconductor element layer 11 via the metal junction 30D. When supplying a common power supply voltage to the semiconductor element layer 11 and the semiconductor element layer 23, the power supply voltage input from the pad 28 can be supplied to the semiconductor element layer 11 and the semiconductor element layer 23 via the metal junction 30D.

[0105] The pad area 27 is provided with a metal junction 30C that is not connected to either the semiconductor element layer 11 or the semiconductor element layer 23. This ensures the bonding strength between chip 1 and chip 2.

[0106] The power supply pads 28 may be separated for each semiconductor element layer. For example, one pad 28 may supply power supply voltage to semiconductor element layer 11 but not to semiconductor element layer 23. Another pad 28 may supply power supply voltage to semiconductor element layer 23 but not to semiconductor element layer 11. In this case, a metal junction 30B is provided in the power supply region 26.

[0107] Pads that input power supply voltage to semiconductor element layer 11 and semiconductor element layer 23 may be mixed with pads that supply power supply voltage to one of the semiconductor element layers. In addition, in the power supply region 26, metal junctions 30C that are not connected to either semiconductor element layer 11 or semiconductor element layer 23 may be provided to ensure the bonding strength between chip 1 and chip 2. For example, in the power supply region 26, metal junctions 30A provided between each pad 28 and the pixel 10 closest to each pad 28 are connected to semiconductor element layer 11 and semiconductor element layer. Metal junctions 30C may be provided at other metal junctions.

[0108] Furthermore, the pad region 27 may also contain a metal junction 30A that is not connected to the pad 28 but is connected to the semiconductor element layer 11 and the semiconductor element layer 23, and a metal junction 30B that is connected to one of the semiconductor element layers.

[0109] According to this embodiment, similar to Embodiment 1, output unevenness due to dark current can be reduced compared to the comparative example. Furthermore, by positioning the metal joint 30C in a suitable location, the bonding strength between chip 1 and chip 2 can be ensured.

[0110] (Embodiment 9) The photoelectric converter according to this embodiment will be described with reference to Figures 19A to 19F and Figure 21. The photoelectric converter according to this embodiment differs from Embodiment 8 in that the wiring structure 12 of the chip 1 has five wiring layers. This point and other configurations not described below are the same as in Embodiment 8, and therefore may be omitted from the description.

[0111] Figure 21 shows the circuit diagram of the pixel in this embodiment. In this embodiment, the capacitive addition transistor 107A is divided into a switch transistor 109 and a capacitor 108, which is different from the pixel circuit described in Figure 2. This makes it easier to improve the dynamic range and linearity at low ISO sensitivity. The gate electrode of the switch transistor 109 is controlled by a control line, and a fixed power supply voltage (e.g., VDD) is supplied to the gate of the capacitor 108.

[0112] The wiring structure 12 is configured such that, starting from the semiconductor element layer 11, the following wiring layers are arranged in order: wiring layer 121 (metal 1), wiring layer 127 (metal 2), wiring layer 126 (metal 3), wiring layer 125 (metal 4), wiring layer 122 (metal 5), and wiring layer 123 (metal 6).

[0113] Figure 19A is a planar layout diagram showing wiring layer 123, wiring layer 122, and via plugs 15 connecting wiring layer 123 and wiring layer 122. As mentioned above, wiring layer 123 has a wiring pattern that constitutes a metal junction. The wiring pattern of wiring layer 123 is shown by dashed or dotted lines. The wiring pattern 122A of wiring layer 122 is connected via via plugs to the metal junction 30A that is connected to semiconductor element layer 11 and semiconductor element layer 23. In addition, the wiring pattern 122B of wiring layer 122 is connected to the metal junction 30B that is connected to semiconductor element layer 11 but not to semiconductor element layer 23 in the region that overlaps with the pixel area in a planar view. In Figure 9A, it is not necessary for all metal junctions 30B to be configured so that they are not connected to the semiconductor element layer 23; some metal junctions 30B may be connected to VDD of the semiconductor element layer 23. In this embodiment, the case where the wiring pattern 122B is a VDD wiring is described as an example, but the embodiment is not limited to this.

[0114] The wiring pattern 122B is arranged in a mesh-like manner in the wiring layer 122, with partial slits formed in a plan view. By increasing the area of ​​the wiring pattern 122B compared to the wiring pattern A in the pixel region in this way, heat from the semiconductor element layer 11 is made easier to dissipate.

[0115] Note that instead of the wiring layer 123 in Figure 19A, a wiring layer as shown in Figure 20 may be used. In Figure 20, the wiring pattern 122B is arranged between multiple metal joints 30B that are arranged in the row, column, and diagonal directions, which is different from the wiring layer shown in Figure 19A. In other words, in a plan view, insulating material may not be placed anywhere other than between the wiring pattern 122B and the wiring pattern 122A, and the wiring pattern 122B may be arranged continuously. In this case, the area of ​​the wiring pattern can be increased compared to Figure 19A, making it easier to dissipate the heat generated in the semiconductor element layer 11.

[0116] Figure 19B is a planar layout diagram showing a wiring layer 125 and via plugs 18 connecting wiring layer 125 and wiring layer 122. Wiring layer 125 has wiring pattern 125D which is connected to wiring pattern 122B, and wiring patterns 125A, 125B, and 125C which are connected to wiring pattern 122A. Wiring pattern 125D is the wiring pattern connected to the metal joint 30B. Also, wiring patterns 125A, 125B, and 125C are wiring patterns connected to the metal joint 30A. Wiring patterns 125A, 125B, and 125C constitute the vertical output lines 17. In Figure 19B, some pixels in the pixel area are shown enlarged, so via plugs 18 are connected to only some of the vertical output lines. In areas not shown, the vertical output lines 17 are connected to the wiring patterns of wiring layer 122 via via plugs 18.

[0117] In the wiring layer 125, the thickness of wiring pattern 125D is greater than that of wiring patterns 125A, 125B, and 125C. This makes it easier to secure a heat dissipation path from the semiconductor element layer 11. In this layer, the thickness of the wiring pattern refers to its width in the left-right direction. For example, the thickness is defined as the width of each wiring pattern in the longitudinal direction and perpendicular direction of the vertical output lines 17A to 17L.

[0118] Figure 19C is a plan layout diagram showing wiring layer 126 and via plugs connecting wiring layer 126 and wiring layer 125. Wiring patterns 126A and 126B constitute the vertical output lines 17. Wiring pattern 126B is connected to wiring pattern 125C. Among the vertical output lines, wiring patterns 126A, 125B, and 125C have offset pitches. In other words, the wiring patterns arranged in wiring layer 126 and extending in the column direction, such as wiring pattern 126A, do not overlap in a plan view with the wiring patterns arranged in wiring layer 125 and extending in the column direction, such as wiring patterns 125B and 125C. That is, the wiring patterns extending vertically in wiring layer 126 are located between the wiring patterns extending vertically in wiring layer 125. Then, the signal output from the pixel is read out from wiring pattern 125C via wiring pattern 126B.

[0119] Wiring pattern 126C is connected to wiring pattern 125D. Additionally, wiring pattern 126D is placed in wiring layer 126. Wiring pattern 126D constitutes the GND wiring.

[0120] Figure 19D is a planar layout diagram showing wiring layer 127 and via plugs connecting wiring layer 127 and wiring layer 126. Wiring patterns 127A and 127B are wirings connected to vertical output lines. As shown in Figure 19D, the positions of the via plugs are shifted row by row in wiring patterns 127A and 127B. This changes the wiring layer 126 and the vertical output lines connected to it row by row.

[0121] Wiring pattern 127C is connected to wiring pattern 126C, forming a VDD connection. Wiring pattern 127D is connected to wiring pattern 126D, forming a GND connection. Wiring patterns 127E to 127K are control lines for each transistor. Wiring patterns 127E to 127K are connected to wiring pattern 126E in Figure 19C at one or more points for each row of the pixel array. Control pulse signals output from the row scanning circuit shown in Figure 1 are supplied to wiring pattern 126E via the metal junction 30A and via plugs, and each transistor is controlled by wiring patterns 127E to 127K connected to wiring pattern 126E via via plugs. Wiring pattern 127L is positioned to supply the source potential of the amplification transistors and is positioned to overlap the FD and FD wiring in a plan view. This shields the FD.

[0122] Figure 19E is a planar layout diagram showing wiring layer 121 and via plugs connecting wiring layer 121 and wiring layer 127. Wiring pattern 121A is connected to wiring pattern 127A and is a wiring that connects to the vertical output line. Wiring pattern 121B is connected to wiring pattern 127B and is a wiring that connects to the vertical output line. Wiring pattern 121C is connected to wiring pattern 127C and constitutes the VDD wiring. Wiring pattern 127D is connected to wiring pattern 127D and constitutes the GND wiring.

[0123] Wiring patterns 121E to 121K are the control lines for each transistor. The connection relationships between each wiring pattern 121E to 121K and each transistor will be described later.

[0124] Wiring pattern 121L is connected to wiring pattern 127L. Wiring pattern 121M is the wiring that connects the FD to the gate of the amplification transistor.

[0125] Figure 19F is a planar layout diagram showing the semiconductor region and polysilicon. Reference numerals 101 to 109 correspond to the respective configurations of the pixel circuit diagram shown in Figure 21.

[0126] The gate of transfer transistor 102A is connected to wiring pattern 121J. Wiring pattern 121J functions as a control line for transfer transistor 102A. The gate of transfer transistor 102B is connected to wiring pattern 121K. Wiring pattern 121K functions as a control line for transfer transistor 102B.

[0127] As mentioned above, the FD and the gate of the amplification transistor 105 are connected by wiring pattern 121M. The source of the amplification transistor 105 is connected to wiring pattern 121L. The drain of the amplification transistor 105 is connected to wiring pattern 121C, forming the VDD wiring.

[0128] The gate of the capacitive transistor 107B is connected to the wiring pattern 121E. The wiring pattern 121E functions as a control line for the capacitive transistor 107B.

[0129] As mentioned above, the capacitive transistor 107A includes a switch transistor 109 and a capacitor 108. The gate of the switch transistor 109 is connected to the wiring pattern 121F. The wiring pattern 121F functions as a control line for the switch transistor 109. The gate of the capacitor 108 is connected to the wiring pattern 121C.

[0130] As shown in Figure 19F, the channel length of capacitor 108 is made longer than the channel length of switch transistor 109. This allows for a larger capacitance of capacitor 108, thereby improving the dynamic range at low ISO sensitivities. Conversely, the channel length of switch transistor 109 is made shorter than the channel length of capacitor 108. This allows for improved ON characteristics of the switch transistor 109, thereby improving linearity at low ISO sensitivities. Furthermore, by separating the capacitor 108 and the switch transistor 109, the threshold voltage Vth of the capacitor-adding transistor 107B, capacitor 108, and switch transistor 109 can be changed. Therefore, it becomes possible to change the ON and OFF characteristics of each transistor, making it possible to achieve both dynamic range and linearity according to the ISO sensitivity.

[0131] The gate of reset transistor 104 is connected to wiring pattern 121I. Wiring pattern 121I is the control line for reset transistor 104. The drain of reset transistor 104 is connected to wiring pattern 121C.

[0132] The drains of selection transistor 106A and selection transistor 106B are connected by a common semiconductor region. The drains of selection transistors 106A and 106B are connected to wiring pattern 121L. The gate of selection transistor 106A is connected to wiring pattern 121H. Wiring pattern 121H functions as a control line for selection transistor 106A. The gate of selection transistor 106B is connected to wiring pattern 121G. Wiring pattern 121G functions as a control line for selection transistor 106B. The source of selection transistor 106A is connected to wiring pattern 121A. The source of selection transistor 106B is connected to wiring pattern 121B.

[0133] Each pixel is provided with a contact 110 that supplies a fixed potential to the well of the semiconductor element layer. The fixed potential is, for example, the power supply voltage (e.g., VDD) or the grounding voltage (e.g., GND). Thus, it is preferable to provide a contact 110 to each pixel considering the imaging performance of each pixel, but the contacts 110 may be provided sparsely.

[0134] In this embodiment, as in Embodiment 1, output unevenness due to dark current can be reduced compared to the comparative example.

[0135] In the diagram of this embodiment, the area of ​​the wiring patterns connected to the metal joint 30B is increased in wiring layers 125 and 122, but this is not the only way to do so. For example, the area of ​​the wiring patterns connected to the metal joint 30B may be increased in other wiring layers such as wiring layer 121 and wiring layer 127.

[0136] (Other embodiments) Although the embodiments have been described above, the present invention is not limited to these embodiments, and various modifications and variations are possible. Furthermore, the embodiments are mutually applicable. [Explanation of Symbols]

[0137] 1 chip 1 2 chips 2 3 Joint surface 11. First semiconductor element layer 23 Second semiconductor device layer 30A 1st metal joint 30B 2nd metal joint

Claims

1. A first chip having a first semiconductor element layer including a pixel region in which multiple pixel circuits are arranged, The device comprises a second chip having a second semiconductor element layer on which a signal processing circuit for processing signals output by the plurality of pixel circuits is arranged, and a first wiring pattern, The first chip and the second chip are joined by a plurality of metal joints at the junction surface between the first semiconductor element layer and the second semiconductor element layer. The plurality of metal joints include a plurality of first metal joints and a plurality of second metal joints arranged in a region that overlaps with the pixel region in a plan view. Each of the plurality of first metal junctions connects at least one pixel circuit among the plurality of pixel circuits to the second semiconductor element layer. Each of the plurality of second metal junctions is not included in the electrical path connecting the plurality of pixel circuits and the signal processing circuit. The first wiring pattern is provided in the layer between the plurality of metal junctions and one of the first semiconductor element layer and the second semiconductor element layer. Each of the plurality of second metal joints is commonly connected to the first wiring pattern. Between the plurality of second metal joints, an insulating material is provided that is in contact with the joint surface. The plurality of metal junctions include a third metal junction that is not connected to the first semiconductor element layer and the second semiconductor element layer. A photoelectric conversion device characterized by the following features.

2. Each of the plurality of second metal junctions has a first surface on the side of the first semiconductor element layer and a second surface on the side of the second semiconductor element layer, The first surface is not connected to the wiring connected to the pixel circuit. The photoelectric converter according to claim 1, characterized in that the second surface is connected to wiring connected to the signal processing circuit.

3. A first chip having a first semiconductor element layer including a pixel region in which a plurality of pixel circuits are arranged, The device comprises a second chip having a second semiconductor element layer on which a signal processing circuit for processing signals output by the plurality of pixel circuits is arranged, and a first wiring pattern, The first chip and the second chip are joined by a plurality of metal joints at the junction surface between the first semiconductor element layer and the second semiconductor element layer. The plurality of metal joints include a plurality of first metal joints and a plurality of second metal joints arranged in a region that overlaps with the pixel region in a plan view. Each of the plurality of first metal junctions connects at least one pixel circuit among the plurality of pixel circuits to the second semiconductor element layer. Each of the plurality of second metal junctions is not included in the electrical path connecting the plurality of pixel circuits and the signal processing circuit. The first wiring pattern is provided in the layer between the plurality of metal junctions and one of the first semiconductor element layer and the second semiconductor element layer. Each of the plurality of second metal joints is commonly connected to the first wiring pattern. Between the plurality of second metal joints, an insulating material is provided that is in contact with the joint surface. Each of the plurality of second metal junctions has a first surface on the side of the first semiconductor element layer and a second surface on the side of the second semiconductor element layer. The first surface is not connected to the wiring connected to the pixel circuit. The second surface is connected to the wiring connected to the signal processing circuit. A photoelectric conversion device characterized by the following features.

4. A first chip having a first semiconductor element layer including a pixel region in which a plurality of pixel circuits are arranged, The device comprises a second chip having a second semiconductor element layer on which a signal processing circuit for processing signals output by the plurality of pixel circuits is arranged, and a first wiring pattern, The first chip and the second chip are joined by a plurality of metal joints at the junction surface between the first semiconductor element layer and the second semiconductor element layer. The plurality of metal joints include a plurality of first metal joints and a plurality of second metal joints arranged in a region that overlaps with the pixel region in a plan view. Each of the plurality of first metal junctions connects at least one pixel circuit among the plurality of pixel circuits to the second semiconductor element layer. Each of the plurality of second metal junctions is not included in the electrical path connecting the plurality of pixel circuits and the signal processing circuit. The first wiring pattern is provided in the layer between the plurality of metal junctions and one of the first semiconductor element layer and the second semiconductor element layer. Each of the plurality of second metal joints is commonly connected to the first wiring pattern. Between the plurality of second metal joints, an insulating material is provided that is in contact with the joint surface. Each of the aforementioned plurality of pixel circuits includes a photoelectric conversion element, The plurality of metal joints are arranged such that one metal joint corresponds to one of the photoelectric conversion elements. A photoelectric conversion device characterized by the following features.

5. The plurality of metal joints are arranged in multiple rows and multiple columns in a plan view, The photoelectric conversion device according to claim 4, characterized in that the number of second metal joints among the metal joints arranged in a predetermined row is greater than the number of first metal joints.

6. The photoelectric conversion device according to claim 5, characterized in that the number of second metal joints among the metal joints arranged in a predetermined row is greater than the number of first metal joints.

7. A first chip having a first semiconductor element layer including a pixel region on which a plurality of pixel circuits are arranged, The device comprises a second chip having a second semiconductor element layer on which a signal processing circuit for processing signals output by the plurality of pixel circuits is arranged, and a first wiring pattern, The first chip and the second chip are joined by a plurality of metal joints at the junction surface between the first semiconductor element layer and the second semiconductor element layer. The plurality of metal joints include a plurality of first metal joints and a plurality of second metal joints arranged in a region that overlaps with the pixel region in a plan view. Each of the plurality of first metal junctions connects at least one pixel circuit among the plurality of pixel circuits to the second semiconductor element layer. Each of the plurality of second metal junctions is not included in the electrical path connecting the plurality of pixel circuits and the signal processing circuit. The first wiring pattern is provided in the layer between the plurality of metal junctions and one of the first semiconductor element layer and the second semiconductor element layer. Each of the plurality of second metal joints is commonly connected to the first wiring pattern. Between the plurality of second metal joints, an insulating material is provided that is in contact with the joint surface. When viewing a 1000 μm × 1000 μm region including the aforementioned pixel region, the area of ​​the first wiring pattern connected to the plurality of second metal junctions is at least 10 times the area of ​​the wiring pattern arranged in the same layer as the first wiring pattern and connected to the first metal junction. A photoelectric conversion device characterized by the following features.

8. A first chip having a first semiconductor element layer including a pixel region on which a plurality of pixel circuits are arranged, The device comprises a second chip having a second semiconductor element layer on which a signal processing circuit for processing signals output by the plurality of pixel circuits is arranged, and a first wiring pattern, The first chip and the second chip are joined by a plurality of metal joints at the junction surface between the first semiconductor element layer and the second semiconductor element layer. The plurality of metal joints include a plurality of first metal joints and a plurality of second metal joints arranged in a region that overlaps with the pixel region in a plan view. Each of the plurality of first metal junctions connects at least one pixel circuit among the plurality of pixel circuits to the second semiconductor element layer. Each of the plurality of second metal junctions is not included in the electrical path connecting the plurality of pixel circuits and the signal processing circuit. The first wiring pattern is provided in the layer between the plurality of metal junctions and one of the first semiconductor element layer and the second semiconductor element layer. Each of the plurality of second metal joints is commonly connected to the first wiring pattern. Between the plurality of second metal joints, an insulating material is provided that is in contact with the joint surface. Each of the plurality of second metal junctions is connected to one of the first semiconductor element layer and the second semiconductor element layer, but is not connected to the other of the first semiconductor element layer and the second semiconductor element layer. A photoelectric conversion device characterized by the following features.

9. A first chip having a first semiconductor element layer including a pixel region in which a plurality of pixel circuits are arranged, The device comprises a second chip having a second semiconductor element layer on which a signal processing circuit for processing signals output by the plurality of pixel circuits is arranged, a first wiring pattern, and a plurality of via plugs. The first chip and the second chip are joined by a plurality of metal joints at the junction surface between the first semiconductor element layer and the second semiconductor element layer. The plurality of metal joints include a plurality of first metal joints and a plurality of second metal joints arranged in a region that overlaps with the pixel region in a plan view. Each of the plurality of first metal junctions connects at least one pixel circuit among the plurality of pixel circuits to the second semiconductor element layer. Each of the plurality of second metal junctions is not included in the electrical path connecting the plurality of pixel circuits and the signal processing circuit. The first wiring pattern is provided in the layer between the plurality of metal junctions and the first semiconductor element layer. Each of the plurality of second metal joints is commonly connected to the first wiring pattern. Between the plurality of second metal joints, an insulating material is provided that is in contact with the joint surface. Each of the plurality of second metal junctions has a first surface facing the first semiconductor element layer and a second surface facing the second semiconductor element layer, which is located between the first surface and the second semiconductor element layer. The first surface of each of the plurality of second metal joints and the first wiring pattern are connected via a corresponding via plug among the plurality of via plugs. The entire second surface of each of the plurality of second metal joints is in contact with the insulating material. A photoelectric conversion device characterized by the following features.

10. A first chip having a first semiconductor element layer including a pixel region in which a plurality of pixel circuits are arranged, The device comprises a second chip having a second semiconductor element layer on which a signal processing circuit for processing signals output by the plurality of pixel circuits is arranged, a first wiring pattern, and a plurality of via plugs. The first chip and the second chip are joined by a plurality of metal joints at the junction surface between the first semiconductor element layer and the second semiconductor element layer. The plurality of metal joints include a plurality of first metal joints and a plurality of second metal joints arranged in a region that overlaps with the pixel region in a plan view. Each of the plurality of first metal junctions connects at least one pixel circuit among the plurality of pixel circuits to the second semiconductor element layer. Each of the plurality of second metal junctions is not included in the electrical path connecting the plurality of pixel circuits and the signal processing circuit. The first wiring pattern is provided in the layer between the plurality of metal junctions and the second semiconductor element layer. Each of the plurality of second metal joints is commonly connected to the first wiring pattern. Between the plurality of second metal joints, an insulating material is provided that is in contact with the joint surface. Each of the plurality of second metal junctions has a first surface facing the first semiconductor element layer and a second surface facing the second semiconductor element layer, which is located between the first surface and the second semiconductor element layer. The second surface of each of the plurality of second metal joints and the first wiring pattern are connected via a corresponding via plug among the plurality of via plugs. The entire first surface of each of the plurality of second metal joints is in contact with the insulating material. A photoelectric conversion device characterized by the following features.

11. The photoelectric converter according to any one of claims 1 to 10, characterized in that the first wiring pattern is a power supply wiring to which a power supply voltage is supplied or a ground voltage is supplied.

12. A second wiring pattern, to which the first metal joint is connected, is arranged on the layer on which the first wiring pattern is arranged. The photoelectric conversion device according to claim 11, characterized in that the first wiring pattern is thicker than the second wiring pattern.

13. The photoelectric converter according to claim 12, characterized in that the second wiring pattern is an output line for transmitting the signal output by the pixel circuit.

14. The photoelectric conversion device according to any one of claims 1 to 13, characterized in that the plurality of second metal joints are repeatedly arranged at predetermined intervals.

15. The photoelectric conversion device according to any one of claims 1 to 14, characterized in that the main component of each of the plurality of metal joints is copper.

16. Each of the aforementioned plurality of pixel circuits includes a photoelectric conversion element, The photoelectric conversion device according to any one of claims 1 to 3, 7 to 10, characterized in that one of the plurality of metal joints is arranged in correspondence with one of the photoelectric conversion elements.

17. The aforementioned multiple metal joints are arranged in multiple rows and multiple columns in a plan view. The photoelectric conversion device according to claim 16, characterized in that the number of second metal joints among the metal joints arranged in a predetermined row is greater than the number of first metal joints.

18. The photoelectric conversion device according to claim 17, characterized in that the number of second metal joints among the metal joints arranged in a predetermined row is greater than the number of first metal joints.

19. The photoelectric conversion device according to any one of claims 1 to 6, 8 to 10, characterized in that when viewing a 1000 μm × 1000 μm region including the pixel region, the area of ​​the first wiring pattern connected to the plurality of second metal junctions is 10 times or more the area of ​​the wiring pattern arranged in the same layer as the first wiring pattern and connected to the first metal junction.

20. The photoelectric conversion device according to any one of claims 1 to 19, characterized in that the first wiring pattern connected to the plurality of second metal joints is arranged in a mesh shape.

21. The photoelectric conversion apparatus according to any one of claims 3 to 10, characterized in that the plurality of metal junctions include a third metal junction that is not connected to the first semiconductor element layer and the second semiconductor element layer.

22. Each of the plurality of second metal junctions has a first surface on the side of the first semiconductor element layer and a second surface on the side of the second semiconductor element layer. The first surface is connected to the wiring connected to the pixel circuit, The photoelectric converter according to any one of claims 1, 4 to 9, characterized in that the second surface is not connected to the wiring connected to the signal processing circuit.

23. Each of the plurality of second metal junctions has a first surface on the side of the first semiconductor element layer and a second surface on the side of the second semiconductor element layer. The first surface is not connected to the wiring connected to the pixel circuit. The photoelectric converter according to any one of claims 1 to 8, characterized in that the second surface is connected to wiring connected to the signal processing circuit.

24. The photoelectric conversion apparatus according to any one of claims 1 to 8, characterized in that the first wiring pattern is provided in the layer between the plurality of metal junctions and the first semiconductor element layer.

25. The photoelectric conversion apparatus according to any one of claims 1 to 8, characterized in that the first wiring pattern is provided in the layer between the plurality of metal junctions and the second semiconductor element layer.

26. A photoelectric conversion device according to any one of claims 1 to 25, A photoelectric conversion system characterized by comprising a signal processing unit for processing signals obtained by the aforementioned photoelectric conversion device.

27. A photoelectric conversion device according to any one of claims 1 to 25, Distance information acquisition means for acquiring distance information to an object based on the signal from the aforementioned photoelectric converter, A mobile body characterized by having control means for controlling the mobile body based on the distance information.

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