Semiconductor equipment

Abstract

A semiconductor device capable of high-speed data transmission and having a reduced circuit area is provided. [Solution] A semiconductor device includes a layer having two opposing surfaces, a semiconductor chip, and an external terminal. The semiconductor chip is provided on one surface of the layer, and the external terminal is provided on the other surface of the layer, at least in a region that does not overlap with the semiconductor chip. The semiconductor chip includes a first circuit including a first transistor, and the layer includes a second circuit including a second transistor. The first circuit is electrically connected to the second circuit, and the second circuit is electrically connected to the external terminal. The second transistor includes a metal oxide in a channel formation region. The second circuit may be a CML circuit. Insulators may be provided above one surface of the layer and on side surfaces of the semiconductor chip.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, an operation method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, as the technical field of one aspect of the present invention disclosed in this specification, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, storage devices, signal processing devices, sensors, processors, electronic devices, systems, their driving methods, their manufacturing methods, or their inspection methods can be cited as an example.

Background Art

[0003] In recent years, in electronic devices such as personal computers and display devices, the amount of data to be processed has been increasing. This is considered to be due to the improvement of the processing ability of processors and the like, the increase in the storage capacity of storage devices and the like, and the progress of high definition of display devices.

[0004] In addition, with the improvement of the processing ability of processors and the increase in the storage capacity of storage devices, the high-speed data transmission has also been required. For example, even if the processing ability of the processor is high, if the data transmission amount is small, the overall processing time may increase. Also, for example, in a storage device, when the amount of data handled in a write operation or a read operation is large, the data transmission input / output to the storage device may also take a long time. Patent Document 1 and Patent Document 2 disclose a circuit configuration capable of high-speed data transmission using a CML (Current Mode Logic) circuit.

Prior Art Documents

Patent Documents

[0005] [Patent Document 1] Japanese Patent Publication No. 2015-2408 [Patent Document 2] Japanese Patent Publication No. 2014-50087 [Overview of the project] [Problems that the invention aims to solve]

[0006] A CML circuit can be constructed using, for example, a bipolar transistor or a MOS transistor. However, for example, a CML circuit using a bipolar transistor is difficult to form on the same substrate as a circuit using a transistor other than a bipolar transistor. Similarly, for example, a CML circuit using a MOS transistor is difficult to form on the same substrate as a circuit using a transistor other than a MOS transistor.

[0007] Therefore, if the CML circuit and other circuits are each composed of different transistors, it is necessary to form the CML circuit and other circuits on different substrates. For example, when the CML circuit and other circuits are mounted on a single printed circuit board, the area of ​​the printed circuit board increases, which may increase the manufacturing cost of the semiconductor device including the CML circuit and other circuits.

[0008] Furthermore, even if the CML circuit and other circuits can be formed on the same substrate (e.g., a semiconductor wafer) using the same transistors, the circuit area may increase depending on the circuit size. In this case as well, a larger circuit area increases the area required to form the circuit on the substrate, which may increase the manufacturing cost of the semiconductor device including the CML circuit and other circuits.

[0009] One aspect of the present invention aims to provide a semiconductor device capable of high-speed data transmission. Alternatively, one aspect of the present invention aims to provide a semiconductor device with reduced circuit area. Alternatively, one aspect of the present invention aims to provide a semiconductor device with reduced manufacturing costs. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device.

[0010] It should be noted that the problems addressed by one aspect of the present invention are not limited to those listed above. The problems listed above do not preclude the existence of other problems. These other problems are those not mentioned in this section, as described below. Those not mentioned in this section can be derived from the description in the specification or drawings, etc., by those skilled in the art, and can be appropriately extracted from these descriptions. It should be noted that one aspect of the present invention solves at least one of the problems listed above and other problems. It should be noted that one aspect of the present invention does not need to solve all of the problems listed above and other problems. [Means for solving the problem]

[0011] (1) One aspect of the present invention is a semiconductor device comprising a layer having two surfaces, a semiconductor chip, and an external terminal. The semiconductor chip is provided on one surface of the layer, and the external terminal is provided on the other surface of the layer, in a region that does not overlap with the semiconductor chip. The semiconductor chip has a first circuit including a first transistor, and the layer has a second circuit including a second transistor. The first circuit is electrically connected to the second circuit, and the second circuit is electrically connected to the external terminal. The second transistor also contains a metal oxide in its channel-forming region.

[0012] (2) Alternatively, in one aspect of the present invention, the second circuit in (1) above may be configured as a CML circuit.

[0013] (3) Alternatively, in one aspect of the present invention, in (1) or (2) above, an insulator may be provided on the upper side of one surface of the layer and on the side surface of the semiconductor chip.

[0014] (4) Alternatively, in one aspect of the present invention, in any one of (1) to (3) above, the semiconductor chip may have a connection terminal, and the first circuit and the second circuit may be electrically connected via the connection terminal. Furthermore, it is preferable that the pitch width of the external terminal is greater than the pitch width of the connection terminal.

[0015] (5) Alternatively, in any one of (1) to (4) above, the metal oxide may have a configuration comprising indium, element M (where M is one or more elements selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

[0016] (6) Alternatively, one aspect of the present invention is an electronic device having any one of the semiconductor devices described in (1) to (5) above, and a housing.

[0017] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices and may contain semiconductor devices.

[0018] Furthermore, when it is stated in this specification that X and Y are connected, it is assumed that this specification discloses the cases in which X and Y are electrically connected, functionally connected, and directly connected. Therefore, it is assumed that the disclosed connections are not limited to predetermined connections, such as those shown in the figures or text, but also include connections other than those shown in the figures or text. X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0019] One example of a case where X and Y are electrically connected is that one or more elements that enable electrical connection between X and Y (e.g., switches, transistors, capacitive elements, inductors, resistors, diodes, display devices, light-emitting devices, loads, etc.) can be connected between X and Y. A switch has the function of controlling on / off states. In other words, a switch has the function of controlling whether or not current flows by being in a conductive state (on state) or a non-conductive state (off state).

[0020] One example of a functional connection between X and Y is when one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signal conversion circuits (digital-to-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplification circuits (circuits that can increase the signal amplitude or current amount, such as operational amplifiers, differential amplifiers, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y.

[0021] Furthermore, when it is explicitly stated that X and Y are electrically connected, this includes both cases where X and Y are electrically connected (i.e., connected with another element or circuit in between) and cases where X and Y are directly connected (i.e., connected without another element or circuit in between).

[0022] Furthermore, it can be expressed as, for example, "X, Y, the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and the connection is in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Alternatively, it can be expressed as, "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Alternatively, it can be expressed as, "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using similar notation to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and their technical scope determined. Note that these notational methods are examples only and are not limited to them. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0023] Even if independent components are shown as electrically connected in a circuit diagram, a single component may possess the functions of multiple components. For example, if part of a wire also functions as an electrode, a single conductive film possesses the functions of both a wire and an electrode. Therefore, in this specification, "electrically connected" includes cases where a single conductive film possesses the functions of multiple components.

[0024] Furthermore, in this specification, "resistive element" can refer to, for example, a circuit element or wiring having a resistance value higher than 0Ω. Therefore, in this specification, "resistive element" includes wiring having a resistance value, transistors, diodes, coils, etc., through which current flows between the source and drain. Therefore, the term "resistive element" can be replaced with terms such as "resistance," "load," or "region having a resistance value," and conversely, the terms "resistance," "load," or "region having a resistance value" can be replaced with terms such as "resistive element." The resistance value can be, for example, preferably 1mΩ or more and 10Ω or less, more preferably 5mΩ or more and 5Ω or less, and even more preferably 10mΩ or more and 1Ω or less. Also, for example, 1Ω or more and 1 × 10 9 It may also be less than or equal to Ω.

[0025] Furthermore, in this specification, "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0F, a region of wiring having a capacitance value, parasitic capacitance, the gate capacitance of a transistor, etc. Therefore, in this specification, "capacitive element" includes not only a circuit element comprising a pair of electrodes and a dielectric material contained between the electrodes, but also parasitic capacitance appearing between wirings, the gate capacitance appearing between one of the sources or drains of a transistor and the gate, etc. Also, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can be replaced with terms such as "capacitance," and conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Also, the term "pair of electrodes" in "capacitance" can be replaced with terms such as "pair of conductors," "pair of conductive regions," and "pair of regions." The capacitance value can be, for example, 0.05fF or more and 10pF or less. Alternatively, it may be, for example, 1pF or more and 10μF or less.

[0026] Furthermore, in this specification, a transistor has three terminals called the gate, source, and drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as either the source or the drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type, p-channel type) and the potential applied to the three terminals of the transistor, one of the two input and output terminals becomes the source and the other becomes the drain. For this reason, in this specification, the terms source and drain can be used interchangeably. Also, in this specification, when describing the connection relationships of a transistor, the notation "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) is used. Depending on the structure of the transistor, in addition to the three terminals described above, there may be a back gate. In this case, in this specification, one of the gate or back gate of the transistor may be called the first gate, and the other of the gate or back gate of the transistor may be called the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, if a transistor has three or more gates, in this specification, each gate may be referred to as the first gate, second gate, third gate, and so on.

[0027] Furthermore, in this specification, the term "node" can be replaced with terms such as terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., depending on the circuit configuration, device structure, etc. Also, terminals, wiring, etc. can be replaced with "node."

[0028] Furthermore, in this specification, "voltage" and "potential" may be used interchangeably as appropriate. "Voltage" is the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be replaced with "potential." Note that the ground potential does not necessarily mean 0V. Also, potential is relative, and as the reference potential changes, the potential applied to the wiring, the potential applied to the circuit, and the potential output from the circuit also change.

[0029] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, if two wires are described as "functioning as wires that supply a high-level potential," the high-level potentials provided by each wire do not have to be equal. Similarly, if two wires are described as "functioning as wires that supply a low-level potential," the low-level potentials provided by each wire do not have to be equal.

[0030] "Electric current" refers to the phenomenon of electric charge movement (electrical conduction). For example, the statement "electrical conduction of positively charged elements is occurring" can be rephrased as "electrical conduction of negatively charged elements is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of electric charge movement associated with the movement of carriers (electrical conduction). Carriers here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., is the direction in which positive carriers move and is expressed as a positive current quantity. In other words, the direction in which negative carriers move is the opposite direction to the direction of the current and is expressed as a negative current quantity. Therefore, in this specification, if there is no specification regarding the positive or negative (or direction) of the current, a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, descriptions such as "current is input to element A" can be rephrased as "current is output from element A."

[0031] Furthermore, the ordinal numbers "1st," "2nd," and "3rd" in this specification are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "1st" in one embodiment of this specification may be referred to as "2nd" in another embodiment or in the claims. Also, for example, a constituent element referred to as "1st" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0032] Furthermore, in this specification, terms indicating placement such as "above" and "below" are sometimes used for convenience to explain the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms explained in the specification are not limited to those described and can be appropriately rephrased depending on the situation. For example, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the lower surface of the conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0033] Furthermore, the terms "above" or "below" do not limit the positional relationship of the components to being directly above or below each other and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0034] Furthermore, in this specification, terms such as "film" and "layer" can be interchanged as needed. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Alternatively, depending on the circumstances, terms such as "film" and "layer" can be omitted and replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Or, for example, the terms "insulating layer" or "insulating film" may be changed to the term "insulator."

[0035] Furthermore, in this specification, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wiring" are formed as a single unit. Also, for example, "terminal" may be used as part of "wiring" and / or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wiring," or "terminals" are formed as a single unit. Therefore, for example, an "electrode" can be part of "wiring" or a "terminal," and for example, a "terminal" can be part of "wiring" or an "electrode." In addition, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" depending on the circumstances.

[0036] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" can be interchanged with each other depending on the circumstances or situation. For example, the term "wiring" may be changed to the term "signal line." Also, for example, the term "wiring" may be changed to the term "power line." Similarly, the reverse is also true; terms such as "signal line" and "power line" may be changed to the term "wiring." Terms such as "power line" may be changed to the term "signal line." Similarly, the reverse is also true; terms such as "signal line" may be changed to the term "power line." In addition, the term "potential" applied to the wiring may be changed to the term "signal," depending on the circumstances or situation. Similarly, the reverse is also true; terms such as "signal" may be changed to the term "potential."

[0037] In this specification, semiconductor impurities refer to elements other than the main components that make up the semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are impurities. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components. In particular, examples include hydrogen (which is also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that alter the properties of the semiconductor include, for example, Group 1 elements (excluding hydrogen), Group 2 elements, Group 13 elements, Group 15 elements, and oxygen.

[0038] In this specification, a switch refers to a device that has the function of controlling whether or not to allow current to flow by being in a conductive (on) state or a non-conductive (off) state. Alternatively, a switch refers to a device that has the function of selecting and switching the path through which current flows. Examples include electrical switches and mechanical switches. In other words, a switch is not limited to any particular type, as long as it can control current.

[0039] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), or logic circuits combining these. When a transistor is used as a switch, the "conducting state" of the transistor refers to a state in which the source and drain electrodes of the transistor can be considered to be electrically short-circuited. Conversely, the "non-conducting state" of the transistor refers to a state in which the source and drain electrodes of the transistor can be considered to be electrically disconnected. When a transistor is used simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0040] One example of a mechanical switch is a switch using MEMS (Micro-Electro-Mechanical Systems) technology. This switch has mechanically movable electrodes, and it operates by controlling the conduction and non-conductivity through the movement of these electrodes.

[0041] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Furthermore, "approximately parallel" or "roughly parallel" means a state in which two lines are positioned at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Furthermore, "approximately perpendicular" or "roughly perpendicular" means a state in which two lines are positioned at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0042] According to one aspect of the present invention, a semiconductor device capable of high-speed data transmission can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with reduced circuit area can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with reduced manufacturing cost can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device can be provided.

[0043] The effects of one aspect of the present invention are not limited to those listed above. The effects listed above do not preclude the existence of other effects. These other effects are those described below and not mentioned in this section. Those not mentioned in this section can be derived from the description in the specification or drawings, etc., by those skilled in the art, and can be appropriately extracted from these descriptions. One aspect of the present invention has at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may, in some cases, not have the effects listed above. [Brief explanation of the drawing]

[0044] [Figure 1] Figure 1 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 2] Figures 2A and 2B are block diagrams showing examples of semiconductor device configurations. [Figure 3] Figures 3A to 3C are circuit diagrams showing an example of a circuit included in a semiconductor device. [Figure 4] Figures 4A to 4C are circuit diagrams showing an example of a circuit included in a semiconductor device. [Figure 5] Figures 5A to 5D are circuit diagrams showing examples of circuits included in semiconductor devices. [Figure 6] Figures 6A to 6E are schematic cross-sectional diagrams illustrating an example of a semiconductor device fabrication method. [Figure 7] Figures 7A to 7E are schematic cross-sectional diagrams illustrating an example of a semiconductor device fabrication method. [Figure 8] Figures 8A to 8E are schematic cross-sectional diagrams illustrating an example of a semiconductor device fabrication method. [Figure 9] Figure 9 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 10] Figure 10 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 11] Figures 11A to 11C are schematic cross-sectional diagrams showing examples of transistor configurations. [Figure 12] Figure 12 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 13] Figure 13A illustrates the classification of IGZO crystal structures, Figure 13B illustrates the XRD spectrum of crystalline IGZO, and Figure 13C illustrates the micro-electron diffraction pattern of crystalline IGZO. [Figure 14] Figure 14A is a perspective view showing an example of a semiconductor wafer, Figure 14B is a perspective view showing an example of a die, Figures 14C and 14D are perspective views showing an example of a semiconductor device, and Figure 14E is a perspective view showing an example of a mounting substrate. [Figure 15] Figure 15 is a perspective view showing an example of an electronic device. [Modes for carrying out the invention]

[0045] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, if a metal oxide can constitute a channel-forming region of a transistor having at least one of amplification, rectification, and switching functions, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0046] Furthermore, in this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Alternatively, metal oxides containing nitrogen may be called metal oxynitrides.

[0047] Furthermore, in this specification, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Also, if multiple configuration examples are shown within one embodiment, these configuration examples can be appropriately combined with each other.

[0048] Furthermore, any content described in one embodiment (even partial content) may be applied to, combined with, or substituted for at least one of the contents described in another embodiment (even partial content) and one or more other embodiments (even partial content).

[0049] The content described in the embodiments refers to the content described using various figures or the content described using text in the specification in each embodiment.

[0050] Furthermore, a diagram (even a part of it) described in one embodiment can be combined with another part of that diagram, another diagram (even a part of it) described in the same embodiment, and at least one diagram (even a part of it) described in one or more other embodiments to form even more diagrams.

[0051] The embodiments described herein will be explained with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention is not to be interpreted as being limited to the contents of the embodiments. In the configuration of the invention in the embodiments, the same reference numerals are used in common across different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. Also, in perspective views and the like, some components may be omitted in order to ensure clarity of the drawings.

[0052] In this specification, when the same symbol is used for multiple elements, and especially when it is necessary to distinguish them, an identifying symbol such as "_1", "[n]", or "[m,n]" may be added to the symbol.

[0053] Furthermore, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0054] (Embodiment 1) This embodiment describes a semiconductor device according to one aspect of the present invention.

[0055] <Example of semiconductor device configuration> Figure 1 shows an example of a cross-sectional view of a semiconductor device with a FOWLP (Fan Out Wafer Level Package) configuration. The semiconductor device PSD, as an example, includes a die SCD, an OSL layer, an PR insulator, and a HBL bump. The die SCD also includes a BSA substrate, a SIL layer, and a ET connector.

[0056] The die SCD can be a semiconductor chip cut from a semiconductor wafer, as described in Embodiment 4 below. In this embodiment, the layer SIL in the die SCD is formed on the substrate BSA. The layer SIL may have, for example, switching circuits, logic circuits, analog circuits, etc. Analog circuits may include, for example, signal conversion circuits, potential level conversion circuits, and amplification circuits. The layer SIL may also include memory devices, arithmetic circuits, etc.

[0057] The substrate BSA can be, for example, a semiconductor substrate made of silicon. Furthermore, by using a silicon semiconductor substrate for the substrate BSA, transistors containing silicon in the channel formation region (hereinafter referred to as Si transistors) can be formed on the substrate BSA, and switching circuits, logic circuits, analog circuits, etc., contained in the SIL layer can be constructed using Si transistors.

[0058] Furthermore, the substrate BSA may be, for example, a semiconductor substrate made of germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. Alternatively, the substrate BSA may also be a semiconductor substrate having an insulating region within the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate.

[0059] Furthermore, an insulating substrate may be used as the substrate BSA. Examples of such insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Alternatively, a conductive substrate may be used as the substrate BSA. Examples of such conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. However, when an insulating substrate or a conductive substrate is used as the substrate BSA, unlike semiconductor substrates, it is not possible to form channel formation regions on the insulating substrate or conductive substrate. Therefore, in order to form a transistor on an insulating substrate or conductive substrate, it is necessary to provide a separate semiconductor film on top of the insulating substrate or conductive substrate.

[0060] The die SCD is provided such that the connection terminal ET contacts the layer OSL. The connection terminal ET functions as a terminal for electrically connecting the circuit contained in the die SCD with the wiring contained in the layer OSL.

[0061] Furthermore, a bump HBL is provided on the opposite side of the layer OSL from the side where the die SCD is located. The layer OSL is provided with wiring for electrically connecting the circuit contained in the die SCD to the bump HBL. Therefore, the layer OSL functions as a redistribution layer in FOWLP.

[0062] In Figure 1, a ball is shown as an example of a bump HBL. Bump HBLs can also be formed using solder. Thus, the semiconductor device PSD has BGA (Ball Grid Array) terminals. However, the terminals of a semiconductor device PSD are not limited to BGA. For example, a semiconductor device PSD may have terminals other than BGA, such as LGA (Land Grid Array) or PGA (Pin Grid Array).

[0063] Furthermore, by providing the bump HBL in a region that does not overlap with the die SCD of the layer OSL, the connection terminal ET can be extended to the outside of the die SCD. For this reason, it is preferable to provide the bump HBL in at least a region that does not overlap with the die SCD of the layer OSL, and in addition, it is preferable to provide it in a region that overlaps with the die SCD of the layer OSL. Also, by providing the bump HBL in a region that does not overlap with the die SCD of the layer OSL, the pitch width of the bump HBL can be made larger than the pitch width of the connection terminal ET of the die SCD.

[0064] Furthermore, a transistor OTr is provided in the OSL layer. For example, an OS transistor can be used as the OTr. The channel-forming region of the OS transistor is more preferably an oxide containing at least one of indium, gallium, and zinc. Alternatively, an oxide containing at least one of indium, element M (for example, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) and zinc may be used. The OS transistor is more preferably the transistor structure described in Embodiment 2.

[0065] Furthermore, by providing a transistor OTr in the redistribution layer OSL, a desired circuit can be configured in the redistribution layer. In other words, for example, the OSL layer may have a circuit that includes a transistor OTr.

[0066] In the semiconductor device PSD shown in Figure 1, the die SCD and the layer OSL are bonded together so that they are electrically connected to each other. Specifically, the electrical connection terminals contained in the die SCD and the electrical connection terminals contained in the layer OSL are bonded together so that they are in contact. Examples of electrical connection terminals here include conductors and wiring. The method of electrical connection between the circuit formed on the die SCD and the redistribution layer of the layer OSL will be described later.

[0067] Furthermore, an insulator PR is provided on the die SCD and the layer OSL as a sealing material. The insulator PR has the function of a protective layer to prevent electrostatic discharge damage to the die SCD and the function of a sealing material to prevent components from the outside environment from entering the die SCD.

[0068] As the insulator PR, for example, an organic resin layer such as epoxy resin can be used.

[0069] Here, as a specific example, the configuration of a circuit included in the semiconductor device PSD of Figure 1 is shown in the block diagram of Figure 2A. In the semiconductor device PSD of Figure 2A, as an example, layer SIL has a circuit SIC, and layer OSL has a circuit OSC. The circuit SIC or circuit OSC can be, for example, a switching circuit, a logic circuit, an analog circuit, etc. Also, in the semiconductor device PSD of Figure 2A, as an example, the circuit SIC is electrically connected to the circuit OSC, and the circuit OSC is electrically connected to the external terminal EXT1. Here, the external terminal EXT1 corresponds to, for example, the bump HBL shown in the semiconductor device PSD of Figure 1. Note that the circuit SIC may also be electrically connected to the external terminal EXT2 without going through the circuit OSC, as shown in Figure 2A. Here, the external terminal EXT2 corresponds to, for example, the bump HBL shown in the semiconductor device PSD of Figure 1, similar to the external terminal EXT1.

[0070] In particular, in the semiconductor device PSD shown in FIG. 2A, as the circuit OSC, for example, a CML (Current Mode Logic) circuit may be provided. The CML circuit is a signal transmission circuit using a small-amplitude differential transmission method using a differential amplifier circuit, and realizes high-speed signal transmission. Further, the CML circuit has a function as an output buffer circuit in high-speed data communication, and the level of the output signal via the CML circuit can be stabilized.

[0071] By providing a CML circuit in the layer OSL, signal transmission from the circuit SIC included in the layer SIL to the outside of the semiconductor device PSD1 and / or signal transmission from the outside of the semiconductor device PSD1 to the circuit SIC included in the layer SIL can be accelerated.

[0072] Incidentally, the semiconductor device of one aspect of the present invention is not limited to the configuration of the semiconductor device PSD shown in FIG. 2A. The semiconductor device of one aspect of the present invention may be, for example, configured as shown in the block diagram of FIG. 2B. The semiconductor device PSD of FIG. 2B has the same circuit configuration as the semiconductor device PSD of FIG. 2A in that the layer SIL has the circuit SIC and the layer OSL has the circuit OSC, but is different from the circuit configuration of the semiconductor device PSD of FIG. 2A in that the circuit DEV is configured by the circuit SIC and the circuit OSC. That is, the circuit OSC may be a part of the circuit that can configure the circuit DEV in combination with the circuit SIC included in the layer SIL. As the circuit DEV, for example, a storage device, an arithmetic circuit, or the like can be used. Further, as shown in FIG. 2B, similar to the semiconductor device PSD of FIG. 2A, the circuit SIC may be electrically connected to the external terminal EXT2 without passing through the circuit OSC.

[0073] <<Configuration Example of CML Circuit>> Here, a configuration example of the CML circuit that can be provided in the circuit OSC will be described.

[0074] [Oscillator] The circuit RGCM shown in Figure 3A is a CML circuit that functions as an oscillator and has differential amplifier circuits CM[1] to CM[n+1] (where n is an even number greater than or equal to 4).

[0075] Furthermore, the RGCM circuit has terminals OCLN and OCLP. Terminals OCLP and OCLN function as output terminals in the RGCM circuit.

[0076] The inverting output terminal of differential amplifier circuit CM[1] is electrically connected to the non-inverting input terminal of differential amplifier circuit CM[2], and the non-inverting output terminal of differential amplifier circuit CM[1] is electrically connected to the inverting input terminal of differential amplifier circuit CM[2]. Furthermore, the inverting output terminal of differential amplifier circuit CM[n-1] is electrically connected to the inverting input terminal of differential amplifier circuit CM[n], and the non-inverting output terminal of differential amplifier circuit CM[n-1] is electrically connected to the non-inverting input terminal of differential amplifier circuit CM[2]. In addition, the inverting output terminal of differential amplifier circuit CM[n] is electrically connected to the inverting input terminal of differential amplifier circuit CM[n+1] and the non-inverting input terminal of differential amplifier circuit CM1, and the non-inverting output terminal of differential amplifier circuit CM[n] is electrically connected to the non-inverting input terminal of differential amplifier circuit CM[n+1] and the inverting input terminal of differential amplifier circuit CM[1]. Furthermore, the inverting input terminal of the differential amplifier circuit CM[n+1] is electrically connected to terminal OCLN, and the non-inverting input terminal of the differential amplifier circuit CM[n+1] is electrically connected to terminal OCLP.

[0077] In other words, as shown in Figure 3A, an oscillator (ring oscillator) can be constructed by coupling differential amplifier circuits CM[1] to CM[n] in a ring shape. In this oscillator configuration, between adjacent differential amplifier circuits, the non-inverting output terminal of one is electrically connected to the non-inverting input terminal of the other, and the inverting output terminal of one is electrically connected to the inverting input terminal of the other. Between the remaining adjacent differential amplifier circuits, the non-inverting output terminal of the preceding differential amplifier circuit is electrically connected to the inverting input terminal of the succeeding differential amplifier circuit, and the inverting output terminal of the preceding differential amplifier circuit is electrically connected to the non-inverting input terminal of the succeeding differential amplifier circuit.

[0078] Note that while the circuit RGCM in Figure 3A includes the differential amplifier circuit CM[n+1], the circuit RGCM in Figure 3A may also be configured without the differential amplifier circuit CM[n+1]. For example, the circuit RGCM in Figure 3A may be configured by electrically connecting the inverting output terminal of the differential amplifier circuit CM[n] to terminal OCLN, and electrically connecting the non-inverting output terminal of the differential amplifier circuit CM[n] to terminal OCLP.

[0079] Differential amplifier circuits can operate at higher speeds compared to logic gates such as NAND gates, AND gates, and NOT gates (inverter circuits). Furthermore, differential amplifier circuits are highly resistant to power supply noise. Therefore, the RGCM circuit shown in Figure 3A can be used as an oscillator, for example, in high-frequency circuits.

[0080] In Figure 3A, the number of ring-shaped differential amplifier circuits is shown as an even number of 4 or more, but in some cases, it may be 2. Also, for example, if the number of ring-shaped differential amplifier circuits is an odd number of 3 or more, the configuration of the circuit RGCM shown in Figure 3B can be applied. The circuit RGCM in Figure 3B is also a CML circuit that functions as an oscillator and has differential amplifier circuits CM[1] to CM[m+1] (where m is an odd number of 3 or more).

[0081] Furthermore, although the circuit RGCM in Figure 3B shows a configuration that includes the differential amplifier circuit CM[m+1], the circuit RGCM in Figure 3B may also be configured without the differential amplifier circuit CM[m+1]. For example, the circuit RGCM in Figure 3B may be configured in which the inverting output terminal of the differential amplifier circuit CM[m] is electrically connected to terminal OCLN, and the non-inverting output terminal of the differential amplifier circuit CM[m] is electrically connected to terminal OCLP.

[0082] [High-speed transmission circuit] The circuit HSTC shown in Figure 3C is a CML circuit that functions as a high-speed transmission circuit and includes a differential amplifier circuit CMA, a differential amplifier circuit CMB, a capacitor C1P, a capacitor C1N, a load LE2P, and a load LE2N.

[0083] Furthermore, the HSTC circuit has terminals HIP, HIN, HON, and HOP. Terminals HIP and HIN function as input terminals in the HSTC circuit, while terminals HON and HOP function as output terminals in the HSTC circuit.

[0084] The non-inverting input terminal of the differential amplifier circuit CMA is electrically connected to terminal HIP, and the inverting input terminal of the differential amplifier circuit CMA is electrically connected to terminal HIN. The inverting output terminal of the differential amplifier circuit CMA is electrically connected to the first terminal of capacitor C1N, and the non-inverting output terminal of the differential amplifier circuit CMA is electrically connected to the first terminal of capacitor C1P. The second terminal of capacitor C1P is electrically connected to the first terminal of load LE2P and the non-inverting input terminal of the differential amplifier circuit CMB, and the second terminal of capacitor C1N is electrically connected to the first terminal of load LE2N and the inverting input terminal of the differential amplifier circuit CMB. The inverting output terminal of the differential amplifier circuit CMB is electrically connected to terminal HON, and the non-inverting output terminal of the differential amplifier circuit CMB is electrically connected to terminal HOP. The second terminal of load LE2P is electrically connected to wiring VBL1, and the second terminal of load LE2N is electrically connected to wiring VBL2.

[0085] Wiring VBL1 and wiring VBL2 function as wiring that provides a constant voltage. This constant voltage can be, for example, a positive potential, a negative potential, or a ground potential. Furthermore, the constant voltages provided by wiring VBL1 and wiring VBL2 may be equal to each other or may be different.

[0086] Capacitors C1P and C1N function as DC blocking capacitors for AC coupling between differential amplifier circuits CMA and CMB.

[0087] The HSTC circuit shown in Figure 3C has a faster edge rate compared to the LVDS (Low Voltage Differential Signaling) circuit, which is also a high-speed transmission circuit. Furthermore, the signal amplitude of the HSTC circuit can sometimes be higher than that of the LVDS circuit.

[0088] [Differential amplifier circuit] Next, we will describe differential amplifier circuits applicable to circuits RGCM and HSTC. Figure 4A shows an example configuration of a differential amplifier circuit applicable to differential amplifier circuits CM[1] to CM[n+1] included in circuit RGCM, and differential amplifier circuits CMA and CMB included in circuit HSTC. The differential amplifier circuit CM shown in Figure 4A, as an example, has transistor DTrA, transistor DTrB, load LE1A, load LE1B, and current source CC. The differential amplifier circuit CM also has terminals INP, INN, OUTP, and OUTN. In particular, transistors DTrA and DTrB function as a differential pair with respect to each other.

[0089] In the differential amplifier circuit CM, terminal INP corresponds to the non-inverting input terminal, terminal INN corresponds to the inverting input terminal, terminal OUTP corresponds to the non-inverting output terminal, and terminal OUTN corresponds to the inverting output terminal.

[0090] Transistor DTrA and / or transistor DTrB are provided, for example, as the transistor OTr described above.

[0091] Furthermore, although transistors DTrA and DTrB shown in Figure 4A have back gates, the semiconductor device according to one embodiment of the present invention is not limited to this. For example, transistors DTrA and DTrB shown in Figure 4A may be configured without back gates, that is, single-gate transistors. Alternatively, some transistors may have back gates, while others may not.

[0092] Furthermore, it is preferable that the sizes of transistors DTrA and DTrB (e.g., channel length, channel width, transistor configuration, etc.) are equal to each other. By making the sizes of the transistors equal, the electrical characteristics of each transistor can be made approximately equal. Therefore, by making the sizes of transistors DTrA and DTrB equal, each of transistors DTrA and DTrB can perform approximately the same operation under identical conditions. Here, identical conditions refer to, for example, the potentials of the source, drain, and gate of transistor DTrA, and the potentials of the source, drain, and gate of transistor DTrB.

[0093] Unless otherwise specified, transistors DTrA and DTrB, when in the ON state, are assumed to operate in the saturation region. That is, the gate voltage, source voltage, and drain voltage of each of the transistors described above are assumed to be appropriately biased to voltages within the range in which they operate in the saturation region. However, one aspect of the present invention is not limited thereto. For example, transistors DTrA and DTrB may operate in the linear region when in the ON state, or they may operate in a mixture of the saturation region and the linear region.

[0094] The gate of transistor DTrA is electrically connected to terminal INP, and the first terminal of transistor DTrA is electrically connected to the first terminal of load LE1A and terminal OUTP. The gate of transistor DTrB is electrically connected to terminal INN, and the first terminal of transistor DTrB is electrically connected to the first terminal of load LE1B and terminal OUTN. The input terminal of current source CC is electrically connected to the second terminal of transistor DTrA and the second terminal of transistor DTrB, and the output terminal of current source CC is electrically connected to wiring VSE. The second terminal of load LE1A and the second terminal of load LE1B are electrically connected to wiring VDE.

[0095] Wiring VDE functions, for example, as wiring that provides a constant voltage. This constant voltage can be, for example, a high-level potential.

[0096] As a wiring VSE, it functions, for example, as wiring that provides a constant voltage. This constant voltage can be, for example, a low-level potential or ground potential (GND).

[0097] In Figure 4A, back gates are shown for transistors DTrA and / or DTrB. Although the connection configuration of these back gates is not shown, the electrical connection destination of the back gates can be determined at the design stage. For example, in a transistor with a back gate, the gate and back gate may be electrically connected to increase the on-current of the transistor. That is, for example, the gate and back gate of transistor DTrA may be electrically connected, or the gate and back gate of transistor DTrB may be electrically connected. Alternatively, for example, in a transistor with a back gate, wiring may be provided to electrically connect the back gate of the transistor to an external circuit, etc., in order to vary the threshold voltage of the transistor or to reduce the off-current of the transistor, thereby providing a potential to the back gate of the transistor via the external circuit, etc. Specifically, the differential amplifier circuit CM can have the configuration shown in Figure 4B. In the differential amplifier circuit CM of Figure 4B, wiring BGE1 is electrically connected to the back gates of transistors DTrA and DTrB, which are included in the differential amplifier circuit CM of Figure 4A. By applying a predetermined potential to the wiring BGE1, the threshold voltages of transistors DTrA and DTrB can be varied.

[0098] Furthermore, in the differential amplifier circuit CM shown in Figure 4B, the desired gain can be obtained by varying the threshold voltages of transistors DTrA and DTrB. In addition, as shown in Figure 1 and other figures, the threshold voltages of transistors DTrA and DTrB can be adjusted in the packaged semiconductor device PSD.

[0099] Furthermore, although transistors DTrA and DTrB shown in Figure 4A are n-channel transistors, the semiconductor device according to one embodiment of the present invention is not limited to this. For example, some or all of transistors DTrA and DTrB may be replaced with p-channel transistors.

[0100] The above examples of changes to the structure and polarity of transistors are not limited to transistors DTrA and DTrB. For example, similar changes may be made to the structure and polarity of transistors described elsewhere in the specification or illustrated in other drawings.

[0101] The current source CC included in the differential amplifier circuit CM in Figure 4A can be configured as shown in the circuit shown in Figure 4C, for example. Figure 4C also shows the wiring VSE to illustrate the connection configuration of the current source CC.

[0102] The current source CC shown in Figure 4C includes, as an example, a transistor TrC.

[0103] Transistor TrC can be any transistor applicable to transistor DTrA or transistor DTrB. For example, transistor TrC can be an OS transistor applicable to transistors DTrA and DTrB.

[0104] Unless otherwise specified, transistor TrC includes cases where it ultimately operates in the saturation region when it is ON. That is, the gate voltage, source voltage, and drain voltage of each transistor described above include cases where they are appropriately biased to voltages within the range in which they operate in the saturation region. For example, transistor TrC may operate in the linear region when it is ON, or it may operate in a mixture of the saturation region and the linear region.

[0105] The first terminal of transistor TrC is electrically connected to the input terminal of current source CC, and the second terminal of transistor TrC is electrically connected to the output terminal of current source CC. In other words, when current source CC in Figure 4C is applied to the differential amplifier circuit CM in Figure 4A, the first terminal of transistor TrC is electrically connected to the second terminal of transistor DTrA and the second terminal of transistor DTrB. Also, the gate of transistor TrC is electrically connected to wiring VAL.

[0106] The wiring VAL functions, for example, as wiring that provides a constant voltage. In particular, this constant voltage should be set so that the gate-source voltage of transistor TrC is higher than the threshold voltage of transistor TrC.

[0107] Loads LE1A and LE1B can be, for example, resistors, diodes, and the like.

[0108] As an example, Figure 5A shows the circuit configuration when loads LE1A and LE1B are resistors. The differential amplifier circuit CM1 shown in Figure 5A has a circuit configuration in which resistors REA and REB are used as loads LE1A and LE1B, respectively. The first terminal of resistor REA is electrically connected to the first terminal of transistor DTrA and terminal OUTP, and the first terminal of resistor REB is electrically connected to the first terminal of transistor DTrB and terminal OUTN. In addition, the second terminal of resistor REA and the second terminal of resistor REB are electrically connected to wiring VDE.

[0109] As an example, Figure 5B shows the circuit configuration when loads LE1A and LE1B are diodes. The differential amplifier circuit CM2 shown in Figure 5B has a circuit configuration in which diodes DEA and DEB are used as loads LE1A and LE1B, respectively. The output terminal of diode DEA is electrically connected to the first terminal of transistor DTrA and terminal OUTP, and the output terminal of diode DEB is electrically connected to the first terminal of transistor DTrB and terminal OUTN. In addition, the input terminals of diode DEA and diode DEB are electrically connected to wiring VDE.

[0110] Furthermore, diodes DEA and DEB included in the differential amplifier circuit CM2 shown in Figure 5B may be replaced with diode-connected transistors. The differential amplifier circuit CM2 shown in Figure 5C has a circuit configuration in which transistors ITrA and ITrB are used as diodes DEA and DEB, respectively. The first terminal of transistor ITrA is electrically connected to the first terminal of transistor DTrA and terminal OUTP, and the first terminal of transistor ITrB is electrically connected to the first terminal of transistor DTrB and terminal OUTN. In addition, the wiring VDE is electrically connected to the second terminal of transistor ITrA, the gate of transistor ITrA, the second terminal of transistor ITrB, and the gate of transistor ITrB.

[0111] Transistors ITrA and ITrB can be replaced with transistors applicable to transistor DTrA or transistor DTrB. For example, transistor TrC can be replaced with an OS transistor.

[0112] Furthermore, as shown in Figure 5C, transistors ITrA and ITrB may be transistors having back gates, similar to transistor DTrA or transistor DTrB. Also, similar to transistors DTrA and DTrB in the differential amplifier circuit CM of Figure 4B, wiring that provides potential to the back gates of transistors ITrA and ITrB may be electrically connected. Specifically, for example, the differential amplifier circuit CM2 of Figure 5C may be configured such that wiring BGE2 is electrically connected to the back gates of transistors ITrA and ITrB, as shown in the differential amplifier circuit CM2 of Figure 5D. In Figure 5D, the threshold voltages of transistors ITrA and ITrB can be varied by applying a predetermined potential to wiring BGE2. Note that the differential amplifier circuit CM2 of Figure 5D is configured such that wiring BGE1 is electrically connected to the back gates of transistors DTrA and DTrB, similar to the configuration of the differential amplifier circuit CM of Figure 4B.

[0113] Furthermore, in the differential amplifier circuit CM shown in Figure 5D, the desired gain can be obtained by varying the threshold voltages of transistors DTrA, DTrB, ITrA, and ITrB. Also, as shown in Figure 1, the threshold voltages of transistors DTrA, DTrB, ITrA, and ITrB can be adjusted in the packaged semiconductor device PSD.

[0114] <Example of semiconductor device fabrication 1> Next, we will explain an example of a method for fabricating a semiconductor device PSD.

[0115] Figures 6A to 6D are schematic cross-sectional views of the semiconductor device PSD1 during the manufacturing process, and Figure 6E is a schematic cross-sectional view of the semiconductor device PSD1 after the manufacturing process is completed. This manufacturing method comprises steps 1 to 5.

[0116] <<Step 1>> First, a die SCD is prepared. A die SCD can be obtained, for example, through semiconductor processes such as forming circuits on a wafer, wafer polishing, and dicing.

[0117] In the die SCD shown in Figures 6A to 6E, the layer SIL is provided with an electrical connection terminal ET.

[0118] Next, the die SCD is attached and fixed onto the support SB having a release layer RL (see Figure 6A). Specifically, the layer SIL and connection terminal ET of the die SCD are bonded together so that they are in contact with the release layer RL of the support SB.

[0119] Examples of support substrates (SBs) include semiconductor substrates (e.g., single crystal substrates or silicon substrates), SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates with stainless steel foil, tungsten substrates, substrates with tungsten foil, flexible substrates, laminated films, paper containing fibrous materials, or base film. Examples of glass substrates include barium borosilicate glass, aluminoborsilicate glass, or soda-lime glass. Examples of flexible substrates, laminated films, and base film include the following: For example, plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Alternatively, synthetic resins such as acrylic are also used. Alternatively, polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride are also used. Alternatively, examples include polyamides, polyimides, aramids, epoxy resins, inorganic vapor-deposited films, or papers.

[0120] Furthermore, the release layer RL can be, for example, a laminated film having a tungsten film and a silicon oxide film, or an organic resin film such as polyimide. Alternatively, the release layer RL may be a tape whose adhesive strength decreases when exposed to light such as ultraviolet light.

[0121] <<Step 2>> Next, the insulator PR is molded onto the die SCD and the release layer RL (see Figure 6B).

[0122] Specifically, for example, the aforementioned organic resin is used as the material for the insulator PR, and the insulator PR is molded using a mold or the like.

[0123] <<Step 3>> Next, the die SCD and the molded insulator PR are peeled off from the support SB and the release layer RL (see Figure 6C). It is preferable that this step exposes the connection terminal ET of the die SCD. Alternatively, after peeling off the support SB and the release layer RL, surface polishing or removal of organic matter by ultraviolet irradiation in an ozone atmosphere may be performed.

[0124] <<Step 4>> Next, a layer OSL is formed on the die SCD and the insulator PR (see Figure 6D).

[0125] Note that the die SCD and insulator PR shown in Figure 6D are the same as the die SCD and insulator PR shown in Figure 6C, rotated 180 degrees.

[0126] Layer OSL can be formed, for example, by semiconductor processes. In particular, during the layer OSL formation process, wiring, terminals, pads, etc. (not shown) are formed on the connection terminals ET included in the die SCD. Furthermore, on the side of the layer OSL opposite to where the die SCD is located, wiring, terminals, pads, etc. (not shown) are formed to be exposed.

[0127] Furthermore, this semiconductor process allows for the formation of transistors (OTr) in the OSL layer.

[0128] By forming a layer OSL, the layer OSL can be provided with wiring that is electrically connected to the connection terminal ET of the die SCD, and a transistor OTr.

[0129] <<Step 5>> Next, bump HBLs are formed on the wiring, terminals, pads, etc. of the layer OSL that are exposed on the side opposite to the side where the die SCD is located (see Figure 6E). The bump HBLs are provided to be electrically connected to the wiring included in the layer OSL.

[0130] The bump HBL may also be formed using solder or the like.

[0131] By performing the manufacturing process described in steps 1 through 5 above, a semiconductor device with a FOWLP configuration can be manufactured.

[0132] <Example of semiconductor device fabrication 2> This section describes an example of a method for manufacturing a semiconductor device with a configuration different from the semiconductor device PSD shown in Figure 1.

[0133] Figures 7A to 7D are schematic cross-sectional views of the semiconductor device PSD2 during the manufacturing process, and Figure 7E is a schematic cross-sectional view of the semiconductor device PSD2 after the manufacturing process is completed. This manufacturing method comprises steps 1 to 5.

[0134] <<Step 1>> First, prepare the die SCD. Refer to the description of the die SCD explained in Semiconductor Device Fabrication Example 1.

[0135] Next, the die SCD is attached and fixed onto the substrate BSB (see Figure 7A). Specifically, the substrate BSA of the die SCD and the substrate BSB are bonded together so that they are in contact with each other.

[0136] As the substrate BSB, for example, semiconductor substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates with stainless steel foil, tungsten substrates, and substrates with tungsten foil can be used. In particular, if the die SCD and the substrate BSB are subjected to heat treatment in the second step and beyond, it is preferable that the substrate BSB is a heat-resistant substrate.

[0137] Furthermore, a die bonding film or the like can be used to bond the die SCD and the substrate BSB (not shown in Figures 7A to 7E).

[0138] <<Step 2>> Next, an insulator PR is formed on the die SCD and the substrate BSB (see Figure 7B).

[0139] Specifically, for example, the aforementioned organic resin is used as the material for the insulator PR, and the insulator PR is molded using a mold or the like.

[0140] <<Step 3>> Next, the upper part of the molded insulator PR is removed until the connection terminal ET of the die SCD is exposed (see Figure 7C). Methods for removing the upper part of the insulator PR include polishing, etching, and ashing. Alternatively, after polishing, etching, or ashing, any organic matter (sometimes called organic residue) such as residual chemicals or residual insulator PR that may have unintentionally adhered to the treated surface may be removed (e.g., by a cleaning process involving ultraviolet irradiation under an ozone atmosphere).

[0141] <<Step 4>> Next, a layer OSL is formed on the die SCD and the insulator PR (see Figure 7D).

[0142] For the formation of the OSL layer, refer to the description of step 4 explained in Semiconductor Device Fabrication Example 1.

[0143] By forming a layer OSL, the layer OSL can be provided with wiring that is electrically connected to the connection terminal ET of the die SCD, and a transistor OTr.

[0144] <<Step 5>> Next, bump HBLs are formed on the wiring, terminals, pads, etc. of the layer OSL (not shown in Figures 7A to 7E) that are exposed on the side of the layer OSL opposite to the side where the die SCD is located (see Figure 7E).

[0145] For the formation of bump HBLs, refer to the description of step 5 explained in Semiconductor Device Fabrication Example 1.

[0146] By following the manufacturing process described in steps 1 through 5 above, a semiconductor device with a FOWLP configuration different from the semiconductor device PSD in Figure 1 (semiconductor device PSD1 in Figure 6E) can be manufactured.

[0147] <Example of semiconductor device fabrication 3> Next, we will describe an example of a semiconductor device PSD manufacturing method that differs from the manufacturing process shown in Figures 6A to 6E and Figures 7A to 7E.

[0148] Figures 8A to 8D are schematic cross-sectional views of the semiconductor device PSD3 during the manufacturing process, and Figure 8E is a schematic cross-sectional view of the semiconductor device PSD3 after the manufacturing process is completed. This manufacturing method comprises steps 1 to 5.

[0149] <<Step 1>> First, prepare a support SB having a release layer RL. The description of the release layer RL or support SB in Semiconductor Device Fabrication Example 1 should be considered.

[0150] Next, a layer OSL is formed on the release layer RL (see Figure 8A). The layer OSL can be formed by a semiconductor process, similar to the semiconductor device fabrication examples 1 and 2 described above. In particular, during the layer OSL formation process, wiring, terminals, pads, etc. (not shown) for electrically connecting to the bump HBL described later are formed on the side where the release layer RL is provided, and wiring, terminals, pads, etc. (not shown) for electrically connecting to the die SCD described later are formed on the opposite side where the release layer RL is provided. Also, a transistor OTr can be formed on the layer OSL, similar to the semiconductor device fabrication examples 1 and 2 described above.

[0151] This allows for the formation of wiring and transistors OTr in the OSL layer.

[0152] <<Step 2>> Next, prepare the die SCD. For details on the die SCD, refer to the description of the die SCD explained in Semiconductor Device Fabrication Example 1.

[0153] Next, the die SCD is mounted on the layer OSL by flip-chip bonding (see Figure 8B). Specifically, the connection terminals ET on the die SCD are electrically connected to the wiring, terminals, pads, etc. exposed on the upper surface of the layer OSL using solder or the like. In Figure 8B, a bump BP is formed so as to be in contact with the connection terminals ET on the die SCD.

[0154] Examples of flip-chip bonding methods include injecting a resin containing anisotropic conductive particles between the OSL layer and the SCD die for bonding, or using SnAg solder for bonding. Alternatively, if both the bumps and the conductors connected to the bumps are made of gold, ultrasonic bonding can be used. Furthermore, in order to reduce physical stress such as impact and thermal stress, an underfill material may be injected between the OSL layer and the SCD die in addition to the above-mentioned flip-chip bonding methods.

[0155] Figure 8B shows an example configuration in which the layer OSL and the die SCD are bonded together with insulating resin IJ. The insulating resin IJ can be, for example, a resin containing anisotropic conductive particles or an underfill material. Depending on the bonding method between the layer OSL and the die SCD, it may not be necessary to inject insulating resin IJ.

[0156] <<Step 3>> Next, an insulator PR is formed on the layer OSL and on the die SCD (see Figure 8C).

[0157] Specifically, for example, the aforementioned organic resin is used as the material for the insulator PR, and the insulator PR is molded using a mold or the like.

[0158] <<Step 4>> Next, the OSL layer, die SCD, and insulator PR are peeled off from the support SB and release layer RL (see Figure 8D). This step preferably exposes the wiring, terminals, pads, etc. (not shown in Figures 8A to 8E) of the OSL layer on the side opposite to the side where the die SCD is located. Alternatively, after peeling off the support SB and release layer RL, surface polishing or removal of organic matter by ultraviolet irradiation in an ozone atmosphere may be performed.

[0159] <<Step 5>> Next, bump HBLs are formed on the wiring, terminals, pads, etc. of the layer OSL that are exposed on the opposite side of the surface where the die SCD is located (see Figure 8E).

[0160] Note that the layer OSL, die SCD, and insulator PR shown in Figure 8E are the same as the die SCD and insulator PR shown in Figure 8D, rotated 180 degrees.

[0161] For the formation of bump HBLs, refer to the description of step 5 explained in Semiconductor Device Fabrication Example 1.

[0162] By performing the manufacturing process described in steps 1 through 5 above, it is possible to manufacture a semiconductor device with a FOWLP configuration that differs from the semiconductor device PSD in Figure 1 (semiconductor device PSD1 in Figure 6E) and the semiconductor device PSD2 in Figure 7E.

[0163] When constructing a semiconductor device using FOWLP, it is difficult to form bipolar transistors or MOS transistors in the FOWLP redistribution layer (corresponding to the OSL layer in Figure 1). For example, it is difficult to provide CML circuits using bipolar transistors or CML circuits using MOS transistors in the FOWLP redistribution layer. On the other hand, OS transistors can be formed in the redistribution layer of a FOWLP semiconductor device, and as mentioned above, circuits using OS transistors can be provided in the redistribution layer of a FOWLP semiconductor device. Therefore, for example, by changing the arrangement of a circuit conventionally formed on a die to a circuit using OS transistors in the redistribution layer of a FOWLP semiconductor device, the mounting area on the die's redistribution layer can be reduced, and the die cost can be reduced.

[0164] In particular, since a CML circuit using an OS transistor can be provided in the redistribution layer of the FOWLP, a semiconductor device composed of FOWLP can perform high-speed data transmission at its input and output.

[0165] In this embodiment, a semiconductor device of type FOWLP, which is a package in which the pitch of the die's connection terminals is widened to exceed the area of ​​the die by a redistribution layer, has been described. However, the present invention is not limited to this. For example, one embodiment of the present invention may be a semiconductor device PSD4 in the form of a wafer-level chip-size package (sometimes called WLCSP or FIWLP (Fan In Wafer Level Package)) as shown in Figure 9. The semiconductor device PSD4 has a configuration in which the connection terminal ET of the die SCD is electrically connected to the bump HBL via a layer OSL corresponding to the redistribution layer. Similar to the layer OSL of the semiconductor device PSD in Figure 1, a circuit using an OS transistor may be provided in the layer OSL of the semiconductor device PSD4 in Figure 9. Alternatively, this circuit may be a CML circuit. As for the method of manufacturing the semiconductor device PSD4, the layer OSL and bump HBL may be formed on the semiconductor wafer before cutting out the die SCD, and then the semiconductor wafer may be cut to a predetermined size. Alternatively, as a method for fabricating the semiconductor device PSD4, layer OSL may be formed on a semiconductor wafer, the semiconductor wafer may be cut to a predetermined size, and then bump HBL may be formed.

[0166] Furthermore, although this embodiment describes a FOWLP semiconductor device using a die with connection terminals on the surface facing the semiconductor substrate, the present invention is not limited to this. For example, one embodiment of the present invention may be a semiconductor device configured such that connection terminals are provided on the semiconductor substrate side of the die using TSV (Through Silicon Via), so that the semiconductor substrate and the redistribution layer face each other.

[0167] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0168] (Embodiment 2) This embodiment describes an example of the configuration of a semiconductor device according to one aspect of the present invention.

[0169] <Example 1 of semiconductor device configuration> Figure 10 is a schematic cross-sectional view showing an example configuration of the semiconductor device PSD1 described in Embodiment 1. Specifically, the semiconductor device PSD1 shown in Figure 10 includes, as an example, a transistor 300 and a transistor 500. Figure 11A shows a cross-sectional view of transistor 500 in the channel length direction, Figure 11B shows a cross-sectional view of transistor 500 in the channel width direction, and Figure 11C shows a cross-sectional view of transistor 300 in the channel width direction.

[0170] Transistor 500 is an OS transistor (OS transistor) having a metal oxide in its channel formation region. Transistor 500 has a low off-current and its field-effect mobility does not change even at high temperatures. By applying transistor 500 to a transistor included in, for example, the semiconductor device PSD1 described in the above embodiment, a semiconductor device can be realized that does not experience a decrease in operating capability even at high temperatures. In particular, because OS transistors have a low off-current, by applying an OS transistor as a transistor included in a memory cell, it is possible to prevent the degradation of the potential held in the memory cell due to the current mediated by the transistor. In other words, the potential held in the memory cell can be stored for a long time.

[0171] The transistor 300 has a conductor 316, an element isolation layer 312, an insulator 315, a semiconductor region 313 consisting of a part of the substrate 310, a low-resistance region 314a that functions as a source region or drain region, and a low-resistance region 314b. The transistor 300 can be applied, for example, to a transistor included in the layer SIL described in the above embodiment.

[0172] Furthermore, the substrate BSA included in the die SCD described in the above embodiment corresponds to the substrate 310 shown in Figure 10. Also, the layer OSL is provided above the die SCD. Therefore, in Figure 10, the semiconductor device PSD1 has a configuration in which transistor 500 is provided above transistor 300.

[0173] As shown in Figure 11C, the transistor 300 has its semiconductor region 313's top surface and side surface in the channel width direction covered by a conductor 316 via an insulator 315. By making the transistor 300 a Fin type in this way, the effective channel width can be increased, thereby improving the on-characteristics of the transistor 300. In addition, the contribution of the gate electrode's electric field can be increased, thus improving the off-characteristics of the transistor 300.

[0174] Note that transistor 300 can be either a p-channel or n-channel type.

[0175] In the low-resistance region 314a and low-resistance region 314b, which are the channel-forming region of the semiconductor region 313, the region near it, the source region, or the drain region, it is preferable that a semiconductor such as a silicon-based semiconductor is included, and it is preferable that single-crystal silicon is included. Alternatively, it may be formed from a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), etc. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing is also possible. Alternatively, the transistor 300 may be made into a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, etc.

[0176] The low-resistance region 314a and the low-resistance region 314b include, in addition to the semiconductor material applied to the semiconductor region 313, elements that impart n-type conductivity, such as arsenic and phosphorus, or elements that impart p-type conductivity, such as boron.

[0177] The conductor 316, which functions as the gate electrode, can be made of a conductive material such as silicon, a semiconductor material, a metallic material, an alloy material, or a metal oxide material, which contains an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.

[0178] Furthermore, since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride or tantalum nitride as the conductor. In addition, in order to achieve both conductivity and embedding properties, it is preferable to use a laminate of metal materials such as tungsten or aluminum as the conductor, and tungsten is particularly preferable in terms of heat resistance.

[0179] The element isolation layer 312 is provided to separate multiple transistors formed on the substrate 310. The element isolation layer 312 can be formed using methods such as LOCOS (LOCal Oxidation of Silicon), STI (Shallow Trench Isolation), or mesa isolation.

[0180] Note that the transistor 300 shown in Figures 10 and 11C is just an example, and its structure is not limited to this example. Any suitable transistor can be used depending on the circuit configuration, driving method, etc. For example, the transistor 300 shown in Figures 10 and 11C may be a planar type transistor.

[0181] <<Example of Die SCD Configuration>> Next, we will explain an example of a die SCD configuration.

[0182] The transistor 300 shown in Figure 10 has insulators 320, 322, 324, and 326 stacked in order from the substrate 310 side.

[0183] For insulators 320, 322, 324, and 326, for example, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, aluminum nitride, etc. may be used.

[0184] In this specification, silicon oxidizide refers to a material in which the oxygen content is greater than the nitrogen content, and silicon nitride refers to a material in which the nitrogen content is greater than the oxygen content. Furthermore, in this specification, aluminum oxidizide refers to a material in which the oxygen content is greater than the nitrogen content, and aluminum nitride refers to a material in which the nitrogen content is greater than the oxygen content.

[0185] The insulator 322 may also function as a planarizing film that flattens steps caused by the insulator 320 and the transistor 300 covered by the insulator 322. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment using chemical mechanical polishing (CMP) or the like to improve its flatness.

[0186] Furthermore, it is preferable to use a film for the insulator 324 that has barrier properties to prevent impurities such as water and hydrogen from diffusing from the substrate 310 or the transistor 300 to the region where the transistor 500 is provided.

[0187] As an example of a film having barrier properties against hydrogen, silicon nitride formed by the CVD method can be used. In this case, hydrogen may diffuse into a semiconductor element having an oxide semiconductor, such as transistor 500, which may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between transistor 500 and transistor 300. Specifically, a film that suppresses hydrogen diffusion is a film that has a low hydrogen desorption rate.

[0188] The amount of hydrogen desorption can be analyzed, for example, using a thermal desorption gas analysis (TDS) method. For example, in TDS analysis, the amount of hydrogen desorption from insulator 324, when the film surface temperature is in the range of 50°C to 500°C, is calculated as 10 × 10¹⁶ hydrogen atoms per unit area of ​​insulator 324. 15 atoms / cm 2 The following is preferably 5 × 10 15 atoms / cm 2 The following is acceptable.

[0189] Furthermore, it is preferable that the dielectric constant of the insulator 326 is lower than that of the insulator 324. For example, the relative permittivity of the insulator 326 is preferably less than 4, and more preferably less than 3. Also, for example, the relative permittivity of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, than that of the relative permittivity of the insulator 324. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced.

[0190] Furthermore, insulators 320, 322, 324, and 326 have conductors 328 and 330 embedded within them. Conductors 328 and 330 function as plugs or wiring. Conductors that function as plugs or wiring may be grouped together and assigned the same reference numeral. In this specification, the wiring and the plug connected to the wiring may be an integrated unit. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0191] The plugs and wiring (conductor 328, conductor 330, etc.) can be made of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials, which can be used in a single layer or in a laminated form. It is preferable to use high-melting-point materials such as tungsten or molybdenum that provide both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form them with low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce the wiring resistance.

[0192] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 10, insulators 350, 352, and 354 are sequentially stacked on the insulator 326 and the conductor 330. Furthermore, a conductor 356 is formed on insulators 350, 352, and 354. The conductor 356 functions, for example, as a plug for connecting to the transistor 300 or as wiring. The conductor 356 can be provided using the same material as the conductors 328 and 330.

[0193] For example, it is preferable that the insulator 350, like the insulator 324, is an insulator that has barrier properties against impurities such as water and hydrogen. Also, for insulators 352 and 354, it is preferable to use insulators with relatively low dielectric constants, like the insulator 326, in order to reduce parasitic capacitance that occurs between the wiring. Furthermore, it is preferable that the conductor 356 contains a conductor that has barrier properties against water and hydrogen. In particular, a conductor that has barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 350. With this configuration, transistor 300 and transistor 500 can be separated by the barrier layer, and the diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0194] For example, tantalum nitride may be used as the conductor that has barrier properties against hydrogen. Furthermore, by laminating tantalum nitride with highly conductive tungsten, it is possible to suppress the diffusion of hydrogen from the transistor 300 while maintaining conductivity as wiring. In this case, it is preferable that the tantalum nitride layer, which has barrier properties against hydrogen, is in contact with the insulator 350, which also has barrier properties against hydrogen.

[0195] Furthermore, insulators 360, 362, and 370 are stacked in order on insulator 354 and conductor 356.

[0196] It is preferable that the insulator 360, like the insulator 324, is an insulator that has barrier properties against impurities such as water and hydrogen. Therefore, as the insulator 360, for example, a material that can be used for the insulator 324 can be used.

[0197] The insulator 362 functions as an interlayer insulating film and a planarizing film. Furthermore, it is preferable to use an insulator 362 that has barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 362 can be made from a material that is applicable to the insulator 324.

[0198] As the insulator 370, it is preferable to use a film that has barrier properties to prevent the diffusion of impurities such as water and hydrogen, similar to the insulator 324. In other words, it is preferable to use a material for the insulator 370 that is applicable to the insulator 324. Alternatively, as the insulator 370, it is also possible to use an insulator with a relatively low dielectric constant, similar to the insulator 326, in order to reduce parasitic capacitance between the wires. In other words, it is also possible to use a material for the insulator 370 that is applicable to the insulator 326.

[0199] Furthermore, openings are formed in the regions of insulators 360, 362, and 370 that overlap with a portion of the conductor 356, and the conductor 366 is provided to fill these openings. The conductor 366 is also formed on insulator 362. Subsequently, the conductor 366 is patterned into the shapes of wiring, terminals, pads, etc., by etching or other processes.

[0200] Examples of materials that can be used as the conductor 366 include copper, aluminum, tin, zinc, tungsten, silver, platinum, and gold. Preferably, the conductor 366 is composed of the same components as the material used in the conductor 406 contained in the layer OSL described later.

[0201] Subsequently, planarization treatment is performed using chemical mechanical polishing (CMP) or the like to improve the flatness of the insulator 370 and the conductor 366. This allows the conductor 366 to be formed on the die SCD as wiring, terminals, pads, etc. Note that the conductor 366 in Figure 10 corresponds to the connection terminal ET of the die SCD of the semiconductor device PSD1 described in the above embodiment.

[0202] <<Example of Layered OSL Configuration>> Next, we will explain an example of a layered OSL configuration.

[0203] In the semiconductor device fabrication example 1 described in Embodiment 1, the semiconductor device PSD1 has a configuration in which a layer OSL is formed on a die SCD. Specifically, the connection terminals ET of the die SCD and the wiring included in the layer OSL are electrically connected. Therefore, a conductor 406 corresponding to the wiring, terminals, pads, etc. of the die SCD is formed on the conductor 366 of the die SCD. In addition, an insulator 402 is formed on the insulator 370 of the die SCD to separate the multiple wirings, terminals, pads, etc. of the die SCD.

[0204] Furthermore, in order to improve the flatness of the conductor 406 and the insulator 402, it is preferable to perform a planarization treatment on the conductor 406 and the insulator 402 using a chemical mechanical polishing method or the like.

[0205] For example, the conductor 406 can be any material that can be used for the conductor 366. Furthermore, as mentioned above, it is preferable to use the same material for the conductor 406 as for the conductor 366.

[0206] Furthermore, as the insulator 402, for example, a material applicable to the insulator 370 can be used.

[0207] In Figure 10, insulators 410, 412, and 414 are stacked in order on the insulator 402 and the conductor 406.

[0208] As the insulator 410, it is preferable to use a film that has barrier properties to prevent the diffusion of impurities such as water and hydrogen into the region where the transistor 500 is provided, similar to the insulator 324. In other words, it is preferable to use a material for the insulator 410 that is applicable to the insulator 324. This allows the die SCD and the transistor 500 to be separated by the barrier layer, and the diffusion of hydrogen from the die SCD to the transistor 500 can be suppressed.

[0209] For insulators 412 and 414, it is preferable to use insulators with a relatively low dielectric constant, similar to insulator 326, in order to reduce parasitic capacitance between the wires. In other words, it is preferable to use materials for insulators 412 and 414 that are applicable to insulator 326.

[0210] Furthermore, wiring layers may be provided in insulators 410, 412, and 414. For example, in Figure 10, conductors 416, which function as wiring, are embedded in insulators 410, 412, and 414. In this case, conductor 416 functions as wiring connecting conductor 497, transistor 300, transistor 500, etc., which will be described later. Therefore, conductor 416 is formed to be in contact with conductor 406. Also, as conductor 416, materials applicable to conductors 328, conductor 330, etc., can be used.

[0211] Furthermore, wiring layers may also be provided on the insulator 414 and the conductor 416. For example, in Figure 10, insulators 420, 422, and 424 are sequentially stacked on insulators 414 and conductor 416. Conductors 426 are formed on insulators 420, 422, and 424. Conductors 426 function as plugs or wiring for connecting, for example, conductor 497, transistor 300, transistor 500, etc., which will be described later. Therefore, conductor 426 is formed to be in contact with conductor 416. Conductors 426 can be provided using the same material as conductors 328 and 330.

[0212] As the insulator 420, it is preferable to use an insulator that has barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Furthermore, as the insulators 422 and 424, it is preferable to use insulators with relatively low dielectric constants, similar to the insulator 326, in order to reduce parasitic capacitance that occurs between the wiring. Furthermore, as the conductor 426, it is preferable to include a conductor that has barrier properties against impurities such as water and hydrogen, similar to the conductor 356. As a result, a conductor that has barrier properties against impurities such as water and hydrogen is formed in the openings of the insulator 420 that has barrier properties against impurities such as water and hydrogen.

[0213] Furthermore, additional wiring layers may be provided on the insulator 424 and the conductor 426. For example, in Figure 10, insulators 430, 432, and 434 are sequentially stacked on insulators 424 and conductor 426. Conductors 436 are formed on insulators 430, 432, and 434. Conductors 436 function as plugs or wiring for connecting, for example, conductor 497, transistor 300, transistor 500, etc., which will be described later. Therefore, conductor 436 is formed to be in contact with conductor 426. Conductors 436 can be provided using the same material as conductors 328 and 330.

[0214] As the insulator 430, it is preferable to use an insulator that has barrier properties against impurities such as water and hydrogen, similar to insulators 324 and 420. Furthermore, as the insulators 432 and 434, it is preferable to use an insulator with a relatively low dielectric constant in order to reduce parasitic capacitance that occurs between the wires, similar to insulator 326. Furthermore, as the conductor 436, it is preferable to include a conductor that has barrier properties against impurities such as water and hydrogen, similar to conductors 356 and 426.

[0215] Insulators 510, 512, 513, 514, and 516 are sequentially layered on the insulator 434 and the conductor 436. Preferably, one of the insulators 510, 512, 513, 514, and 516 is made of a material that has barrier properties against oxygen and hydrogen.

[0216] For example, it is preferable to use a film for insulators 510 and 514 that has barrier properties to prevent impurities such as water and hydrogen from diffusing from the substrate 310 or the like to the region where the transistor 500 is installed. Therefore, the same material as for insulator 324 can be used.

[0217] As an example of a film having barrier properties against hydrogen, silicon nitride formed by the CVD method can be used. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor, such as transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between transistor 500 and substrate 310. Specifically, a film that suppresses hydrogen diffusion is a film that has a low hydrogen desorption rate.

[0218] Furthermore, as a film having barrier properties against hydrogen, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for insulators 510 and 514.

[0219] In particular, aluminum oxide exhibits a high barrier effect, preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical properties of transistors. Therefore, aluminum oxide can prevent the ingress of impurities such as hydrogen and moisture into the transistor 500 during and after the transistor manufacturing process. It can also suppress the release of oxygen from the oxides constituting the transistor 500. For this reason, it is suitable for use as a protective film for transistor 500.

[0220] Furthermore, for example, as the insulator 513, it is preferable to use a film that has barrier properties to prevent the diffusion of impurities such as water and hydrogen, similar to the insulators 510 and 514. In particular, in Figure 10, the insulator 513 functions as a film that seals the transistor 500 together with the insulator 576, which will be described later. For this reason, it is preferable to use a material for the insulator 513 that is applicable to the insulator 576. Alternatively, the insulator 513 may be made of a material applicable to the insulator 510 or the insulator 514.

[0221] Furthermore, for example, the same materials as those used for insulator 320 or insulator 326 can be used for insulator 512 and insulator 516. Additionally, by applying materials with relatively low dielectric constants to these insulators, parasitic capacitance between wiring can be reduced. For example, silicon oxide films, silicon oxynitride films, etc., can be used as insulators 512 and insulator 516.

[0222] Furthermore, the insulators 510, 512, 513, 514, and 516 have a conductor 518 and a conductor constituting the transistor 500 (for example, the conductor 503 shown in Figures 11A and 11B) embedded in them. The conductor 518 functions as a plug or wiring for connecting the conductor 497, the transistor 300, etc., which will be described later. The conductor 518 can be provided using, for example, the same material as the conductors 328 and 330.

[0223] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having barrier properties against oxygen, hydrogen, and water. With this configuration, the transistor 300 and the transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and the diffusion of hydrogen from the die SCD to the transistor 500 can be suppressed.

[0224] A transistor 500 is provided above the insulator 516.

[0225] As shown in Figures 11A and 11B, the transistor 500 includes a conductor 503 arranged to be embedded in insulators 514 and 516, an insulator 520 arranged on top of insulators 516 and 503, an insulator 522 arranged on top of insulator 520, an insulator 524 arranged on top of insulator 522, an oxide 530a arranged on top of insulator 524, an oxide 530b arranged on top of oxide 530a, conductors 542a and 542b arranged spaced apart from each other on oxide 530b, an insulator 580 arranged on top of conductors 542a and 542b with an opening formed between conductors 542a and 542b, an oxide 530c arranged on the bottom and side surfaces of the opening, an insulator 550 arranged on the forming surface of oxide 530c, and a conductor 560 arranged on the forming surface of insulator 550. In this specification, conductors 542a and 542b are collectively referred to as conductor 542.

[0226] Furthermore, as shown in Figures 11A and 11B, it is preferable that an insulator 544 is placed between the oxide 530a, oxide 530b, conductor 542a, and conductor 542b and the insulator 580. Also, as shown in Figures 11A and 11B, it is preferable that the conductor 560 has a conductor 560a provided inside the insulator 550 and a conductor 560b provided so as to be embedded inside the conductor 560a. Furthermore, as shown in Figures 11A and 11B, it is preferable that an insulator 574 is placed on top of the insulator 580, conductor 560, and insulator 550.

[0227] In the following, oxides 530a, 530b, and 530c may be collectively referred to as oxide 530.

[0228] Although the transistor 500 shows a configuration in which three layers of oxide 530a, oxide 530b, and oxide 530c are stacked in the region where the channel is formed and in its vicinity, the present invention is not limited to this configuration. For example, a single layer of oxide 530b, a two-layer structure of oxide 530b and oxide 530a, a two-layer structure of oxide 530b and oxide 530c, or a stacked structure of four or more layers may be provided. Also, although the conductor 560 is shown as a two-layer stacked structure in the transistor 500, the present invention is not limited to this configuration. For example, the conductor 560 may be a single-layer structure or a stacked structure of three or more layers. Furthermore, the transistor 500 shown in Figures 10, 11A, and 11B is just an example, and the present invention is not limited to its structure; an appropriate transistor may be used depending on the circuit configuration, driving method, etc.

[0229] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source electrode or drain electrode, respectively. As described above, the conductor 560 is formed to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. In other words, in the transistor 500, the gate electrode can be positioned in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductor 560 can be formed without providing a positional margin, the occupied area of ​​the transistor 500 can be reduced. This enables miniaturization and high integration of semiconductor devices.

[0230] Furthermore, since the conductor 560 is formed self-aligned in the region between the conductors 542a and 542b, the conductor 560 does not have any region that overlaps with the conductors 542a or 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b. Therefore, the switching speed of the transistor 500 can be improved, and it can be given high frequency characteristics.

[0231] Conductor 560 may function as a first gate (also called a top gate) electrode. Conductor 503 may function as a second gate (also called a bottom gate) electrode. In this case, the threshold voltage of transistor 500 can be controlled by changing the potential applied to conductor 503 independently of the potential applied to conductor 560, without linking them. In particular, by applying a negative potential to conductor 503, it is possible to make the threshold voltage of transistor 500 greater than 0V and reduce the off-current. Therefore, applying a negative potential to conductor 503 reduces the drain current when the potential applied to conductor 560 is 0V compared to not applying a negative potential.

[0232] The conductor 503 is positioned to overlap with the oxide 530 and the conductor 560. As a result, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 connect, covering the channel-forming region formed in the oxide 530. In this specification, a transistor structure in which the channel-forming region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is called a surrounded channel (S-channel) structure.

[0233] Furthermore, the conductor 503 has a similar configuration to the conductor 518, with conductor 503a formed in contact with the inner walls of the openings of the insulators 514 and 516, and conductor 503b formed further inside. Although the transistor 500 shows a configuration in which conductors 503a and conductor 503b are stacked, the present invention is not limited to this. For example, the conductor 503 may be provided as a single layer or as a stacked structure of three or more layers.

[0234] Here, it is preferable to use a conductive material for the conductor 503a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (i.e., the above impurities are less permeable). Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one such as oxygen atoms or oxygen molecules) (i.e., the above oxygen is less permeable). In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of any one or all of the above impurities or oxygen.

[0235] For example, the conductor 503a has a function of suppressing oxygen diffusion, which can prevent the conductor 503b from oxidizing and reducing its conductivity.

[0236] Furthermore, if the conductor 503 also functions as wiring, it is preferable that the conductor 503b be made of a highly conductive material mainly composed of tungsten, copper, or aluminum. Also, if the conductivity of the wiring can be maintained at a high level, the conductor 503a does not necessarily have to be provided. Although the conductor 503b is shown as a single layer, it may also be a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material.

[0237] Insulators 520, 522, and 524 function as second gate insulating films.

[0238] Here, it is preferable to use an insulator 524 that contains more oxygen than satisfies the stoichiometric composition for the insulator 530. In other words, it is preferable that an excess oxygen region is formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, the oxygen vacancy in the oxide 530 can be reduced, and the reliability of the transistor 500 can be improved. Note that in this specification, oxygen vacancies in metal oxides are defined as V O It is sometimes referred to as (oxygen vacancy).

[0239] A transistor using a metal oxide may have unstable electrical characteristics and poor reliability if impurities or oxygen vacancies (V O ) exist in the region where the channel in the metal oxide is formed. In addition, hydrogen near the oxygen vacancy (V O ) may form a defect in which hydrogen enters the oxygen vacancy (V O ) (hereinafter sometimes referred to as V O H) and generate electrons serving as carriers. Therefore, if the region where the channel in the oxide semiconductor is formed contains oxygen vacancies, the transistor tends to have normally-on characteristics (characteristics in which a channel exists without applying a voltage to the gate electrode and current flows through the transistor). Therefore, in the region where the channel in the oxide semiconductor is formed, it is preferable that impurities, oxygen vacancies, and V O H are reduced as much as possible. In other words, the region where the channel in the oxide semiconductor is formed preferably has a reduced carrier concentration and is of i-type (intrinsic) or substantially i-type.

[0240] Specifically, as the insulator having an excessive oxygen region, it is preferable to use an oxide material in which some oxygen desorbs by heating. The oxide that desorbs oxygen by heating is an oxide film in which the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19 atoms / cm 3 or more, more preferably 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 or more in TDS (Thermal Desorption Spectroscopy) analysis. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or more and 700°C or less, or 100°C or more and 400°C or less.

[0241] Further, the insulator having the excess oxygen region and the oxide 530 may be subjected to any one or more of heat treatment, microwave treatment, or RF treatment while being in contact with each other. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, in the oxide 530, a reaction occurs in which the bond of VoH is broken, or in other words, a reaction of "V O H→V O +H" occurs, enabling dehydrogenation. Part of the hydrogen generated at this time may combine with oxygen and be removed as H2O from the oxide 530 or the insulator near the oxide 530. Also, part of the hydrogen may diffuse or be trapped (also referred to as gettering) in the conductors 542a and 542b.

[0242] Further, the microwave treatment is preferably performed using, for example, a device having a power source for generating high-density plasma or a device having a power source for applying RF to the substrate side. For example, by using a gas containing oxygen and high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or the insulator near the oxide 530. Also, the microwave treatment may be performed at a pressure of 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. Also, as the gas introduced into the device for performing the microwave treatment, for example, oxygen and argon are used, and the oxygen flow ratio (O2 / (O2+Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0243] Further, during the manufacturing process of the transistor 500, it is preferable to perform heat treatment in a state where the surface of the oxide 530 is exposed. The heat treatment may be performed, for example, at 100°C or more and 450°C or less, more preferably 350°C or more and 400°C or less. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530 to create oxygen vacancies (V OReduction of can be achieved. Also, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after heat treatment in an atmosphere of nitrogen gas or an inert gas to supplement the desorbed oxygen. Alternatively, after heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, heat treatment may be continuously performed in an atmosphere of nitrogen gas or an inert gas.

[0244] Note that by performing an oxygen addition treatment on the oxide 530, the oxygen deficiency in the oxide 530 can be repaired with the supplied oxygen. In other words, the reaction of "V O +O→null" can be promoted. Furthermore, by reacting the supplied oxygen with the hydrogen remaining in the oxide 530, the hydrogen can be removed (dehydrated) as H2O. As a result, the hydrogen remaining in the oxide 530 can be prevented from recombining with the oxygen deficiency to form V O H.

[0245] Also, when the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the oxygen is difficult to permeate).

[0246] It is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen, impurities, etc., so that the oxygen possessed by the oxide 530 does not diffuse to the insulator 520 side. Also, the conductor 503 can be prevented from reacting with the oxygen possessed by the insulator 524 and the oxide 530.

[0247] The insulator 522 preferably uses a single-layer or multi-layer insulator containing so-called high-k materials such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more integrated, thinning of the gate insulating film can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0248] In particular, it is preferable to use an insulator containing an oxide of either aluminum or hafnium, or both, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (the above-mentioned oxygen is less permeable). As an insulator containing an oxide of either aluminum or hafnium, or both, it is preferable to use aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When an insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530, the mixing of impurities such as hydrogen from the periphery of the transistor 500 into the oxide 530, and so on.

[0249] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be subjected to nitriding treatment. Silicon oxide, silicon oxide nitride, or silicon nitride may be laminated onto the above insulators.

[0250] Furthermore, it is preferable that the insulator 520 is thermally stable. For example, silicon oxide and silicon oxide-nitride are suitable because they are thermally stable. Also, by combining a high-k material insulator with silicon oxide or silicon oxide-nitride, an insulator 520 with a thermally stable and high dielectric constant laminated structure can be obtained.

[0251] In Figures 11A and 11B, transistor 500 is shown with insulators 520, 522, and 524 as a second gate insulating film consisting of a three-layer laminated structure. However, the second gate insulating film may have a single-layer, two-layer, or four-layer or more laminated structure. In that case, it is not limited to a laminated structure made of the same material, but may also be a laminated structure made of different materials.

[0252] In transistor 500, it is preferable to use a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel formation region. For example, as the oxide 530, a metal oxide such as In-M-Zn oxide (where element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) is preferable. In particular, the In-M-Zn oxide that can be applied as oxide 530 is preferably CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) or CAC-OS (Cloud-Aligned Composite Oxide Semiconductor). Alternatively, In-Ga oxide, In-Zn oxide, In oxide, etc., may be used as the oxide 530.

[0253] Furthermore, it is preferable to use a metal oxide with a low carrier concentration for transistor 500. When the carrier concentration of the metal oxide is low, the impurity concentration in the metal oxide should be lowered to reduce the defect level density. In this specification, a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Examples of impurities in metal oxides include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0254] In particular, hydrogen contained in metal oxides reacts with oxygen bonded to metal atoms to form water, which can create oxygen vacancies in the metal oxide. Furthermore, if hydrogen enters an oxygen vacancy in oxide 530, the oxygen vacancy and hydrogen combine to form V O It may form H. O H can function as a donor, and electrons, which are carriers, can be generated. In addition, some hydrogen can combine with oxygen that is bonded to metal atoms, generating electrons, which are carriers. Therefore, transistors using metal oxides that contain a large amount of hydrogen tend to exhibit normally-on characteristics. Furthermore, since hydrogen in metal oxides is easily moved by stress such as heat and electric fields, the reliability of the transistor may deteriorate if the metal oxide contains a large amount of hydrogen. In one embodiment of the present invention, V in oxide 530 O It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. Thus, V O To obtain a metal oxide with sufficiently reduced H content, it is important to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration and dehydrogenation treatment) and to supply oxygen to the metal oxide to compensate for oxygen deficiency (sometimes referred to as oxygenation treatment). O By using metal oxides with sufficiently reduced impurities such as H in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0255] Defects where hydrogen fills an oxygen vacancy can function as donors for metal oxides. However, quantitatively evaluating such defects is difficult. Therefore, in metal oxides, evaluation is sometimes done using carrier concentration rather than donor concentration. Accordingly, in this specification, the carrier concentration, assuming no electric field is applied, may be used as a parameter for metal oxides, rather than the donor concentration. In other words, "carrier concentration" as described in this specification may sometimes be rephrased as "donor concentration."

[0256] Therefore, when using metal oxides in oxide 530, it is preferable that the hydrogen content in the metal oxide is reduced as much as possible. Specifically, in metal oxides, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 It should be less than [amount]. By using metal oxides with sufficiently reduced impurities such as hydrogen in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0257] Furthermore, when a metal oxide is used for oxide 530, the metal oxide is a semiconductor with a high band gap, is intrinsic (also called type I), or substantially intrinsic, and the carrier concentration of the metal oxide in the channel-forming region is 1 × 10⁻⁶ 18 cm -3 Preferably less than 1 × 10 17 cm -3 It is more preferable that it be less than 1 × 10 16 cm -3 It is even more preferable that it be less than 1 × 10 13 cm -3 It is even more preferable that it be less than 1 × 10 12 cm -3 It is even more preferable that it be less than . There are no particular limitations on the lower limit of the carrier concentration of the metal oxide in the channel-forming region, but for example, 1 × 10 -9 cm -3 It can be done this way.

[0258] Furthermore, when a metal oxide is used for oxide 530, contact between conductors 542a and 542b and oxide 530 may cause oxygen in oxide 530 to diffuse into conductors 542a and 542b, leading to oxidation of conductors 542a and 542b. Oxidation of conductors 542a and 542b is highly likely to decrease their conductivity. Note that the diffusion of oxygen in oxide 530 into conductors 542a and 542b can be rephrased as conductors 542a and 542b absorbing oxygen in oxide 530.

[0259] Furthermore, oxygen in the oxide 530 may diffuse into the conductors 542a and 542b, forming a heterogeneous layer between the conductor 542a and the oxide 530b, and between the conductor 542b and the oxide 530b. Since this heterogeneous layer contains more oxygen than the conductors 542a and 542b, it is presumed to have insulating properties. In this case, the three-layer structure of the conductor 542a or 542b, the heterogeneous layer, and the oxide 530b can be considered a three-layer structure consisting of a metal-insulator-semiconductor, and may be referred to as an MIS (Metal-Insulator-Semiconductor) structure, or as a diode junction structure mainly composed of an MIS structure.

[0260] Furthermore, the above-mentioned heterogeneous layer is not limited to being formed between the conductors 542a and 542b and the oxide 530b; for example, the heterogeneous layer may be formed between the conductors 542a and 542b and the oxide 530c.

[0261] In oxide 530, it is preferable to use a metal oxide that functions as a channel-forming region and has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0262] By having oxide 530a below oxide 530b, the diffusion of impurities from structures formed below oxide 530a to oxide 530b can be suppressed. Furthermore, by having oxide 530c above oxide 530b, the diffusion of impurities from structures formed above oxide 530c to oxide 530b can be suppressed.

[0263] Furthermore, it is preferable that oxide 530 has a layered structure comprising multiple oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for oxide 530a, it is preferable that the atomic ratio of element M in the constituent elements is greater than the atomic ratio of element M in the constituent elements of the metal oxide used for oxide 530b. Also, in the metal oxide used for oxide 530a, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Furthermore, in the metal oxide used for oxide 530b, it is preferable that the atomic ratio of In to element M is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a. In addition, oxide 530c can be any metal oxide that can be used for oxide 530a or oxide 530b.

[0264] Specifically, as the oxide 530a, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4 or 1:1:0.5 may be used. As the oxide 530b, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:3 or 1:1:1 may be used. As the oxide 530c, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4, or an atomic ratio of Ga:Zn = 2:1, or Ga:Zn = 2:5 may be used. Specific examples of the case where the oxide 530c has a laminated structure include a laminated structure of In:Ga:Zn = 4:2:3 and In:Ga:Zn = 1:3:4, a laminated structure of Ga:Zn = 2:1 and In:Ga:Zn = 4:2:3, a laminated structure of Ga:Zn = 2:5 and In:Ga:Zn = 4:2:3, a gallium oxide, and a laminated structure of In:Ga:Zn = 4:2:3, etc.

[0265] Further, for example, when the atomic ratio of In to element M in the metal oxide used for the oxide 530a is smaller than the atomic ratio of In to element M in the metal oxide used for the oxide 530b, as the oxide 530b, an In-Ga-Zn oxide having a composition such as In:Ga:Zn = 5:1:6 or in the vicinity thereof, In:Ga:Zn = 5:1:3 or in the vicinity thereof, In:Ga:Zn = 10:1:3 or in the vicinity thereof can be used.

[0266] As compositions other than those described above, for the oxide 530b, for example, metal oxides having a composition such as In:Zn = 2:1, In:Zn = 5:1, In:Zn = 10:1, or a composition in the vicinity of any one of these can be used.

[0267] It is preferable to combine these oxides 530a, 530b, and 530c in a manner that satisfies the above-mentioned atomic ratio relationship. For example, it is preferable that oxides 530a and 530c be metal oxides having a composition of In:Ga:Zn = 1:3:4 or a composition close to it, and oxide 530b be a metal oxide having a composition of In:Ga:Zn = 4:2:3 to 4.1 or a composition close to it. Note that the above composition refers to the atomic ratio in the oxide formed on the substrate, or the atomic ratio in the sputtering target. Furthermore, increasing the ratio of In in the composition of oxide 530b is preferable because it can increase the on-current or field-effect mobility of the transistor.

[0268] Furthermore, it is preferable that the energy at the lower end of the conduction band of oxide 530a and oxide 530c is higher than the energy at the lower end of the conduction band of oxide 530b. In other words, it is preferable that the electron affinity of oxide 530a and oxide 530c is smaller than the electron affinity of oxide 530b.

[0269] Here, at the junctions of oxide 530a, oxide 530b, and oxide 530c, the energy level at the lower end of the conduction band changes smoothly. In other words, the energy level at the lower end of the conduction band at the junctions of oxide 530a, oxide 530b, and oxide 530c can be said to change continuously or be continuously joined. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between oxide 530a and oxide 530b, and at the interface between oxide 530b and oxide 530c.

[0270] Specifically, a mixed layer with a low defect level density can be formed if oxide 530a and oxide 530b, and oxide 530b and oxide 530c, have a common element other than oxygen (as the main component). For example, if oxide 530b is In-Ga-Zn oxide, then In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc., can be used as oxide 530a and oxide 530c.

[0271] In this case, the primary carrier pathway is oxide 530b. By configuring oxides 530a and 530c as described above, the defect level density at the interface between oxide 530a and oxide 530b, and at the interface between oxide 530b and oxide 530c, can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 500 can obtain a high on-current.

[0272] Conductors 542a and 542b, which function as source electrodes and drain electrodes, are provided on the oxide 530b. It is preferable to use metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum as conductors 542a and 542b, or alloys composed of the above metallic elements, or alloys combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. In addition, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen or oxygen.

[0273] Furthermore, although conductors 542a and 542b are shown as single-layer structures in Figures 11A and 11B, they may also be laminated structures of two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. Alternatively, a titanium film and an aluminum film may be laminated. In addition, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, or a two-layer structure in which a copper film is laminated on a tungsten film may also be used.

[0274] Furthermore, there are three-layer structures such as a titanium film or titanium nitride film, an aluminum film or copper film laminated on top of the titanium film or titanium nitride film, and a titanium film or titanium nitride film formed on top of that; and a molybdenum film or molybdenum nitride film, an aluminum film or copper film laminated on top of the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film formed on top of that. Transparent conductive materials containing indium oxide, tin oxide, or zinc oxide may also be used.

[0275] Furthermore, as shown in Figure 11A, regions 543a and 543b may be formed as low-resistance regions at and near the interface between the oxide 530 and the conductor 542a (conductor 542b). In this case, region 543a functions as either a source region or a drain region, and region 543b functions as either a source region or a drain region. In addition, a channel-forming region is formed in the region sandwiched between regions 543a and 543b.

[0276] By providing the conductor 542a (conductor 542b) in contact with the oxide 530, the oxygen concentration in region 543a (region 543b) may be reduced. In addition, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the components of the oxide 530 may be formed in region 543a (region 543b). In such cases, the carrier concentration in region 543a (region 543b) increases, and region 543a (region 543b) becomes a low-resistance region.

[0277] The insulator 544 is provided so as to cover the conductors 542a and 542b, thereby suppressing oxidation of the conductors 542a and 542b. In this case, the insulator 544 may be provided so as to cover the respective sides of the oxide 530 and the insulator 524 and be in contact with the insulator 522.

[0278] As the insulator 544, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, or magnesium can be used. Alternatively, silicon nitride or silicon nitride can also be used as the insulator 544.

[0279] In particular, it is preferable to use an insulator 544 that contains an oxide of either aluminum or hafnium, or both, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Hafnium aluminate is especially preferable because it has higher heat resistance than hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize during heat treatment in a later process. Note that if the conductors 542a and 542b are made of oxidation-resistant materials, or if their conductivity does not significantly decrease even when oxygen is absorbed, the insulator 544 is not an essential component. It can be designed appropriately according to the desired transistor characteristics.

[0280] The presence of the insulator 544 suppresses the diffusion of water and other impurities such as hydrogen contained in the insulator 580 to the oxide 530b via the oxide 530c and insulator 550. Furthermore, it suppresses the oxidation of the conductor 560 due to excess oxygen present in the insulator 580.

[0281] The insulator 550 functions as a first gate insulating film. It is preferable that the insulator 550 is placed in contact with the inside (top surface and side surface) of the oxide 530c. It is preferable that the insulator 550 is formed using an insulator that contains an excess of oxygen and releases oxygen upon heating, similar to the insulator 524 described above.

[0282] Specifically, silicon oxide with excess oxygen, silicon oxide-nitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide can be used. Silicon oxide and silicon oxide-nitride are particularly preferred because they are stable to heat.

[0283] By providing an insulator 550, which releases oxygen upon heating, in contact with the upper surface of oxide 530c, oxygen can be effectively supplied from the insulator 550 to the channel-forming region of oxide 530b through oxide 530c. Furthermore, similar to the insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 550 is reduced. The film thickness of the insulator 550 is preferably between 1 nm and 20 nm.

[0284] Furthermore, in order to efficiently supply excess oxygen from the insulator 550 to the oxide 530, a metal oxide may be provided between the insulator 550 and the conductor 560. It is preferable that the metal oxide suppresses the diffusion of oxygen from the insulator 550 to the conductor 560. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. In other words, the reduction in the amount of excess oxygen supplied to the oxide 530 can be suppressed. In addition, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, any material that can be used for the insulator 544 may be used.

[0285] Furthermore, the insulator 550 may have a multilayer structure, similar to the second gate insulating film. As transistors become smaller and more integrated, thinning of the gate insulating film can lead to problems such as leakage current. Therefore, by using a multilayer structure of a high-k material and a thermally stable material for the insulator that functions as the gate insulating film, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, a multilayer structure that is thermally stable and has a high dielectric constant can be achieved.

[0286] The conductor 560, which functions as the first gate electrode, is shown as a two-layer structure in Figures 11A and 11B, but it may also be a single-layer structure or a stacked structure of three or more layers.

[0287] It is preferable to use a conductive material for the conductor 560a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules). By having the function of suppressing the diffusion of oxygen in the conductor 560a, it is possible to suppress the oxidation of the conductor 560b by the oxygen contained in the insulator 550, which reduces the conductivity. As a conductive material that has the function of suppressing the diffusion of oxygen, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Furthermore, an oxide semiconductor applicable to the oxide 530 can be used as the conductor 560a. In that case, by depositing the conductor 560b by sputtering, the electrical resistance value of the conductor 560a can be reduced to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0288] Furthermore, it is preferable that the conductor 560b is made of a conductive material mainly composed of tungsten, copper, or aluminum. Also, since the conductor 560b functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. The conductor 560b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0289] The insulator 580 is provided on the conductors 542a and 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably has silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, or a resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Silicon oxide and porous silicon oxide are particularly preferred because they can easily form an excess oxygen region in a later process.

[0290] Because the insulator 580 has an excess oxygen region, oxygen can be released by heating the insulator 580. Therefore, by providing the insulator 580, which releases oxygen upon heating, in contact with the oxide 530c, oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. It is preferable that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced.

[0291] The opening in the insulator 580 is formed superimposed on the region between the conductors 542a and 542b. As a result, the conductor 560 is formed to be embedded in the opening in the insulator 580 and in the region sandwiched between the conductors 542a and 542b.

[0292] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to ensure that the conductivity of the conductor 560 does not decrease. If the film thickness of the conductor 560 is increased to achieve this, the conductor 560 may take on a shape with a high aspect ratio. In this embodiment, since the conductor 560 is embedded in the opening of the insulator 580, even if the conductor 560 has a shape with a high aspect ratio, it can be formed without the conductor 560 collapsing during the manufacturing process.

[0293] The insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550. By forming the insulator 574 by sputtering, an excess oxygen region can be created in the insulator 550 and the insulator 580. This allows oxygen to be supplied to the oxide 530 from the excess oxygen region.

[0294] For example, as the insulator 574, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used.

[0295] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in thin films between 0.5 nm and 3.0 nm in thickness. Therefore, aluminum oxide deposited by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.

[0296] To form an opening, portions of insulators 574, 580, 544, 522, 520, 516, and 514 are removed so as to surround transistor 500 and expose insulator 513, thereby forming insulator 576, which has high barrier properties against hydrogen or water. As a result, the sides of each of insulators 574, 580, 544, 522, 520, 516, and 514 are in contact with insulator 576. This prevents moisture and hydrogen from entering transistor 500 from the outside.

[0297] As described above, it is preferable that the insulators 513 and 576 have a high function of suppressing the diffusion of hydrogen (for example, at least one such as a hydrogen atom or hydrogen molecule) or water molecules. For example, it is preferable to use silicon nitride or silicon nitride oxide, which are materials with high hydrogen barrier properties, as the insulators 513 and 576. This makes it possible to suppress the diffusion of hydrogen, etc., into the oxide 530, and thus suppress the deterioration of the characteristics of the transistor 500. Therefore, the reliability of the semiconductor device according to one embodiment of the present invention can be improved.

[0298] Furthermore, it is preferable to provide an insulator 581 on the insulator 576 that functions as an interlayer film and a planarization film. It is preferable that the insulator 581, like the insulator 524, has a reduced concentration of impurities such as water or hydrogen in the film.

[0299] Furthermore, an insulator 552 is provided on the side surface of the opening formed in insulators 581, 576, 574, 580, and 544. Conductors 540a and 540b are provided so as to be in contact with the side surface of the insulator 552 and the bottom surface of the opening. In Figure 11A, conductors 540a and 540b are provided opposite each other with conductor 560 in between.

[0300] The insulator 552 is provided in contact with, for example, the insulators 581, 576, 574, 580, and 544. Preferably, the insulator 552 has the function of suppressing the diffusion of hydrogen or water molecules. For example, it is preferable to use an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide as the insulator 552, as it is a material with high hydrogen barrier properties. In particular, silicon nitride is a material with high hydrogen barrier properties, so it is suitable for use as the insulator 552. By using a material with high hydrogen barrier properties as the insulator 552, it is possible to suppress the diffusion of impurities such as water or hydrogen from the insulator 580, etc., through the conductors 540a and 540b to the oxide 530. In addition, it is possible to suppress the absorption of oxygen contained in the insulator 580 by the conductors 540a and 540b. As a result, the reliability of the semiconductor device according to one embodiment of the present invention can be improved.

[0301] The conductors 540a and 540b can be made of materials similar to those used for conductors 328, 330, and 503, for example. In particular, it is preferable that each of the conductors 540a and 540b has a laminated structure of two or more layers, with the first layer in contact with the insulator 552 being a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (making it difficult for the above impurities to permeate), and the second and subsequent layers being a highly conductive material mainly composed of tungsten, copper, aluminum, etc.

[0302] In Figure 10, an insulator 582 is provided on the insulator 581. It is preferable to use a material that has barrier properties against oxygen, hydrogen, etc. for the insulator 582. Therefore, the same material as the insulator 514 can be used for the insulator 582. For example, it is preferable to use a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide for the insulator 582.

[0303] In particular, aluminum oxide exhibits a high barrier effect, preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical properties of transistors. Therefore, aluminum oxide can prevent the ingress of impurities such as hydrogen and moisture into the transistor 500 during and after the transistor manufacturing process. It can also suppress the release of oxygen from the oxides constituting the transistor 500. For this reason, it is suitable for use as a protective film for transistor 500.

[0304] Furthermore, an insulator 586 is provided on the insulator 582. The insulator 586 can be made of the same material as the insulator 320. By applying materials with relatively low dielectric constants to these insulators, parasitic capacitance between wirings can be reduced. For example, silicon oxide films, silicon oxynitride films, etc., can be used as the insulator 586.

[0305] Furthermore, as shown in Figures 10 and 11A, conductors 540a, 540b, 546, etc., are embedded in insulators 520, 522, 524, 544, 580, 574, 576, 581, 582, and 586. For example, the conductor 546 can be made from a material applicable to conductors 540a and 540b.

[0306] Conductors 540a, 540b, and 546 function as plugs or wiring for connecting transistors 500, 300, and 497 (described later). Conductors 540a and 540b can be made from the same materials as conductors 328 and 330. In particular, in Figure 10, conductor 546 is formed to be in contact with conductor 518.

[0307] In addition, a conductor 450 may be provided on the conductors 540a, 540b, 546, and insulator 586. The conductor 450 functions as wiring to connect the conductor 497, transistor 300, transistor 500, etc., which will be described later. In particular, in Figure 10, the conductor 450 is formed to be in contact with the conductors 540a, 540b, 546, etc.

[0308] For the conductor 450, for example, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) composed of the above elements can be used. Alternatively, conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with silicon oxide added can also be used.

[0309] In Figure 10, the conductor 450 is shown as having a single-layer structure, but it is not limited to this configuration and may have a laminated structure of two or more layers. For example, a conductor with high adhesion to both a barrier conductor and a highly conductive conductor may be formed between the barrier conductor and the highly conductive conductor.

[0310] Furthermore, in the OSL layer of the semiconductor device PSD1 shown in Figure 10, a wiring layer is provided above the transistor 500 as an example.

[0311] Insulators 451, 452, and 454 are layered in order on the insulator 586 and the conductor 450.

[0312] As the insulator 451, it is preferable to use a film that has barrier properties to prevent the diffusion of impurities such as water and hydrogen into the region where the transistor 500 is provided, similar to the insulator 324. In other words, it is preferable to use a material as the insulator 451 that can be applied to the insulator 324, etc.

[0313] For insulators 452 and 454, it is preferable to use insulators with a relatively low dielectric constant, similar to insulator 326. In other words, it is preferable to use materials for insulators 452 and 454 that are applicable to insulator 326.

[0314] Furthermore, insulators 451, 452, and 454 have conductors 456 embedded within them. The conductors 456 function as plugs or wiring for connecting the conductor 497, transistor 300, transistor 500, etc., which will be described later. For example, the conductor 456 can be made from a material that can be used for conductors 328, 330, etc.

[0315] Furthermore, a wiring layer may be provided on the insulators 451, 452, 454, and 456. For example, in Figure 10, insulators 460, 462, and 464 are sequentially stacked on insulator 454 and conductor 456. Conductors 466 are formed on insulators 460, 462, and 464. Conductors 466 function as plugs or wiring for connecting, for example, conductor 497, transistor 300, transistor 500, etc., which will be described later. Conductors 466 can be provided using the same material as conductors 328 and 330.

[0316] As the insulator 460, it is preferable to use an insulator that has barrier properties against impurities such as water and hydrogen, similar to insulators 324 and 420. Furthermore, as the insulators 462 and 464, it is preferable to use an insulator with a relatively low dielectric constant in order to reduce parasitic capacitance that occurs between the wiring, similar to insulator 326. Furthermore, as the conductor 466, it is preferable to include a conductor that has barrier properties against impurities such as water and hydrogen, similar to conductors 356 and 426. In particular, a conductor that has barrier properties against impurities such as water and hydrogen is formed in the openings of the insulator 460 that has barrier properties against impurities such as water and hydrogen. This allows the transistor 500 and the area above the OSL layer to be separated by the barrier layer, and the diffusion of impurities such as water and hydrogen from the area above the OSL layer to the transistor 500 can be suppressed.

[0317] Furthermore, an insulator 470 and an insulator 472 are stacked in order on the insulator 464 and the conductor 466.

[0318] It is preferable that the insulator 470, like the insulator 324, is an insulator that has barrier properties against impurities such as water and hydrogen. Therefore, as the insulator 470, for example, a material that can be used for the insulator 324 can be used.

[0319] The insulator 472 functions as a planarization film. Furthermore, it is preferable to use an insulator 472 that, like the insulator 324, has barrier properties against impurities such as water and hydrogen. Therefore, the insulator 472 can be made from a material that is applicable to the insulator 324.

[0320] Furthermore, openings are formed in the regions of the insulator 470 and the insulator 472 that overlap with a portion of the conductor 466, and the conductor 493 is provided to fill these openings. The conductor 493 is also formed on the insulator 472. Subsequently, the conductor 493 is patterned into the shapes of wiring, terminals, pads, etc., by etching or other processes.

[0321] Examples of conductors 493 include copper, aluminum, tin, zinc, tungsten, silver, platinum, and gold. Furthermore, conductor 493 can be any material applicable to conductor 366 or conductor 406.

[0322] Next, an insulator 492 is formed to cover the insulator 472 and the conductor 493, and then a planarization treatment using chemical mechanical polishing (CMP) or the like is performed until the conductor 493 is exposed. This improves the flatness between the insulator 492 and the conductor 493.

[0323] As the insulator 492, it is preferable to provide an insulator that functions as a planarization film, similar to the insulator 362. Therefore, as the insulator 492, for example, a material that can be applied to the insulator 362 can be used.

[0324] Next, insulators 494 and 495 are sequentially deposited on insulator 492 and conductor 493. Then, openings are formed in insulators 494 and 495 so that conductor 493 is exposed, and conductor 496 is formed in these openings.

[0325] As the insulator 494, it is preferable to provide an insulator that functions as a planarization film, similar to the insulator 362. Therefore, as the insulator 494, for example, a material that can be applied to the insulator 362 can be used.

[0326] As the insulator 495, it is preferable to use an insulator that has barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, as the insulator 495, for example, a material that can be used for the insulator 324 can be used.

[0327] For example, the conductor 496 can be a material that can be applied to the conductor 493. Furthermore, it is preferable that the conductor 496 is a material on which the conductor 497, described later, can be formed.

[0328] On the conductor 496, for example, a conductor 497 corresponding to the bump HBL of the semiconductor device PSD1 described in Embodiment 1 is provided. The conductor 497 can be formed, for example, using solder. Alternatively, the conductor 497 can be formed using one or more alloys selected from, for example, Sn, Cu, Ag, Au, Bi, etc. In Figure 10, the conductor 497 is shown as a ball-shaped bump as an example, but conical, pyramidal, mushroom-shaped, columnar, or other types of bumps may also be used. Methods for forming the conductor 497 include electroplating, electroless plating, and printing.

[0329] <Example of semiconductor device configuration 2> Next, an example of the configuration of the semiconductor device PSD3 described in Embodiment 1 will be explained. Figure 12 is a schematic cross-sectional view showing an example of the configuration of the semiconductor device PSD3, and as an example, the semiconductor device PSD3 has a transistor 300 and a transistor 500, similar to the semiconductor device PSD1.

[0330] The semiconductor device PSD3 has a configuration in which a die SCD is mounted on a layer OSL after the layer OSL has been formed. Therefore, the orientation of the transistor 500 included in the layer OSL is different from the orientation of the transistor 300 included in the die SCD. This is because, in the layer OSL of the semiconductor device PSD3, wiring, insulators, etc. are formed from below the transistor 500, and wiring, terminals, pads, etc. for electrical connection with the die SCD are provided above the transistor 500.

[0331] Note that in the semiconductor device PSD3 shown in Figure 12, explanations are omitted for parts that are the same as those described in the example configuration of the semiconductor device PSD1 above.

[0332] The OSL layer of the semiconductor device PSD3 is formed sequentially from insulator 402 and conductor 406 to insulator 482 and conductor 486, which will be described later. Regarding the structure and manufacturing method of the OSL layer from insulator 402 and conductor 406 to insulator 472, insulator 474, and conductor 476, refer to the example of the OSL layer structure of the semiconductor device PSD1 described above.

[0333] A conductor 486 is formed on the insulator 474 and the conductor 476. The conductor 486 corresponds to multiple wirings, terminals, pads, etc. for connecting to the die SCD in the layer OSL. In addition, an insulator 482 is formed on the insulator 474 to separate the multiple wirings, terminals, pads, etc. of the layer OSL.

[0334] As a method for forming the insulator 474 and the conductor 486, for example, first a film of the conductor 486 is deposited, and then the conductor 486 is patterned into the shape of wiring, terminals, pads, etc. by etching or the like. Next, an insulator 482 is deposited so as to cover the insulator 474 and the conductor 486, and then a planarization treatment using chemical mechanical polishing (CMP) or the like is performed until the conductor 486 is exposed. This allows the conductor 486 to be formed as wiring, terminals, pads, etc. in an OSL layer.

[0335] Furthermore, the die SCD of the semiconductor device PSD3 has a transistor 300 formed on the substrate 310, and an insulator 320, an insulator 332, and a conductor 328 formed on the transistor 300. In addition, insulators 324, an insulator 326, and conductors 330 through 362, an insulator 370, and conductor 366 are formed on the insulators 320, an insulator 332, and conductor 328. The configuration and manufacturing method of the die SCD of the semiconductor device PSD3 should be considered in reference to the example of the die SCD configuration of the semiconductor device PSD1 described above.

[0336] In the semiconductor device PSD3, the conductor 366 of the die SCD is electrically connected to the conductor 486 of the layer OSL via the conductor 376. The conductor 376 corresponds to the bump BP of the semiconductor device PSD1 described in Embodiment 1. The conductor 376 can be formed using, for example, solder. Alternatively, the conductor 376 can be formed using one or more alloys selected from, for example, Sn, Cu, Ag, Au, Bi, etc. In Figure 12, the conductor 376 is shown as a ball-shaped bump as an example, but conical, pyramidal, mushroom-shaped, or columnar bumps may also be used. Methods for forming the conductor 486 include electroplating, electroless plating, and printing.

[0337] Furthermore, in the semiconductor device PSD3, the layer OSL and the die SCD can be joined, for example, by flip-chip bonding. In the semiconductor device PSD3 shown in Figure 12, an insulator 380 is injected between the layer OSL and the die SCD as an insulating resin. The insulator 380 corresponds to the insulating resin IJ of the semiconductor device PSD3 described in Embodiment 1.

[0338] Although not shown in Figures 10 and 12, semiconductor device PSD1 and semiconductor device PSD3 may have capacitive elements.

[0339] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0340] (Embodiment 3) This embodiment describes metal oxides (hereinafter also referred to as oxide semiconductors) that can be used in the OS transistor described in the above embodiment.

[0341] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. In addition, it is preferable that it contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0342] <Classification of crystal structures> First, we will explain the classification of crystal structures in oxide semiconductors using Figure 13A. Figure 13A is a diagram illustrating the classification of crystal structures in oxide semiconductors, specifically IGZO (a metal oxide containing In, Ga, and Zn).

[0343] As shown in Figure 13A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous materials. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Composite) (excluding single crystal and polycrystal). Note that single crystal, polycrystal, and completely amorphous materials are excluded from the "Crystalline" classification. "Crystal" includes single crystal and polycrystal materials.

[0344] The structure within the thick frame shown in Figure 13A represents an intermediate state between "Amorphous" and "Crystal," and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as being completely different from the energetically unstable "Amorphous" and "Crystal" states.

[0345] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 13B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline" (the horizontal axis is 2θ [deg.], and the vertical axis represents intensity in arbitrary units (au)). The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 13B will simply be referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 13B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 13B is 500 nm.

[0346] As shown in Figure 13B, the XRD spectrum of the CAAC-IGZO film shows a peak indicating clear crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating c-axis orientation near 2θ=31°. As shown in Figure 13B, the peak near 2θ=31° is asymmetrical with respect to the angle at which the peak intensity was detected.

[0347] Furthermore, the crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 13C. Figure 13C shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 13C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0348] As shown in Figure 13C, the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation.

[0349] <<Oxide semiconductor structure>> Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 13A. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0350] Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above.

[0351] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0352] Each of the multiple crystalline regions described above is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single minute crystal, the maximum diameter of that crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nanometers.

[0353] Furthermore, in In-M-Zn oxides (where element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer). Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Also, the In layer may contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images.

[0354] When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the c-axis orientation peak (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0355] Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0356] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to factors such as the non-dense arrangement of oxygen atoms in the ab-plane direction and the change in interatomic bond distances due to the substitution of metal atoms.

[0357] A crystal structure in which clear grain boundaries are observed is called a polycrystal. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more than In oxide.

[0358] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities and the formation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0359] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS and amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0360] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0361] <<Oxide Semiconductor Composition>> Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0362] [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing these metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0363] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0364] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than the [In] in the second region, and [Ga] is smaller than the [Ga] in the second region. The second region is the region where [Ga] is greater than the [Ga] in the first region, and [In] is smaller than the [In] in the first region.

[0365] Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. Similarly, the second region can be rephrased as a region whose main component is Ga.

[0366] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0367] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0368] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I) can be achieved. on This enables high field-effect mobility (μ) and good switching operation.

[0369] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0370] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0371] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0372] It is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. For example, the carrier concentration of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm-3 This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations may be referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0373] Furthermore, oxide semiconductor films that are highly pure or substantially highly pure have a low defect level density, which may result in a low trap level density.

[0374] Furthermore, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear, sometimes behaving like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties.

[0375] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0376] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0377] In oxide semiconductors, the presence of silicon, carbon, and other elements, which are part of Group 14, leads to the formation of defect levels within the oxide semiconductor. Therefore, the concentration of silicon, carbon, and other elements in the oxide semiconductor and the concentration of silicon, carbon, and other elements near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are compared by 2 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 1017 atoms / cm 3 The following applies:

[0378] Furthermore, if an oxide semiconductor contains alkali metals or alkaline earth metals, it may form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0379] Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in oxide semiconductors obtained by SIMS should be set to 5 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 Do the following:

[0380] Furthermore, hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. Hydrogen can then fill these vacancies, generating electrons, which act as carriers. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to reduce the hydrogen content in oxide semiconductors as much as possible. Specifically, in oxide semiconductors, the hydrogen concentration obtained by SIMS should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0381] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0382] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0383] (Embodiment 4) This embodiment describes a semiconductor wafer, a semiconductor chip obtained by cutting the semiconductor wafer, and a semiconductor device incorporating the semiconductor chip using FOWLP.

[0384] <Semiconductor wafers and semiconductor chips> First, an example of a semiconductor wafer with circuits and other structures formed on it will be explained using Figure 14A.

[0385] The semiconductor wafer 4800 shown in Figure 14A comprises a wafer 4801 and a plurality of circuit sections 4802 provided on the upper surface of the wafer 4801. The portion of the upper surface of the wafer 4801 without circuit sections 4802 is the spacing 4803, which is the region for dicing.

[0386] The semiconductor wafer 4800 can be manufactured by forming multiple circuit sections 4802 on the surface of wafer 4801 in a previous process. Alternatively, the wafer 4801 may be thinned by grinding the opposite side of the wafer 4801 from where the circuit sections 4802 are formed. This process reduces warping of the wafer 4801, enabling miniaturization of the component.

[0387] The next step is the dicing process. Dicing is performed along the scribe lines SCL1 and SCL2 (sometimes referred to as dicing lines or cutting lines) indicated by the dashed lines. In order to facilitate the dicing process, it is preferable that the spacing 4803 be arranged so that multiple scribe lines SCL1 are parallel, multiple scribe lines SCL2 are parallel, and scribe lines SCL1 and SCL2 are perpendicular.

[0388] By performing the dicing process, a semiconductor chip 4800a, as shown in Figure 14B, can be cut from the semiconductor wafer 4800. The semiconductor chip 4800a has a wafer 4801a, a circuit section 4802, and spacing 4803a. It is preferable to make the spacing 4803a as small as possible. In this case, the width of the spacing 4803 between adjacent circuit sections 4802 should be approximately the same length as the cutting allowance of the scribe line SCL1 or the cutting allowance of the scribe line SCL2.

[0389] The shape of the element substrate in one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 shown in Figure 14A. For example, it may be a rectangular semiconductor wafer. The shape of the element substrate can be appropriately changed depending on the manufacturing process of the element and the apparatus for manufacturing the element.

[0390] <Semiconductor device> Figure 14C shows a perspective view of the semiconductor device 4700. In the semiconductor device 4700 shown in Figure 14C, a semiconductor chip 4800a is mounted on top of a redistribution layer 4716, and a sealing material 4711 is provided above the redistribution layer 4716 so as to cover the semiconductor chip 4800a. Note that in order to show the inside of the semiconductor device 4700, a portion of the sealing material 4711 is not shown in Figure 14C.

[0391] Figure 14D is a perspective view of the bottom side of the semiconductor device 4700. The bottom surface of the semiconductor device 4700 has, for example, a BGA (Ball Grid Array) designated as bump 4717. Note that the semiconductor device 4700 is not limited to a BGA; it may also have an LGA, PGA, or other type of array.

[0392] Furthermore, the semiconductor device 4700 may be mounted on other boards using various mounting methods, not limited to BGA, LGA, or PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package) may be used.

[0393] Additionally, a heat sink (heat dissipation plate) may be provided on top of the semiconductor device 4700, semiconductor chip 4800a, etc.

[0394] As described above, the semiconductor device 4700 can be manufactured by packaging the semiconductor chip 4800a using FOWLP. The semiconductor device 4700 can be, for example, a high-bandwidth memory (HBM). Furthermore, the semiconductor device 4700 can utilize integrated circuits (semiconductor devices) such as CPUs, GPUs, FPGAs, and memory devices.

[0395] By mounting the semiconductor device 4700 onto a printed circuit board (PCB), circuit boards such as main boards and system boards for electronic devices can be created. Figure 14E shows a perspective view of a board (mounted board 4704) on which the semiconductor device 4700 is mounted, as an example. Also in Figure 14E, the semiconductor device 4700 is mounted on, for example, a printed circuit board 4702. In this way, multiple semiconductor devices are combined and electrically connected on the printed circuit board 4702 to complete the mounted board 4704.

[0396] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0397] (Embodiment 5) This embodiment describes an example of an electronic device having the semiconductor device described in the above embodiment. Figure 15 illustrates, for example, how the semiconductor device 4700 is included in each electronic device.

[0398] [mobile phone] The information terminal 5500 shown in Figure 15 is a type of information terminal, specifically a mobile phone (smartphone). The information terminal 5500 has a housing 5510 and a display unit 5511. For input interfaces, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0399] Although not shown in Figure 15, the information terminal 5500 also includes semiconductor devices such as a memory device, an imaging device, and a display device. For example, by applying a semiconductor device 4700, which has a CML circuit in its redistribution layer, to the information terminal 5500, signals can be transmitted at high speed between the circuits included in the semiconductor device 4700 and the external circuits of the semiconductor device 4700. This increases the processing speed of the information terminal 5500.

[0400] [Wearable devices] Figure 15 also shows a wristwatch-type information terminal 5900 as an example of a wearable device. The information terminal 5900 includes a housing 5901, a display unit 5902, operation buttons 5903, a control element 5904, a band 5905, and the like.

[0401] Similar to the information terminal 5500 mentioned earlier, the processing speed of a wearable device can be increased by applying a semiconductor device 4700 in which a CML circuit is provided in the redistribution layer.

[0402] [Information terminal] Figure 15 also illustrates a desktop information terminal 5300. The desktop information terminal 5300 comprises a main unit 5301, a display 5302, and a keyboard 5303.

[0403] Similar to the information terminal 5500 described above, the desktop information terminal 5300 can reduce the power consumption of its semiconductor device by applying the semiconductor device described in the above embodiment.

[0404] In the above, smartphones, desktop information terminals, and wearable devices were used as examples of electronic devices and illustrated in Figure 15, but other information devices can also be applied. Examples of information devices other than smartphones, desktop information terminals, and wearable devices include PDAs (Personal Digital Assistants), notebook computers, and workstations.

[0405] [electric appliances] Figure 15 also shows an electric refrigerator-freezer 5800 as an example of an electrical appliance. The electric refrigerator-freezer 5800 has a casing 5801, a refrigerator door 5802, a freezer door 5803, etc.

[0406] Furthermore, the electric refrigerator 5800 may be equipped with communication devices and configured to connect to a network. In other words, the electric refrigerator 5800 may be an electronic device compatible with IoT (Internet of Things). Also, by applying a semiconductor device 4700 with a CML circuit in the redistribution layer to the electric refrigerator 5800, for example, the processing speed related to IoT of the electric refrigerator 5800 can be increased.

[0407] In this example, an electric refrigerator was described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction heating (IH) cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0408] [Game console] Figure 15 also shows a portable game console 5200, which is an example of a game console. The portable game console 5200 has a casing 5201, a display unit 5202, buttons 5203, etc.

[0409] Furthermore, Figure 15 illustrates a home console 7500, which is an example of a game console. The home console 7500 has a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a wired connection. Although not shown in Figure 15, the controller 7522 may also be equipped with a display unit for displaying game images, a touch panel as an input interface other than buttons, a joystick, a rotary knob, a sliding knob, etc. Moreover, the shape of the controller 7522 is not limited to the shape shown in Figure 15, and the shape of the controller 7522 may be changed in various ways depending on the genre of game. For example, in shooting games such as FPS (First Person Shooter), a controller with triggers as buttons and a shape that mimics a gun can be used. Also, for example, in music games, a controller with a shape that mimics a musical instrument or musical equipment can be used. Furthermore, home game consoles may not use controllers, but instead be equipped with cameras, depth sensors, microphones, etc., and operated by the game player's gestures and / or voice.

[0410] Furthermore, the video from the aforementioned game console can be output by display devices such as televisions, personal computer displays, game displays, and head-mounted displays.

[0411] By applying a semiconductor device 4700, which has a CML circuit in its redistribution layer, to the portable game console 5200, the processing speed of the portable game console 5200 can be increased.

[0412] Figure 15 illustrates a portable game console as an example of a game console, but the electronic devices of one aspect of the present invention are not limited to this. Examples of electronic devices of one aspect of the present invention include home game consoles, arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), and pitching machines for batting practice installed in sports facilities.

[0413] [Mobile] The semiconductor device described in the above embodiment can be applied to a mobile vehicle and the area around the driver's seat of the vehicle.

[0414] Figure 15 shows an example of a mobile vehicle, the automobile 5700.

[0415] The driver's seat area of ​​the 5700 automobile is equipped with an instrument panel that can display information such as the speedometer, tachometer, odometer, fuel gauge, gear status, and air conditioning settings. Additionally, a display device showing this information may be provided around the driver's seat.

[0416] In particular, by displaying images from an imaging device (not shown) installed in the automobile 5700, the display device can compensate for obstructed views from pillars and other obstructions, as well as blind spots in the driver's seat, thereby enhancing safety. In other words, by displaying images from an imaging device installed on the outside of the automobile 5700, blind spots can be compensated for, and safety can be enhanced.

[0417] The semiconductor device described in the above embodiment can be applied to the instrument panel, imaging device, etc. In particular, by providing a CML circuit in the redistribution layer of the semiconductor device, the processing speed of the instrument panel, imaging device, etc., provided in the automobile 5700 can be increased.

[0418] Although automobiles are described above as an example of a mobile device, mobile devices are not limited to automobiles. For example, mobile devices can also include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and the semiconductor device according to one aspect of the present invention can be applied to these mobile devices to increase processing speed.

[0419] [camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0420] Figure 15 shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation buttons 6243, a shutter button 6244, etc., and a detachable lens 6246 is attached to the digital camera 6240. In this example, the digital camera 6240 is configured so that the lens 6246 can be removed from the housing 6241 and replaced, but the lens 6246 and housing 6241 may be integrated. Furthermore, the digital camera 6240 may be configured to allow for the attachment of a strobe device, viewfinder, etc. separately.

[0421] By applying a semiconductor device 4700, which has a CML circuit in its redistribution layer, to the digital camera 6240, the processing speed of the digital camera 6240 can be increased.

[0422] [Video camera] The semiconductor device described in the above embodiment can be applied to a video camera.

[0423] Figure 15 shows a video camera 6300, which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, operation keys 6304, a lens 6305, a connection unit 6306, etc. The operation keys 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0424] Similar to the digital camera 6240 described above, the processing speed of the video camera 6300 can be increased by applying a semiconductor device 4700 in which a CML circuit is provided in the redistribution layer to the video camera 6300.

[0425] This embodiment can be appropriately combined with other embodiments shown in this specification. [Explanation of Symbols]

[0426] PSD: Semiconductor device, SCD: Die, PR: Insulator, OSL: Layer, HBL: Bump, BSA: Substrate, SIL: Layer, ET: Connector, OTr: Transistor, SIC: Circuit, OSC: Circuit, EXT1: External terminal, EXT2: External terminal, DEV: Circuit, RGCM: Circuit, HSTC: Circuit, CM: Differential amplifier circuit, CM1: Differential amplifier circuit, CM2: Differential amplifier circuit, CM[1]: Differential amplifier circuit, CM[2]: Differential amplifier circuit, CM[n-1]: Differential amplifier circuit, CM[n]: Differential amplifier circuit, CM[m]: Differential amplifier circuit, CM[n+1]: Differential amplifier circuit, CM[m+1] : Differential amplifier circuit, CMA: Differential amplifier circuit, CMB: Differential amplifier circuit, C1P: Capacitor, C1N: Capacitor, LE1A: Load, LE1B: Load, LE2P: Load, LE2N: Load, DTrA: Transistor, DTrB: Transistor, TrC: Transistor, ITrA: Transistor, ITrB: Transistor, DEA: Diode, DEB: Diode, CC: Current source, VBL1: Wiring, VBL2: Wiring, VDE: Wiring, VSE: Wiring, BGE1: Wiring, BGE2: Wiring, VAL: Wiring, OCLN: Terminal, OCLP: Terminal, HIP: Terminal, HIN: Terminal, HON: Terminal, HOP: Terminal, INP: Terminal, INN: Terminal, OUTP: Terminal, OUTN: Terminal, PSD1: Semiconductor device, PSD2: Semiconductor device, PSD3: Semiconductor device, PSD4: Semiconductor device, BSB: Substrate, SB: Support, RL: Release layer, BP: Bump, IJ: Insulating resin, SCL1: Scribe line, SCL2: Scribe line, 300: Transistor, 310: Substrate, 312: Element isolation layer, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator , 326: insulator, 328: conductor, 330: conductor, 332: insulator, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 360: insulator, 362: insulator, 366: conductor, 370: insulator, 376: conductor, 380: insulator, 402: insulator, 406: conductor, 410: insulator, 412: insulator, 414: insulator, 416: conductor, 420: insulator, 422: insulator, 424: insulator, 426: conductor, 430: insulator, 432: insulator, 434: insulator, 436: conductor, 450: conductor, 451: insulator, 452: insulator,454: Insulator, 456: Conductor, 460: Insulator, 462: Insulator, 464: Insulator, 466: Conductor, 470: Insulator, 472: Insulator, 474: Insulator, 476: Conductor, 482: Insulator, 486: Conductor, 492: Insulator, 493: Conductor, 494: Insulator, 495: Insulator, 496: Conductor, 497: Conductor, 500: Transistor, 503: Conductor, 503a: Conductor, 503b: Conductor, 510: Insulator, 512: Insulator, 513: Insulator, 514: Insulator, 516: Insulator, 518: Conductor, 520: Insulator, 522: Insulator 524: insulator, 530: oxide, 530a: oxide, 530b: oxide, 530c: oxide, 540a: conductor, 540b: conductor, 542: conductor, 542a: conductor, 542b: conductor, 543a: region, 543b: region, 544: insulator, 546: conductor, 550: insulator, 552: insulator, 560: conductor, 560a: conductor, 560b: conductor, 574: insulator, 576: insulator, 580: insulator, 581: insulator, 582: insulator, 586: insulator, 4700: semiconductor device, 4702: printed circuit board, 4704: mounted circuit board, 47 11: Encapsulation material, 4716: Redistribution layer, 4717: Bump, 4800: Semiconductor wafer, 4800a: Semiconductor chip, 4801: Wafer, 4801a: Wafer, 4802: Circuit section, 4803: Spacing, 4803a: Spacing, 5200: Portable game console, 5201: Enclosure, 5202: Display unit, 5203: Button, 5300: Desktop information terminal, 5301: Main unit, 5302: Display, 5303: Keyboard, 5500: Information terminal, 5510: Enclosure, 5511: Display unit, 5700: Automobile, 5800: Electric refrigerator / freezer, 5801: 5802: Door for refrigerator compartment, 5803: Door for freezer compartment, 5900: Information terminal, 5901: Casing, 5902: Display unit, 5903: Operation buttons, 5904: Control unit, 5905: Band, 6240: Digital camera, 6241: Casing, 6242: Display unit, 6243: Operation buttons, 6244: Shutter button, 6246: Lens, 6300: Video camera, 6301: Casing, 6302: Casing, 6303: Display unit, 6304: Operation keys, 6305: Lens, 6306: Connection unit, 7500: Home game console, 7520: Main unit, 7522: Controller,

Claims

1. It has a wiring layer with two sides, a semiconductor chip, and an external terminal. The semiconductor chip is provided on one side of the wiring layer, The external terminal is provided in an area on the other side of the wiring layer that does not overlap with the semiconductor chip. The semiconductor chip has a first circuit, The aforementioned wiring layer has a second circuit, The first circuit is electrically connected to the second circuit, The second circuit is electrically connected to the external terminal, The second circuit comprises first to fourth transistors and a current source. Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the first output wiring, The gate of the first transistor is electrically connected to the first wiring, Either the source or the drain of the second transistor is electrically connected to the first wiring. The source or drain of the second transistor, the other of which is electrically connected to the second output wiring, The gate of the second transistor is electrically connected to the first wiring. Either the source or drain of the third transistor is electrically connected to the first output wiring. The source or drain of the third transistor, the other of which is electrically connected to the current source, The gate of the third transistor is electrically connected to the second wiring. Either the source or drain of the fourth transistor is electrically connected to the second output wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the current source, The gate of the fourth transistor is electrically connected to the third wiring. At least one of the first to fourth transistors contains a metal oxide in its channel forming region. Semiconductor equipment.

2. In claim 1, The semiconductor chip has connection terminals, The first circuit and the second circuit are electrically connected via the connection terminals. The pitch width of the external terminal is greater than the pitch width of the connection terminal. Semiconductor equipment.

Images