Semiconductor device and its manufacturing method

Abstract

To provide a technology in which degradation of breakdown voltage is suppressed in a semiconductor device that comprises a connection region connecting a SJ structure and a body region.SOLUTION: A semiconductor device 1 comprises a plurality of second conductivity type connection regions 17 that are provided in a cell part 10A and a boundary part 10B. The plurality of connection regions are arranged between a plurality of bottom regions 14, 15, and a body region 18 in a thickness direction of a semiconductor layer 10, contact with the plurality of bottom regions and the body region, and are repetitively arranged so as to be spaced from each other along at least one direction. This permits drift regions 16 to be arranged between their spaces.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The technology disclosed in this specification relates to a semiconductor device and a method for manufacturing the same.

[0002] The development of semiconductor devices having trench gates has been underway. The semiconductor layer of this type of semiconductor device is partitioned into a cell portion, an outer peripheral portion disposed so as to surround the cell portion, and a boundary portion disposed between the cell portion and the outer peripheral portion so as to surround the cell portion. A trench gate is provided in the cell portion of the semiconductor layer. A breakdown voltage structure such as a guard ring region is provided in the outer peripheral portion of the semiconductor layer. The boundary portion of the semiconductor layer is a region between the cell portion and the outer peripheral portion.

[0003] Patent Document 1 discloses a semiconductor device provided with a super junction structure (hereinafter referred to as "SJ structure") in the cell portion and the boundary portion. The SJ structure is a structure in which n-type regions and p-type regions are alternately and repeatedly arranged along at least one direction. A semiconductor device provided with an SJ structure can achieve both high breakdown voltage and low on-resistance.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a semiconductor device having a trench gate, the SJ structure may be formed at a position deeper than the trench gate. In this case, a p-type connecting region for connecting the p-type region constituting the SJ structure and the p-type body region provided in the surface layer portion of the semiconductor layer is required. This specification provides a technique for suppressing a decrease in breakdown voltage in a semiconductor device provided with a connecting region for connecting the SJ structure and the body region.

Means for Solving the Problems

[0006] The semiconductor device (1, 2, 3) disclosed herein may include a semiconductor layer (10) divided into a cell portion (10A), an outer peripheral portion (10C) arranged to encircle the cell portion, and a boundary portion (10B) between the cell portion and the outer peripheral portion, also arranged to encircle the cell portion, and a ton wrench gate (30) provided on one main surface of the semiconductor layer. The semiconductor layer may have: drift regions (12, 16) of a first conductivity type provided in the cell portion, the boundary portion, and the outer periphery; body regions (18) of a second conductivity type provided in at least the cell portion and the boundary portion and positioned on the drift regions; source regions (19) of a first conductivity type provided in the cell portion and positioned on the body regions; a plurality of bottom regions (14, 15) of a second conductivity type provided in the cell portion and the boundary portion, positioned deeper than the trench gate, and repeatedly arranged at intervals along at least one direction, thereby having the drift regions positioned at their intervals; and a plurality of connecting regions (17) of a second conductivity type provided in the cell portion and the boundary portion, positioned between the plurality of bottom regions and the body regions in the thickness direction of the semiconductor layer, in contact with the plurality of bottom regions and the body regions, and repeatedly arranged at intervals along at least one direction, thereby having the drift regions positioned at their intervals. The trench gate is provided in the cell portion and extends from one main surface of the semiconductor layer beyond the source region and the body region to the drift region located between the plurality of connecting regions.

[0007] In the semiconductor device described above, similar to the cell portion of the semiconductor layer, a plurality of connecting regions are formed at the boundary portion of the semiconductor layer, with a repeating arrangement of these regions spaced apart from each other. As a result, the plurality of connecting regions located at the cell portion and the boundary portion of the semiconductor layer can have a generally uniform shape. This suppresses the occurrence of unintended electric field concentration at the boundary portion of the semiconductor layer, thereby reducing the breakdown voltage.

[0008] This specification further discloses a method for manufacturing a semiconductor device (1, 2, 3) comprising: a semiconductor layer (10) divided into a cell portion (10A), an outer peripheral portion (10C) arranged to encircle the cell portion, and a boundary portion (10B) between the cell portion and the outer peripheral portion, also arranged to encircle the cell portion; and a ton wrench gate (30) provided on one main surface of the semiconductor layer. This manufacturing method may include the steps of: forming a plurality of bottom regions (14, 15) of a second conductivity type on the upper surface of a lower drift region (12) of a first conductivity type; forming an upper drift region (16) of a first conductivity type on the lower drift region and the plurality of bottom regions; patterning a mask on the upper drift region and introducing a second conductivity type impurity to the upper surface of the upper drift region through the mask to form a plurality of bridging regions (17); forming a body region (18) of a second conductivity type on the upper drift region and the plurality of bridging regions; and forming a source region (19) of a first conductivity type on the body region. The lower drift region is provided in the cell portion, the boundary portion and the outer periphery. The plurality of bottom regions are provided in at least the cell portion and the boundary portion, are located deeper than the trench gate, and are repeatedly arranged at intervals along at least one direction, so that the lower drift region is located in those intervals. The upper drift region is provided at least between the cell portion and the boundary portion. The plurality of connecting regions are provided at least between the cell portion and the boundary portion and are repeatedly arranged at intervals along at least one direction, so that the upper drift region is located at these intervals. The trench gate is provided in the cell portion and extends from one main surface of the semiconductor layer, beyond the source region and the body region, to the upper drift region located between the plurality of connecting regions.

[0009] In the above manufacturing method, similar to the cell portion of the semiconductor layer, a plurality of connecting regions are formed in the boundary portion of the semiconductor layer, with intervals between them and repeated arrangements. Therefore, when forming the plurality of connecting regions in the cell portion and the boundary portion of the semiconductor layer, differences in the abrasion depth of the upper surface of the cell portion and the boundary portion due to differences in the size of the mask opening are suppressed. As a result, the plurality of connecting regions arranged in the cell portion and the boundary portion of the semiconductor layer can have a generally uniform shape. As a result, the occurrence of unintended electric field concentration in the boundary portion of the semiconductor layer is suppressed, and the breakdown voltage is suppressed. [Brief explanation of the drawing]

[0010] [Figure 1] This diagram shows the positional relationship between the cell portions, boundary portions, and outer periphery portions of a semiconductor layer when viewed from a planar perspective. [Figure 2] This is a cross-sectional view of the main part of the semiconductor device of the first embodiment, schematically showing the cross-sectional view corresponding to the line II-II in Figure 1. [Figure 3] This diagram schematically shows a perspective view of the main part of the cell section of a semiconductor layer. [Figure 4] This figure shows the layout of the guard ring region, boundary bottom region, cell bottom region, and connecting region of the semiconductor device according to the first embodiment. [Figure 5] This diagram shows a flowchart of the manufacturing process for semiconductor devices. [Figure 6] This diagram schematically shows a cross-sectional view of the main parts of the manufacturing process for a comparative example semiconductor device. [Figure 7] This diagram schematically shows a cross-sectional view of the main parts of the manufacturing process for a comparative example semiconductor device. [Figure 8] This diagram schematically shows a cross-sectional view of the main parts of the manufacturing process for a comparative example semiconductor device. [Figure 9] This is a cross-sectional view of the main part of the semiconductor device of the second embodiment, schematically showing the cross-sectional view corresponding to the line II-II in Figure 1. [Figure 10]This figure shows the layout of the guard ring region, boundary bottom region, cell bottom region, and connecting region of the semiconductor device according to the second embodiment. [Figure 11] This figure shows the layout of the guard ring region, boundary bottom region, cell bottom region, and connecting region of the semiconductor device according to the third embodiment. [Modes for carrying out the invention]

[0011] Hereinafter, semiconductor devices to which the technology disclosed herein is applied and methods for manufacturing the same will be described with reference to the drawings. In the following drawings, for the purpose of clarity, only some of the common components may be denoted by reference numerals. Also, common components in each embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0012] (First Embodiment) As shown in Figures 1-3, the semiconductor device 1 is a type of power device called a MOSFET and is constructed using a semiconductor layer 10. The material of the semiconductor layer 10 is not particularly limited, but may be silicon carbide (SiC), for example. The semiconductor device 1 may also be a type of power device called an IGBT.

[0013] As shown in Figure 1, when the semiconductor layer 10 is viewed from above (hereinafter referred to as "when viewed from above"), it is divided into a cell portion 10A, a boundary portion 10B, and an outer peripheral portion 10C. The cell portion 10A is a region divided in the central inner part of the semiconductor layer 10, and as will be described later, it is a region in which a switching structure is formed. The boundary portion 10B is a region divided between the cell portion 10A and the outer peripheral portion 10C, and encircles the cell portion 10A. The outer peripheral portion 10C is a region divided around the cell portion 10A and the boundary portion 10B, and encircles the cell portion 10A and the boundary portion 10B. As will be described later, a breakdown voltage structure is formed in the outer peripheral portion 10C.

[0014] As shown in FIG. 2, the semiconductor device 1 includes a semiconductor layer 10, a drain electrode 22, a source electrode 24, and a plurality of trench gates 30. The semiconductor layer 10 has a drain region 11, a lower drift region 12, a plurality of guard ring regions 13, a plurality of boundary bottom regions 14, a plurality of cell bottom regions 15, an upper drift region 16, a plurality of connecting regions 17, a body region 18, a plurality of source regions 19, and a plurality of contact regions 20. Here, the cell portion 10A is a region where a plurality of trench gates 30 are provided, and is a region where current flows between the drain electrode 22 and the source electrode 24. The outer peripheral portion 10C is a region where a plurality of guard ring regions 13 are provided, and is a region outside the innermost guard ring region 13. The boundary portion 10B is a region between the cell portion 10A and the outer peripheral portion 10C, and is a region from the outermost peripheral end of the trench gate 30 provided in the cell portion 10A to the innermost guard ring region 13 of the outer peripheral portion 10C.

[0015] The upper surface of the semiconductor layer 10 is processed in a concave shape in a range corresponding to the outer peripheral portion 10C, and a step is formed between the boundary portion 10B and the outer peripheral portion 10C. In other words, the cell portion 10A and the boundary portion 10B of the semiconductor layer 10 are configured in a mesa shape and protrude above the upper surface of the outer peripheral portion 10C.

[0016] The drain electrode 22 is provided so as to cover the lower surface of the semiconductor layer 10. The drain electrode 22 is disposed across the cell portion 10A, the boundary portion 10B, and the outer peripheral portion 10C, and is in contact with the entire lower surface of the semiconductor layer 10.

[0017] The source electrode 24 is provided so as to cover the upper surface of the semiconductor layer 10. The source electrode 24 is disposed across a part of the cell portion 10A and the boundary portion 10B, and is in contact with the upper surface of the semiconductor layer 10 exposed from an opening in an interlayer insulating film formed on the upper surface of the semiconductor layer 10.

[0018] The drain region 11 is an n-type region containing a high concentration of n-type impurities. The drain region 11 is provided across the cell portion 10A, the boundary portion 10B, and the outer peripheral portion 10C, and is disposed on the lower surface of the semiconductor layer 10. The drain region 11 makes an ohmic contact with the drain electrode 22.

[0019] The lower drift region 12 is an n-type region having an n-type impurity concentration lower than that of the drain region 11. The lower drift region 12 is provided across the cell portion 10A, the boundary portion 10B, and the outer peripheral portion 10C. The lower drift region 12 is formed, for example, by crystal growth from the surface of the drain region 11 using a crystal growth technique. The lower drift region 12, together with the upper drift region 16 described later, is referred to as a drift region.

[0020] The plurality of guard ring regions 13 are p-type regions containing p-type impurities. Each of the plurality of guard ring regions 13 is provided in the outer peripheral portion 10C and is arranged to go around the cell portion 10A and the periphery of the boundary portion 10B along the outer peripheral portion 10C (see FIG. 4). The plurality of guard ring regions 13 are repeatedly arranged at intervals along the inner-outer direction (the direction connecting the center of the cell portion 10A and the outer peripheral portion 10C) when the semiconductor layer 10 is viewed in plan. A part of the lower drift region 12 is disposed between adjacent guard ring regions 13. The plurality of guard ring regions 13 are formed, for example, by introducing p-type impurities into a part of the upper surface of the lower drift region 12 using an ion implantation technique. The plurality of guard ring regions 13 are an example of a breakdown voltage structure. The potentials of the plurality of guard ring regions 13 are floating.

[0021] The multiple boundary bottom regions 14 are p-type regions containing p-type impurities. Each of the multiple boundary bottom regions 14 is located in the boundary 10B and is arranged to encircle the cell 10A along the boundary 10B (see Figure 4). The multiple boundary bottom regions 14 are located deeper than the trench gate 30. When the semiconductor layer 10 is viewed from above, the multiple boundary bottom regions 14 are repeatedly arranged with spacing along the inward and outward directions. A portion of the lower drift region 12 is located between adjacent boundary bottom regions 14. The multiple boundary bottom regions 14 and the portion of the lower drift region 12 located between them have their width and impurity concentration adjusted to achieve charge balance, forming an SJ structure. The portion of the lower drift region 12 located between adjacent boundary bottom regions 14 may have a higher impurity concentration than other areas of the lower drift region 12. Multiple boundary bottom regions 14 are formed, for example, by introducing p-type impurities into a portion of the upper surface of the lower drift region 12 using ion implantation technology. The multiple boundary bottom regions 14, together with the multiple cell bottom regions 15 described later, are referred to as the bottom region.

[0022] As shown in Figures 2 and 3, the multiple cell bottom regions 15 are p-type regions containing p-type impurities. Each of the multiple cell bottom regions 15 is provided in the cell portion 10A and is located deeper than the trench gate 30. When the semiconductor layer 10 is viewed in plan, the multiple cell bottom regions 15 extend along at least one direction (in this example, the y-direction, which is perpendicular to the longitudinal direction of the trench gate 30) and are repeatedly arranged at intervals along a direction perpendicular to that direction (in this example, the x-direction, which is parallel to the longitudinal direction of the trench gate 30). A portion of the lower drift region 12 is located between adjacent cell bottom regions 15. The multiple cell bottom regions 15 and the portion of the lower drift region 12 located between them have their width and impurity concentration adjusted to achieve charge balance, forming an SJ structure. Furthermore, a portion of the lower drift region 12 located between adjacent cell bottom regions 15 may be adjusted to have a higher concentration of n-type impurities than other portions of the lower drift region 12. Multiple cell bottom regions 15 are formed, for example, by introducing p-type impurities into a portion of the upper surface of the lower drift region 12 using ion implantation technology.

[0023] The upper drift region 16 is an n-type region containing n-type impurities. The upper drift region 16 extends across the cell portion 10A and the boundary portion 10B. The concentration of n-type impurities in the upper drift region 16 may be the same as that of the lower drift region 12, or it may be more concentrated than that of the lower drift region 12. The upper drift region 16 is in contact with the bottom surface and the lower portion of the sides of the trench gate 30. The upper drift region 16 is also in contact with a portion of the lower drift region 12, which is located between adjacent cell bottom regions 15. The upper drift region 16 is formed, for example, by crystal growth from the upper surfaces of the lower drift region 12 and bottom regions 14 and 15 using crystal growth technology.

[0024] The multiple bonding regions 17 are p-type regions containing p-type impurities. The multiple bonding regions 17 are provided across the cell portion 10A and the boundary portion 10B, and are positioned between the multiple bottom regions 14, 15 and the body region 18 in the thickness direction (z-direction in this example) of the semiconductor layer 10. Each of the multiple bonding regions 17 is in contact with the multiple bottom regions 14, 15 on its lower surface and in contact with the body region 18 on its upper surface. As a result, the multiple bottom regions 14, 15 are electrically connected to the body region 18 via the multiple bonding regions 17. Each of the multiple bonding regions 17 extends in a direction different from the longitudinal direction of the cell portion bottom region 15 when the semiconductor layer 10 is viewed from above. In this example, each of the multiple bonding regions 17 extends along a direction perpendicular to the longitudinal direction of the cell bottom region 15 when the semiconductor layer 10 is viewed from above (in this example, the x-direction, which is parallel to the longitudinal direction of the trench gate 30), and is repeatedly arranged at intervals along a direction perpendicular to that direction (in this example, the y-direction, which is perpendicular to the longitudinal direction of the trench gate 30). Upper drift regions 16 are arranged between adjacent bonding regions 17. The multiple bonding regions 17 are formed, for example, by introducing p-type impurities into a portion of the upper surface of the upper drift regions 16 using ion implantation technology.

[0025] As shown in Figure 4, each of the multiple connecting regions 17 extends along the x-direction when the semiconductor layer 10 is viewed in plan view. Parts of the multiple connecting regions 17 extend beyond the cell portion 10A to the boundary portion 10B. Parts of the multiple connecting regions 17 intersect each of the multiple cell portion bottom regions 15 and also intersect each of the multiple boundary portion bottom regions 14.

[0026] As shown in Figures 2 and 3, the body region 18 is a p-type region containing p-type impurities. The body region 18 extends across the cell portion 10A and the boundary portion 10B and is located on the upper drift region 16 and a plurality of connecting regions 17. The body region 18 is in contact with the side surface of the trench gate 30 and separates the upper drift region 16 from the source region 19. The body region 18 is formed, for example, by crystal growth from the upper surface of the upper drift region 16 using crystal growth technology.

[0027] The multiple source regions 19 are n-type regions containing high concentrations of n-type impurities. The multiple source regions 19 are provided in the cell portion 10A and are located on the body region 18 and on the upper surface of the semiconductor layer 10. Each of the multiple source regions 19 is in contact with the upper portion of the side surface of the trench gate 30. Each of the multiple source regions 19 extends parallel to the longitudinal direction of the trench gate 30 when the semiconductor layer 10 is viewed from above. Each of the multiple source regions 19 is exposed through an opening in the interlayer insulating film formed on the upper surface of the semiconductor layer 10 and is in ohmic contact with the source electrode 24. The multiple source regions 19 are formed by n-type layers grown from the upper surface of the body region 18 using, for example, crystal growth technology.

[0028] The multiple contact regions 20 are p-type regions containing a higher concentration of p-type impurities than the body region 18. The multiple contact regions 20 are provided in the cell portion 10A and are located on the body region 18 and on the upper surface of the semiconductor layer 10. Each of the multiple contact regions 20 extends parallel to the longitudinal direction of the trench gate 30 when the semiconductor layer 10 is viewed from above. Each of the multiple contact regions 20 is exposed through an opening in the interlayer insulating film formed on the upper surface of the semiconductor layer 10 and is in ohmic contact with the source electrode 24. The multiple contact regions 20 are formed, for example, by introducing p-type impurities into the n-type layer for forming the source region 19 using ion implantation technology. The multiple source regions 19 are formed as the remainder after ion implantation of the multiple contact regions 20 into the n-type layer.

[0029] Multiple trench gates 30 are provided in the cell portion 10A and extend from the upper surface of the semiconductor layer 10 beyond the source region 19 and body region 18 to the upper drift region 16. When the semiconductor layer 10 is viewed from above, the multiple trench gates 30 extend along at least one direction (the x-direction in this example) and are repeatedly arranged at intervals along a direction perpendicular to that direction (the y-direction in this example). In this way, when the semiconductor layer 10 is viewed from above, the multiple trench gates 30 are arranged in a stripe pattern. Note that the stripe pattern is just one example, and the multiple trench gates 30 may be arranged in other layouts. Each of the multiple trench gates 30 has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 is insulated from the upper drift region 16, body region 18 and source region 19 by the gate insulating film 34, and is insulated from the source electrode 24 by the interlayer insulating film.

[0030] Thus, the cell section 10A has a switching structure formed by a drain electrode 22, a drain region 11, a lower drift region 12, a cell section bottom region 15, an upper drift region 16, a connecting region 17, a body region 18, a source region 19, a contact region 20, a source electrode 24, and a trench gate 30, etc.

[0031] Next, the operation of the semiconductor device 1 will be described. When a voltage is applied between the drain and source such that the drain electrode 22 is at a higher potential than the source electrode 24, and a voltage greater than or equal to the gate threshold voltage is applied to the gate electrode 32, a channel is formed in the body region 18 adjacent to the gate insulating film 34. Electrons supplied from the source region 19 flow into the upper drift region 16 through this channel. Electrons that have flowed into the upper drift region 16 flow to the drain region 11 through the lower drift region 12. As a result, conduction occurs between the drain electrode 22 and the source electrode 24, and the semiconductor device 1 turns on. On the other hand, when a voltage less than the gate threshold voltage is applied to the gate electrode 32, the channel disappears, and the semiconductor device 1 turns off. In this way, the semiconductor device 1 can operate as a switching element that controls the current flowing between the drain electrode 22 and the source electrode 24 according to the voltage applied to the gate electrode 32.

[0032] Next, referring to Figure 5, some of the manufacturing processes for semiconductor device 1 will be described. Other processes can be conventionally known processes.

[0033] First, in step S1, a SiC substrate that functions as a drain region 11 is prepared, and the lower drift region 12 is formed by crystal growth from the upper surface of the drain region 11 using crystal growth technology.

[0034] Next, in step S2, after patterning the mask on the lower drift region 12, ion implantation is used to introduce p-type impurities into a portion of the upper surface of the lower drift region 12 through the mask to form the guard ring region 13, the boundary bottom region 14, and the cell bottom region 15. After ion implantation, the mask is removed. Note that the steps for forming the guard ring region 13 and the steps for forming the boundary bottom region 14 and the cell bottom region 15 may be performed separately.

[0035] Next, in step S3, the upper drift region 16 is formed by crystal growth from the upper surface of the lower drift region 12, which includes the guard ring region 13, the boundary bottom region 14, and the cell bottom region 15, using crystal growth technology.

[0036] Next, in step S4, after patterning the mask on the upper drift region 16, ion implantation is used to introduce p-type impurities into a portion of the upper surface of the upper drift region 16 through the mask to form a binding region 17. After ion implantation, the mask is removed.

[0037] Next, in step S5, a body region 18 is formed by crystal growth from the upper surface of the upper drift region 16, which includes multiple connecting regions 17, using crystal growth technology.

[0038] Next, in step S6, an n-type layer is formed by crystal growth from the upper surface of the body region 18 using crystal growth technology. Then, p-type impurities are introduced into a portion of the n-type layer using ion implantation technology to form contact regions 20. The remaining portion of the n-type layer after ion implantation of multiple contact regions 20 becomes multiple source regions 19.

[0039] Next, in step S7, a trench gate 30 is formed that extends beyond the source region 19 and the body region 18 to the upper drift region 16.

[0040] Subsequently, the drain electrode 22 and source electrode 24, etc., can be formed to complete the semiconductor device 1.

[0041] Next, the multiple junction regions 17 will be described. The multiple junction regions 17 located in the cell portion 10A are repeatedly arranged at intervals in the planar direction of the semiconductor layer 10 in order to secure a current path, that is, to provide an upper drift region 16. On the other hand, the boundary portion 10B is not a region where current flows, so such a junction region 17 is not necessary in the boundary portion 10B. For example, it is conceivable to form a single junction region 17 that extends over the entire area of ​​the boundary portion 10B. However, it has been found that when such a single junction region 17 is formed in the boundary portion 10B, the following problems arise.

[0042] Referring to Figures 6-8, the problem of the comparative example in which a single connecting region 17 is formed at the boundary portion 10B will be explained. Figures 6-8 are cross-sectional views of key parts corresponding to the boundary between the cell portion 10A and the boundary portion 10B, and correspond to the diagrams used to explain the process of step S4 in Figure 5 of the comparative example.

[0043] First, as shown in Figure 6, a mask 42 is deposited on the upper drift region 16. Next, as shown in Figure 7, the mask 42 is patterned. The openings formed in the mask 42 of the boundary region 10B correspond to a single connecting region 17 and are wider than the openings formed in the mask 42 of the cell region 10A. Therefore, during etching to form the openings in the mask 42, more etchant is supplied to the upper surface of the boundary region 10B than to the upper surface of the cell region 10A. As a result, the depth D1 to which the upper surface of the boundary region 10B is removed is greater than the depth D2 to which the upper surface of the cell region 10A is removed, and the upper surface of the boundary region 10B is removed more deeply than the upper surface of the cell region 10A. Next, as shown in Figure 8, ion implantation technology is used to introduce p-type impurities into a part of the upper drift region 16 to form a connecting region 17. In this case, since the upper surface of the boundary portion 10B is eroded more deeply than the upper surface of the cell portion 10A, the single connecting region 17 formed in the boundary portion 10B is formed deeper than the multiple connecting regions 17 formed in the cell portion 10A. Thus, in the comparative example in which a single connecting region 17 is formed in the boundary portion 10B, the depth of the connecting region 17 between the cell portion 10A and the boundary portion 10B will vary in plane, and there is a concern that unintended electric field concentration will occur, particularly in the boundary portion 10B, leading to a decrease in withstand voltage.

[0044] On the other hand, in the semiconductor device 1 of this embodiment, similar to the cell portion 10A, multiple connecting regions 17 are formed in the boundary portion 10B, which are repeatedly arranged at intervals from each other. Therefore, the multiple connecting regions 17 arranged in the cell portion 10A and the boundary portion 10B can have a generally uniform shape. As a result, the occurrence of unintended electric field concentration in the boundary portion 10B is suppressed, and the breakdown voltage is suppressed. In order to suppress in-plane variation as in the above comparative example, the width in the short direction of the multiple connecting regions 17 arranged in the boundary portion 10B (width in the y direction in Figure 2) may be 10 times or less the width in the short direction of the multiple connecting regions 17 arranged in the cell portion (width in the y direction in Figure 2).

[0045] (Second Embodiment) Figures 9 and 10 show the semiconductor device 2 of the second embodiment. Similar to the semiconductor device 1 of the first embodiment, in the semiconductor device 2, each of the multiple boundary bottom regions 14 is arranged to encircle the cell region 10A along the boundary 10B. Therefore, each of the multiple boundary bottom regions 14 has a portion extending along the x-direction and a portion extending along the y-direction when the semiconductor layer 10 is viewed in plan view.

[0046] Each of the multiple connecting regions 17 extends along the x-direction when the semiconductor layer 10 is viewed from above. Therefore, in the parts where each of the multiple boundary bottom regions 14 extends along the y-direction, each of the multiple connecting regions 17 extends perpendicularly to each of the multiple boundary bottom regions 14 located below it when the semiconductor layer 10 is viewed from above, and intersects with each of the multiple boundary bottom regions 14. As a result, the multiple boundary bottom regions 14 and the multiple connecting regions 17 can come into contact over many areas. Furthermore, in the parts where each of the multiple boundary bottom regions 14 extends along the x-direction, each of the multiple connecting regions 17 extends parallel to the corresponding bottom region 14 located below it when the semiconductor layer 10 is viewed from above. As a result, the multiple boundary bottom regions 14 and the multiple connecting regions 17 can come into contact over a large area.

[0047] In the semiconductor device 2, at the boundary portion 10B, multiple connecting regions 17 and multiple boundary bottom regions 14 can be in contact over a large area, thus stabilizing the potential of the boundary bottom region 14.

[0048] (Third embodiment) Figure 11 shows a semiconductor device 3 of the third embodiment. In the semiconductor device 3, in the portion where each of the multiple boundary bottom regions 14 extends along the y-direction, each of the multiple connecting regions 17 extends perpendicularly to each of the multiple boundary bottom regions 14 located below it when the semiconductor layer 10 is viewed from above, and intersects with each of the multiple boundary bottom regions 14. Similarly, in the portion where each of the multiple boundary bottom regions 14 extends along the x-direction, each of the multiple connecting regions 17 extends perpendicularly to each of the multiple boundary bottom regions 14 located below it when the semiconductor layer 10 is viewed from above, and intersects with each of the multiple boundary bottom regions 14. Note that in the portion where each of the multiple boundary bottom regions 14 extends along the x-direction, each of the multiple connecting regions 17 may extend in a direction that is inclined with respect to each of the multiple boundary bottom regions 14 located below it when the semiconductor layer 10 is viewed from above.

[0049] In the semiconductor device 3, multiple connecting regions 17 and multiple boundary bottom regions 14 can be in contact over many areas at the boundary region 10B, thus stabilizing the potential of the boundary bottom region 14.

[0050] The features of the technology disclosed herein are summarized below. Note that the technical elements described below are independent elements that exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

[0051] (Feature 1) A semiconductor device disclosed herein may include a semiconductor layer divided into a cell portion, an outer peripheral portion arranged to encircle the cell portion, and a boundary portion between the cell portion and the outer peripheral portion, also arranged to encircle the cell portion, and a Tonle Wrench gate provided on one main surface of the semiconductor layer. The semiconductor layer may have: a drift region of a first conductivity type provided in the cell portion, the boundary portion, and the outer periphery; a body region of a second conductivity type provided in at least the cell portion and the boundary portion and positioned on the drift region; a source region of a first conductivity type provided in the cell portion and positioned on the body region; a plurality of bottom regions of a second conductivity type provided in the cell portion and the boundary portion, positioned deeper than the trench gate, and repeatedly arranged at intervals along at least one direction, thereby positioning the drift region between them; and a plurality of connecting regions of a second conductivity type provided in the cell portion and the boundary portion, positioned between the plurality of bottom regions and the body region in the thickness direction of the semiconductor layer, in contact with the plurality of bottom regions and the body region, and repeatedly arranged at intervals along at least one direction, thereby positioning the drift region between them. The trench gate is provided in the cell portion and extends from one main surface of the semiconductor layer beyond the source region and the body region to the drift region located between the plurality of connecting regions.

[0052] (Feature 2) In the semiconductor device of Feature 1, each of the multiple bottom regions located in the cell portion of the multiple bottom regions may be repeatedly arranged at intervals along a first direction when the semiconductor layer is laid flat. Furthermore, each of the multiple bottom regions located in the boundary portion of the multiple bottom regions may be repeatedly arranged at intervals along the inward and outward directions, encircling the cell portion. Furthermore, each of the multiple connecting regions located in the cell portion of the multiple connecting regions may be repeatedly arranged at intervals along a second direction different from the first direction when the semiconductor layer is laid flat.

[0053] (Feature 3) In the semiconductor device of Feature 2, each of the plurality of connecting regions located at the boundary of the plurality of connecting regions may extend parallel to the corresponding bottom region located below it when the semiconductor layer is viewed in plan view.

[0054] (Feature 4) In the semiconductor device of feature 2 or 3, each of the plurality of connecting regions located at the boundary of the plurality of connecting regions may extend so as to intersect with each of the plurality of bottom regions located below it when the semiconductor layer is viewed in plan view.

[0055] (Feature 5) In the semiconductor device of Feature 4, each of the plurality of connecting regions located at the boundary of the plurality of connecting regions may extend in a direction orthogonal to each of the plurality of bottom regions located below it when the semiconductor layer is viewed in plan view.

[0056] (Feature 6) In the semiconductor device described in any one of features 1 to 5, the width in the short direction of the plurality of connecting regions located at the boundary of the plurality of connecting regions may be 10 times or less the width in the short direction of the plurality of connecting regions located at the cell portion of the plurality of connecting regions.

[0057] (Feature 7) In the semiconductor device described in any one of features 1 to 6, the semiconductor layer may be silicon carbide.

[0058] (Feature 8) A semiconductor device manufacturing method disclosed herein is a semiconductor device manufacturing method comprising: a cell portion; an outer peripheral portion arranged to encircle the cell portion; a boundary portion located between the cell portion and the outer peripheral portion and also encircling the cell portion; and a ton wrench gate provided on one main surface of the semiconductor layer. This manufacturing method may include the steps of: forming a plurality of bottom regions of a second conductivity type on the upper surface of a lower drift region of a first conductivity type; forming an upper drift region of a first conductivity type on the lower drift region and the plurality of bottom regions; patterning a mask on the upper drift region and introducing a second conductivity type impurity to the upper surface of the upper drift region via the mask to form a plurality of connecting regions; forming a body region of a second conductivity type on the upper drift region and the plurality of connecting regions; and forming a source region of a first conductivity type on the body region. The lower drift region is provided in the cell portion, the boundary portion, and the outer peripheral portion. The plurality of bottom regions are provided at least between the cell portion and the boundary portion, are located deeper than the trench gate, and are repeatedly spaced apart along at least one direction, so that the lower drift regions are located in those spaces. The upper drift regions are provided at least between the cell portion and the boundary portion. The plurality of connecting regions are provided at least between the cell portion and the boundary portion, and are repeatedly spaced apart along at least one direction, so that the upper drift regions are located in those spaces. The trench gate is provided in the cell portion and extends from one main surface of the semiconductor layer beyond the source region and the body region to the upper drift regions located between the plurality of connecting regions.

[0059] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]

[0060] 1, 2, 3: Semiconductor device, 10: Semiconductor layer, 10A: Cell region, 10B: Boundary region, 10C: Outer periphery, 11: Drain region, 12: Lower drift region, 13: Guard ring region, 14: Boundary bottom region, 15: Cell bottom region, 16: Upper drift region, 17: Connecting region, 18: Body region, 19: Source region, 20: Contact region, 22: Drain electrode, 24: Source electrode, 30: Trench gate

Claims

1. Semiconductor devices (1, 2, 3), A semiconductor layer (10) is divided into a cell portion (10A), an outer peripheral portion (10C) arranged to encircle the cell portion, and a boundary portion (10B) located between the cell portion and the outer peripheral portion and also encircling the cell portion. The semiconductor layer comprises a plurality of trench gates (30) provided on one main surface of the semiconductor layer, The aforementioned semiconductor layer is The first conductivity type drift regions (12, 16) provided in the cell portion, the boundary portion, and the outer periphery, A second conductive body region (18) is provided at least in the cell portion and the boundary portion and is located on the drift region, A first conductivity type source region (19) is provided in the cell portion and is arranged on the body region, A plurality of bottom regions (14, 15) of the second conductivity type provided in the cell portion and the boundary portion, which are located deeper than the plurality of trench gates and are repeatedly arranged at intervals along an arbitrary direction, A plurality of second conductivity type connecting regions (17) provided in the cell portion and the boundary portion, wherein the plurality of connecting regions are arranged between the plurality of bottom regions and the body region in the thickness direction of the semiconductor layer, are in contact with the plurality of bottom regions and the body region, and are repeatedly arranged at intervals along an arbitrary direction, The outer periphery is provided with a plurality of second conductivity type guard ring regions (13), which, when the semiconductor layer is viewed in plan view, are arranged repeatedly at intervals along the inward and outward directions, encircling the cell portion and the boundary portion. The plurality of trench gates are provided in the cell portion and extend from one main surface of the semiconductor layer beyond the source region and the body region. The boundary portion is defined as the region from the outermost end of the trench gate to the innermost guard ring region, The plurality of connecting regions include a plurality of connecting regions located in the cell portion and a plurality of connecting regions located in the boundary portion, wherein the plurality of connecting regions include a plurality of connecting regions located in the cell portion.

2. (1) The impurity concentration of the first conductivity type in the region located between the bottom regions is different from the impurity concentration of the first conductivity type in the drift region located below the bottom region. (2) The impurity concentration of the first conductivity type in the region located between the connecting regions is different from the impurity concentration of the first conductivity type in the drift region located below the bottom region. A semiconductor device according to claim 1, satisfying at least one of (1) and (2) above.

3. The semiconductor device according to claim 2, wherein the impurity concentration of the first conductivity type in the region located between the bottom regions is higher than the impurity concentration of the first conductivity type in the drift region located below the bottom regions.

4. The semiconductor device according to claim 2, wherein the impurity concentration of the first conductivity type in the region located between the connecting regions is higher than the impurity concentration of the first conductivity type in the drift region located below the bottom region.

5. Of the plurality of bottom regions, the plurality of bottom regions located in the cell portion are arranged repeatedly at intervals along the first direction when the semiconductor layer is viewed in plan view. The multiple bottom regions located at the boundary of the multiple bottom regions are arranged in a planar view of the semiconductor layer, and are repeatedly arranged with intervals along the inward and outward directions, encircling the cell portion. The semiconductor device according to claim 1, wherein each of the plurality of connecting regions located in the cell portion of the plurality of connecting regions is repeatedly arranged at intervals along a second direction different from the first direction when the semiconductor layer is viewed in plan view.

6. The semiconductor device according to claim 5, wherein each of the plurality of connecting regions located at the boundary of the plurality of connecting regions extends parallel to the corresponding bottom region so as to overlap with the corresponding bottom region located below the semiconductor layer when the semiconductor layer is viewed in plan view.

7. The semiconductor device according to claim 5, wherein each of the plurality of connecting regions located at the boundary of the plurality of connecting regions extends so as to intersect with each of the plurality of bottom regions located below the semiconductor layer when the semiconductor layer is viewed in plan view.

8. The semiconductor device according to claim 7, wherein each of the plurality of connecting regions located at the boundary of the plurality of connecting regions extends in a direction perpendicular to each of the plurality of bottom regions located below the semiconductor layer when viewed in plan.

9. The semiconductor device according to any one of claims 1 to 8, wherein the width in the short direction of the plurality of connecting regions located at the boundary of the plurality of connecting regions is 10 times or less the width in the short direction of the plurality of connecting regions located at the cell portion of the plurality of connecting regions.

10. The semiconductor device according to claim 1, wherein the semiconductor layer is silicon carbide.

11. A semiconductor layer (10) is divided into a cell portion (10A), an outer peripheral portion (10C) arranged to encircle the cell portion, and a boundary portion (10B) located between the cell portion and the outer peripheral portion and also encircling the cell portion. A method for manufacturing a semiconductor device (1, 2, 3) comprising a plurality of trench gates (30) provided on one main surface of the semiconductor layer, The process involves forming a plurality of bottom regions (14, 15) and a plurality of guard ring regions (13) of the second conductivity type on the upper surface of the lower drift region (12) of the first conductivity type, The process of forming an upper drift region (16) of the first conductivity type on the lower drift region and the plurality of bottom regions, The process involves patterning a mask on the upper drift region, introducing a second conductivity type impurity to the upper surface of the upper drift region through the mask, and forming a plurality of connecting regions (17). A step of forming a second conductive body region (18) on the upper drift region and the plurality of connecting regions, The process includes the step of forming a first conductivity type source region (19) on the body region, The lower drift region is provided in the cell portion, the boundary portion, and the outer periphery. The plurality of bottom regions are provided at least in the cell portion and the boundary portion, are located deeper than the trench gate, and are repeatedly arranged at intervals along any direction. The upper drift region is provided at least between the cell portion and the boundary portion, The plurality of connecting regions are provided at least between the cell portion and the boundary portion, and are repeatedly arranged at intervals along any direction. The plurality of guard ring regions are provided on the outer periphery and, when the semiconductor layer is viewed in plan, are arranged repeatedly at intervals along the inward and outward directions, encircling the cell portion and the boundary portion. The plurality of trench gates are provided in the cell portion and extend from one main surface of the semiconductor layer beyond the source region and the body region. The boundary portion is defined as the region from the outermost end of the trench gate to the innermost guard ring region, A method for manufacturing a semiconductor device, wherein the plurality of connecting regions include a plurality of connecting regions arranged in the cell portion and a plurality of connecting regions arranged in the boundary portion.

12. (1) The impurity concentration of the first conductivity type in the region located between the bottom regions is different from the impurity concentration of the first conductivity type in the lower drift region located below the bottom region. (2) The impurity concentration of the first conductivity type in the region located between the connecting regions is different from the impurity concentration of the first conductivity type in the lower drift region located below the bottom region. A method for manufacturing a semiconductor device according to claim 11, which satisfies at least one of (1) and (2) above.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the impurity concentration of the first conductivity type in the region located between the bottom regions is higher than the impurity concentration of the first conductivity type in the lower drift region located below the bottom regions.

14. The method for manufacturing a semiconductor device according to claim 12 or 13, wherein the impurity concentration of the first conductivity type in the region arranged between the connecting regions is higher than the impurity concentration of the first conductivity type in the lower drift region arranged below the bottom region.

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