Multilayer electronic components

Abstract

To provide a multilayer electronic component which is excellent in reliability, is improved in electrostatic capacity, is excellent in a high-temperature load life, suppresses internal electrode coagulation phenomenon and internal electrode breakage phenomenon, improves dose and crystal grain size distribution, and improves insulation resistance distribution.SOLUTION: A multilayer electronic component according to an embodiment of the present invention includes: a body including a plurality of dielectric layers and a plurality of internal electrodes alternately disposed with the dielectric layers in a first direction; and external electrodes disposed on the body, where the plurality of internal electrodes includes Ni and In. In one or more of the plurality of internal electrodes, ratio of points having molar ratio of In / (Ni+In) of 0.002 or more among points 10 nm away from an interface with the dielectric layer may be 70% or more, and ratio of points having molar ratio of In / (Ni+In) of 0.002 or more among points of a center portion in the first direction may be 35% or less.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] This invention relates to a stacked electronic component. [Background technology]

[0002] A multilayer ceramic capacitor (MLCC), a type of multilayer electronic component, is a chip-type capacitor that is mounted on the printed circuit boards of various electronic products such as liquid crystal displays (LCDs) and plasma display panels (PDPs), computers, smartphones, and mobile phones, and plays the role of charging or discharging electricity.

[0003] Multilayer ceramic capacitors offer the advantages of being small yet guaranteeing high capacitance and being easy to mount, making them suitable for use as components in various electronic devices. As electronic devices such as computers and mobile devices become smaller and more powerful, the demand for smaller and higher-capacitance multilayer ceramic capacitors is increasing.

[0004] With the trend toward miniaturization and increased capacitance of multilayer ceramic capacitors, the importance of increasing the capacitance per unit volume of multilayer ceramic capacitors is increasing. To achieve miniaturization and increased capacitance of multilayer ceramic capacitors, it is necessary to reduce the thickness of the dielectric layer and internal electrodes and increase the number of layers. Furthermore, to improve the reliability of multilayer ceramic capacitors, the connectivity of the internal electrodes must be high and the thickness of the internal electrodes must be uniform.

[0005] However, when using finer metal powder than conventional methods to reduce the thickness of the internal electrodes, the sintering shrinkage initiation temperature becomes lower, leading to a greater mismatch in shrinkage behavior with the dielectric layer, which can cause internal electrode aggregation and internal electrode breakage.

[0006] Furthermore, as applications in automotive electrical components and other applications increase, high reliability in various environments is required. To ensure high reliability, it is important to improve the connectivity and thickness uniformity of the internal electrodes to disperse the concentration of the electric field. In addition, excellent high-temperature load life is required to ensure high reliability in various environments.

[0007] On the other hand, there have been attempts to solve the aforementioned problems by adding Sn to the internal electrode paste and placing a region with a high Sn content at the interface between the dielectric layer and the internal electrode. However, in this case, problems such as decreased capacitance, increased capacitance dispersion, and increased insulation resistance dispersion sometimes occurred. [Overview of the project] [Problems that the invention aims to solve]

[0008] One of the problems that this invention aims to solve is to provide a highly reliable stacked electronic component.

[0009] One of the problems that this invention aims to solve is to provide a multilayer electronic component with improved capacitance.

[0010] One of the problems that this invention aims to solve is to provide a multilayer electronic component with excellent lifespan under high-temperature loads.

[0011] One of the problems that this invention aims to solve is to suppress the internal electrode aggregation phenomenon and the internal electrode breakage phenomenon.

[0012] One of the problems that this invention aims to solve is to improve the distribution of dosage and crystal grain size.

[0013] One of the problems that this invention aims to solve is to improve the distribution of insulation resistance.

[0014] However, the problems that the present invention aims to solve are not limited to those described above, and can be more easily understood in the process of describing specific embodiments of the present invention. [[Means for Solving the Problem]]

[0015] A multilayer electronic component according to an embodiment of the present invention comprises: a main body including a plurality of dielectric layers, and a plurality of internal electrodes alternately arranged with the dielectric layers in a first direction; and external electrodes disposed on the main body, wherein the plurality of internal electrodes include Ni and In, for at least one of the plurality of internal electrodes, among points spaced 10 nm apart from the interface with the dielectric layer, the proportion of points at which the molar ratio of In / (Ni+In) is 0.002 or more is 70% or more, and among points in a central portion in the first direction, the proportion of points at which the molar ratio of In / (Ni+In) is 0.002 or more can be 35% or less.

[0016] A multilayer electronic component according to an embodiment of the present invention comprises: a main body including a plurality of dielectric layers, and a plurality of internal electrodes alternately arranged with the dielectric layers in a first direction; and external electrodes disposed on the main body, wherein the plurality of internal electrodes include Ni and In, for at least one of the plurality of internal electrodes, when X represents an average value of the molar ratio of In / (Ni+In) at points spaced 2 nm apart from the interface with the dielectric layer, and Y represents an average value of the molar ratio of In / (Ni+In) in a region spaced 10 nm apart from the interface with the dielectric layer, X-Y can be 0.0041 or more. [[Effects of the Invention]]

[0017] As one of the various effects of the present invention, the reliability of the multilayer electronic component can be improved by controlling the In content for each position within the internal electrode.

[0018] As one of the various effects of the present invention, the capacitance and high-temperature load lifespan of the multilayer electronic component can be improved.

[0019] As one of the various effects of the present invention, the connectivity of the internal electrodes can be improved, and the thickness deviation of the internal electrodes can be reduced.

[0020] As one of the various effects of the present invention, variation in dosage and crystal grain size can be suppressed.

[0021] As one of the various effects of the present invention, variation in insulation resistance can be suppressed.

[0022] However, the various yet significant advantages and effects of the present invention are not limited to the above description, and can be more easily understood in the process of describing specific embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] [Figure 1] FIG. 1 is a schematic perspective view showing a multilayer electronic component according to an embodiment of the present invention. [Figure 2] FIG. 2 is a schematic cross-sectional view taken along line I-I' of FIG. 1. [Figure 3] FIG. 3 is a schematic cross-sectional view taken along line II-II' of FIG. 1. [Figure 4] FIG. 4 is a drawing for explaining the measurement region of the present invention, as a cross-sectional view taken along line II-II' of FIG. 1. [Figure 5] FIG. 5 is an exploded perspective view showing the main body of FIG. 1 in an exploded manner. [Figure 6] FIG. 6 is an enlarged view of the region P1 in FIG. 3. [Figure 7] FIG. 7 is an enlarged view of the region P2 in FIG. 6. [Figure 8] FIG. 8 is an enlarged view of the region P3 in FIG. 6. [Figure 9] FIG. 9 shows images obtained by analyzing the interface between an internal electrode and a dielectric layer according to an embodiment of the present invention by STEM-EDS, where (a) is an image obtained by mapping Ni element by STEM-EDS, (b) is an image obtained by mapping Ti element by STEM-EDS, and (c) is an image obtained by mapping In element by STEM-EDS. [Figure 10]Figure 9(c) shows the line profile obtained using STEM-EDS along L1. (b) is an enlarged graph of a portion of (a). [Figure 11] As graphs showing the insulation resistance, (a) is Comparative Example 1, (b) is Comparative Example 2, and (c) is a graph showing the insulation resistance compared to the inventive example. [Figure 12] The images show the dielectric crystal grains of Comparative Example 1, where (a) is an image showing the dielectric crystal grains of the cover portion and (b) is an image showing the dielectric crystal grains of the capacitance-forming portion. [Figure 13] These are images showing the dielectric crystal grains of the example invention; (a) is an image showing the dielectric crystal grains of the cover portion, and (b) is an image showing the dielectric crystal grains of the capacitance forming portion. [Figure 14] The images show the interface between the internal electrode and the dielectric layer analyzed by STEM-EDS according to one embodiment of the present invention. (a) is an image showing the mapping of the Ni element by STEM-EDS, (b) is an image showing the mapping of the Ti element by STEM-EDS, and (c) is an image showing the mapping of the In element by STEM-EDS. [Modes for carrying out the invention]

[0024] Embodiments of the present invention will be described below with reference to specific embodiments and accompanying drawings. However, embodiments of the present invention can be modified into several other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, embodiments of the present invention are provided to give a more complete explanation of the present invention to a person of the ordinary skill. Accordingly, the shapes and sizes of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for a clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements.

[0025] Furthermore, in order to clearly illustrate the present invention in the drawings, parts unrelated to the explanation have been omitted, and the size and thickness of each illustrated component are shown arbitrarily for the convenience of explanation; therefore, the present invention is not necessarily limited by the illustrations. Also, components with the same function within the scope of the same idea can be described using the same reference numerals. Moreover, throughout the specification, when a part "includes" a certain component, unless otherwise stated to the contrary, it does not mean that other components are excluded, but rather that other components may be further included.

[0026] In drawings, the first direction can be defined as the lamination direction or thickness (T) direction, the second direction as the length (L) direction, and the third direction as the width (W) direction.

[0027] Multilayer electronic components Figure 1 is a schematic perspective view of a stacked electronic component according to one embodiment of the present invention; Figure 2 is a schematic cross-sectional view along the line I-I' in Figure 1; Figure 3 is a schematic cross-sectional view along the line II-II' in Figure 1; Figure 4 is a diagram illustrating the measurement area of ​​the present invention as a cross-sectional view along the line II-II' in Figure 1; Figure 5 is an exploded perspective view showing the main body of Figure 1 disassembled; Figure 6 is an enlarged view of the P1 area in Figure 3; Figure 7 is an enlarged view of the P2 area in Figure 6; and Figure 8 is an enlarged view of the P3 area in Figure 6.

[0028] The following describes in detail a multilayer electronic component 100 according to one embodiment of the present invention with reference to Figures 1 to 8. While a multilayer ceramic capacitor (MLCC) is described as an example of a multilayer electronic component, the present invention is not limited to this and can be applied to various multilayer electronic components using ceramic materials, such as inductors, piezoelectric elements, varistors, or thermistors.

[0029] A stacked electronic component 100 according to one embodiment of the present invention includes a body 110 including a dielectric layer 111 and internal electrodes 121 and 122 arranged alternately with the dielectric layer, and external electrodes 131 and 132 arranged on the body, wherein one or more of the plurality of internal electrodes 121 and 122 have a molar ratio of In / (Ni+In) of 0.002 or more at a distance of 10 nm from the interface IF with the dielectric layer, and a proportion of locations with a molar ratio of In / (Ni+In) of 0.002 or more at a distance of 10 nm from the interface IF with the dielectric layer is 70% or more, and the proportion of locations in the central part of the first direction with a molar ratio of In / (Ni+In) of 0.002 or more is 35% or less.

[0030] According to one embodiment of the present invention, if one or more of the multiple internal electrodes 121, 122 satisfy the following conditions: the proportion of locations (▲) at which the In / (Ni+In) molar ratio is 0.002 or higher among locations 10 nm away from the interface IF with the dielectric layer is 70% or higher; and the proportion of locations (●) in the central part of the first direction where the In / (Ni+In) molar ratio is 0.002 or higher is 35% or lower, the breakage and aggregation phenomena of the internal electrodes can be suppressed, thereby improving the reliability of the multilayer electronic component.

[0031] The following describes in detail each component of the stacked electronic component 100.

[0032] The main body 110 can have dielectric layers 111 and internal electrodes 121 and 122 stacked alternately.

[0033] There are no particular restrictions on the specific shape of the main body 110, but as shown, the main body 110 can be hexahedral or a similar shape. Due to the shrinkage of the ceramic powder contained in the main body 110 during the firing process, the main body 110 may not be a perfectly straight hexahedron, but rather substantially hexahedral.

[0034] The main body 110 may have a first surface 1 and a second surface 2 facing each other in a first direction, a third surface 3 and a fourth surface 4 connected to the first surface 1 and the second surface 2 and facing each other in a second direction, and a fifth surface 5 and a sixth surface 6 connected to the first surface 1 and the second surface 2 and connected to the third surface 3 and the fourth surface 4 and facing each other in a third direction.

[0035] Due to the overlap of margin regions on the dielectric layer 111 where internal electrodes 121 and 122 are not placed, a step difference occurs due to the thickness of the internal electrodes 121 and 122, and the corners connecting the first surface with the third to fifth surfaces and / or the second surface with the third to fifth surfaces may have a shape that is contracted toward the center in the first direction of the main body 110 when viewed with reference to the first or second surface. Alternatively, due to the contraction behavior during the sintering process of the main body, the corners connecting the first surface 1 with the third to sixth surfaces 6 and / or the corners connecting the second surface 2 with the third to sixth surfaces 6 may have a shape that is contracted toward the center in the first direction of the main body 110 when viewed with reference to the first or second surface. Alternatively, in order to prevent chipping defects, the edges connecting each surface of the main body 110 can be rounded by performing a separate process to round the edges, thereby allowing the corners connecting the first surface with the third to sixth surfaces and / or the corners connecting the second surface with the third to sixth surfaces to have a rounded shape.

[0036] On the other hand, in order to suppress the step caused by the internal electrodes 121 and 122, if the internal electrodes are cut after lamination so that they are exposed on the fifth and sixth surfaces 5 and 6 of the main body, and then a single dielectric layer or two or more dielectric layers are laminated on both sides of the capacitance forming portion Ac in the third direction (width direction) to form margin portions 114 and 115, the portions connecting the first surface and the fifth and sixth surfaces, and the portions connecting the second surface and the fifth and sixth surfaces, do not have a contracted form.

[0037] The multiple dielectric layers 111 forming the main body 110 are in a fired state, and the boundaries between adjacent dielectric layers 111 can be integrated to such an extent that they are difficult to see without using a scanning electron microscope (SEM). There is no particular limit to the number of dielectric layers stacked, and it can be determined considering the size of the multilayer electronic component. For example, the main body can be formed by stacking 400 or more dielectric layers.

[0038] The dielectric layer 111 can be formed by producing a ceramic slurry containing ceramic powder, an organic solvent and a binder, applying the slurry onto a carrier film and drying the slurry to provide a ceramic green sheet, and then firing the ceramic green sheet. The ceramic powder is not particularly limited as long as a sufficient capacitance can be obtained. For example, barium titanate (BaTiO3)-based powder can be used as the ceramic powder. As a more specific example, the ceramic powder comprises BaTiO3, (Ba 1-x Ca x )TiO3(0<x<1), Ba(Ti 1-y Ca y )O3(0<y<1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3(0<x<1, 0<y<1) and Ba(Ti 1-y Zr y )O3(0<y<1).

[0039] In one embodiment, the dielectric layer 111 may contain Ba(Ti 1-z In z )O3(0<z<1). Trivalent In can be substituted at the Ti sites of BaTiO3, which is the main component of the dielectric layer. When substituted at the Ti sites, In acts as an acceptor, which can improve the reliability of a multilayer electronic component. However, the main components of the dielectric layer 111 are selected from BaTiO3, (Ba 1-x Ca x )TiO3(0<x<1), Ba(Ti 1-y Ca y )O3(0<y<1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3(0<x<1, 0<y<1) and Ba(Ti 1-y Zr y )O3(0<y<1), wherein In diffuses into the dielectric layer 111 and is substituted at some Ti sites in the above main components, and Ba(Ti 1-z Inz In some cases, the dielectric layer does not contain O₃ (0<z<1) as a main component.

[0040] In one embodiment, the dielectric layer 111 may contain Sn. Further, in the dielectric layer 111, the average content of Sn relative to Ti in a region 2 nm away from the interface IF between the dielectric layer 111 and the internal electrodes 121 and 122 may be 0.02 at% or more and 0.42 at% or less. Sn has a low melting point, can serve to facilitate diffusion of In to the interface IF, and can serve to facilitate trapping of In at the interface IF, thereby facilitating improvement of capacitance and high-temperature load life. However, in the dielectric layer 111, if the average content of Sn relative to Ti in the region 2 nm away from the interface IF between the dielectric layer 111 and the internal electrodes 121 and 122 is less than 0.02 at%, the above-described effect may be insufficient; if the average content exceeds 0.42 at%, excessive diffusion of In may conversely occur, which may reduce the In content trapped at the interface.

[0041] In one embodiment, the dielectric layer 111 may contain Dy. Dy can serve to improve high-temperature load life and dielectric constant. Further, in the dielectric layer 111, the average content of Dy relative to Ti in a region 2 nm away from the interface IF between the dielectric layer 111 and the internal electrodes 121 and 122 may be 3 at% or more and 7 at% or less. This makes it easier to improve the high-temperature load life and can improve the dielectric constant.

[0042] On the other hand, the dielectric layer 111 may further contain various elements in addition to the elements described above. For example, the dielectric layer 111 may further contain one or more elements selected from the group consisting of Ca, Mn, V, Cr, Fe, Ni, Co, Cu, Zn, Mg, Si, and rare earth elements (RE, Rare earth Element).

[0043] According to the present invention, reliability can be prevented from decreasing even when the thickness of the multiple dielectric layers 111 is thin, and reliability can be further improved when the thickness of the dielectric layers is thick. Therefore, the average thickness td of the dielectric layers 111 does not need to be particularly limited, and the average thickness td of the dielectric layers 111 can be arbitrarily set according to the desired characteristics and application. As a specific example, the average thickness td of the dielectric layers 111 can be 300 nm or more and 10 μm or less. In addition, the average thickness td of at least one of the multiple dielectric layers 111 can be 300 nm or more and 10 μm or less.

[0044] Here, the average thickness td of the dielectric layer 111 can mean the average size in the first direction of the dielectric layer 111 that is placed between the internal electrodes 121 and 122. The average thickness of the dielectric layer 111 can be measured by scanning the cross-sections of the main body 110 in the first and second directions using a scanning electron microscope (SEM) at 10,000x magnification. More specifically, the thickness of a single dielectric layer 111 can be measured at multiple points, for example, 30 points equally spaced in the second direction, and the average value can be measured. The 30 equally spaced points can be specified in the capacitance forming section Ac described later. Furthermore, by extending such average value measurement to 10 dielectric layers 111 and measuring the average value, the average thickness of the dielectric layer 111 can be further generalized.

[0045] The main body 110 may include a capacitance forming section Ac which is located inside the main body 110 and includes a first internal electrode 121 and a second internal electrode 122 which are arranged to face each other with a dielectric layer 111 in between, and cover sections 112 and 113 formed on the upper and lower parts of the capacitance forming section Ac in a first direction.

[0046] Furthermore, the capacitance-forming portion Ac is a part that contributes to the capacitance formation of the capacitor, and can be formed by repeatedly stacking a plurality of first internal electrodes 121 and second internal electrodes 122 with a dielectric layer 111 in between.

[0047] The cover portions 112 and 113 may include an upper cover portion 112 positioned above the volume-forming portion Ac in the first direction and a lower cover portion 113 positioned below the volume-forming portion Ac in the first direction.

[0048] The upper cover portion 112 and the lower cover portion 113 described above can be formed by stacking a single dielectric layer or two or more dielectric layers in the thickness direction on the upper and lower surfaces of the capacitance forming portion Ac, respectively, and can essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0049] The upper cover portion 112 and the lower cover portion 113 described above do not include internal electrodes and may contain the same material as the dielectric layer 111.

[0050] In other words, the upper cover portion 112 and the lower cover portion 113 may include a ceramic material, for example, a barium titanate (BaTiO3) based ceramic material.

[0051] On the other hand, the thickness of the cover portions 112 and 113 is not particularly limited. For example, the thickness tc of the cover portions 112 and 113 can be 10 to 300 μm. However, in order to more easily achieve miniaturization and high capacitance of the stacked electronic component, the thickness tc of the cover portions 112 and 113 can be 15 μm or less.

[0052] The average thickness tc of the cover portions 112 and 113 can represent the size in the first direction, and can be the average value of the sizes of the cover portions 112 and 113 in the first direction measured at five equally spaced points on the upper or lower part of the volume forming portion Ac.

[0053] Furthermore, margin portions 114 and 115 can be arranged on the side surface of the volume-forming portion Ac.

[0054] The margin portions 114 and 115 may include a first margin portion 114 located on the fifth surface 5 of the main body 110 and a second margin portion 115 located on the sixth surface 6. That is, the margin portions 114 and 115 can be located on both end surfaces in the width direction of the ceramic main body 110.

[0055] As shown in Figure 3, the margin portions 114 and 115 can represent the region between the interface between both ends of the first internal electrode 121 and the second internal electrode 122 and the body 110 in a cross-section obtained by cutting the main body 110 in the width-thickness (WT) direction.

[0056] The margins 114 and 115 can essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0057] The margin portions 114 and 115 can be formed by applying conductive paste to the ceramic green sheet, except where the margin portions are formed, to form internal electrodes.

[0058] Furthermore, in order to suppress the step caused by the internal electrodes 121 and 122, after lamination, the internal electrodes can be cut so that they are exposed on the fifth and sixth surfaces 5 and 6 of the main body, and then a single dielectric layer or two or more dielectric layers can be laminated on both sides of the capacitance forming portion Ac in the third direction (width direction) to form margin portions 114 and 115.

[0059] On the other hand, the width of the margin portions 114 and 115 does not need to be particularly limited. For example, the width of the margin portions 114 and 115 can be 5 to 300 μm. However, in order to more easily achieve miniaturization and high capacitance of the multilayer electronic component, the average width of the margin portions 114 and 115 can be 15 μm or less.

[0060] The average width of the margin portions 114 and 115 can represent the average size in the third direction of the region where the internal electrode is separated from the fifth surface, and the average size in the third direction of the region where the internal electrode is separated from the sixth surface, and can be the average value of the sizes in the third direction of the margin portions 114 and 115 measured at five equally spaced points on the side surface of the capacitance forming portion Ac.

[0061] Therefore, in one embodiment, the average size in the third direction of the region where the internal electrodes 121 and 122 are separated from the fifth and sixth surfaces can be 15 μm or less.

[0062] The internal electrodes 121 and 122 may include a first internal electrode 121 and a second internal electrode 122. The first internal electrode 121 and the second internal electrode 122 are arranged alternately so as to face each other across the dielectric layer 111 that constitutes the main body 110, and can be exposed on the third surface 3 and the fourth surface 4 of the main body 110, respectively.

[0063] The first internal electrode 121 is separated from the fourth surface 4 and exposed via the third surface 3, and the second internal electrode 122 can be separated from the third surface 3 and exposed via the fourth surface 4. The first external electrode 131 is positioned on the third surface 3 of the main body and connected to the first internal electrode 121, and the second external electrode 132 is positioned on the fourth surface 4 of the main body and can be connected to the second internal electrode 122.

[0064] In other words, the first internal electrode 121 is not connected to the second external electrode 132, but is connected to the first external electrode 131, and the second internal electrode 122 is not connected to the first external electrode 131, but is connected to the second external electrode 132. Therefore, the first internal electrode 121 can be formed at a certain distance apart on the fourth surface 4, and the second internal electrode 122 can be formed at a certain distance apart on the third surface 3. Furthermore, the first internal electrode 121 and the second internal electrode 122 can be arranged at a distance from the fifth and sixth surfaces of the main body 110.

[0065] According to one embodiment of the present invention, one or more of the multiple internal electrodes 121, 122 can satisfy the following conditions: the proportion (A) of locations (▲) where the molar ratio of In / (Ni+In) is 0.002 or more among points (▲) 10 nm away from the interface IF with the dielectric layer is 70% or more; and the proportion (B) of locations (●) in the central part of the first direction where the molar ratio of In / (Ni+In) is 0.002 or more is 35% or less. In this way, by arranging a region with a high In content in the region of the internal electrodes 121, 122 adjacent to the interface IF with the dielectric layer, the interfacial bonding force between the dielectric layer and the internal electrodes can be improved. The region with a high In content acts as a kind of semiconductor barrier that hinders electron transfer from the internal electrodes to the dielectric layer, or from the dielectric layer to the internal electrodes, thereby improving both capacitance and high-temperature load life.

[0066] Here, the molar ratio of In / (Ni+In) can be calculated as [moles of In / (moles of Ni + moles of In)]. Below, "A" will be defined as the proportion of points (▲) within the internal electrode, located 10 nm away from the interface IF with the dielectric layer, where the molar ratio of In / (Ni+In) is 0.002 or greater, and "B" will be defined as the proportion of points (●) in the central part of the first direction of the internal electrode, where the molar ratio of In / (Ni+In) is 0.002 or greater. Furthermore, "A" and "B" can each be measured at a minimum of 20 points.

[0067] When "A" is greater than 0% but less than 70%, the capacitance can be improved compared to when "A" is 0%, but the lifespan of the high-temperature load may be reduced. Therefore, it is preferable that "A" be 70% or more, and it may be even preferable that "A" be 75% or more in order to further improve capacitance and the lifespan of the high-temperature load. On the other hand, there is no particular need to limit the upper limit of "A," and as a preferred example, "A" can be 90% or less.

[0068] On the other hand, if "B" exceeds 35%, capacitance may decrease or the lifespan of the high-temperature load may be reduced, so "B" can be 35% or less. Also, there is no particular lower limit for "B", but if "B" is greater than 0% but less than 20%, capacitance can be improved compared to when "B" is 0%, but the lifespan of the high-temperature load may be reduced. Therefore, as a preferred example, "B" can be 20% or more.

[0069] Referring to Figures 6 to 8 as an example of a method for measuring "A" and "B", after polishing the multilayer electronic component to the center in the second direction to expose the cross-sections in the first and third directions, 20 points (▲) located 10 nm away from the interface IF with the dielectric layer 111 and 20 points (●) in the center of the first direction are selected from one of the internal electrodes 121, 122. At each of the selected points, the molar ratio of In / (Ni+In) can be measured by quantitative analysis of In and Ni using STEM-EDS to determine "A" and "B". In this case, the 20 points (▲) located 10 nm away from the interface IF with the dielectric layer 111 can be specified to be equally spaced. Similarly, the 20 points (●) in the center of the first direction can also be specified to be equally spaced. However, this is not the only way to define it. The central part of the internal electrode in the first direction can mean the region located in the center when the internal electrode is divided into three equal parts in the first direction, and the 20 points (●) in the central part of the first direction can be any 20 points selected from the central part of the internal electrode in the first direction. On the other hand, as shown in Figure 4, the values ​​of "A" and "B" can also be more generalized by selecting one internal electrode each in the central region located in the center of the width and thickness direction of the main body 100, the upper region adjacent to the upper cover portion 112, and the lower region adjacent to the lower cover portion 113, determining "A" and "B" for each internal electrode, and then calculating their average value.

[0070] Furthermore, the interface IF between the dielectric layer 111 and the internal electrodes 121 and 122 can be identified by observing the lines that appear on both sides of the interface, i.e., Fresnel fringes, using a STEM (scanning transmission electron microscope). The interface can be defined as the point where the contrast of the Fresnel fringes changes almost symmetrically from both sides when the focus is changed.

[0071] On the other hand, there is no particular limit to the method of controlling "A" and "B". As a concrete example, "A" and "B" can be controlled by adjusting the amount of In relative to Ni added to the conductive paste and by adjusting the oxygen partial pressure conditions during firing. Indium (In) is an element that oxidizes more readily than nickel (Ni). When In is added as a material for the internal electrode and then fired, some of it is oxidized and diffuses into the dielectric layer, replacing Ti sites such as BaTiO3, while other parts remain unoxidized and can form an alloy with the Ni that remains in the internal electrode. In addition, some of the In that diffuses from the internal electrode to the dielectric layer can be trapped at the interface between the dielectric layer and the internal electrode, creating regions with a high In content at and adjacent to the interface.

[0072] In one embodiment, if one or more of the multiple internal electrodes 121, 122 have an average value of the molar ratio of In / (Ni+In) at a point 2 nm away from the interface IF with the dielectric layer, X is the average value of the molar ratio of In / (Ni+In) at a point 10 nm away from the interface IF with the dielectric layer, then XY can be 0.0041 or greater.

[0073] If XY is greater than 0 but less than 0.0041, the capacitance may decrease and the lifespan of the high-temperature load may be reduced compared to when XY is 0, making it difficult to improve both the capacitance and the lifespan of the high-temperature load. Therefore, it is preferable that XY be 0.0041 or greater, and it is even preferable that XY be 0.0057 or greater in order to further improve the capacitance and the lifespan of the high-temperature load. On the other hand, there is no particular need to limit the upper limit of XY, and as a preferred example, XY can be 0.0098 or less.

[0074] Referring to Figure 7 as an example of a method for measuring X and Y, after polishing the multilayer electronic component to the center in the second direction to expose the cross-sections in the first and third directions, 20 points (x) 2 nm away from the interface IF with the dielectric layer 111 and 20 points (▲) 10 nm away are selected from the internal electrodes 121 and 122. At each of the selected points, the molar ratio of In / (Ni+In) is determined by quantitative analysis of In and Ni by STEM-EDS. Then, the average value of the molar ratio of In / (Ni+In) measured at the 20 points (x) 2 nm away can be taken as X, and the average value of the molar ratio of In / (Ni+In) measured at the 20 points (▲) 10 nm away can be taken as Y.

[0075] Furthermore, the interface IF between the dielectric layer 111 and the internal electrodes 121 and 122 was determined by observing the lines appearing on both sides of the interface, i.e., Fresnel fringes, using a STEM (scanning transmission electron microscope). The interface was defined as the point where the contrast of the Fresnel fringes changed almost symmetrically from both sides when the focus was changed.

[0076] In one embodiment, X can be 0.0139 or less. If X exceeds 0.0139, the capacitance may decrease or the lifespan of the high-temperature load may decrease, making it difficult to improve both the capacitance and the lifespan of the high-temperature load.

[0077] In one embodiment, in order to improve the lifespan of both capacitance and high-temperature load, it is more preferable that X is 0.0046 or more and 0.0139 or less, and Y is 0.0005 or more and 0.0041 or less. Furthermore, in order to further improve the lifespan of both capacitance and high-temperature load, it is even more preferable that X is 0.0067 or more and 0.0139 or less, and Y is 0.0010 or more and 0.0041 or less.

[0078] In one embodiment, when Gc is the average grain size of dielectric crystal grains included in cover portions 112 and 113, Ga is the average grain size of dielectric crystal grains included in capacitance forming portion Ac, and Gm is the average grain size of dielectric crystal grains included in margin portions 114 and 115, the conditions 1 < Gc / Ga and 1 < Gm / Ga can be satisfied. By controlling the average grain size Ga of the dielectric crystal grains included in the capacitance forming portion Ac to be smaller than the average grain sizes Gc and Gm of the dielectric crystal grains included in the cover portions 112, 113 and the margin portions 114, 115, the insulation resistance of the multilayer electronic component 100 can be improved.

[0079] For the grain size of a dielectric crystal grain, when a straight line is drawn from one point on the grain boundary of the dielectric crystal grain to another point, the line having the largest value is defined as the major axis, and the largest value among straight lines orthogonal to the major axis is defined as the minor axis, and the average value of the major axis and the minor axis can be used as the grain size of the dielectric crystal grain. Furthermore, a value obtained by averaging the grain sizes of at least 100 or more dielectric crystal grains can be used as the average grain size of the dielectric crystal grains.

[0080] As an example of a method for measuring Ga, Gc, and Gm, after polishing a multilayer electronic component to the center in the second direction to expose cross-sections in the first direction and the third direction, measurement can be performed on image data obtained by scanning using a scanning electron microscope (SEM, Scanning Electron Microscope). In this case, the magnification can be varied depending on the grain size of the dielectric crystal grains, and the magnification can be adjusted such that the grain size of at least 100 or more dielectric crystal grains can be measured. More specifically, referring to FIG. 4, Ga can be measured from a scanned image that includes at least 100 or more dielectric crystal grains in a central region located at the center in the width and thickness directions of the main body 100; Gc can be measured from a scanned image that includes at least 100 or more dielectric crystal grains in a central region of the cover parts located at the center in the width and thickness directions of the cover parts 112 and 113; and Gm can be measured from a scanned image that includes at least 100 or more dielectric crystal grains in a central region of the margin parts located at the center in the width and thickness directions of the margin parts 114 and 115.

[0081] In one embodiment, the aforementioned Ga and Gc can satisfy 1 < Gc / Ga ≤ 1.28. If Gc / Ga exceeds 1.28, the average grain size Ga of the dielectric crystal grains included in the capacitance forming part Ac may be too small, which may cause a decrease in capacitance, and may lead to increased variation in capacitance and / or DF (Dissipation Factor).

[0082] In one embodiment, the aforementioned Ga and Gm can satisfy 1 < Gm / Ga ≤ 1.07. If Gm / Ga exceeds 1.07, the average grain size Ga of the dielectric crystal grains included in the capacitance forming part Ac may be too small, which may cause a decrease in capacitance, and may lead to increased variation in capacitance and / or DF (Dissipation Factor).

[0083] In one embodiment, the internal electrodes 121 and 122 contain Ni and In, and at least a portion of the In contained in the internal electrodes 121 and 122 can exist in the form of an alloy with Ni. This reduces the grain boundary energy and surface tension of Ni, thereby improving the connectivity of the internal electrodes and reducing the thickness deviation of the internal electrodes. Whether or not Ni and In exist in an alloy form can be confirmed by whether or not the peak position of Ni has shifted during analysis by XRD (X-ray diffraction). As a specific example, the internal electrodes of a multilayer electronic component can be crushed to obtain a powder, and then the powder can be analyzed by XRD (X-ray diffraction) to confirm whether or not the peak position of Ni has shifted.

[0084] In one embodiment, the internal electrodes 121 and 122 may contain Sn. Sn has a low melting point and can play a role in allowing In to easily diffuse into the interface IF, and can play a role in allowing In to easily be trapped in the interface IF, thereby more easily improving capacitance and high-temperature load life.

[0085] On the other hand, the internal electrodes 121 and 122 may also contain other metals in addition to Ni, In, Ni-In, and Sn. For example, the internal electrodes 121 and 122 may further contain one or more of Cu, Pd, Ag, Au, Pt, Al, Ti, and their alloys.

[0086] In one embodiment, the region within 2 nm from the interface IF between the internal electrode and the dielectric layer can have a higher average In content than other regions. This can further improve the interfacial bonding force between the dielectric layer and the internal electrode, enhance the effect of acting as a kind of semiconductor barrier that hinders electron transfer from the internal electrode to the dielectric layer or from the dielectric layer to the internal electrode, and further improve capacitance and high-temperature load life.

[0087] Figure 9 shows an image of the interface between the internal electrode and the dielectric layer analyzed by STEM-EDS according to one embodiment. Figure 9(a) is an image of the Ni element mapped by STEM-EDS, Figure 9(b) is an image of the Ti element mapped by STEM-EDS, and Figure 9(c) is an image of the In element mapped by STEM-EDS. Referring to Figures 9(a) and (b), it can be confirmed that the dielectric layer and the internal electrode can be clearly distinguished by the Ni and Ti content, and referring to Figure 9(c), it can be confirmed that the In content is high at the interface between the dielectric layer and the internal electrode.

[0088] Performing a line profile using STEM-EDS along L1, a line perpendicular to the interface between the dielectric layer and the internal electrode as shown in Figures 7 and 9(c), allows for a more quantitative analysis of changes in elemental content depending on the location. Referring to Figure 10, which shows the results of a line profile performed using STEM-EDS along L1 as shown in Figure 9(c), it can be confirmed that peak values ​​for In, Dy, and Sn content are detected in the region adjacent to the interface between the dielectric layer and the internal electrode.

[0089] Furthermore, a peak value for In content is detected in the region where the Ni content exceeds 50 at% but is 90 at% or less. This can be attributed to the diffusion of In contained in the conductive paste for the internal electrodes into the dielectric layer. Therefore, in one embodiment, when analyzing the line profile in a direction perpendicular to the interface between the dielectric layer and the internal electrodes in a region adjacent to the interface IF, a peak value for In content can be detected in the region where the Ni content exceeds 50 at% but is 90 at% or less. A peak value for Sn content can also be detected in the region where the Ni content exceeds 50 at% but is 90 at% or less. In this case, the line profile analysis can be performed using STEM-EDS.

[0090] On the other hand, a peak value of Dy content is detected in the region where the Ni content is between 10 at% and less than 50 at%, which can be attributed to the diffusion of Dy added to the ceramic green sheet into the internal electrode. Therefore, in one embodiment, when analyzing the line profile in a region adjacent to the interface IF in a direction perpendicular to the interface between the dielectric layer and the internal electrode, a peak value of Dy content can be detected in the region where the Ni content is between 10 at% and less than 50 at%. In this case, the line profile analysis can be performed using STEM-EDS.

[0091] In one embodiment, the internal electrodes 121 and 122 contain ceramic particles, and these ceramic particles may contain In.

[0092] The ceramic particles contained in the internal electrodes 121 and 122 can reduce the difference in sintering start temperature between the dielectric layer and the internal electrodes, and the ceramic particles added to the conductive paste for the internal electrodes can be trapped within the internal electrodes after firing. Furthermore, by adding In to the conductive paste for the internal electrodes, the ceramic particles contained in the internal electrodes 121 and 122 can contain In.

[0093] In this case, In can be mainly distributed on the surface of the ceramic particles, which is the interface between the ceramic particles and the internal electrode, similar to the interface IF between the internal electrode and the dielectric layer. Therefore, the In content on the surface of the ceramic particles is higher than the In content inside, and the average In content relative to Ti on the surface of the ceramic particles can be 0.3 at% or more. Furthermore, the average In content relative to Ti on the surface of the ceramic particles can be between 0.3 at% and 3.8 at%.

[0094] Figure 14 shows an image of the interface between the internal electrode and the dielectric layer analyzed by STEM-EDS according to one embodiment of the present invention. Figure 14(a) is an image of the Ni element mapped by STEM-EDS, Figure 14(b) is an image of the Ti element mapped by STEM-EDS, and Figure 14(c) is an image of the In element mapped by STEM-EDS. Referring to Figures 14(a) and (b), it can be confirmed that ceramic particles are trapped inside the internal electrode. Referring to Figure 14(c), it can be confirmed that the In content is high on the surface of the ceramic particles, and that the In content on the surface of the ceramic particles is similar to the In content at the interface IF between the internal electrode and the dielectric layer.

[0095] As an example of a method for measuring the average In content relative to Ti on the surface of ceramic particles, a multilayer electronic component is polished to the center in the second direction to expose the cross-sections in the first and third directions. Then, five points are selected from the boundaries formed between one of the ceramic particles trapped within the internal electrodes 121 and 122 and the internal electrode. Quantitative analysis of Ti and In is then performed at these five points using STEM-EDS to determine the In content relative to Ti, and the average value of these results is calculated. Furthermore, this method can be generalized by selecting four different ceramic particles from among the trapped ceramic particles, measuring five regions at the boundary between each ceramic particle and the internal electrode, and calculating the average of a total of 20 measurements.

[0096] On the other hand, the average thickness te of the internal electrodes 121 and 122 does not need to be particularly limited and can be set arbitrarily according to the desired characteristics and application. As a specific example, the average thickness te of the internal electrodes 121 and 122 can be between 300 nm and 3 μm. Also, the average thickness te of at least one of the multiple internal electrodes 121 and 122 can be between 300 nm and 3 μm.

[0097] The thickness of the internal electrodes 121 and 122 can refer to the size of the internal electrodes 121 and 122 in the first direction. The average thickness te of the internal electrodes can be measured by scanning the cross-sections of the main body 110 in the first and second directions using a scanning electron microscope (SEM) at 10,000x magnification. More specifically, the thickness of a single internal electrode 121 or 122 can be measured at multiple points, for example, 30 points equally spaced in the second direction, and the average value can be measured. These 30 equally spaced points can be specified in the capacitance forming section Ac. Furthermore, by extending this average value measurement to 10 internal electrodes 121 and 122 and measuring the average value, the average thickness of the internal electrodes 121 and 122 can be further generalized.

[0098] In one embodiment, when the average thickness of the internal electrodes 121 and 122 is denoted as te and the standard deviation of the thicknesses of the internal electrodes 121 and 122 is denoted as σte, σte / te can be 0.2 or less. That is, the coefficient of variation (CV) of the thickness of the internal electrodes can be 0.2 or less, which means that the thickness uniformity of the internal electrodes is within 20%. Furthermore, σte / te can more preferably be 0.18 or less, and even more preferably 0.17 or less. Furthermore, the standard deviation σte of the thicknesses of the internal electrodes 121 and 122 can more preferably be within ±70 nm.

[0099] When σte / te is 0.2 or less, ensuring uniformity of the thickness of the internal electrodes 121 and 122 prevents the phenomenon of uneven stress application to the internal electrodes 121 and 122 and electric field concentration, thereby improving reliability.

[0100] The standard deviation σte of the thickness of the internal electrodes can be measured by subtracting the average thickness te of the internal electrodes from each thickness measured at 30 equally spaced points in the second direction for measuring the average thickness te of the internal electrodes 121 and 122, squaring the result, calculating the average of these values ​​to obtain the variance, and then taking the square root of the variance.

[0101] In one embodiment, the connectivity of the internal electrodes 121 and 122 can be 85% or more. More preferably, the connectivity of the internal electrodes 121 and 122 can be 90% or more.

[0102] Referring to Figure 6, the internal electrode IE includes multiple conductive parts EP, and can include gaps DP between adjacent conductive parts EP. When the total length of the internal electrode IE is b, and the lengths of the multiple conductive parts EP are e1, e2, e3, and e4, respectively, the ratio of the sum of the lengths of the multiple conductive parts EP (e = e1 + e2 + e3 + e4) to the total length b of the internal electrode IE can be defined as the connectivity of the internal electrode.

[0103] The connectivity of the internal electrodes can be measured by scanning the cross-sections of the main body 110 in the first and second directions using a scanning electron microscope (SEM) at 10,000x magnification. More specifically, after measuring the connectivity of each of the 10 internal electrodes 121 and 122 in the above image, the average value can be used as the connectivity of the internal electrodes.

[0104] External electrodes 131 and 132 can be arranged on the third surface 3 and fourth surface 4 of the main body 110.

[0105] The external electrodes 131 and 132 are arranged on the third surface 3 and fourth surface 4 of the main body 110, respectively, and may include a first external electrode 131 and a second external electrode 132 that are connected to a first internal electrode 121 and a second internal electrode 122, respectively.

[0106] In this embodiment, a structure is described in which the stacked electronic component 100 has two external electrodes 131 and 132. However, the number and shape of the external electrodes 131 and 132 can be changed according to the form of the internal electrodes 121 and 122 or other purposes.

[0107] On the other hand, the external electrodes 131 and 132 can be formed using any material that has electrical conductivity, such as metal, and the specific material can be determined by considering electrical properties, structural stability, etc. Furthermore, they can have a multilayer structure.

[0108] For example, the external electrodes 131 and 132 may include electrode layers 131a and 132a placed on the main body 110, and plating layers 131b and 132b formed on the electrode layers 131a and 132a.

[0109] As a more specific example for electrode layers 131a and 132a, the electrode layers 131a and 132a can be firing electrodes containing a conductive metal and glass, or resin-based electrodes containing a conductive metal and resin.

[0110] Furthermore, the electrode layers 131a and 132a can be formed in a manner in which a fired electrode and a resin-based electrode are sequentially formed on the main body. Also, the electrode layers 131a and 132a can be formed by transferring a sheet containing a conductive metal onto the main body, or by transferring a sheet containing a conductive metal onto a fired electrode. Additionally, the electrode layers 131a and 132a can be formed as a plating layer, or as layers formed using a vapor deposition method such as sputtering or ALD (Atomic Layer Deposition).

[0111] The conductive metal contained in the electrode layers 131a and 132a can be any material with excellent electrical conductivity, and is not particularly limited. For example, the conductive metal can be one or more of nickel (Ni), copper (Cu), and their alloys.

[0112] The plating layers 131b and 132b play a role in improving mounting characteristics. The types of plating layers 131b and 132b are not particularly limited and can be plating layers containing one or more of Ni, Sn, Pd, and their alloys, and can be formed in multiple layers.

[0113] As a more specific example for the plating layers 131b and 132b, the plating layers 131b and 132b can be Ni plating layers or Sn plating layers, and can be configured such that the Ni plating layer and the Sn plating layer are formed sequentially on the electrode layers 131a and 132a, or can be configured such that the Sn plating layer, Ni plating layer, and Sn plating layer are formed sequentially. Furthermore, the plating layers 131b and 132b can also contain multiple Ni plating layers and / or multiple Sn plating layers. In addition, the plating layers 131b and 132b can be configured such that the Ni plating layer and the Pd plating layer are formed sequentially on the electrode layers 131a and 132a.

[0114] The size of the stacked electronic component 100 is not particularly limited. According to the present invention, it is advantageous for miniaturization and high capacity, so it can be applied to the size of small IT products, and because high reliability can be ensured in a variety of environments, it can also be applied to the size of automotive electronic products where high reliability is required.

[0115] The present invention will be described in more detail below with reference to experimental examples, but this is intended to aid in a concrete understanding of the invention and does not limit the scope of the present invention.

[0116] (Experimental Example 1) A sample chip was fabricated by laminating ceramic green sheets coated with internal electrode paste, cutting and firing them to form the main body, and then applying external electrode paste to the main body and firing it.

[0117] In this experiment, sample chips were prepared by varying the In content relative to the Ni powder in the internal electrode paste for each test number. For test number 1, no In was added to the internal electrode paste.

[0118] Furthermore, the ceramic green sheet was manufactured by adding organic solvents, binders, and dispersants to barium titanate (BaTiO3) powder, and no indigo was added to the ceramic green sheet.

[0119] After polishing the sample chip to the center in the second direction to expose the cross-sections in the first and third directions, thin sections were prepared using a microsampling method with FIB for each of the following regions: the central region located in the center in the width and thickness directions, the upper region adjacent to the upper cover, and the lower region adjacent to the lower cover, as shown in Figure 4.

[0120] The thinned samples were processed to a thickness of 60 nm or less. Meanwhile, the damage layer formed on the sample surface during FIB processing was removed by Ar ion milling.

[0121] One internal electrode was selected from each of the thinned samples prepared as described above, and analyzed using STEM (Scanning Transmission Electron Microscope) and EDS (Energy Dispersive X-ray Spectrometer). For STEM analysis, an ARM-200F (JEOL product) was used as the scanning transmission electron microscope, with an acceleration voltage of 200kV. An Oxford EDS was used for the EDS system.

[0122] "A" represents the percentage of locations within the internal electrode, 10 nm away from the interface IF with the dielectric layer, where the molar ratio of In / (Ni+In) is 0.002 or greater. "B" represents the percentage of locations within the internal electrode, in the central part of the first direction, where the molar ratio of In / (Ni+In) is 0.002 or greater. These values ​​are recorded in Table 1 below. Referring to Figure 7, for each test specimen, 20 locations (▲) 10 nm away from the interface IF with the dielectric layer 111 were observed, and a total of 60 locations were analyzed to determine "A". Referring to Figure 8, for each test specimen, 20 locations (●) in the central part of the first direction of the internal electrodes 121 and 122 were observed, and a total of 60 locations were analyzed to determine "B".

[0123] Furthermore, the average value of the molar ratio of In / (Ni+In) at point (x) 2 nm away from the interface IF with the dielectric layer, X, and the average value of the molar ratio of In / (Ni+In) at point 10 nm away from the interface IF with the dielectric layer, Y, were measured and are shown in Table 2 below. Referring to Figure 7, for each test specimen, 20 points (x) 2 nm away from the interface IF with the dielectric layer 111 were observed, and a total of 60 points were analyzed to determine X. For each test specimen, 20 points (▲) 10 nm away from the interface IF with the dielectric layer 111 were observed, and a total of 60 points were analyzed to determine Y.

[0124] Furthermore, the electron beam measurement probe diameter was set to approximately 1 nm, and the measurement time was 30 seconds. On the other hand, the quantitative correction from the obtained EDS spectrum was performed using the Cliff-Lorimer correction.

[0125] The interface IF between the dielectric layer 111 and the internal electrodes 121 and 122 was determined by observing the lines appearing on both sides of the interface, i.e., Fresnel fringes, using a scanning transmission electron microscope (STEM). The interface was defined as the point where the contrast of the Fresnel fringes changed almost symmetrically on both sides when the focus was changed.

[0126] Capacitance was measured for 10 sample chips per test number. An automated bridge-type measuring instrument was used to measure the capacitance under the conditions of AC voltage 1Vrms and 1kHz, and the average value for each test number was calculated. The capacitance of test number 1 was set as the baseline value "1," and the values ​​for test numbers 2 to 9 are listed as relative values ​​to the capacitance of test number 1.

[0127] The Mean Time To Failure (MTTF) was measured for 10 sample chips per test number. High-temperature load tests were conducted under conditions of 165°C and 7.5V, and the time at which the insulation resistance fell below 10kΩ was defined as the failure time. The average value was then calculated. The MTTF for test number 1 was set as the baseline value "1," and the MTTFs for test numbers 2 through 9 are listed relative to the MTTF of test number 1.

[0128] The connectivity of the internal electrodes was measured by polishing the sample tip to the center in the second direction to expose the cross-sections in the first and third directions. Then, as shown in Figure 4, 10 internal electrodes were selected in the central region located in the center of the width and thickness directions, and the average value of the measurement is recorded. The average thickness te and the standard deviation σte of the internal electrodes were determined by selecting one internal electrode in the central region and measuring its thickness at 30 equally spaced points in the second direction of the selected internal electrode.

[0129] [Table 1]

[0130] Referring to Table 1 above, when "A" is greater than 0% but less than 70% (test numbers 2 and 7), capacitance can be improved compared to when "A" is 0% (test number 1), but it can be confirmed that the lifespan of the high-temperature load decreases. Also, when "B" is greater than 35% (test numbers 7-9), it can be confirmed that capacitance decreases or the lifespan of the high-temperature load decreases.

[0131] On the other hand, when "A" is 70% or more and "B" is 35% or less (test numbers 3-6), it can be confirmed that there is a remarkable effect in that capacitance and MTTF are all improved compared to test number 1. In addition, in the case of test numbers 3-6, the connectivity of the internal electrodes is 85% or more, and the thickness deviation of the internal electrodes σte / te is small at 0.20 or less, confirming excellent smoothness and thickness uniformity of the internal electrodes. Therefore, it can be confirmed that it is preferable for "A" to be 70% or more and "B" to be 35% or less.

[0132] Furthermore, when "A" is 75% or more and "B" is 35% or less (test numbers 4-6), not only are the capacitance and MTTF all improved compared to test number 1, but it can be confirmed that the capacitance and MTTF have improved significantly by 15% or more each. Therefore, it can be confirmed that it is more preferable for "A" to be 75% or more and "B" to be 35% or less.

[0133] [Table 2]

[0134] Referring to Table 2 above, when XY is greater than 0 but less than 0.0041 (test numbers 2, 7-9), it can be confirmed that the capacitance decreases or the lifespan of the high-temperature load decreases compared to when XY is 0 (test number 1).

[0135] On the other hand, when XY is 0.0041 or higher (test numbers 3-6), a remarkable improvement in capacitance and MTTF is observed compared to test number 1. Furthermore, in test numbers 3-6, the connectivity of the internal electrodes is 85% or higher, and the thickness deviation σte / te of the internal electrodes is small, at 0.20 or less, confirming excellent smoothness and thickness uniformity of the internal electrodes. Therefore, it can be confirmed that it is preferable for XY to be 0.0041.

[0136] Furthermore, when XY is 0.0057 or higher (test numbers 4-6), not only are the capacitance and MTTF all improved compared to test number 1, but it can be confirmed that the capacitance and MTTF have improved significantly by 15% or more. Therefore, it can be confirmed that it is more preferable for XY to be 0.0057 or higher.

[0137] (Experimental Example 2) Additional experiments were conducted to confirm the structural and effectal differences in the following cases: when no region with high Sn or In content is placed at the interface between the dielectric layer and the internal electrode (Comparative Example 1), when a region with high Sn content is placed at the interface between the dielectric layer and the internal electrode (Comparative Example 2), and when a region with high In content is placed at the interface between the dielectric layer and the internal electrode (Inventive Example).

[0138] Comparative Example 1 corresponds to test number 1 in Experimental Example 1, and the inventive example corresponds to test number 4 in Experimental Example 1. In Comparative Example 2, a sample chip was prepared by adding Sn to the internal electrode paste without adding In, so that the In content relative to the Ni powder in the internal electrode paste of Test Number 4 was the same as the Sn content relative to the Ni powder in the internal electrode paste of Comparative Example 2.

[0139] After preparing 50 samples each of Comparative Example 1, Comparative Example 2, and the Inventive Example, the insulation resistance was measured by sequentially applying the conditions of STEP 1, STEP 2, and STEP 3 below, and the resulting graphs are shown in Figure 11. Figure 11(a) shows the insulation resistance for Comparative Example 1, Figure 11(b) shows the insulation resistance for Comparative Example 2, and Figure 11(c) shows the insulation resistance for the Inventive Example. STEP 1: Maintain a temperature of 85°C, humidity of 25%, and voltage of 6.3V for 1 hour. STEP 2: Maintain a temperature of 85°C, humidity of 25%, and voltage of 7.56V for 3.5 hours. STEP 3: Maintain a temperature of 105°C, humidity of 25%, and voltage of 7.56V for 6 hours.

[0140] Referring to Figure 11, it can be seen that in Comparative Example 2, in which Sn was added, the insulation resistance improved compared to Comparative Example 1, but the dispersion of insulation resistance did not improve. On the other hand, in the case of the inventive example, it can be seen that not only did the insulation resistance improve compared to Comparative Examples 1 and 2, but the dispersion of insulation resistance also improved significantly. The dispersion of insulation resistance (CV value) for Comparative Example 1 was measured as 15%, for Comparative Example 2 as 18%, and for the inventive example as 7%.

[0141] To compare the dielectric crystal grains in cases where no region with high Sn or In content is located at the interface between the dielectric layer and the internal electrode (Comparative Example 1) and in cases where a region with high In content is located at the interface between the dielectric layer and the internal electrode (Inventive Example), each sample chip was polished to the center in the second direction to expose the cross-sections in the first and third directions, and then observed with a scanning electron microscope (SEM).

[0142] Referring to Figure 4, after scanning the image so that more than 100 dielectric crystal grains were included in each of the central region, the central region of the cover, and the central region of the margin, the average particle size Ga of the dielectric crystal grains included in the capacitance formation region, the average particle size Gc of the dielectric crystal grains included in the cover region, and the average particle size Gm of the dielectric crystal grains included in the margin region were measured, and the Gc / Ga and Gm / Ga ratios are listed in Table 3 below.

[0143] Furthermore, after preparing 50 samples each of Comparative Example 1 and the Inventive Example, the capacitance and DF (Dissipation Factor) were measured, and their average values ​​and CV values ​​are listed in Table 3 below. Capacitance and DF (Dissipation Factor) were measured using an automatic bridge type measuring instrument under the conditions of AC voltage 1Vrms and 1kHz. The capacitance of Comparative Example 1 was set as the reference value "1," and the capacitance of the Inventive Example is listed as a relative value to the capacitance of Comparative Example 1.

[0144] [Table 3]

[0145] Referring to Table 3 above, it can be seen that the capacitance of the inventive example with added In is higher than that of Comparative Example 1, and in particular, the capacitance CV value is significantly improved. Furthermore, although the DF of the inventive example is slightly higher than that of Comparative Example 1, it can be seen that the DF CV value is remarkably lower.

[0146] Figures 12 and 13 show scanned images of dielectric crystal grains using an SEM in two cases: when no region with high Sn or In content is located at the interface between the dielectric layer and the internal electrode (Comparative Example), and when a region with high In content is located at the interface between the dielectric layer and the internal electrode (Inventive Example). Figure 12 is an image of the dielectric crystal grains of Comparative Example 1, where Figure 12(a) is an image of the dielectric crystal grains of the cover portion, and Figure 12(b) is an image of the dielectric crystal grains of the capacitance-forming portion. Figure 13 is an image of the dielectric crystal grains of the Inventive Example, where Figure 13(a) is an image of the dielectric crystal grains of the cover portion, and Figure 13(b) is an image of the dielectric crystal grains of the capacitance-forming portion.

[0147] Referring to Table 1, Figures 12 and 13 above, it can be seen that in Comparative Example 1, the average particle size Ga of the dielectric crystal grains contained in the capacitance-forming portion is significantly smaller than the average particle size Gc of the dielectric crystal grains contained in the cover portion and the average particle size Gm of the dielectric crystal grains contained in the margin portion. On the other hand, in the case of the inventive example with added In, it can be seen that the average particle size Ga of the dielectric crystal grains contained in the capacitance-forming portion is similar to the average particle size Gc of the dielectric crystal grains contained in the cover portion and the average particle size Gm of the dielectric crystal grains contained in the margin portion.

[0148] In summary, in the case of the invention with added In, it can be confirmed that there is a remarkable effect in which both capacitance and MTTF are improved without the occurrence of problems such as increased dispersion of capacitance or increased dispersion of insulation resistance.

[0149] Although embodiments of the present invention have been described in detail above, the present invention is not limited by the embodiments described above and the accompanying drawings, but is limited by the claims provided. Therefore, within the scope of the technical idea of ​​the present invention as described in the claims, various forms of substitution, modification, and alteration are possible by persons with ordinary skill in the art, and these also fall within the scope of the present invention.

[0150] Furthermore, the expression "one embodiment" as used in this disclosure does not mean that each embodiment is identical to the others, but is provided to highlight and describe the unique and distinct features of each embodiment. However, the present embodiments are not excluded from being realized in combination with features of other embodiments. For example, even if a matter described in one embodiment is not described in another embodiment, it can be understood as a description related to the other embodiment, unless there is a description in the other embodiment that contradicts or is inconsistent with that matter.

[0151] The terms used in this disclosure are used solely to describe one embodiment and are not intended to limit the disclosure. Where otherwise, singular expressions include plural expressions unless the context clearly indicates otherwise. [Explanation of Symbols]

[0152] 100 Stacked Electronic Components 110 Main Unit 111 Dielectric layer 112, 113 Cover section 114, 115 Margin section 121, 122 Internal electrode 131, 132 External electrode 131a, 132a electrode layer 131b, 132b Plating layer

Claims

1. A body including multiple dielectric layers and multiple internal electrodes arranged alternately with the multiple dielectric layers in a first direction, The main body includes an external electrode, The aforementioned plurality of internal electrodes include Ni and In. One or more of the aforementioned internal electrodes are Of the points located 10 nm away from the interface with the dielectric layer, the proportion of points where the molar ratio of In / (Ni+In) is 0.002 or higher is 70% or higher, and of the points in the central part of the first direction, the proportion of points where the molar ratio of In / (Ni+In) is 0.002 or higher is 35% or lower. One or more of the aforementioned internal electrodes are When X is the average value of the molar ratio of In / (Ni+In) at a point 2 nm away from the interface with the dielectric layer, if X is 0.0139 or less, The plurality of dielectric layers include Sn, forming a multilayer electronic component.

2. One or more of the aforementioned internal electrodes are The stacked electronic component according to claim 1, wherein, among the points 10 nm away from the interface with the dielectric layer, the proportion of points where the molar ratio of In / (Ni+In) is 0.002 or more is 70% or more and 90% or less, and among the central region in the first direction, the proportion of points where the molar ratio of In / (Ni+In) is 0.002 or more is 20% or more and 35% or less.

3. One or more of the aforementioned internal electrodes are The stacked electronic component according to claim 1, wherein when X is the average value of the molar ratio of In / (Ni+In) at a point 2 nm away from the interface with the dielectric layer, and Y is the average value of the molar ratio of In / (Ni+In) at a point 10 nm away from the interface with the dielectric layer, X - Y is 0.0041 or greater.

4. The aforementioned X is 0.0046 or more and 0.0139 or less. The stacked electronic component according to claim 3, wherein Y is 0.0005 or more and 0.0041 or less.

5. The main body includes a first and second surface facing the first direction, a third and fourth surface connected to the first and second surfaces and facing the second direction, and a fifth and sixth surface connected to the first to fourth surfaces and facing the third direction. The stacked electronic component according to claim 1, comprising a capacitance forming portion including a plurality of internal electrodes, a cover portion disposed on both end faces in a first direction of the capacitance forming portion, and a margin portion disposed on both end faces in a third direction of the capacitance forming portion.

6. The average particle size of the dielectric crystal grains contained in the cover portion is Gc, The average grain size of the dielectric crystal grains contained in the dielectric layer of the capacitance forming portion is Ga, When the average grain size of the dielectric crystal grains contained in the margin portion is Gm, The stacked electronic component according to claim 5, satisfying 1 < Gc / Ga and 1 < Gm / Ga.

7. The stacked electronic component according to claim 6, wherein Ga and Gc satisfy 1 < Gc / Ga ≤ 1.

28.

8. The stacked electronic component according to claim 7, wherein Ga and Gm satisfy 1 < Gm / Ga ≤ 1.

07.

9. The multilayer electronic component according to claim 1, wherein at least a portion of the In contained in the internal electrode exists in the form of an alloy with Ni.

10. The dielectric layer is Ba(Ti １－ｚ In ｚ ) O ３ A stacked electronic component according to claim 1, including (0 < z < 1).

11. The stacked electronic component according to claim 1, wherein at least one of the plurality of internal electrodes includes ceramic particles, and the ceramic particles include In.

12. The stacked electronic component according to claim 11, wherein the In content on the surface of the ceramic particles is 0.4 at% or more.

13. The stacked electronic component according to claim 1, wherein the internal electrode includes a plurality of conductive portions and a gap disposed between adjacent conductive portions, and the connectivity of the internal electrode, which is the ratio of the sum of the lengths of the plurality of conductive portions to the total length of the internal electrode, is 85% or more.

14. The stacked electronic component according to any one of claims 1 to 13, wherein when the average thickness of the internal electrodes is te and the standard deviation of the thickness of the internal electrodes is σte, σte / te is 0.2 or less.

15. A body including multiple dielectric layers and multiple internal electrodes arranged alternately with the multiple dielectric layers in a first direction, The main body includes an external electrode, The aforementioned plurality of internal electrodes include Ni and In. One or more of the aforementioned internal electrodes are When X is the average value of the molar ratio of In / (Ni+In) at a point 2 nm away from the interface with the dielectric layer, and Y is the average value of the molar ratio of In / (Ni+In) in a region 10 nm away from the interface with the dielectric layer, then X-Y is 0.0041 or greater. The aforementioned X is 0.0139 or less, The plurality of dielectric layers include Sn, Stacked electronic components.

16. The aforementioned X is 0.0046 or more and 0.0139 or less. The stacked electronic component according to claim 15, wherein Y is 0.0005 or more and 0.0041 or less.

17. The multilayer electronic component according to any one of claims 15 or 16, wherein at least a portion of the In contained in the internal electrode exists in the form of an alloy with Ni.

18. The stacked electronic component according to claim 17, wherein one or more of the plurality of internal electrodes include ceramic particles, and the ceramic particles include In.

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