RF Impedance Matching Network

Abstract

In one embodiment, an RF impedance matching circuit is disclosed. The matching circuit includes a series electronically variable capacitor (EVC) with a first fixed capacitor. Each of the first fixed capacitors has a corresponding switch for switching the fixed capacitor on and off to vary the series variable capacitance. Each switch includes one or more diodes. A first inductor has a first terminal electrically coupled to a common ground and a second terminal electrically coupled between an RF input and an RF output. A control circuit determines a first parameter associated with the plasma chamber while an RF source provides an RF signal to the RF input. While the RF signal continues to be provided to the RF input, the control circuit varies the series variable capacitance based on the determined first parameter. The variation reduces RF power reflected back to the RF source.

Description

[Technical Field]

[0001] (Cross-reference of related applications) This application claims priority under U.S. Provisional Application No. 63 / 170,768, filed on April 5, 2021, the entire contents of which are incorporated herein by reference. [Background technology]

[0002] In the manufacture of semiconductor devices such as microprocessors, memory chips, and other integrated circuits, the semiconductor device manufacturing process utilizes plasma processing at different stages of the manufacturing process. Plasma processing involves energizing a gas mixture by introducing RF (radio frequency) energy into the gas mixture, thereby imparting energy to the gas molecules. This gas mixture is typically contained within a vacuum chamber, also known as a plasma chamber, and the RF energy is introduced into the chamber through electrodes or other means. In a typical plasma process, a high-frequency power supply generates power at the desired RF frequency and RF power, and this power is transmitted to the plasma chamber through RF cables and networks.

[0003] To provide efficient power transfer from the high-frequency power supply to the plasma chamber, an RF matching network is positioned between the high-frequency power supply and the plasma chamber. The purpose of the RF matching network is to convert the plasma impedance to a value suitable for the high-frequency power supply. Often, especially in semiconductor manufacturing processes, RF power is transmitted through 50-ohm coaxial cables, and the system impedance (output impedance) of the high-frequency power supply is also 50 ohms. On the other hand, the impedance of the plasma driven by the RF power varies based on plasma chemistry and other conditions inside the plasma chamber. This impedance must be converted to a non-reactive 50 ohms (i.e., 50+j0) for maximum power transmission. The RF matching network performs this task of continuously converting the plasma impedance to 50 ohms for the high-frequency power supply. In most cases, this conversion is performed so that the input impedance of the RF matching network becomes 50+j0 ohms, i.e., a purely resistive 50 ohms.

[0004] RF matching networks may include a variable capacitor and a microprocessor-based control circuit for controlling the capacitor. The value and size of the variable capacitor are influenced by the power handling capability, operating frequency, and impedance range of the plasma chamber. The primary variable capacitor used in RF matching networks is the vacuum variable capacitor (VVC). A VVC is an electromechanical device consisting of two concentric metal rings that move relative to each other to change capacitance. In complex semiconductor processes where impedance changes are very rapid, the rapid and frequent movement stresses the VVC, leading to its failure. VVC-based RF matching networks are one of the last electromechanical components in semiconductor manufacturing processes.

[0005] However, as semiconductor devices shrink in size and become more complex, the geometric shapes of features become extremely small. As a result, the processing time required to manufacture these features also becomes extremely small, typically in the range of 5-6 seconds. Current RF matching networks take 1-2 seconds to adjust the process, which results in unstable process parameters for a significant portion of the process time. Electronically variable capacitor (EVC) technology (see, for example, U.S. Patent No. 7,251,121, which is incorporated herein by reference in its entirety) makes it possible to reduce this semiconductor processing adjustment time from 1-2 seconds to less than 500 microseconds. EVC-based matching networks are a type of solid-state matching network. The reduction in adjustment time significantly increases the available stable processing time, thereby improving yield and performance.

[0006] While EVC technology is well-known, it has not yet been developed as an industry-recognized replacement for VVCs. However, because EVCs are purely electronic devices, they do not replace VVCs one-to-one in an RF-matched network. Therefore, further advancements are needed to more fully utilize the use of EVCs as part of an RF-matched network. [Overview of the project] [Means for solving the problem]

[0007] The disclosure may also relate to radio frequency (RF) impedance matching circuits, the matching circuit comprising: an RF input configured to be operably coupled to an RF source providing an RF signal; an RF output configured to be operably coupled to a plasma chamber; a series electronic variable capacitor (EVC) electrically coupled in series between the RF input and the RF output, wherein the series EVC has a series variable capacitance, and the series EVC comprises a first fixed capacitor, each of which has a corresponding switch for switching the fixed capacitor on or off to change the series variable capacitance, each switch comprising one or more diodes; a first inductor having a first terminal electrically coupled to common ground and a second terminal electrically coupled between the RF input and the RF output; and a control circuit operably coupled to the series EVC, the control circuit configured to determine a first parameter related to the plasma chamber while the RF source is providing an RF signal to the RF input, and to change the series variable capacitance based on the determined first parameter while the RF signal continues to be provided to the RF input, wherein the change in the series variable capacitance reduces the RF power reflected to the RF source.

[0008] In another embodiment, a method of impedance matching is to couple an impedance matching circuit between an RF source and a plasma chamber, the impedance matching circuit comprising an RF input configured to be operably coupled to the RF source, the RF source providing an RF signal, an RF output configured to be operably coupled to the plasma chamber, and a series electronically variable capacitor (EVC) electrically coupled in series between the RF input and the RF output, the series EVC having a series variable capacitance, the series EVC comprising a first fixed capacitor, each of the first fixed capacitors switching the fixed capacitor on / off to control the series variable capacitance The RF source comprises a series variable capacitance having a first terminal electrically coupled to common ground and a second terminal electrically coupled between an RF input and an RF output, and having a corresponding switch for changing the RF power reflected in the RF source. The RF source comprises a series EVC having one or more diodes and a first inductor having a first terminal electrically coupled to common ground and a second terminal electrically coupled between an RF input and an RF output. The RF source comprises a series variable capacitance having a corresponding switch for changing the RF power, each switch comprising a series EVC having one or more diodes and a first inductor having a first terminal electrically coupled to common ground and a second terminal electrically coupled between an RF input and an RF output, and a first parameter relating to a plasma chamber while an RF source is supplying an RF signal to an RF input, and a series variable capacitance having a determined first parameter while an RF signal continues to be supplied to an RF input, wherein the change in the series variable capacitance reduces or changes the RF power reflected in the RF source.

[0009] In another embodiment, a method for manufacturing a semiconductor includes placing a substrate configured to deposit a material layer on a substrate or to etch a material layer from the substrate into a plasma chamber, energizing a plasma in the plasma chamber by coupling RF power from an RF source into the plasma chamber to carry out deposition or etching, and coupling an impedance matching circuit between the RF source and the plasma chamber while the plasma is energized, the impedance matching circuit including an RF input configured to be operably coupled to the RF source, the RF source providing an RF signal, an RF output configured to be operably coupled to the plasma chamber, and a series electronically variable capacitor (EVC) electrically connected in series between the RF input and the RF output, wherein the series EVC is series variable The RF source provides a series variable capacitance EVC comprising a series EVC having a first fixed capacitor, each of the first fixed capacitors having a corresponding switch for switching the fixed capacitor on / off to change the series variable capacitance, each switch comprising one or more diodes; and a first inductor having a first terminal electrically coupled to common ground and a second terminal electrically coupled between an RF input and an RF output; determining a first parameter related to the plasma chamber while the RF source is providing an RF signal to the RF input; and changing the series variable capacitance based on the determined first parameter while the RF signal continues to be provided to the RF input, wherein the change in the series variable capacitance reduces or changes the RF power reflected in the RF source.

[0010] In another embodiment, the semiconductor processing tool comprises a plasma chamber configured to deposit material on or etch material from a substrate, and an impedance matching circuit operably coupled to the plasma chamber, the matching circuit comprising an RF input configured to operably couple to an RF source providing an RF signal, an RF output configured to operably couple to the plasma chamber, and a series electronically variable capacitor (EVC) electrically coupled in series between the RF input and the RF output, wherein the series EVC has a series variable capacitance, and the series EVC comprises a first fixed capacitor, each of which switches the fixed capacitor on or off to control the series variable capacitance. The present invention comprises a series EVC having corresponding switches for changing capacitance, each switch comprising one or more diodes; a first inductor having a first terminal electrically coupled to common ground and a second terminal electrically coupled between an RF input and an RF output; and a control circuit operably coupled to the series EVC, the control circuit being configured to determine a first parameter related to a plasma chamber while an RF source is supplying an RF signal to an RF input, and to change the series variable capacitance based on the determined first parameter while the RF signal continues to be supplied to the RF input, wherein the change in the series variable capacitance reduces the RF power reflected to the RF source.

[0011] This disclosure will be better understood from the detailed description and accompanying drawings. [Brief explanation of the drawing]

[0012] [Figure 1] Figure 1 is a block diagram of an embodiment of a semiconductor processing system. [Figure 2A] Figure 2A is a schematic diagram of an LC-type embodiment of an L-matched network. [Figure 2B] Figure 2B is a schematic diagram of a CL-type embodiment of an L-matched network. [Figure 3] Figure 3 is a block diagram of an embodiment of a semiconductor processing system having an LC-type L-configuration matched network. [Figure 4]Figure 4 is a block diagram of an embodiment of a circuit for providing variable capacitance using an electronic variable capacitor. [Figure 5] Figure 5 is a schematic diagram of a variable capacitance system for switching individual capacitors of an electronic variable capacitor on and off. [Figure 6] Figure 6 is a block diagram of an embodiment of a switching circuit for an EVC. [Figure 7] Figure 7 is a schematic diagram of an embodiment of an L matching network utilizing a PIN diode switch and a bias circuit. [Figure 8] Figure 8 is a schematic diagram of an alternative bias circuit utilizing a series or parallel combination of reactance elements. [Figure 9] Figure 9 is a schematic diagram of an alternative bias circuit in which the bias inductor is replaced with an LC resonant circuit. [Figure 10] Figure 10 is a flowchart of an exemplary process for impedance matching by varying variable capacitance. [Figure 11] Figure 11 is a flowchart of an exemplary process for impedance matching by varying variable capacitance using a parameter matrix. DETAILED DESCRIPTION OF THE INVENTION

[0013] The following description of preferred embodiments is essentially illustrative and is not intended to limit the invention in any way. The description of exemplary embodiments is intended to be read in conjunction with the accompanying drawings and is considered to be part of the whole written description. Any reference to direction or orientation in the description of exemplary embodiments disclosed herein is intended solely for illustrative purposes and is not intended to limit the scope of the invention in any way. The discussion herein describes and illustrates several possible and non-limiting combinations of features that may exist alone or in combination with other features. Furthermore, where used herein, the term “or” should be interpreted as a logical operator that yields true if one or more of its operands are true. Furthermore, where used herein, the phrase “based on” should be interpreted as “based at least partially,” and is not limited to the interpretation “based entirely.”

[0014] Features of the present invention may be implemented in software, hardware, firmware, or a combination thereof. The computer programs described herein are not limited to any particular embodiment and may be implemented as an operating system, application program, foreground or background process, driver, or any combination thereof. The computer programs may run on a single computer or server processor, or on multiple computers or server processors.

[0015] The processors described herein may be any central processing unit (CPU), microprocessor, microcontroller, computing device, or programmable device or circuit configured to execute computer program instructions (e.g., code). Various processors may be embodied in any suitable type of computer and / or server hardware (e.g., desktop, laptop, notebook, tablet, mobile phone, etc.) and may also include all the usual auxiliary components necessary to form a functional data processing device, including but not limited to buses, software and data storage such as volatile and non-volatile memory, input / output devices, graphical user interfaces (GUIs), removable data storage devices, and wired and / or wireless communication interface devices including Wi-Fi, Bluetooth, and LAN.

[0016] The computer-executable instructions or programs (e.g., software or code) and data described herein may be programmed and tangibly embodied on non-temporary computer-readable media accessible to and obtainable by each of the processors described herein, which configure and instruct the processor to perform desired functions and processes by executing instructions encoded on the medium. A device embodying such a programmable processor configured with such non-temporary computer-executable instructions or programs may be referred to as a “programmable device” or “device,” and a group of programmable devices communicating with each other may be referred to as a “programmable system.” The non-temporary “computer-readable media” described herein includes, but is not limited to, any suitable volatile or non-volatile memory, including random-access memory (RAM) and various types thereof, read-only memory (ROM) and various types thereof, USB flash memory, and magnetic or optical data storage devices (e.g., internal / external hard disks, floppy disks, magnetic tape CD-ROMs, DVD-ROMs, optical discs, ZIP® drives, Blu-ray discs, and others) that can be written to and / or read by a processor operably connected to the medium.

[0017] In certain embodiments, the present invention may be embodied in the form of computer implementation processes and devices, such as processor-based data processing and communication systems, or computer systems for carrying out those processes. The present invention may also be embodied in the form of software or computer program code embodied in a non-temporary computer-readable storage medium, which, when loaded into and executed within a data processing and communication system or computer system, configures the processor to create specific logic circuits configured to carry out processes.

[0018] In the following descriptions in which circuits are shown and described, those skilled in the art will recognize, for clarity, that not all peripheral circuits or components are shown in the diagrams or described in the description. Furthermore, the terms “coupled” and “operably coupled” may refer to the direct or indirect coupling of two components of a circuit.

[0019] The following description of preferred embodiments is purely illustrative and is not intended to limit the invention in any way. The description of exemplary embodiments is intended to be read in conjunction with the accompanying drawings and is considered to be part of the whole written description. Any reference to direction or orientation in the description of exemplary embodiments disclosed herein is purely for illustrative purposes and is not intended to limit the scope of the invention in any way. Relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “left,” “right,” “top,” “bottom,” “front,” and “rear,” as well as their derivatives (e.g., “horizontally,” “downwardly,” “upwardly,” etc.), should be interpreted as referring to the orientation described or the orientation shown in the drawings considered. These relative terms are for illustrative purposes only and do not imply that the device is constructed or operated in a particular orientation unless explicitly stated otherwise. Terms such as “attached,” “affixed,” “connected,” “coupled,” “interconnected,” “secured,” and other similar terms refer, unless otherwise explicitly stated, to relationships in which structures are fixed or attached to one another, either directly or indirectly, through the intervening structure, as well as both movable and rigid attachments or relationships. The discussion herein describes and illustrates some possible and non-limiting combinations of features that may exist alone or in combination with other features. Furthermore, where used herein, the term “or” should be interpreted as a logical operator that yields true if one or more of its operands are true. Furthermore, where used herein, the phrase “based on” should be interpreted as “based at least partially,” and therefore not limited to the interpretation “based entirely.”

[0020] When used throughout, a range is used as a concise expression to describe all values ​​within that range. Any value within the range can be selected as the end of the range. Furthermore, all references cited herein are incorporated herein in their entirety by reference. In the event of any conflict between the definitions in this disclosure and the definitions in the cited references, this disclosure shall prevail.

[0021] Semiconductor processing system Referring to Figure 1, a semiconductor device processing system 5 utilizing a high-frequency power supply 15 is shown. System 85 includes the high-frequency power supply 15 and a semiconductor processing tool 86. The semiconductor processing tool 86 includes a matching network 11 and a plasma chamber 19. In other embodiments, a generator 15 or other power supply may form part of the semiconductor processing tool.

[0022] The semiconductor device can be a microprocessor, a memory chip, or other type of integrated circuit or device. The substrate 27 can be placed in a plasma chamber 19, which is configured to deposit a material layer on the substrate 27 or to etch a material layer from the substrate 27. Plasma processing involves energizing a gas mixture by introducing RF energy into the gas mixture, thereby imparting energy to the gas molecules. This gas mixture is typically contained within a vacuum chamber (plasma chamber 19), and the RF energy is typically introduced into the plasma chamber 19 through electrodes. Thus, the plasma can be energized by coupling RF power from an RF source 15 to the plasma chamber 19 to carry out deposition or etching.

[0023] In a typical plasma process, a high-frequency power supply 15 generates power at radio frequencies, typically in the range of 3 kHz to 300 GHz, and this power is transmitted to the plasma chamber 19 through RF cables and networks. To provide efficient power transfer from the high-frequency power supply 15 to the plasma chamber 19, an intermediate circuit is used to match the fixed impedance of the high-frequency power supply 15 with the variable impedance of the plasma chamber 19. Such intermediate circuits are generally called RF impedance matching networks, or more simply RF matching networks. The purpose of the RF matching network 11 is to convert the variable plasma impedance to a value that more closely matches the fixed impedance of the high-frequency power supply 15. Co-owned and the entire disclosure of which is incorporated herein by reference, U.S. Publication No. 1697781340134_0 No. and No. 1697781340134_1 This issue provides an example of such a harmonized network.

[0024] Unified Network RF matching networks can be constructed using different configurations such as "pi," "L," or "T." In some cases, the matching network is a combination of these configurations. The configuration used often depends on the impedance of the plasma process. Even among these configurations, there are subtle differences. For example, an L-type RF matching network may be an "LC" or "CL" configuration, depending on which reactance element comes first as it progresses from the input to the output of the matching network.

[0025] Figure 2A is a schematic diagram of an LC-type embodiment of the L-matching network 11A. As the signal proceeds from the RF input 13 to the RF output 17, the shunt variable capacitor 33 is the first to appear, and therefore closest to the RF input. The first terminal of the shunt variable capacitor 33 is electrically coupled between the RF input 13 and the RF output 17. The second terminal of the shunt variable capacitor 33 is electrically coupled to the common ground 40. The series variable capacitor 31 is the second to appear as the signal proceeds from the RF input 13 to the RF output 17. The series variable capacitor 31, like the series inductor 35, is coupled in series between the RF input 13 and the RF output 17.

[0026] Figure 2B is a schematic diagram of a CL-type embodiment of the L-matching network 11B. As the signal proceeds from the RF input 13 to the RF output 17, the series variable capacitor 31B is the first to appear, and therefore closest to the RF input. Similar to Figure 2A, the series variable capacitor 31B, like the series inductor 35, is coupled in series between the RF input 13 and the RF output 17. The shunt variable capacitor 33B is the second to appear as the signal proceeds from the RF input 13 to the RF output 17. Similar to Figure 2A, the first terminal of the shunt variable capacitor 33B is electrically coupled between the RF input 13 and the RF output 17, and the second terminal of the shunt variable capacitor 33B is electrically coupled to the common ground 40.

[0027] Figure 3 is a block diagram of one embodiment of a semiconductor processing system 85 having a processing tool 86 including an LC-type L-configuration RF impedance matching network 11. As will be discussed in more detail below, the exemplary matching network 11 utilizes electronically variable capacitors (EVCs) for both the shunt variable capacitor 33 and the series variable capacitor 31. It should be noted that the present invention is not limited in this way. For example, one of the EVCs (e.g., the shunt EVC 33) may be a mechanically variable VVC or may be replaced with a variable inductor.

[0028] An exemplary impedance matching network 11 has an RF input 13 connected to an RF source 15 and an RF output 17 connected to a plasma chamber 19. An RF input sensor 21 may be connected between the RF impedance matching network 11 and the RF source 15. An RF output sensor 49 may be connected between the RF impedance matching network 11 and the plasma chamber 19 so that the RF output from the impedance matching network and the plasma impedance presented by the plasma chamber 19 can be monitored. Certain embodiments may include only one of the input sensor 21 and the output sensor 49. The functions of these sensors 21, 49 are described in more detail below.

[0029] As described above, the RF impedance matching network 11 helps maximize the amount of RF power transmitted from the RF source 15 to the plasma chamber 19 by matching the impedance at the RF input 13 to the fixed impedance of the RF source 15. The matching network 11 may consist of a single module in a single housing designed for electrical connections to the RF source 15 and the plasma chamber 19. In other embodiments, the components of the matching network 11 may be located in different housings, some components may be outside the housing, and / or some components may share a housing with components outside the matching network.

[0030] As is well known in the art, the plasma in the plasma chamber 19 is typically subject to certain fluctuations outside of operational control, such that the impedance presented by the plasma chamber 19 is a variable impedance. Because the variable impedance of the plasma chamber 19 cannot be fully controlled, an impedance matching network may be used to create impedance matching between the plasma chamber 19 and the RF source 15. Furthermore, the impedance of the RF source 15 may be fixed to a set value by the design of the particular RF source 15. The fixed impedance of the RF source 15 may undergo slight fluctuations during use, for example, due to temperature or other environmental fluctuations, but since the fluctuations do not significantly change the fixed impedance from the originally set impedance value, the impedance of the RF source 15 is still considered a fixed impedance for the purposes of impedance matching. Other types of RF sources 15 may be designed so that the impedance of the RF source 15 can be set at or during use. The impedance of such types of RF sources 15 may be controlled by the user (or at least by a programmable controller), and the set value of the impedance may be known at any point during operation, and therefore the set value is effectively a fixed impedance and is still considered fixed.

[0031] The RF source 15 may be a high-frequency power supply of a type well known in the art, which generates an RF signal at a frequency and power appropriate for the process carried out in the plasma chamber 19. The RF source 15 may also be electrically connected to the RF input 13 of the RF impedance matching network 11 using a coaxial cable, which will have the same fixed impedance as the RF source 15 for impedance matching purposes.

[0032] The plasma chamber 19 includes a first electrode 23 and a second electrode 25, and in processes well known in the art, the first and second electrodes 23 and 25, together with a suitable control system (not shown) and plasma in the plasma chamber, enable either or both of the deposition of material on a substrate 27 and etching of material from the substrate 27.

[0033] In an exemplary embodiment, the RF impedance matching network 11 includes a series variable capacitor 31, a shunt variable capacitor 33, and a series inductor 35, forming an L-type matching network. The shunt variable capacitor 33 is shown as having been shunted to a reference potential between the series variable capacitor 31 and the series inductor 35, in this case to common ground 40. Those skilled in the art will recognize that the RF impedance matching network 11 may be configured with a shunt variable capacitor 33 that shunts to a reference potential at the RF input 13 or RF output 17.

[0034] As described above, the RF impedance matching network may alternatively be configured in other configurations, such as a T-type or pi-type configuration, as shown in Figure 3 of U.S. Patent Publication 2021 / 0327684, which is incorporated entirely herein by reference. In certain embodiments, the variable capacitors and switching circuits described below may be included in any configuration suitable for the RF impedance matching network.

[0035] In exemplary embodiments, each of the series variable capacitor 31 and the shunt variable capacitor 33 may be an electronically variable capacitor (EVC) as described in U.S. Patent No. 7,251,121 (which is incorporated in whole by reference), where the EVC may be substantially formed as a capacitor array formed by a plurality of individual fixed capacitors. The series variable capacitor 31 is coupled in series between the RF input 13 and the RF output 17 (which is also in parallel between the RF source 15 and the plasma chamber 19). The shunt variable capacitor 33 is coupled in parallel between the RF input 13 and ground 40. In other configurations, the shunt variable capacitor 33 may be coupled in parallel between the RF output 19 and ground 40. Other configurations may also be implemented without deviating from the functionality of the RF matching network. In yet another configuration, the shunt variable capacitor 33 may be coupled in parallel between a reference potential and one of the RF input 13 and RF output 19.

[0036] The series variable capacitor 31 is connected to the series RF choke and filter circuit 37 and the series driver circuit 39. Similarly, the shunt variable capacitor 33 is connected to the shunt RF choke and filter circuit 41 and the shunt driver circuit 43. Each of the series driver circuit 39 and the shunt driver circuit 43 is connected to the control circuit 45, which consists of a suitable processor and / or signal generation circuit to provide input signals for controlling the series driver circuit 39 and the shunt driver circuit 43. The power supply 47 is connected to each of the RF input sensor 21, the series driver circuit 39, the shunt driver circuit 43, and the control circuit 45, providing operating power to each of these components at the designed current and voltage. The voltage levels provided by the power supply 47, and therefore the voltage levels of each of the RF input sensor 21, the series driver circuit 39, the shunt driver circuit 43, and the control circuit 45 used to perform their respective designated tasks, are a matter of design selection. In other embodiments, various electronic components can be used to enable the control circuit 45 to send commands to the variable capacitors. Furthermore, although the driver circuit, RF choke, and filter are shown separately from the control circuit 45, these components can also be considered to form part of the control circuit 45.

[0037] In exemplary embodiments, the control circuit 45 includes a processor. The processor may be any type of appropriately programmed processing unit (or a set of two or more processing units working together), such as a computer or microprocessor, configured to execute computer program instructions (e.g., code). The processor may be embodied in any appropriate type of computer and / or server hardware (e.g., desktop, laptop, notebook, tablet, mobile phone, etc.) and may also include all the usual auxiliary components necessary to form a functional data processing unit, including but not limited to buses, software and data storage such as volatile and non-volatile memory, input / output devices, graphical user interfaces (GUIs), removable data storage devices, and wired and / or wireless communication interface devices including Wi-Fi, Bluetooth, and LAN. The processor in exemplary embodiments consists of specific algorithms that enable the harmonized network to perform the functions described herein.

[0038] The combination of the series variable capacitor 31 and the shunt variable capacitor 33 allows the combined impedance of the RF impedance matching network 11 and the plasma chamber 19 to be controlled to match, or at least substantially match, the fixed impedance of the RF source 15 using the control circuit 45, the series driver circuit 39, and the shunt driver circuit 43.

[0039] The control circuit 45 is the brain of the RF impedance matching network 11. This is because it receives multiple inputs from sources such as the RF input sensor 21 and the series variable capacitor 31 and shunt variable capacitor 33, determines the changes to the series variable capacitor 31 and shunt variable capacitor 33, and performs the calculations necessary to send commands to the series variable capacitor 31 and shunt variable capacitor 33 to generate impedance matching. The control circuit 45 is a type of control circuit commonly used in semiconductor manufacturing processes and is therefore known to those skilled in the art. The difference between the control circuit 45 and prior art control circuits lies in the programming differences, which explain the speed at which the RF impedance matching network 11 can perform the switching of the variable capacitors 31 and 33 and impedance matching.

[0040] Each of the series RF choke and filter circuit 37 and the shunt RF choke and filter circuit 41 is configured to allow a DC signal to pass between the series driver circuit 39 and the shunt driver circuit 43 and their respective series variable capacitors 31 and shunt variable capacitors 33, while simultaneously blocking the RF signal from the RF source 15 to prevent the RF signal from leaking to the outputs of the series driver circuit 39 and the shunt driver circuit 43 and the output of the control circuit 45. The series RF choke and filter circuit 37 and the shunt RF choke and filter circuit 41 are of a type known to those skilled in the art.

[0041] EVC Capacitor Array Figure 4 is a block diagram of one embodiment of an electronic circuit 150 for providing variable capacitance using an electronic variable capacitor 151. The circuit 150 utilizes an EVC 151 which includes two capacitor arrays 151a and 151b. The exemplary first capacitor array 151a has a first group of individual fixed capacitors, each having a first capacitance value. The second capacitor array 151b has a second group of individual fixed capacitors, each having a second capacitance value. The first capacitance value is different from the second capacitance value so that the EVC 151 can provide coarse and fine control of the capacitance generated by the EVC 151. The first and second capacitor arrays are coupled in parallel between a signal input 113 and a signal output 130.

[0042] The first and second capacitance values ​​can be any values ​​sufficient to provide the desired overall capacitance value for the EVC 151. In one embodiment, the second capacitance value is half (1 / 2) or less of the first capacitance value. In another embodiment, the second capacitance value is one-third (1 / 3) or less of the first capacitance value. In yet another embodiment, the second capacitance value is one-quarter (1 / 4) or less of the first capacitance value.

[0043] The electronic circuit 150 further includes a control circuit 145, which may have features similar to the control circuit 45 described above. The control circuit 145 is operably coupled to the first capacitor array 151a and the second capacitor array 151b by a command input 129, the command input 129 being operably coupled to the first capacitor array 151a and the second capacitor array 151b. In the exemplary embodiment, the command input 129 has a direct electrical connection to the capacitor arrays 151a and 151b, but in other embodiments, this connection may be indirect. The coupling of the control circuit 145 to the capacitor arrays 151a and 151b will be described in more detail below.

[0044] The control circuit 145 is configured to change the variable capacitance of the EVC 151 by controlling the on and off states of (a) each individual fixed capacitor of the first plurality of individual fixed capacitors, and (b) each individual fixed capacitor of the second plurality of individual fixed capacitors. As described above, the control circuit 145 may have similar features to those described with respect to the control circuit 45 in the Figure above. For example, the control circuit 145 can receive inputs from capacitor arrays 151a and 151b, perform calculations to determine changes to capacitor arrays 151a and 151b, and send commands to capacitor arrays 151a and 151b to change the capacitance of the EVC 151. The EVC 151 in Figure 4 may include a plurality of electronic switches. Each electronic switch may be configured to activate and deactivate one or more individual capacitors.

[0045] Similar to the control circuit 45 in the aforementioned figure, the control circuit 145 may also be connected to a driver circuit 139 and an RF choke and filter circuit 137. The control circuit 145, the driver circuit 139, and the RF choke and filter circuit 137 may have capabilities similar to those discussed with respect to the aforementioned figure. In an exemplary embodiment, the driver circuit 139 is operably coupled between the control circuit 145 and a first capacitor array 151a and a second capacitor array 151b. The driver circuit 139 is configured to change the variable capacitance based on a control signal received from the control circuit 145. The RF filter 137 is operably coupled between the driver circuit 139 and the first capacitor array 151a and the second capacitor array 151b. In response to a control signal transmitted by the control unit 145, the driver circuit 139 and the RF filter 137 are configured to transmit a command signal to the command input 129. The command signal is configured to change the variable capacitance by instructing at least one of the electronic switches to either (a) activate or deactivate at least one of the first set of individual capacitors, or (b) activate or deactivate at least one of the second set of individual capacitors.

[0046] In exemplary embodiments, the driver circuit 139 is configured to switch the high-voltage source on or off in less than 15 microseconds, and the high-voltage source controls the respective electronic switches of the first and second capacitor arrays for the purpose of changing the variable capacitance. However, the EVC 151 may also be switched by any of the means or speeds considered in this application.

[0047] The control circuit 145 may be configured to calculate the coarse capacitance and fine capacitance values ​​provided by the respective capacitor arrays 151a and 151b. In an exemplary embodiment, the control circuit 145 is configured to calculate the coarse capacitance value provided by controlling the on and off states of the first capacitor array 151a. Furthermore, the control circuit is configured to calculate the fine capacitance value provided by controlling the on and off states of the second capacitor array 151b. In other embodiments, the capacitor arrays 151a and 151b may provide alternative levels of capacitance. In other embodiments, the EVC may utilize additional capacitor arrays.

[0048] The EVC 151 in Figure 4 can be used in a variety of systems that require varying capacitance. For example, the EVC 151 can be used as a series EVC and / or shunt EVC in an L-matched network, or as one or both of a shunt EVC in a pi-matched network. Regarding the difference between capacitance values, it is often desirable to have both a sufficiently fine resolution of the overall capacitance of the circuit and a wide range of capacitance values ​​that allows for better impedance matching at the input of an RF-matched network, and the EVC 151 makes this possible.

[0049] Switching individual capacitors on / off to change the EVC capacitance. As described above, an EVC is a type of variable capacitor that can use multiple switches, each used to generate an open circuit or a short circuit, along with individual series capacitors to change the capacitance of the variable capacitor. The switches can be mechanical (such as relays) or solid-state (such as PIN diodes, transistors, or other switching devices). The following is a consideration of methods for setting up an EVC or other variable capacitor to provide a changing capacitance.

[0050] In what is called a "cumulative setup" for EVCs or other variable capacitors, the approach of linearly increasing the capacitor value from the minimum starting point (all switches open) is to progressively increase the number of fine-tuning capacitors that are switched into the circuit. When the maximum number of fine-tuning capacitors are switched into the circuit, the coarse-tuning capacitors are switched on and the fine-tuning capacitors are switched off. The process restarts by increasing the number of fine-tuning capacitors that are switched into the circuit until all fine-tuning and coarse-tuning capacitors are switched on, at which point another coarse-tuning capacitor is switched on and a fine-tuning capacitor is switched off. This process can continue until all coarse-tuning and fine-tuning capacitors are switched on.

[0051] In this embodiment, all fine-tuning capacitors have the same or substantially similar values, and all coarse-tuning capacitors have the same or substantially similar values. Furthermore, the capacitance value of one coarse-tuning capacitor is approximately equal to the combined capacitance value of all fine-tuning capacitors and any additional fine-tuning capacitors in the circuit, thus allowing for a linear increase in capacitance. However, the embodiments are not limited in this way. Fine-tuning capacitors (and coarse-tuning capacitors) do not need to have the same or substantially similar values. Furthermore, the capacitance value of one coarse-tuning capacitor does not need to be equal to the combined capacitance value of all fine-tuning capacitors and any additional fine-tuning capacitors. In one embodiment, the coarse capacitance value and the fine capacitance value have a ratio substantially similar to 10:1. In another embodiment, the second capacitance value is less than or equal to half (1 / 2) of the first capacitance value. In yet another embodiment, the second capacitance value is less than or equal to one-third (1 / 3) of the first capacitance value. In yet another embodiment, the second capacitance value is less than or equal to one-quarter (1 / 4) of the first capacitance value.

[0052] An example of the aforementioned embodiment in an ideal setting is when the fine-tuning capacitor is equal to 1pF and the coarse-tuning capacitor is equal to 10pF. In this ideal setting, when all switches are open, the capacitance is equal to 0pF. When the first switch is closed, there is 1pF in the circuit. When the second switch is closed, there is 2pF in the circuit, and so on until 9pF is obtained when the nine fine-tuning switches are closed. Next, the first 10pF capacitor is switched into the circuit, opening the nine fine-tuning switches, and the total capacitance becomes 10pF. Next, the fine-tuning capacitors are switched into the circuit at 11pF to 19pF. Next, another coarse-tuning capacitor can be switched into the circuit, and all fine-tuning capacitors can be switched out of the circuit, potentially yielding 20pF. This process can be repeated until the desired capacitance is reached.

[0053] This may be carried out in one more step. Using the previous embodiment with nine 1pF capacitors and nine 10pF capacitors, the variable capacitor circuit can have an even larger value, 100pF, to switch the circuit on / off. This increases the previous capacitor array up to 99pF, and then the 100pF capacitor can be used for the next increment. This can be repeated further with larger increments and can also be used in conjunction with any counting system. According to the cumulative setup, increasing the total capacitance of the variable capacitor is achieved by switching on more fine-tuning capacitors or fine-tuning capacitors than are already switched on, without switching off the coarse-tuning capacitors that are already switched on. Furthermore, if the control circuit has not switched on more coarse-tuning capacitors than are already switched on, the control circuit will switch on more fine-tuning capacitors than are already switched on, without switching off the fine-tuning capacitors that are already switched on. U.S. Patents 10,431,428 and 11,195,698 relating to cumulative setups are incorporated herein by reference in their entirety. It should be noted that the claimed invention is not limited to the use of cumulative setups. For example, U.S. Patents 10,679,824 and 10,692,699, which are incorporated herein by reference in their entirety, consider alternative setups such as “partial binaries.”

[0054] Figure 5 is a schematic diagram of a variable capacitance system 155 for switching the on / off of individual fixed capacitors of an electronic variable capacitor. Where this figure uses similar reference numerals to those in Figure 4, it should be understood that the relevant components may have similar characteristics to those discussed in Figure 4. The variable capacitance system 155 comprises a variable capacitor 151 for providing a changing capacitance. The variable capacitor 151 has an input 113 and an output 130. The variable capacitor 151 includes a plurality of individual fixed capacitors 153 operably coupled in parallel. The plurality of capacitors 153 include a first (fine-tuning) capacitor 151a and a second (coarse-tuning) capacitor 151B. Furthermore, the variable capacitor 151 includes a plurality of switches 161. Of the switches 161, one switch is operably coupled in series to each of the plurality of capacitors, allowing each capacitor to be switched on / off, thereby enabling the variable capacitor 151 to provide a changing total capacitance. The variable capacitor 151 has a variable total capacitance that increases when an individual capacitor 153 is switched on and decreases when an individual capacitor 153 is switched off.

[0055] Switch 161 may be coupled to a switch driver circuit 139 to drive the switch on and off. The variable capacitance system 155 may further include a control unit 145 operably coupled to a variable capacitor 151. Specifically, the control unit 145 may be operably coupled to the driver circuit 139 to command the driver circuit 139 to switch one or more of the switches 161, thereby turning one or more of the capacitors 153 on or off. In one embodiment, the control unit 145 may form part of a control unit that controls a variable capacitor, such as a control unit that commands the variable capacitor of a matching network to change its capacitance to achieve impedance matching. The driver circuit 139 and the control unit 145 may have features similar to those described above with reference to Figure 4, and therefore, RF chokes and filters as discussed above may also be utilized.

[0056] Electronic variable capacitor switching circuit Figure 6 shows an embodiment of a switching circuit 140A for the EVC 151 of a matched network according to one embodiment. In the exemplary embodiment, the EVC 151 is the EVC 151 of Figure 5, but the EVC of the present invention is not so limited as it may have any of the other features discussed herein, including a different number of individual fixed capacitors 153 and individual fixed capacitors with values ​​different from those discussed with respect to Figure 5. Furthermore, the EVC may form part of any type of matched network, including the various types of matched networks discussed herein. An exemplary matched network is coupled between an RF source and a plasma chamber, for example, as shown in the preceding figures.

[0057] An exemplary EVC includes a plurality of individual fixed capacitors 153A, 153B coupled to a first terminal 113. Each individual capacitor 153A, 153B has a corresponding switch 161A, 161B configured to switch the individual capacitor on and the individual capacitor off, thereby changing the total capacitance of the EVC 151. In the exemplary embodiment, switch 161A is in series with the individual capacitor 153A, but the invention is not limited thereto. Furthermore, in the exemplary embodiment, switch 161A is a PIN diode, but the invention is not limited thereto and may be another type of switch, such as a NIP diode. In yet another embodiment, the switch may be a MOSFET, a JFET, or another type of switch. Furthermore, in the exemplary embodiment, the PIN diodes have a common anode configuration such that the anode of each PIN diode 161A, 161B is coupled to ground 40, which may be any common node. However, the present invention is not limited thereto, as in other embodiments the EVC may use a common cathode configuration such that the cathode of each PIN diode is coupled to ground 40 (and the components of the driver circuit are changed accordingly). Furthermore, it should be noted that two or more switches may be used in series to increase the rated voltage and / or two or more switches may be used in parallel to increase the rated current of the channel.

[0058] Each PIN diode switch 161A, 161B has its own switching circuit 140A, 140B, which is connected to the control circuit 145. The switching circuit 140B is shown as including a switch 161B, a filter 141B (which may be similar to the filter circuits 37, 41 discussed above), and a driver circuit 139B. The filter 141B may be, for example, an LC circuit similar to the filter circuit 9 of U.S. Patent No. 10,340,879, or a filter circuit other than output 207 in Figure 6A of U.S. Patent No. 9,844,127. Each of these patents is incorporated herein by reference in whole.

[0059] The exemplary switching circuit 140A has the same components as the switching circuit 140B, but the driver circuit 139A is shown in more detail. The driver circuit 139A may be integrated with the PIN diode 161A (or other type of switch), or with the individual fixed capacitors of the EVC of the matching network. Those skilled in the art will recognize that certain components of the driver circuit 139A can be replaced with other components that perform the same essential function, while greater functionality allows for variability of other circuit parameters (e.g., voltage range, current range, etc.).

[0060] The exemplary driver circuit 139A has two inputs 105A-1 and 105A-2 for receiving control signals from the control circuit to control the voltage to a common output 107A connected to a PIN diode 161A. The voltage to the common output 107A switches the PIN diode 161A between an on state and an off state, and therefore switches the individual capacitor 153A to which the PIN diode 161A is connected on and off. In this exemplary embodiment, the state of the individual capacitor follows the state of the corresponding PIN diode, so that when the PIN diode is on, the individual capacitor is also on, and similarly, when the PIN diode 161A is off, the individual capacitor is also off. Thus, the description herein regarding the state of the PIN diode 161A essentially describes the simultaneous state of the corresponding individual capacitor 153A of the EVC 151.

[0061] In a preferred embodiment, each of the first power switch 111A and the second power switch 113A is a MOSFET having a body diode, but in other embodiments, either of the power switches may be another type of switch, including any other type of semiconductor switch. The present invention can utilize a variety of switching circuit configurations. For example, the present invention may use either the switching circuit shown in Figures 3, 6A, and 6B disclosed in U.S. Patent Application No. 9,844,127, or the switching circuit shown in Figure 18 disclosed in U.S. Patent Application No. 10,340,879. As stated above, each of these patents is incorporated herein by reference in its entirety.

[0062] In an exemplary embodiment, a high-voltage power supply 115A is connected to a first power switch 111A and provides a high-voltage input that is switchably connected to a common output 107A. A low-voltage power supply 117A is connected to a second power switch 113A and similarly provides a low-voltage input that is switchably connected to a common output 107A. In the configuration of the driver circuit 139A shown, the low-voltage power supply 117A may supply a low-voltage input of about -3.3V. Such a low voltage having negative polarity is sufficient to provide a forward bias for switching the PIN diode 161A. For other configurations of the driver circuit 139A, higher or lower voltage inputs may be used, and the low-voltage inputs may have positive polarity depending on the configuration and type of the electronic switch being controlled.

[0063] In the exemplary switching circuit 140A, a first power switch 111A and a second power switch 113A are configured to asynchronously connect a high-voltage power supply 115A and a low-voltage power supply 117A to a common output 107A for the purpose of switching a PIN diode 161A between an on and off state, thereby switching the corresponding individual fixed capacitor 153A in or out. The high-voltage power supply 115A provides a reverse bias DC voltage for the PIN diode switch 161A. This reverse-biases the PIN diode 161A, thus preventing current from flowing, and therefore switches its corresponding individual capacitor 153A off, and may therefore also be called a “blocking voltage.” As used herein, the term “blocking voltage” refers to any voltage used to switch its corresponding individual capacitor off or on. It should be further noted that the switching circuit may be any circuit for switching an individual capacitor on and off, including, but not limited to, the one shown in Figure 6, and including, the one shown in whole in U.S. Patent No. 9,844,127, which is incorporated herein by reference.

[0064] In an exemplary embodiment, the control circuit provides separate control signals to separate inputs 105A-1 and 105A-2 of the driver circuit 139A. In this embodiment, the separate inputs 105A-1 and 105A-2 are coupled to first and second power switches 111A and 113A, respectively. The control signals for the separate inputs may have opposite polarity. In a preferred embodiment, the first power switch 161A and the second power switch 113A are MOSFETs, and the separate control signals proceed to separate drivers to power the MOSFETs. In an alternative embodiment, the control circuit 145 provides a common input signal. The common input signal may asynchronously control the on and off states of the first power switch 111A and the second power switch 113A, so that when the first power switch 111A is ON, the second power switch 113A is OFF, and similarly, when the first power switch is OFF, the second power switch 113A is ON. In this way, a common input signal asynchronously connects the high-voltage and low-voltage inputs to the common output for the purpose of controlling the first power switch 111A and the second power switch 113A to switch the PIN diode 161A between the on and off states. However, the present invention is not limited to such asynchronous control.

[0065] Inputs 105A-1 and 105A-2 may be configured to receive any type of appropriate control signal for the selected switch type for the first power switch 111A and the second power switch 113A, which may be, for example, a +15V control signal. In a preferred embodiment, the driver circuit has separate drivers for driving the first power switch 111A and the second power switch 112A, respectively. In another embodiment, the first power switch 111A and the second power switch 113A are selected so as to receive a common input signal.

[0066] In exemplary embodiments, power supply 118 is coupled to the input of low-voltage power supply 117A. In preferred embodiments, power supply 118 provides 24VDC. However, the present invention is not limited in this way, as other power supplies may be used.

[0067] In an exemplary embodiment, when the second power switch 113A is ON, current 163A flows between the PIN diode 161A and the low-voltage power supply 117A. Simultaneously, current flows from power supply 118 to the input of low-voltage power supply 117A and to ground 40. A sensor may be positioned at a node of the switching circuit 140A to measure a parameter associated with the current 163A flowing between the low-voltage power supply 117A and the PIN diode switch 161A. In an exemplary embodiment, sensor 164A is positioned at the input of low-voltage power supply 117A and measures the current 167A flowing from power supply 118 to the input, which is related to current 163A. In other embodiments, the sensor may be located at other locations in the switching circuit 140A, such as at node 165A (output of the low-voltage power supply) or node 166A (anode of PIN diode 161A), or in the path of filter 141A between the driver circuit and the switch (e.g., driver output 107A or output of filter 141A). In an exemplary embodiment, the parameter is the value of the current flowing through the node, but in other embodiments, the measured parameter may be any parameter (including voltage) associated with the current flowing through the switch(s). In yet another embodiment, the parameter is any parameter associated with the driver circuit.

[0068] Bias circuit for matched networks Figure 7 is a schematic diagram of an embodiment of an LC-type L-matched network 30 having PIN diode switches 161-1, 161-2 and a bias circuit 124, and utilizing EVCs 151-1, 151-2. The EVCs and their components are equivalent to the EVC 151 shown in Figure 6. Thus, the bias outputs 107-1, 107-2 are equivalent to the bias output 107A of the driver circuit 139A. Each of the bias outputs 107-1, 107-2 determines whether the PIN diodes are reverse-biased or forward-biased, and therefore whether the PIN diodes are switched on or off. It should be noted that the present invention is not limited to the method of switching the diodes on / off as shown in Figure 6, as other methods can be used.

[0069] Certain features of the matched network, such as those shown in Figure 3 (sensors, chokes, filters, drivers, control circuits, and power supplies), have been omitted for clarity to allow for the identification of the features shown. It is understood that these features may, among other things, be included in the matched network 30. In the exemplary embodiment, the diode is a PIN diode, but in other embodiments, the diode may be a NIP diode or another type of diode.

[0070] In this embodiment, the matching network uses EVCs for both the shunt variable capacitor 151-1 and the series variable capacitor 151-2. This is not mandatory. For example, the shunt variable capacitor 151-1 may be a mechanically variable VVC or a variable inductor (mechanically or electronically variable). In yet another embodiment, the second variable capacitor may be omitted. In such examples, for example, frequency adjustment (adjustment of the frequency of the RF signal from the RF source) may be used in conjunction with capacitance adjustment to achieve impedance matching.

[0071] A specific challenge arises when using PIN diodes to switch fixed individual capacitors of EVCs in series, such as series EVC 151-2. While the shunt variable capacitor 151-1 in the L matching network 30 is grounded (see PIN diode 153A in Figure 6, which is grounded by common ground 40), this is not the case for series EVC 151-2. To address this problem, the exemplary matching network 30 utilizes a bias inductor 126 that forms part of the bias circuit 124. The bias inductor 126 provides a DC bias path for forward and reverse biasing the PIN diode 161-2.

[0072] As described above with respect to Figure 6, the PIN diode is a two-terminal device that can be turned on by passing a bias current through the PIN diode, or turned off by applying a sufficiently high blocking voltage to reverse-bias the PIN diode and prevent any RF voltage from turning on the PIN diode. For the bias to work properly, as shown in Figure 6, there must be a DC path to the bias circuit through the PIN diode for the shunted PIN diode. The bias circuit 124 allows the series-connected PIN diode 161-2 to be biased using a DC source (e.g., power supply 115A or 117A in Figure 6) because the series-connected PIN diode 161A does not have a connection to ground 40 in Figure 6.

[0073] The exemplary bias circuit 124 allows the DC bias current to flow through the bias inductor 126 and complete the bias circuit path. Furthermore, the blocking capacitor 128 prevents the DC blocking voltage from appearing at the output 17.

[0074] The bias signals to each PIN diode switch 161-1, 161-2 are applied through bias outputs 107-1, 107-2. As shown in Figure 6, the connection point is connected to the PIN diode driver 139A through a suitable RF block filter 141A.

[0075] The following is the capacitor C of the series-switched EVC 151-2. 21 Let's explain an example. In this case, as discussed in Figure 6, a negative (forward) bias (for example, from a low-voltage power supply 117A) is applied to bias output B 21 Through PIN diode D 21 This applies to the following: Negative (forward) bias is applied from bias inductor 126 to PIN diode D 21 Bias connection B through 21 This results in a bias current flowing inward. Similarly, when a (reverse bias) blocking voltage is applied (for example, from the high-voltage power supply 115A in Figure 6), the positive blocking voltage causes the PIN diode D 21 The DC blocking voltage is applied to the cathode terminal and again completes the blocking voltage circuit through the bias inductor 126. The blocking capacitor 128 prevents the DC blocking voltage from appearing at the output 17 of the matching network.

[0076] The presented "L" type matched network is an example, and it should be noted that several modifications are possible to this shape and component configuration. For example, the anodes of the PIN diodes 161-1 and 161-2 can be connected to the individual fixed capacitors 153-1 and 153-2 instead of the cathodes. Furthermore, the relative positions of the series EVC 151-2 and the blocking capacitor 128 may be reversed so that the blocking capacitor 128 is on the RF input 13 side. Moreover, the shape of the L matched network may be a CL configuration (such as that shown in Figure 2B) where the series leg is on the RF input 13 and the shunt leg is on the RF output 17, rather than an LC configuration. In this case, the positions of the bias conductor 126 and the blocking capacitor 128 also change accordingly.

[0077] Figures 8-9 show further modifications. Figure 8 is a schematic diagram of an alternative bias circuit 124B. This bias circuit 124B illustrates an example of how to fabricate a bias inductor and / or blocking capacitor using a series or parallel combination of one or more reactance elements. For example, the bias inductor may comprise multiple inductors 126A-C electrically coupled in series (and / or parallel). Furthermore, the blocking capacitor may comprise multiple capacitors 128A-C electrically coupled in parallel (and / or series). Figure 9 is a schematic diagram of an alternative bias circuit 124C, where the bias inductor is replaced with an LC resonant circuit comprising inductor 126-1 and capacitor 126-2 coupled in parallel. Finally, note that a series combination of consecutive diodes (two anodes or two cathodes connected together) can also be in parallel with the bias inductor.

[0078] Determining the capacitance value to achieve matching Figure 10 is a flowchart of process 500A for impedance matching according to one embodiment. The matching network may include components similar to those discussed above. In one embodiment, the matching network of Figure 3 is used. In the first step of the illustrated process 500A in Figure 10, the input impedance at RF input 13 is determined (step 501A). The input impedance is based on RF input parameters detected at RF input 13 by RF input sensor 21. RF input sensor 21 can be any sensor configured to detect RF input parameters at RF input 13. Input parameters can be any parameters measurable at RF input 13, including voltage, current, or phase at RF input 13. In the exemplary embodiment, RF input sensor 21 detects voltage, current, and phase at RF input 13 of the matching network 11. Based on the RF input parameters detected by RF input sensor 21, control circuit 45 determines the input impedance.

[0079] Next, the control circuit 45 determines the plasma impedance presented by the plasma chamber 19 (step 502A). In one embodiment, the determination of the plasma impedance is based on the input impedance (determined in step 501A), the capacitance of the series EVC 31, and the capacitance of the shunt EVC 33. In another embodiment, the determination of the plasma impedance can be performed using an output sensor 49 operably coupled to the RF output, the RF output sensor 49 being configured to detect RF output parameters. The RF output parameters can be any parameters measurable at the RF output 17, including voltage, current, or phase at the RF output 17. The RF output sensor 49 may detect output parameters at the RF output 17 of the matched network 11. Based on the RF output parameters detected by the RF output sensor 21, the control circuit 45 may determine the plasma impedance. In yet another embodiment, the determination of the plasma impedance may be based on both RF output parameters and RF input parameters.

[0080] Once the variable impedance of the plasma chamber 19 is known, the control circuit 45 can determine the changes to be made to one or both of the variable capacitances of the series EVC and shunt EVCs 31, 33 in order to achieve impedance matching. Specifically, the control circuit 45 determines a first capacitance value for the series variable capacitance and a second capacitance value for the shunt variable capacitance (step 503A). These values ​​represent the new capacitance values ​​for the series EVC 31 and shunt EVC 33 in order to enable impedance matching, or at least substantial impedance matching. In exemplary embodiments, the determination of the first and second capacitance values ​​is based on the variable plasma impedance (determined in step 502A) and the fixed RF source impedance.

[0081] Once the first and second capacitance values ​​are determined, the control circuit 45 generates a control signal to change at least one of the series variable capacitance and shunt variable capacitance to the first and second capacitance values, respectively (step 504A). This takes approximately t = -5 μs. The control signal instructs the switching circuit to change one or both of the series EVC 31 and shunt EVC 33 variable capacitances.

[0082] In an exemplary embodiment, the EVC is changed while the RF source continues to supply an RF signal to the RF input to the matched network. It is not necessary to stop supplying the RF signal before changing the EVC. The determination of the new capacitance value and the change in the EVC can be performed continuously (and repeatedly) while the RF signal continues to be supplied to the matched network.

[0083] The changes in EVCs 31 and 33 take a total of approximately 9–11 microseconds, compared to approximately 1–2 seconds in an RF matching network using VVCs. Once the switching to the different variable capacitances is complete, there is a delay as the additional individual capacitors making up the EVCs couple and charge the circuit. This part of the matching tuning process takes approximately 55 microseconds. Finally, the RF power profile 403 shows a decrease from a peak-to-peak value of approximately 380 mV to a peak-to-peak value of approximately 100 mV just before t=56 microseconds. This decrease in the RF power profile 403 represents a decrease in reflected power 407, which occurs over a period of approximately 10 microseconds, at which point the matching tuning process is considered complete.

[0084] Changes in the series variable capacitance and shunt variable capacitance may include transmitting control signals to a series driver circuit 39 and a shunt driver circuit 43 to control the series variable capacitance and the shunt variable capacitance, respectively, wherein the series driver circuit 39 is operably coupled to the series EVC 31, and the shunt driver circuit 43 is operably coupled to the shunt EVC 43. When the EVCs 31, 33 are switched to their desired capacitance values, the input impedance may be matched to a fixed RF source impedance (e.g., 50 ohms), thus impedance matching can be achieved. If sufficient impedance matching does not occur due to fluctuations in plasma impedance, the 500A process may be repeated one or more times to achieve impedance matching, or at least substantial impedance matching.

[0085] Using an RF matching network 11 such as that shown in Figure 3, the input impedance can be expressed as follows. [Mathematical Expression]

[0086] where Z in is the input impedance, Z P is the plasma impedance, Z L is the series inductor impedance, Z series is the series EVC impedance, and Z shunt is the shunt EVC impedance. In an exemplary embodiment, the input impedance (Z in ) is determined using the RF input sensor 21. The EVC impedances (Z series and Z shunt ) are known at any given time by the control circuit, as the control circuit uses it to command various individual fixed capacitors of each of the series and shunt EVCs to turn on or off. Furthermore, the series inductor impedance (Z L ) is a fixed value. Accordingly, the system can use these values to solve for the plasma impedance (Z P ).

[0087] This determined plasma impedance (Z P ) and known desired input impedance (Z' in ) (typically 50 ohms), and known series inductor impedance (Z L Based on this, the system uses a new series EVC impedance (Z' series ) and shunt EVC impedance (Z' shunt ) can be determined.

number

[0088] Newly calculated series EVC variable impedance (Z' series ) and shunt EVC variable impedance (Z' shunt Based on this, the system can determine a new capacitance value for the series variable capacitance (first capacitance value) and a new capacitance value for the shunt variable capacitance (second capacitance value). When these new capacitance values ​​are used for the series EVC 31 and shunt EVC 33, respectively, impedance matching can be achieved.

[0089] An exemplary method for calculating desired first and second capacitance values ​​and reaching those values ​​in a single step is significantly faster than stepwise moving the two EVCs to either zero out the error signal or minimize the reflected power / reflection coefficient. In semiconductor plasma processing where a faster tuning scheme is desirable, this approach provides a significant improvement in the tuning speed of the matching network. It should be noted that the method for determining new EVC capacitance values ​​discussed herein is merely illustrative. In other embodiments, other parameters and / or methods may be used to determine new EVC capacitance values. For example, the parameters on which the new capacitance values ​​are based may be any parameters related to the plasma chamber.

[0090] Determining capacitance values ​​using a parameter matrix Figure 11 provides an alternative process 500 for impedance matching using a parameter matrix. In the exemplary process, the control circuit 45 (see Figure 3 for matching network components) is configured and / or programmed to perform each of the steps. As one of two initial steps, RF parameters are measured at RF input 13 by RF input sensor 21, and the input impedance at RF input 13 is calculated using the measured RF parameters (step 501). For this exemplary process 500, forward voltage and forward current are measured at RF input 13. In certain other embodiments, RF parameters may be measured at RF output 17 by RF output sensor 49, but such embodiments may require calculations different from those described below. In yet another embodiment, RF parameters may be measured at both RF input 13 and RF output 17.

[0091] An impedance matching circuit coupled between the RF source 15 and the plasma chamber 19 may be characterized by one of several types of parameter matrices known to those skilled in the art, including a two-port parameter matrix. The S-parameter matrix and the Z-parameter matrix are two examples of such parameter matrices. Other examples include, but are not limited to, the Y-parameter matrix, G-parameter matrix, H-parameter matrix, T-parameter matrix, and ABCD-parameter matrix. Those skilled in the art will also recognize that these various parameter matrices can be mathematically converted to one another for electrical circuits such as matching networks. A second initial step of the exemplary process 500 is to look up the parameter matrix for an existing configuration of the impedance matching circuit in a parameter lookup table (step 502). The existing configuration of the impedance matching circuit is defined by the existing operating parameters of the impedance matching circuit, in particular, the existing array configuration for both the series EVC 31 and the shunt EVC 33. To achieve impedance matching, the existing configuration of the impedance matching circuit is changed to a new configuration of the impedance matching circuit as part of the exemplary process 500.

[0092] A parameter lookup table includes multiple parameter matrices, each parameter matrix associated with a specific configuration of the serial EVC 31 and shunt EVC 33. The parameter lookup table may include one or more of the parameter matrices of the types described above. In exemplary process 500, the parameter lookup table includes at least several S-parameter matrices. In certain embodiments, the parameter lookup table may include at least several Z-parameter matrices. In embodiments where the parameter lookup table includes multiple types of parameter matrices, different types of parameter matrices are associated within the parameter lookup table in such a way that the need for mathematical transformations between different types of parameter matrices is eliminated. For example, a T-parameter matrix may be included as part of the parameter lookup table, and each T-parameter matrix is ​​associated with a corresponding S-parameter matrix resulting from a transformation between two matrices.

[0093] The input impedance calculation (step 501) and parameter matrix lookup (step 502) may be performed in any order. After the input impedance is calculated (step 501) and the parameter matrix for the existing configuration of the impedance matching circuit is identified in the parameter lookup table (step 502), the plasma or load impedance may be calculated using the calculated input impedance and the parameter matrix for the existing configuration (step 503). Next, from the calculated plasma impedance, matching configurations of the series EVC 31 and shunt EVC 33 that achieve impedance matching, or at least substantial impedance matching, between the RF source 15 and the plasma chamber 19 are retrieved in the array configuration lookup table (step 504). These matching configurations from the array configuration lookup table are array configurations that result in new capacitance values ​​for the series EVC 31 and shunt EVC 33, and impedance matching is achieved with the new array configuration and the associated new capacitance values. The array configuration lookup table is a table of array configurations for series EVCs 31 and shunt EVCs 33, and when used in combination, includes each possible array configuration for series EVCs 31 and shunt EVCs 33. As an alternative to using the array configuration lookup table, the actual capacitance values ​​of EVCs 31 and 33 may be calculated during the process, but such real-time calculations of capacitance values ​​are inherently more time-consuming than searching for a matched configuration in the array configuration lookup table. After the matched configurations for series EVCs 31 and shunt EVCs 33 are identified in the array configuration lookup table, one or both of the series and shunt array configurations are changed to the identified matched configurations for series EVCs 31 and shunt EVCs 33, respectively (step 505).

[0094] The change between the series array configuration and the shunt array configuration (step 505) may include the control circuit 45 controlling the series array configuration and the shunt array configuration, respectively, by transmitting control signals to the series driver circuit 39 and the shunt driver circuit 43, the series driver circuit 39 being operably coupled to the series EVC 31 and the shunt driver circuit 43 being operably coupled to the shunt EVC 43. When the EVCs 31, 33 are switched to a matched configuration, the input impedance may be matched to a fixed RF source impedance (e.g., 50 ohms), thus resulting in impedance matching. If sufficient impedance matching does not occur due to fluctuations in plasma impedance, the process of 500 may be repeated one or more times to achieve impedance matching, or at least substantial impedance matching.

[0095] The lookup tables used in the process described above are compiled before the RF matched network is used in conjunction with the plasma chamber 19. In creating the lookup tables, the RF matched network 11 is tested before use in the plasma chamber to determine at least one parameter matrix of each type, as well as the load impedance associated with each array configuration of the series EVC 31 and shunt EVC 33. The parameter matrices resulting from the testing are compiled into a parameter lookup table so that at least one parameter matrix of each type is associated with the respective array configurations of the EVCs 31 and 33. Similarly, the load impedances are compiled into an array configuration lookup table so that each parameter matrix is ​​associated with the respective array configurations of the EVCs 31 and 33. The compiled lookup tables may also take into account other factors related to the operation of the RF matched network, such as a fixed RF source impedance (e.g., 50 ohms), the power output of the RF source, and the operating frequency of the RF source. Thus, each lookup table may have hundreds of thousands or more entries to consider all possible configurations of the EVCs 31 and 33. The number of possible configurations is primarily determined by the number of individual fixed capacitors that make up each of the EVCs 31 and 33. When compiling the lookup table, possible safety limits, such as the maximum allowable voltage and current at critical locations in the matched network, may be considered, which may serve to exclude one or more entries in the lookup table for a particular configuration of the EVCs 31 and 33.

[0096] As is well known in the art, an S-parameter matrix is ​​composed of components called scattering parameters, or S-parameters for short. The S-parameter matrix of an impedance matching circuit consists of four S-parameters, namely, S 11 S 12 S 21 , and S 22It has, each of which represents the ratio of the voltages at RF input 13 and RF output 17. All four S-parameters of the impedance matching circuit are determined and / or calculated in advance so that the entire S-parameter matrix is ​​known. The parameters of other types of parameter matrices may also be determined and / or calculated in advance and incorporated into the parameter matrix. For example, the Z-parameter matrix of an impedance matching circuit has four Z-parameters, namely, Z 11 , Z 12 , Z 21 , and Z 22 It holds.

[0097] By compiling parameter lookup tables in this manner, the total time cost of any particular calculation occurs during the testing phase of the RF matching network and not during actual use of the RF matching network 11 with the plasma chamber 19. Furthermore, since retrieving values ​​from the lookup tables takes less time than calculating those same values ​​in real time, using lookup tables can help reduce the overall time required to achieve impedance matching. In plasma deposition or etching processes that potentially involve hundreds or thousands of impedance matching adjustments throughout the entire process, this time saving can directly translate into overall cost savings in the manufacturing process.

[0098] From the start of the matching tuning process, which begins with the control circuit determining the variable impedance of the plasma chamber and the matching configuration of the series and shunts, to the end of the matching tuning process, which is when the RF power reflected toward the RF source decreases, the entire matching tuning process of an RF impedance matching network using an EVC has an elapsed time of approximately 110 μs, or approximately 150 μs or less. This short elapsed time for a single iteration of the matching tuning process represents a significant increase compared to a VVC matching network. Furthermore, due to this short elapsed time for a single iteration of the matching tuning process, an RF impedance matching network using an EVC may perform the matching tuning process iteratively, generating two decision steps and another control signal for further changes to the array configuration of one or both of the electronic variable capacitors. By iteratively repeating the matching tuning process, it is expected that better impedance matching can be achieved within approximately 2 to 4 iterations of the matching tuning process. Furthermore, depending on the time required for each iteration of the matching tuning process, it is expected that 3 to 4 iterations can be performed in 500 μs or less. Considering the 1-2 second matching time for a single iteration of the matching and tuning process for RF impedance matching networks using VVCs, the ability to perform multiple iterations in a short time represents a significant advantage of RF impedance matching networks using EVCs.

[0099] Those skilled in the art will recognize that several factors can contribute to the sub-millisecond elapsed time of the impedance matching process in an RF impedance matching network using an EVC. These factors may include the power of the RF signal, the configuration and design of the EVC, the type of matching network used, and the type and configuration of the driver circuit used. Other factors not listed may also contribute to the overall elapsed time of the impedance matching process. Thus, the total time required for the matching and tuning process for an RF impedance matching network with an EVC is expected to be approximately 500 microseconds or less, from the start of the process (i.e., when the control circuit measures and calculates the adjustments necessary to produce impedance matching) to the end of the process (when the efficiency of the RF power coupled to the plasma chamber increases due to impedance matching and reduction of reflected power). Even a matching and tuning process of around 500 microseconds still represents a significant improvement over RF impedance matching networks using a VVC.

[0100] Table 1 shows data comparing the operating parameters of an example EVC with those of an example VVC. As can be seen, in addition to enabling high-speed switching for RF impedance-matched networks, the EVC offers several advantages. [Table 1]

[0101] As can be seen, in addition to the high-speed switching capability enabled by EVC, EVC also offers advantages in terms of reliability, current operation, and size. Further advantages of RF impedance matching networks that use the switching circuit itself for EVC and / or EVC include: The disclosed RF impedance matching network contains no moving parts, thus reducing the possibility of mechanical failure to that of other complete electrical circuits that may be used as part of the semiconductor manufacturing process. For example, a typical EVC may be formed from a highly durable ceramic substrate with copper metallization to form individual capacitors. The removal of moving parts also increases resistance to failure due to thermal fluctuations during use. EVCs are more compact in size compared to VVCs, and as a result, the reduction in weight and volume can save valuable space within the manufacturing facility. • EVC design offers an increased ability to customize RF matching networks to specific design needs for particular applications. EVCs may consist of custom capacitance ranges, one example being nonlinear capacitance ranges. Such custom capacitance ranges can provide better impedance matching for a wider range of processes. As another example, custom capacitance ranges can provide greater resolution in specific areas of impedance matching. Custom capacitance ranges can also enable the generation of higher ignition voltages to facilitate plasma collisions. • A short matching and tuning process (approximately 500 μs or less) allows the RF impedance matching network to withstand plasma changes within the manufacturing process, thereby increasing plasma stability and providing more controlled power to the manufacturing process. In RF impedance matching networks, using digitally controlled EVCs instead of mechanical devices offers a greater opportunity to fine-tune control algorithms through programming. • EVC exhibits superior low-frequency (kHz) performance compared to VCC.

[0102] While the embodiments of the matched networks discussed herein used L or pi configurations, it should be noted that the matched networks covered by the claims may consist of other matched network configurations, such as a "T" configuration. Unless otherwise stated, the variable capacitors, switching circuits, and methods discussed herein may be used in any configuration suitable for RF impedance matched networks.

[0103] The embodiments discussed herein use one or more variable capacitors in a matching network to achieve impedance matching, but it should be noted that any variable reactance element can be used. The variable reactance element may include one or more individual reactance elements, which are capacitors, inductors, or similar reactive devices.

[0104] While the present invention has been described in relation to specific embodiments, including current preferred methods of implementation, those skilled in the art will understand that there are numerous variations and modifications of the systems and techniques described above. Naturally, other embodiments may be utilized and structural and functional modifications may be made without departing from the scope of the invention. Accordingly, the spirit and scope of the invention should be interpreted broadly as set out in the appended claims. [Explanation of Symbols]

[0105] 11. Integrity Network 15 RF source 19 Plasma Chamber 27 Base material 85 Systems 86 Processing Tools

Claims

1. A radio frequency (RF) impedance matching circuit, An RF input configured to be operably coupled to an RF source that provides an RF signal, An RF output configured to be operably coupled to the plasma chamber, A series electronically variable capacitor (EVC) electrically coupled in series between the RF input and the RF output, The series EVC has a series variable capacitance, The series EVC comprises a first fixed capacitor, each of the first fixed capacitors having a corresponding switch for switching the fixed capacitor on or off to change the series variable capacitance, and each switch comprises one or more diodes. A first inductor having a first terminal electrically coupled to common ground and a second terminal electrically coupled between the RF input and the RF output, A control circuit operably coupled to the series EVC, wherein the control circuit is While the RF source is supplying the RF signal to the RF input, a first parameter related to the plasma chamber is determined, and The control circuit is configured to change the series variable capacitance based on a first parameter determined while the RF signal continues to be supplied to the RF input, wherein the change in the series variable capacitance reduces the RF power reflected to the RF source. A matching circuit in which the first inductor provides a DC bias path for forward biasing and reverse biasing the switch of the series EVC.

2. The matching circuit according to claim 1, further comprising a blocking capacitor electrically coupled in series between the RF input and the RF output.

3. The matching circuit according to claim 2, wherein at least one of the blocking capacitor or the first inductor comprises a plurality of reactance elements coupled in series or in parallel.

4. The matching circuit according to claim 1, wherein the corresponding switch for each of the first fixed capacitors includes one or more PIN diodes or NIP diodes.

5. The matching circuit according to claim 1, wherein the capacitor is in parallel with the first inductor to form an LC circuit.

6. The matching circuit according to claim 1, further comprising a variable reactance element different from the series EVC.

7. The matching circuit according to claim 6, wherein the variable reactance element comprises one or more reactance elements that are capacitors or inductors.

8. The matching circuit according to claim 7, wherein the variable reactance element is electrically coupled between a common ground and one of the RF input and the RF output.

9. The variable reactance element is a shunt EVC, The aforementioned shunt EVC has a shunt variable capacitance, The shunt EVC comprises a second fixed capacitor, each of which has a corresponding switch for switching the fixed capacitor on or off to change the shunt variable capacitance. The matching circuit according to claim 8, wherein the control circuit is operably coupled to the shunt EVC and changes the shunt variable capacitance in conjunction with the change in the series EVC, and the changes in the series variable capacitance and the shunt variable capacitance reduce the RF power reflected to the RF source.

10. The matching circuit according to any one of claims 1 to 9, further comprising a series inductor electrically coupled in series between the RF input and the RF output.

11. A method for matching impedances, wherein the method is The impedance matching circuit is coupled between the RF source and the plasma chamber, wherein the impedance matching circuit is An RF input configured to be operably coupled to an RF source, wherein the RF source provides an RF signal to the RF input, An RF output configured to be operably coupled to the plasma chamber, A series electronically variable capacitor (EVC) electrically coupled in series between the RF input and the RF output, The series EVC has a series variable capacitance, The series EVC comprises a first fixed capacitor, each of the first fixed capacitors having a corresponding switch for switching the fixed capacitor on or off to change the series variable capacitance, and each switch comprises one or more diodes. A first inductor having a first terminal electrically coupled to common ground and a second terminal electrically coupled between the RF input and the RF output, comprising coupling, While the RF source is supplying an RF signal to the RF input, the first parameter related to the plasma chamber is determined, While the RF signal continues to be supplied to the RF input, the series variable capacitance is changed based on the first parameter determined, wherein the change in the series variable capacitance reduces or alters the RF power reflected to the RF source. A method wherein the first inductor provides a DC bias path for forward-biasing and reverse-biasing the switch of the series EVC.

12. The method according to claim 11, wherein the matching circuit further comprises a blocking capacitor electrically coupled in series between the RF input and the RF output.

13. The method according to claim 12, wherein at least one of the blocking capacitor or the first inductor comprises a plurality of reactance elements coupled in series or in parallel.

14. The method according to any one of claims 11 to 13, wherein the corresponding switch for each of the first fixed capacitors includes one or more PIN diodes or NIP diodes.

15. It is a semiconductor processing tool, A plasma chamber configured to deposit a material onto a substrate or to etch a material from the substrate, An impedance matching circuit operably coupled to a plasma chamber, wherein the matching circuit is An RF input configured to be operably coupled to an RF source that provides an RF signal, An RF output configured to be operably coupled to the plasma chamber, A series electronically variable capacitor (EVC) electrically coupled in series between the RF input and the RF output, The series EVC has a series variable capacitance, The series EVC comprises a first fixed capacitor, each of the first fixed capacitors having a corresponding switch for switching the fixed capacitor on or off to change the series variable capacitance, and each switch comprises one or more diodes. A first inductor having a first terminal electrically coupled to common ground and a second terminal electrically coupled between the RF input and the RF output, A control circuit operably coupled to the series EVC, wherein the control circuit is While the RF source is supplying the RF signal to the RF input, a first parameter related to the plasma chamber is determined, and The control circuit is configured to change the series variable capacitance based on a first parameter determined while the RF signal continues to be supplied to the RF input, wherein the change in the series variable capacitance reduces the RF power reflected to the RF source. A semiconductor processing tool wherein the first inductor provides a DC bias path for forward and reverse biasing the switch of the series EVC.

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