Three-dimensional memory device and method for forming it

Abstract

To provide three-dimensional (3D) memory devices and methods for producing the same.SOLUTION: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes: a stack structure including interleaved conductive layers and dielectric layers; a channel structure extending through the stack structure; and a doped semiconductor layer. The doped semiconductor layer includes a plate and a plug extending from the plate into the channel structure. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion, and a part of the doped portion of the semiconductor channel extends beyond the stack structure in a first direction. The doped portion of the semiconductor channel circumscribes the plug of the doped semiconductor layer.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] This disclosure relates to a three-dimensional (3D) memory device and a method for manufacturing the same. [Background technology]

[0002] Planar memory cells can be scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches its lower limit, planar processes and manufacturing techniques become difficult and costly. As a result, the memory density for planar memory cells approaches its upper limit.

[0003] 3D memory architectures can address the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. [Overview of the project] [Means for solving the problem]

[0004] In one embodiment, a 3D memory device includes a stack structure comprising alternating conductive and dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer, the doped semiconductor layer comprising a plate and a plug extending from the plate into the channel structure. The channel structure comprises a memory film and a semiconductor channel. The semiconductor channel includes a doped portion, a portion of which extends beyond the stack structure in a first direction. The doped portion of the semiconductor channel surrounds the plug of the doped semiconductor layer.

[0005] In another embodiment, a 3D memory device includes a stack structure comprising alternating conductive and dielectric layers, a doped semiconductor layer, and a channel structure extending through the stack structure. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion. The channel structure extends beyond the stack structure in a first direction and is in contact with the doped semiconductor layer. The semiconductor channel includes a doped portion extending beyond one of the conductive layers in a second direction opposite to the first direction.

[0006] In yet another embodiment, a method for forming a 3D memory device is provided. A packing layer is formed on top of a substrate. A stack structure is formed on top of the packing layer. A channel structure is formed extending through the stack structure and the packing layer. The channel structure includes a memory film and a semiconductor channel. A portion of the channel structure extending beyond the substrate and the packing layer is successively removed to expose a portion of the semiconductor channel. A doped semiconductor layer is formed in contact with the exposed portion of the semiconductor channel. The doped semiconductor layer and the portion of the semiconductor channel in contact with the doped semiconductor layer are locally activated.

[0007] In yet another embodiment, the system includes a 3D memory device configured to store data and a memory controller, the memory controller being coupled to the 3D memory device and configured to control the 3D memory device. The 3D memory device includes a stack structure comprising alternating conductive and dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer, the doped semiconductor layer comprising a plate and a plug extending from the plate into the channel structure. The channel structure comprises a memory film and a semiconductor channel. The semiconductor channel includes a doped portion, a portion of which extends beyond the stack structure in a first direction. The doped portion of the semiconductor channel surrounds the plug of the doped semiconductor layer.

[0008] The accompanying drawings are incorporated herein and form part of the specification, illustrating aspects of the disclosure, further serving to illustrate the principles of the disclosure together with the description, and enabling those skilled in the art to construct and use the disclosure. [Brief explanation of the drawing]

[0009] [Figure 1A] This is a cross-sectional side view of an exemplary 3D memory device according to some aspects of the present disclosure. [Figure 1B] This is a cross-sectional side view of another exemplary 3D memory device according to some aspects of the present disclosure. [Figure 2] Figure 1A is an enlarged side view of a cross-section of an exemplary channel structure in a 3D memory device according to some aspects of the present disclosure. [Figure 3A] This figure illustrates a manufacturing process for forming an exemplary 3D memory device according to several aspects of the present disclosure. [Figure 3B] This figure illustrates a manufacturing process for forming an exemplary 3D memory device according to several aspects of the present disclosure. [Figure 3C]This figure illustrates a manufacturing process for forming an exemplary 3D memory device according to several aspects of the present disclosure. [Figure 3D] This figure illustrates a manufacturing process for forming an exemplary 3D memory device according to several aspects of the present disclosure. [Figure 3E] This figure illustrates a manufacturing process for forming an exemplary 3D memory device according to several aspects of the present disclosure. [Figure 3F] This figure illustrates a manufacturing process for forming an exemplary 3D memory device according to several aspects of the present disclosure. [Figure 3G] This figure illustrates a manufacturing process for forming an exemplary 3D memory device according to several aspects of the present disclosure. [Figure 3H] This figure illustrates a manufacturing process for forming an exemplary 3D memory device according to several aspects of the present disclosure. [Figure 3I] This figure illustrates a manufacturing process for forming an exemplary 3D memory device according to several aspects of the present disclosure. [Figure 3J] This figure illustrates a manufacturing process for forming an exemplary 3D memory device according to several aspects of the present disclosure. [Figure 3K] This figure illustrates a manufacturing process for forming an exemplary 3D memory device according to several aspects of the present disclosure. [Figure 3L] This figure illustrates a manufacturing process for forming an exemplary 3D memory device according to several aspects of the present disclosure. [Figure 3M] This figure illustrates a manufacturing process for forming an exemplary 3D memory device according to several aspects of the present disclosure. [Figure 3N] This figure illustrates a manufacturing process for forming an exemplary 3D memory device according to several aspects of the present disclosure. [Figure 3O] This figure illustrates a manufacturing process for forming an exemplary 3D memory device according to several aspects of the present disclosure. [Figure 4A] This figure illustrates a manufacturing process for forming another exemplary 3D memory device according to several aspects of the present disclosure. [Figure 4B] This figure illustrates a manufacturing process for forming another exemplary 3D memory device according to several aspects of the present disclosure. [Figure 4C] This figure illustrates a manufacturing process for forming another exemplary 3D memory device according to several aspects of the present disclosure. [Figure 5] This is a flowchart illustrating an exemplary method for forming a 3D memory device according to some aspects of the present disclosure. [Figure 6] This is a flowchart of another exemplary method for forming a 3D memory device according to some aspects of the present disclosure. [Figure 7] This is a block diagram of an exemplary system having a 3D memory device according to some aspects of the present disclosure. [Figure 8A] Diagrams of exemplary memory cards having a 3D memory device according to some aspects of the present disclosure. [Figure 8B] Diagrams of exemplary solid-state drives (SSDs) having 3D memory devices according to some aspects of the present disclosure. [Modes for carrying out the invention]

[0010] This disclosure will be described with reference to the attached drawings.

[0011] While specific configurations and arrangements are discussed, it should be understood that this is done solely for illustrative purposes. Therefore, other configurations and arrangements can be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described herein can be combined, adjusted, and modified with respect to each other and in ways not specifically shown in the drawings, and such combinations, adjustments, and modifications are intended to fall within the scope of this disclosure.

[0012] In general, technical terms can be understood, at least partially, from their usage in context. For example, the term “one or more” as used herein can, at least partially depending on the context, be used in a singular sense to describe any feature, structure, or characteristic, or in a plural sense to describe a combination of features, structures, or characteristics. Similarly, terms such as “a,” “an,” or “the” can, again, be understood, at least partially depending on the context, to convey either a singular or plural usage. In addition, the term “based on” can be understood not necessarily intended to convey an exclusive set of factors, but rather, again, at least partially depending on the context, may allow for the presence of additional factors that are not necessarily explicitly stated.

[0013] The meanings of “on top of,” “above,” and “over” in this disclosure should be interpreted in the broadest sense, and it should be readily understood that “on top of” can mean not only “directly on top of” something, but also “on top of” something with intermediate features or layers between them, and “above” or “over” can mean not only “above” or “over” something, but also “above” or “over” something (i.e., directly on top of something) with no intermediate features or layers between them.

[0014] Furthermore, spatially relative terms such as "below," "downward," "underside," "above," and "upperside" may be used herein to describe the relationship of one element or feature to another element or feature, as illustrated in the figures, for the sake of clarity. Spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated by 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted in such ways as well.

[0015] As used herein, the term “substrate” refers to a material on which subsequent material layers are added. The substrate itself can be patterned. The material added to the substrate can be patterned or left unpatterned. Furthermore, the substrate can contain a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, and indium phosphide. Alternatively, the substrate can be made from non-conductive materials, such as glass, plastic, or sapphire wafers.

[0016] As used herein, the term “layer” refers to a portion of a material comprising a region having a given thickness. A layer can extend over the entire structure beneath or above it, or it can have an extension less than the extension of the structure beneath or above it. Furthermore, a layer can be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between the top and bottom surfaces of a continuous structure (or on the top and bottom surfaces). A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, and can contain one or more layers, and / or have one or more layers above, above, and / or below it. A layer can contain multiple layers. For example, an interconnection layer can contain one or more conductor and contact layers (with interconnection lines and / or vertical interconnection access (via) contacts formed therein) and one or more dielectric layers.

[0017] In some 3D NAND memory devices, the semiconductor layer is selectively grown to surround the sidewalls of the channel structure (for example, known as sidewall selective epitaxial growth (SEG)). Compared to another type of semiconductor layer, which is epitaxial growth at the source edge of the channel structure (for example, bottom SEG), forming sidewall SEG avoids etching of the memory film and semiconductor channel at the bottom surface of the channel hole (known as SONO punch), thereby increasing the process window when fabricating 3D NAND memory devices using advanced technologies (for example, having 90 or more levels by multi-deck architecture).

[0018] However, because intrinsic (pure, undoped) semiconductor materials (e.g., intrinsic polysilicon) are used to form the semiconductor channels, a relatively high potential barrier exists between the semiconductor channels and the sidewall SEGs or the conductive layer in contact with the semiconductor channels, thereby introducing high contact resistance between them. The electrical performance of 3D memory devices can be affected by this high contact resistance.

[0019] To address the aforementioned problems, this disclosure introduces solutions that can reduce the contact resistance between the semiconductor channel and the sidewall SEG or conductive layer. In some implementations, the semiconductor channel is partially doped, with a portion of the semiconductor channel forming the source contact area remaining undoped or a portion of the semiconductor channel forming a memory cell that is highly doped to reduce the potential barrier. In some implementations, one end of each channel structure is open from the back side, exposing a doped portion of each semiconductor channel, and the 3D memory device further includes a doped semiconductor layer that electrically connects the exposed doped portion of the semiconductor channel to further reduce contact resistance and sheet resistance. For example, the doped semiconductor layer may include a plug that extends the channel structure by replacing a portion of the capping layer of the channel structure, thereby increasing the contact area and further reducing contact resistance. As a result, the electrical performance of the 3D memory device may be improved.

[0020] In line with the scope of this disclosure, a doped portion of a semiconductor channel and a doped semiconductor layer can be locally activated (for example, through local annealing) to activate the dopants within them without damaging other parts on the thermally sensitive device chip (e.g., bonding interfaces and copper interconnects). For example, the heat required to activate the dopants can be confined to an area that excludes thermally sensitive components on the device chip. In some implementations, the local activation process also serves as an in-situ doping process for doping a portion of the intrinsic semiconductor channel in contact with the doped semiconductor layer.

[0021] Figure 1A illustrates a cross-sectional side view of an exemplary 3D memory device 100 according to several embodiments of the present disclosure. In some implementations, the 3D memory device 100 is a bonded chip comprising a first semiconductor structure 102 and a second semiconductor structure 104 stacked on top of the first semiconductor structure 102. According to some implementations, the first and second semiconductor structures 102 and 104 are bonded at a bonding interface 106 between them. As shown in Figure 1A, the first semiconductor structure 102 may include a substrate 101, which may include silicon (e.g., single-crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0022] The first semiconductor structure 102 of the 3D memory device 100 may include peripheral circuits 108 on the substrate 101. It should be noted that the x and y axes are included in Figure 1A to further illustrate the spatial relationships of the components within the 3D memory device 100 having the substrate 101. The substrate 101 includes two transverse surfaces (e.g., a top surface and a bottom surface) that extend transversely in the x-direction (i.e., the transverse direction). Whether one component (e.g., a layer or device) is "on top of," "above," or "below" another component (e.g., a layer or device) of the semiconductor device is determined in the y-direction (i.e., perpendicular to) the substrate of the semiconductor device (e.g., the substrate 101) when the substrate is positioned in the lowest plane of the semiconductor device (e.g., the 3D memory device 100) in the y-direction. The same concepts for describing spatial relationships apply throughout this disclosure.

[0023] In some implementations, the peripheral circuitry 108 is configured to control and sense the 3D memory device 100. The peripheral circuitry 108 can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to facilitate the operation of the 3D memory device 100, including, but not limited to, a page buffer, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry 108 may include transistors formed on the substrate 101, with all or part of the transistors formed within the substrate 101 (e.g., below the upper surface of the substrate 101) and / or directly on the substrate 101. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of the transistors) can also be formed within the substrate 101. In some implementations, transistors are accelerated by advanced logic processes (e.g., technology nodes such as 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, and 2nm). In some implementations, it is understood that peripheral circuits 108 may further include any other circuits that conform to advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs)) or memory circuits (e.g., static random access memory (SRAM) and dynamic RAM (DRAM)).

[0024] In some implementations, the first semiconductor structure 102 of the 3D memory device 100 further includes an interconnection layer (not shown) above the peripheral circuit 108 for transferring electrical signals to and from the peripheral circuit 108. The interconnection layer may include a plurality of interconnections (also referred to herein as contacts), including lateral interconnection lines and vertical interconnection access (VIA) contacts. As used herein, the term interconnection can broadly include any suitable type of interconnection, such as middle-end-of-line (MEOL) interconnections and back-end-of-line (BEOL) interconnections. The interconnection layer may further include one or more interlayer dielectric (ILD) layers (also known as intermetallic dielectric (IMD) layers), and the interconnection lines and VIA contacts may be formed within one or more interlayer dielectric (ILD) layers. In other words, the interconnection layer may include interconnection lines and via contacts within a plurality of ILD layers. The interconnection lines and via contacts within the interconnection layer may include, but are not limited to, conductive materials including tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The ILD layers within the interconnection layer may include, but are not limited to, dielectric materials including silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectrics, or any combination thereof.

[0025] As shown in Figure 1A, the first semiconductor structure 102 of the 3D memory device 100 may further include a bonding layer 110 at the bonding interface 106 and above the interconnection layer and peripheral circuitry 108. The bonding layer 110 may include a plurality of bonding contacts 111 and a dielectric that electrically isolates the bonding contacts 111. The bonding contacts 111 may include, but are not limited to, conductive materials including W, Co, Cu, Al, silicide, or any combination thereof. The remaining area of ​​the bonding layer 110 may be formed of a dielectric, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The bonding contacts 111 and the surrounding dielectric within the bonding layer 110 may be used for hybrid bonding.

[0026] Similarly, as shown in Figure 1A, the second semiconductor structure 104 of the 3D memory device 100 may also include a bonding layer 112 at the bonding interface 106 and above the bonding layer 110 of the first semiconductor structure 102. The bonding layer 112 may include a plurality of bonding contacts 113 and a dielectric that electrically isolates the bonding contacts 113. The bonding contacts 113 may include, but are not limited to, conductive materials including W, Co, Cu, Al, silicide, or any combination thereof. The remaining area of ​​the bonding layer 112 may be formed by a dielectric, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The bonding contacts 113 and the surrounding dielectric in the bonding layer 112 may be used for hybrid bonding. In some implementation configurations, the bonding contact portion 113 is in contact with the bonding contact portion 111 at the bonding interface 106.

[0027] As described in detail below, the second semiconductor structure 104 can be bonded on the first semiconductor structure 102 in a manner facing each other at a bonding interface 106. In some implementations, the bonding interface 106 is located between bonding layers 110 and 112 as a result of hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer (e.g., solder or adhesive)) and makes it possible to obtain metal-metal bonding and dielectric-dielectric bonding simultaneously. In some implementations, the bonding interface 106 is where bonding layers 112 and 110 meet and bond. In practice, the bonding interface 106 can be a layer of a specific thickness, including the upper surface of bonding layer 110 of the first semiconductor structure 102 and the bottom surface of bonding layer 112 of the second semiconductor structure 104.

[0028] In some implementations, the second semiconductor structure 104 of the 3D memory device 100 further includes an interconnection layer (not shown) above the bonding layer 112 for transferring electrical signals. The interconnection layer may include a plurality of interconnections (e.g., MEOL interconnections and BEOL interconnections). The interconnection layer may further include one or more ILD layers, and interconnection lines and via contacts may be formed within one or more ILD layers. The interconnection lines and via contacts within the interconnection layer may include, but are not limited to, conductive materials including W, Co, Cu, Al, silicide, or any combination thereof. The ILD layers within the interconnection layer may include, but are not limited to, dielectric materials including silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0029] In some implementations, the 3D memory device 100 is a NAND flash memory device, and memory cells are provided within the NAND flash memory device in the form of an array of NAND memory strings. Each NAND memory string may contain a channel structure 124. As shown in Figure 1A, each channel structure 124 may extend vertically through multiple pairs, each containing a stacked conductive layer 116 and a stacked dielectric layer 118. The alternatingly arranged stacked conductive layers 116 and stacked dielectric layers 118 constitute a memory stack 114. The number of pairs of stacked conductive layers 116 and stacked dielectric layers 118 in the memory stack 114 determines the number of memory cells in the 3D memory device 100. In some implementations, the memory stack 114 may have a multi-deck architecture (not shown), which is understood to include multiple memory decks stacked on top of each other. The number of pairs of stacked conductive layers 116 and stacked dielectric layers 118 in each memory deck may be the same or different.

[0030] The memory stack 114 may include a plurality of alternately arranged stack conductive layers 116 and stack dielectric layers 118. The stack conductive layers 116 and stack dielectric layers 118 in the memory stack 114 may be alternated vertically. In other words, except for those at the top or bottom of the memory stack 114, each stack conductive layer 116 may be adjacent to two stack dielectric layers 118 on both sides, and each stack dielectric layer 118 may be adjacent to two stack conductive layers 116 on both sides. The stack conductive layers 116 may include, but are not limited to, conductive materials including W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each stack conductive layer 116 may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the stack conductive layer 116 may extend laterally as a word line and terminate in one or more stepped structures of the memory stack 114. The stacked dielectric layer 118 may include, but is not limited to, a dielectric material including silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0031] As shown in Figure 1A, the second semiconductor structure 104 of the 3D memory device 100 may also include a packing layer 120 above the memory stack 114. The packing layer 120 may include polysilicon, a high dielectric constant (high k) dielectric, or a metal. For example, the high k dielectric may include any dielectric material having a dielectric constant higher than that of silicon oxide (e.g., k > 3.7). Unlike some known solutions in which the packing layer 120 acts as a sidewall SEG surrounding the channel structure 124 and / or a conductive layer (e.g., a doped polysilicon layer) electrically connecting the channel structure 124, the packing layer 120 of the second semiconductor structure 104 of the 3D memory device 100 may not act as a sidewall SEG and / or a conductive layer, and therefore may include materials other than doped polysilicon, such as dielectrics (e.g., high k dielectrics), metals (e.g., W, Co, Cu, or Al), metal silicides, or undoped polysilicon. In some examples, it is understood that the packed layer 120 can similarly contain doped polysilicon.

[0032] In some implementations, each channel structure 124 includes a channel hole filled with a semiconductor layer (e.g., as a semiconductor channel 128) and a composite dielectric layer (e.g., as a memory film 126). In some implementations, the semiconductor channel 128 includes silicon (e.g., amorphous silicon, polysilicon, or single-crystal silicon). In some implementations, the memory film 126 is a composite layer including a tunneling layer, a storage layer (also known as a "charge trap layer"), and a blocking layer. As shown in Figure 1A, the remaining space of the channel hole can be partially filled with a capping layer 127 including a dielectric material (e.g., silicon oxide) and / or an air gap (not shown). The channel structure 124 can have a cylindrical shape (e.g., a pillar shape). According to some implementations, the capping layer, semiconductor channel 128, the tunneling layer of the memory film 126, the storage layer, and the blocking layer are arranged in this order radially from the center toward the outer surface of the pillar. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer may include silicon oxide, silicon oxynitride, high-k dielectric, or any combination thereof. In one example, the memory film 126 may include a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer.

[0033] In some implementations, the channel structure 124 further includes a channel plug 129 at the bottom portion of the channel structure 124 (for example, at the lower end). As used herein, when the substrate 101 is positioned on the lowest plane of the 3D memory device 100, the upper end of the component (e.g., the channel structure 124) is the end that is further away from the substrate 101 in the y-direction, and the lower end of the component (e.g., the channel structure 124) is the end that is closer to the substrate 101 in the y-direction. The channel plug 129 may include a semiconductor material (e.g., polysilicon). In some implementations, the channel plug 129 functions as a drain of the channel structure 124.

[0034] As shown in Figure 1A, each channel structure 124 can extend vertically into the packing layer 120 through the alternating stack conductive layers 116 and stack dielectric layers 118 of the memory stack 114. That is, the channel structure 124 can extend beyond the memory stack 114 in the positive y direction. In some implementations, the upper edge of the memory film 126 is coplanar with the upper edge of the semiconductor channel 128, i.e., they are vertically aligned with each other. In some implementations, the upper edges of the memory film 126 and the semiconductor channel 128 are coplanar with the upper surface of the packing layer 120.

[0035] Referring to the enlarged side view of the channel structure 124 in Figure 2, the semiconductor channel 128 may include a doped portion 128a and an undoped portion 128b. In some implementations, at least a portion of the doped portion 128a of the semiconductor channel 128 extends beyond the memory stack 114 in a first direction (for example, the positive y direction in Figure 2). That is, the upper end of the doped portion 128a may be above the interface between the packing layer 120 and the memory stack 114 (i.e., between the bottom surface of the packing layer 120 and the top surface of the memory stack 114). Similarly, the upper end of the memory film 126 may also be above the interface between the packing layer 120 and the memory stack 114. In some implementations, the doped portion 128a of the semiconductor channel 128 also extends beyond one of the stack conductive layers 116 in a second direction opposite to the first direction (for example, the negative y direction in Figure 2). It is understood that one or more of the stacked conductive layers 116 near the packed layer 120 can be source-selection gate lines 201 (SSG lines; sometimes referred to as bottom-selection gate (BSG) lines), and the rest of the stacked conductive layers 116 can include word lines 203. Also, according to some implementations, the doped portion 128a of the semiconductor channel 128 extends beyond the source-selection gate line 201 closest to the packed layer 120. If the second semiconductor structure 104 of the 3D memory device 100 includes two or more source-selection gate lines 201, it is understood that the doped portion 128a can extend beyond all of the source-selection gate lines 201. On the other hand, the doped portion 128a may not extend further to face the word lines 203. That is, according to some implementations, the lower end of the doped portion 128a is between the source-selection gate line 201 and the word line 203 in the vertical direction.For example, as shown in FIG. 2, a portion of the doped portion 128a of the semiconductor channel 128 extending beyond the memory stack 114 can face the filling layer 120, while the remaining portion of the doped portion 128a can face the source select gate line 201.

[0036] In some implementations, the doped portion 128a of the semiconductor channel 128 includes N-type doped polysilicon. The dopant can be any suitable N-type dopant, for example phosphorus (P), arsenic (As), or antimony (Sb), which contributes free electrons and increases the conductivity of an intrinsic semiconductor. In some implementations, the doping concentration of the doped portion 128a is about 10 19 cm -3 to about 10 21 cm -3 for example between 10 19 cm -3 to 10 21 cm -3 for example between 10 19 cm -3 , 2×10 19 cm -3 , 3×10 19 cm -3 , 4×10 19 cm -3 , 5×10 19 cm -3 , 6×10 19 cm -3 , 7×10 19 cm -3 , 8×10 19 cm -3 , 9×10 19 cm -3 , 10 20 cm -3 , 2×10 20 cm -3 , 3×10 20 cm -3 , 4×10 20 cm -3 , 5×10 20 cm -3 , 6×10 20 cm -3, 7×10 20 cm -3 , 8×10 20 cm -3 , 9×10 20 cm -3 , 10 21 cm -3 , any range defined by the lower end of any of these values, or any range defined by any two of these values. The doping concentrations of the doped portion 128a disclosed herein can significantly reduce the contact resistance between the semiconductor channel 128 and the doped semiconductor layer 122 compared to the intrinsic semiconductor. In some examples, it is understood that dopant diffusion can be confined within the doped portion 128a of the semiconductor channel 128, and the rest of the semiconductor channel 128 (i.e., the portion facing the word line 203) is an undoped portion 128b that still contains the intrinsic semiconductor (e.g., intrinsic polysilicon, etc.) (i.e., the doping concentration is nominally zero). The doping concentration profiles described above can reduce the potential barrier, contact resistance, and sheet resistance in the doped portion 128a of the semiconductor channel 128, thereby creating an electrical connection for the corresponding NAND memory string source without altering the intrinsic properties of the undoped portion 128b of the semiconductor channel 128 that forms the memory cells of the NAND memory string.

[0037] In some implementations, the second semiconductor structure 104 of the 3D memory device 100 includes a doped semiconductor layer 122. Each channel structure 124 can extend beyond the memory stack 114 in a first direction and can be in contact with the doped semiconductor layer 122. In some embodiments, at least a portion of the doped portion 128a of each semiconductor channel 128 can extend beyond the memory stack 114 in a first direction and is in contact with the doped semiconductor layer 122, so that the doped semiconductor layer 122 can electrically connect multiple channel structures 124 through their doped portions 128a of the semiconductor channels 128. For example, the doped semiconductor layer 122 can provide electrical connectivity between the sources of an array of NAND memory strings in the same block (i.e., array common source (ACS)) with or without the packing layer 120 (depending on whether the packing layer 120 is conductive). In other words, the packed layer 120 may not need to contain a conductive material (for example, a metal or doped polysilicon). This is because the doped semiconductor layer 122 can electrically connect the sources of multiple NAND memory strings on its own. As a result, the material and dimensional constraints on the packed layer 120 may be relaxed.

[0038] As shown in Figure 1A, in some implementations, the doped semiconductor layer 122 includes two parts: a plate 121 in contact with the packing layer 120, and plugs 123 extending from the plate 121 into the channel structure 124. Also, referring to Figure 2, the doped portion 128a of the semiconductor channel 128 surrounds the plugs 123 of the doped semiconductor layer 122, according to some embodiments. As described in detail below regarding the fabrication of the 3D memory device 100, the channel structure 124 can fill a portion of the channel holes formed within it with plugs 123, which replace a portion of the capping layer 127 in the channel holes, and the doped portion 128a of the semiconductor channel 128 can surround and contact the plugs 123 laterally. Furthermore, the plugs 123 of the doped semiconductor layer 122 can contact the capping layer 127 vertically. As shown in Figure 2, in some implementations, the plug 123 protrudes into the channel structure 124, with the lower end of the plug 123 (and the upper end of the capping layer 127) located below the interface between the packing layer 120 and the memory stack 114. That is, according to some embodiments, the capping layer 127 does not extend beyond the memory stack 114 due to the extension of the plug 123.

[0039] Similar to the doped portion 128a of the semiconductor channel 128, the plug 123 of the doped semiconductor layer 122 also extends beyond one of the stacked conductive layers 116 in a second direction (e.g., the negative y direction in Figures 1A and 2). Furthermore, according to some implementations, the plug 123 extends beyond the nearest source selection gate line 201 of the packed layer 120. If the second semiconductor structure 104 of the 3D memory device 100 includes two or more source selection gate lines 201, it is understood that the plug 123 can extend beyond all source selection gate lines 201. In some embodiments, the plug 123 is aligned with the doped portion 128a of the semiconductor channel 128 in the vertical direction. That is, the upper end of the plug 123 and the upper end of the doped portion 128a of the semiconductor channel 128 can be on the same plane, and similarly, the lower end of the plug 123 and the lower end of the doped portion 128a of the semiconductor channel 128 can be on the same plane. As described in detail below regarding the fabrication of the 3D memory device 100, the plug 123 can act as a doping source for forming the doped portion 128a of the semiconductor channel 128, so that only the portion of the semiconductor channel 128 in contact with the plug 123 is doped by the plug 123, forming the doped portion 128a of the semiconductor channel 128. In some examples, it is understood that a portion of the semiconductor channel 128 can be doped before the formation of the plug 123, so that the lower end of the plug 123 and the lower end of the doped portion 128a of the semiconductor channel 128 do not have to be on the same plane.

[0040] As shown in Figure 1A, according to some embodiments, the plate 121 of the doped semiconductor layer 122 lies above and in contact with the packing layer 120 and the memory film 126 of the channel structure 124. In other words, the memory film 126 can extend beyond the memory stack 114 in a first direction (e.g., the positive y direction) and is in contact with the plate 121 of the doped semiconductor layer 122, and the packing layer 120 can be formed between the memory stack 114 and the plate 121 of the doped semiconductor layer 122. By extending laterally above a plurality of channel structures 124, the plate 121 can connect a plurality of plugs 123, each of which protrudes into its respective channel structure 124.

[0041] As described in detail below, the formation of the memory stack 114, as well as the doped portion 128a of the semiconductor channel 128 and the doped semiconductor layer 122, can occur on the opposite side of the packed layer 120, thereby avoiding any deposition or etching process through openings extending through the memory stack 114, thereby reducing the complexity and cost of fabrication and improving yield and vertical scalability.

[0042] Similar to the doped portion 128a of the semiconductor channel 128, in some implementation configurations, the doped semiconductor layer 122 (including the plate 121 and plug 123) also contains N-type doped polysilicon. The dopant can be any suitable N-type dopant (e.g., P, Ar, or Sb), which contributes to free electrons and increases the conductivity of the intrinsic semiconductor. Similar to the doped portion 128a of the semiconductor channel 128, in some implementation configurations, the doping concentration of the doped semiconductor layer 122 is approximately 10 19 cm -3 From about 10 21 cm -3 It is between, for example, 10 19 cm -3 from 1021 cm -3 (for example, 10 19 cm -3 , 2×10 19 cm -3 , 3×10 19 cm -3 , 4×10 19 cm -3 , 5×10 19 cm -3 , 6×10 19 cm -3 , 7×10 19 cm -3 , 8×10 19 cm -3 , 9×10 19 cm -3 , 10 20 cm -3 , 2×10 20 cm -3 , 3×10 20 cm -3 , 4×10 20 cm -3 , 5×10 20 cm -3 , 6×10 20 cm -3 , 7×10 20 cm -3 , 8×10 20 cm -3 , 9×10 20 cm -3 , 10 21 cm -3, any range defined by the lower end of any of these values, or any range defined by any two of these values. The doping concentrations of the doped semiconductor layer 122 disclosed herein can significantly reduce the contact resistance between the semiconductor channel 128 and the doped semiconductor channel 122, and the sheet resistance of the doped semiconductor layer 122, compared to the intrinsic semiconductor. As described in detail below, in some implementations, the doped portion 128a of the semiconductor channel 128 and the doped semiconductor layer 122 have the same material (e.g., N-type doped polysilicon) with the same dopant and have a continuous doping profile due to the same local activation process performed thereon. Therefore, it is understood that the interface and boundary between the doped portion 128a of the semiconductor channel 128 and the plug 123 of the doped semiconductor layer 122 may be indistinguishable and therefore indistinguishable within the 3D memory device 100.

[0043] By doping and contacting the semiconductor channel 128 and the doped semiconductor layer 122, the contact resistance between NAND memory strings (i.e., in the ACS of NAND memory strings within the same block) can be reduced, thereby improving the electrical performance of the 3D memory device 100. As shown in Figures 1A and 2, by extending the plug 123 into the channel structure 124, the doped portion 128a of the semiconductor channel 128 can surround the plug 123 of the doped semiconductor layer 122, thereby increasing the contact area between the semiconductor channel 128 and the doped semiconductor layer 122, which further reduces the contact resistance between them. The plug 123 of the N-type doped semiconductor layer 122 (which is surrounded by the doped portion 128a of the semiconductor channel 128) can enable gate-induced drain leakage (GIDL) assisted body biasing for erase operations for the 3D memory device 100. GIDL around the source selection gate line 201 can generate hole current (i.e., source leakage current) from the source of the corresponding NAND memory string into the semiconductor channel 128, thereby increasing the body potential for erase operations. That is, the plug 123 of the N-type doped semiconductor layer 122 is configured, according to some implementations, to generate GIDL-assisted body biasing when an erase operation is performed. In some implementations, the GIDL effect can be further enhanced by doping a portion of the semiconductor channel 128 facing the source selection gate line 201.

[0044] As shown in Figure 1A, the second semiconductor structure 104 of the 3D memory device 100 may further include insulating structures 130 that extend vertically through the alternating stack conductive layers 116 and stack dielectric layers 118 of the memory stack 114, respectively. Unlike the channel structures 124 that extend further into the packing layer 120, the insulating structures 130, according to some implementation configurations, stop at the bottom surface of the packing layer 120, i.e., do not extend vertically into the packing layer 120. That is, the upper surface of the insulating structure 130 can be coplanar with the bottom surface of the packing layer 120. In addition, each insulating structure 130 can extend laterally to separate separate channel structures 124 into multiple blocks. That is, the memory stack 114 can be divided into multiple memory blocks by the insulating structures 130, and the array of channel structures 124 can be separated into individual memory blocks. Unlike the slit structures in existing 3D NAND memory devices (which include front-side ACS contacts), the insulating structure 130, according to some implementations, does not contain any contacts therein (i.e., does not function as source contacts) and therefore does not introduce parasitic capacitance and leakage current by the stack conductive layer 116. In some implementations, each insulating structure 130 includes an opening (e.g., a slit) filled with one or more dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure 130 can be filled with silicon oxide. In some examples (as shown in Figure 1A), it is understood that the insulating structure 130 can be partially filled with a non-dielectric material (e.g., polysilicon) to modify the mechanical properties (e.g., hardness and / or stress) of the insulating structure 130.

[0045] Furthermore, as described in detail below, since the openings for forming the insulating structure 130 are not used to form the doped semiconductor layer 122 and the doped portion 128a of the semiconductor channel 128, an increase in the aspect ratio of the openings as the number of alternately arranged stacked conductive layers 116 and stacked dielectric layers 118 increases (for example, greater than 50) does not affect the formation of the doped semiconductor layer 122 and the doped portion 128a of the semiconductor channel 128.

[0046] Instead of front-side source contacts, the 3D memory device 100 may include one or more back-side source contacts 132 above the doped semiconductor layer 122 and in contact with the doped semiconductor layer 122, as shown in Figure 1A. The source contacts 132 and the memory stack 114 (and the insulating structure 130 through which it passes) may be located on the opposite side of the packing layer 120 and thus may be viewed as "back-side" source contacts. In some implementations, the source contacts 132 are electrically connected to the semiconductor channels 128 of the channel structure 124 through the doped semiconductor layer 122. The source contacts 132 may include any suitable type of contact. In some implementations, the source contacts 132 include VIA contacts. In some implementations, the source contacts 132 include laterally extending wall-shaped contacts. The source contact portion 132 may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., titanium nitride (TiN)).

[0047] As shown in Figure 1A, the 3D memory device 100 may further include a BEOL interconnect layer 133 that is electrically connected to the source contact 132 above the source contact 132 for pad-out (for example, to transfer electrical signals between the 3D memory device 100 and an external circuit). In some implementations, the interconnect layer 133 includes one or more ILD layers 134 on a doped semiconductor layer 122 and a redistribution layer 136 on the ILD layers 134. The upper end of the source contact 132 is coplanar with the upper surface of the ILD layer 134 and the bottom surface of the redistribution layer 136, and the source contact 132 extends vertically through the ILD layers 134 to contact the doped semiconductor layer 122, according to some implementations. The ILD layers 134 in the interconnect layer 133 may include, but are not limited to, dielectric materials including silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The redistribution layer 136 within the interconnection layer 133 may contain conductive materials, but are not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In some implementations, the interconnection layer 133 further includes a passivation layer 138 as the outermost layer for passivation and protection of the 3D memory device 100. A portion of the redistribution layer 136 may be exposed from the passivation layer 138 as a contact pad 140. That is, the interconnection layer 133 of the 3D memory device 100 may also include a contact pad 140 for wire bonding and / or bonding with an interposer. In some implementations, as described below with respect to the manufacturing process, the source contact portion 132 and the redistribution layer 136 may be formed by the same process and have the same material (e.g., Al). Thus, the source contact portion 132 may, in some examples, also be seen as part of the BEOL interconnection layer 133.

[0048] In some implementations, the second semiconductor structure 104 of the 3D memory device 100 further includes contact portions 142 and 144 extending through the doped semiconductor layer 122 and the packed layer 120. Since the doped semiconductor layer 122 may contain polysilicon, the contact portions 142 and 144 are through-silicon contacts (TSCs) according to some implementations. In some implementations, the contact portion 142 extends through the doped semiconductor layer 122, the packed layer 120, and the ILD layer 134 and is in contact with the redistribution layer 136, so that the doped semiconductor layer 122 is electrically connected to the contact portion 142 through the source contact portion 132 of the interconnection layer 133 and the redistribution layer 136. In some implementations, the contact portion 144 extends through the doped semiconductor layer 122, the packed layer 120, and the ILD layer 134 and is in contact with the contact pad 140. The contact portions 142 and 144 may each include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., tin). In some mounting configurations, at least the contact portion 144 further includes a spacer (e.g., a dielectric layer) to electrically isolate the contact portion 144 from the doped semiconductor layer 122 and the packing layer 120.

[0049] In some implementations, the 3D memory device 100 further includes peripheral contacts 146 and 148 that extend vertically outside the memory stack 114, respectively. Each peripheral contact 146 or 148 has a depth greater than the depth of the memory stack 114 and can extend vertically from the bonding layer 112 to the packing layer 120 in the peripheral region outside the memory stack 114. In some implementations, the peripheral contact 146 is located below and in contact with the contact 142, so that the doped semiconductor layer 122 is electrically connected to the peripheral circuit 108 in the first semiconductor structure 102 through at least the source contact 132, the redistribution layer 136, the contact 142, and the peripheral contact 146. In some implementations, the peripheral contact portion 148 is located below the contact portion 144 and is in contact with the contact portion 144, so that the peripheral circuit 108 in the first semiconductor structure 102 is electrically connected to the contact pad 140 for pad-out, at least through the contact portion 144 and the peripheral contact portion 148. The peripheral contact portions 146 and 148 may each include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

[0050] As shown in Figure 1A, the 3D memory device 100 also includes various local contacts (also known as "C1") as part of the interconnect structure, which are in direct contact with the structures in the memory stack 114. In some implementations, the local contacts include channel local contacts 150, each located below and in contact with the lower end of each channel structure 124. Each channel local contact 150 can be electrically connected to a bit line contact (not shown) for bit line fan-out. In some implementations, the local contacts further include word line local contacts 152, each located below and in contact with each stack conductive layer 116 (including the word line) in the stepped structure of the memory stack 114 for word line fan-out. Local contacts (e.g., channel local contacts 150 and wordline local contacts 152) can be electrically connected to peripheral circuits 108 of the first semiconductor structure 102 through at least bonding layers 112 and 110. Each local contact (e.g., channel local contacts 150 and wordline local contacts 152) may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

[0051] An exemplary 3D memory device 100 is shown in Figure 1A, but it will be understood that any other suitable architecture of a 3D memory device may be applicable in this disclosure without further detail by changing the relative positions of the first and second semiconductor structures 102 and 104, the use of the back-side source contact portion 132 or a known front-side source contact portion (not shown), and / or the pad-out location (for example, through the first semiconductor structure 102 and / or the second semiconductor structure 104).

[0052] Figure 1B illustrates a cross-sectional side view of another exemplary 3D memory device 160 according to several embodiments of the present disclosure. The 3D memory device 160 is similar to the 3D memory device 100, except for a different structure at the upper edges of the doped semiconductor layer 122 and the capping layer 127. It will be understood that details of other identical structures in both the 3D memory devices 160 and 100 are not repeated for the sake of clarity.

[0053] As shown in Figure 1B, the doped semiconductor layer 122 does not include any plugs (e.g., plug 123 in Figure 1A) extending into the channel structure 124, according to some embodiments. That is, in some embodiments, the entire doped semiconductor layer 122 can be viewed as a plate 121. Without the plugs 123 extending into the channel structure 124, the capping layer 127 of the channel structure 124 can completely fill the channel holes and thus extend beyond the memory stack 114 in a first direction (e.g., the positive y direction in Figure 1B) and in contact with the doped semiconductor layer 122. That is, the upper edges of the memory film 126, the semiconductor channel 128, and the capping layer 127 can be coplanar with each other and in contact with the doped semiconductor layer 122. As a result, in some embodiments, the channel structure 124 extends beyond the memory stack 114 in a first direction (for example, the positive y direction in Figure 1B) and is in contact with the doped semiconductor layer 122.

[0054] Figure 7 illustrates a block diagram of an exemplary system 700 having a 3D memory device according to several aspects of the present disclosure. System 700 can be a mobile phone, desktop computer, laptop computer, tablet, vehicle computer, gaming console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage within it. As shown in Figure 7, system 700 can include a host 708 and a memory system 702, the memory system 702 having one or more 3D memory devices 704 and a memory controller 706. The host 708 can be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 708 can be configured to send data to or receive data from the 3D memory device 704.

[0055] The 3D memory device 704 can be any 3D memory device disclosed herein (for example, 3D memory devices 100 and 160 shown in Figures 1A and 1B). In some implementations, each 3D memory device 704 includes NAND flash memory. Consistent with the scope of this disclosure, the semiconductor channels of the 3D memory device 704 can be partially doped, with some portions of the semiconductor channels forming the source contacts remaining undoped or being highly doped to reduce the potential barrier, while other portions of the semiconductor channels forming memory cells remain undoped or less doped. One end of each channel structure of the 3D memory device 704 can be opened from the back side to expose the doped portion of each semiconductor channel. The 3D memory device 704 may further include a doped semiconductor layer that electrically connects the exposed doped portions of the semiconductor channels to further reduce contact resistance and sheet resistance. As a result, the electrical performance of the 3D memory device 704 can be improved, which in turn improves the performance of the memory systems 702 and 700, for example, by achieving higher operating speeds.

[0056] The memory controller 706 is connected to the 3D memory device 704 and the host 708, and is configured to control the 3D memory device 704 according to some implementations. The memory controller 706 can manage the data stored in the 3D memory device 704 and communicate with the host 708. In some implementations, the memory controller 706 is designed to operate in low-duty-cycle environments, such as in Secure Digital (SD) cards, CompactFlash® (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some implementations, the memory controller 706 is designed to operate in high-duty-cycle environments, such as in SSDs or embedded multimedia cards (eMMCs) used as data storage and enterprise storage arrays for mobile devices (e.g., smartphones, tablets, laptop computers, etc.). The memory controller 706 can be configured to control the operation of the 3D memory device 704 (e.g., read operations, erase operations, and program operations). Furthermore, the memory controller 706 can be configured to manage various functions relating to data stored or to be stored in the 3D memory device 704 (including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.). In some implementations, the memory controller 706 is further configured to handle error correction codes (ECC) relating to data read from or written to the 3D memory device 704. Any other suitable functions can be similarly performed by the memory controller 706, for example, forming the 3D memory device 704. The memory controller 706 can communicate with an external device (e.g., host 708) according to a specific communication protocol.For example, the memory controller 706 can communicate with external devices through at least one of various interface protocols (e.g., USB protocol, MMC protocol, Peripheral Component Interconnection (PCI) protocol, PCI-express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.).

[0057] The memory controller 706 and one or more 3D memory devices 704 can be integrated into various types of storage devices, for example, in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). In other words, the memory system 702 can be implemented and packaged in different types of end electronic products. In one example, as shown in Figure 8A, the memory controller 706 and a single 3D memory device 704 can be integrated into a memory card 802. The memory card 802 can include PC cards (PCMCIA, International Association for Personal Computer Memory Cards), CF cards, SmartMedia (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 802 may further include a memory card connector 804 that electrically connects the memory card 802 to a host (e.g., host 708 in Figure 7). In another example, as shown in Figure 8B, the memory controller 706 and multiple 3D memory devices 704 can be integrated into an SSD 806. The SSD 806 may further include an SSD connector 808 that electrically connects the SSD 806 to a host (for example, the host 708 in Figure 7). In some implementations, the storage capacity and / or operating speed of the SSD 806 is greater than that of the memory card 802.

[0058] Figures 3A–3O illustrate the manufacturing process for forming exemplary 3D memory devices in several implementations of the Disclosure. Figure 5 illustrates a flowchart of Method 500 for forming exemplary 3D memory devices in several implementations of the Disclosure. Examples of 3D memory devices depicted in Figures 3A–3O and Figure 5 include the 3D memory device 100 depicted in Figure 1A. Figures 3A–3O and Figure 5 will be explained together. It should be understood that the operations shown in Method 500 are not exhaustive, and that other operations can be performed before, after, or in between any of the illustrated operations. Furthermore, some of the operations can be performed simultaneously or in a different order than that shown in Figure 5.

[0059] Referring to Figure 5, Method 500 begins in Operation 502, in which peripheral circuits are formed on a first substrate. The first substrate can be a silicon substrate. As illustrated in Figure 3G, multiple transistors are formed on the silicon substrate 350 using multiple processes, including, but not limited to, photolithography, etching, thin film deposition, thermal expansion, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some implementations, doped regions (not shown) are formed in the silicon substrate 350 by ion implantation and / or thermal diffusion, which function, for example, as source and / or drain regions of the transistor. In some implementations, isolation regions (e.g., STI) are also formed in the silicon substrate 350 by wet etching and / or dry etching and thin film deposition. It is possible to form peripheral circuits 352 on the silicon substrate 350.

[0060] As illustrated in Figure 3G, a bonding layer 348 is formed above the peripheral circuit 352. The bonding layer 348 includes bonding contacts that are electrically connected to the peripheral circuit 352. To form the bonding layer 348, an ILD layer is deposited using one or more thin-film deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof; the bonding contacts through the ILD layer are formed using wet etching and / or dry etching (e.g., reactive ion etching (RIE)), followed thereby by one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0061] Method 500 proceeds to operation 504, as illustrated in Figure 5, in which a packing layer is formed above the second substrate and a stack structure is formed above the packing layer. The packing layer and stack structure can be formed on the front side of the second substrate on which a semiconductor device may be formed. The second substrate can be a silicon substrate. Since the second substrate will be removed from the final product, it is understood that the second substrate can be part of a dummy wafer (e.g., a carrier substrate) made from any suitable material (to name a few, glass, sapphire, plastic, silicon, etc.) in order to reduce the cost of the second substrate. In some packaging configurations, the substrate is a carrier substrate. In some packaging configurations, the packing layer includes polysilicon, a high-k dielectric, or a metal, and the stack structure includes a dielectric stack having alternating stack dielectric layers and a stack sacrificial layer. In some examples, it is understood that the stack structure can include a memory stack having alternating stack dielectric layers (e.g., silicon oxide layers) and a stack conductive layer (e.g., polysilicon layers).

[0062] Various stop layers can be formed between the second substrate and the packing layer to better control the gauging and surface flatness of the various structures to be formed on the second substrate. In some configurations, a first stop layer and a second stop layer are formed sequentially between the second substrate and the packing layer. The first stop layer may contain silicon oxide or silicon nitride, and the second stop layer may contain silicon oxide or polysilicon. In some configurations, a third stop layer (e.g., a silicon nitride layer or a polysilicon layer) is formed between the second stop layer and the packing layer. In some configurations, a single stop layer (e.g., a silicon oxide layer or a high-k dielectric layer) is formed between the second substrate and the packing layer.

[0063] As illustrated in Figure 3A, a first stop layer 303 is formed above the carrier substrate 302, a second stop layer 304 is formed on top of the first stop layer 303, and a packing layer 306 is formed on top of the second stop layer 304. The packing layer 306 can contain polysilicon, a high-k dielectric, or a metal. The second stop layer 304 can act as an etching stop layer when etching the channel holes from the front side, and therefore can contain any suitable material that has high etching selectivity (e.g., greater than about 5) with respect to the material on top of the second stop layer 304 (e.g., silicon oxide or polysilicon). The first stop layer 303 can act as a CMP / etching stop layer when removing the carrier substrate 302 from the back side, and therefore can contain any suitable material other than the material of the carrier substrate 302 (e.g., silicon nitride or silicon oxide). In some examples, it is understood that a pad oxide layer (e.g., a silicon oxide layer) is formed between the carrier substrate 302 and the first stop layer 303, which can relieve stress between different layers and prevent delamination.

[0064] As shown in Figure 3A, the stack of silicon oxide layers (pad oxide layer), silicon nitride layer (first stop layer 303), and silicon oxide layer (second stop layer 304) can be sequentially formed on the carrier substrate 302 using one or more thin-film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some packaging configurations, the packing layer 306 is formed by depositing polysilicon or any other suitable material (e.g., high-k dielectric or metal) on the second stop layer 304 using one or more thin-film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. For ease of explanation, the stop layer combination shown in Figure 3A is used throughout this disclosure to illustrate the fabrication process. However, it will be understood that any other suitable combination of stop layers can also be used in other examples. In examples not shown, a single oxide layer or high-k dielectric layer (as the first and second stop layers 303 and 304) can be formed on the carrier substrate 302 using one or more thin-film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0065] As illustrated in Figure 3B, a dielectric stack 308 is formed on a packing layer 306, comprising a plurality of pairs of first dielectric layers (referred herein to as “stack sacrificial layers” 312) and second dielectric layers (referred herein to as “stack dielectric layers” 310; both referred herein to as “dielectric layer pairs”). The dielectric stack 308 comprises alternating stack sacrificial layers 312 and stack dielectric layers 310, according to some implementation configurations. The stack dielectric layers 310 and stack sacrificial layers 312 can be formed alternately on the packing layer 306 above the carrier substrate 302 to form the dielectric stack 308. In some implementation configurations, each stack dielectric layer 310 comprises a layer of silicon oxide, and each stack sacrificial layer 312 comprises a layer of silicon nitride. The dielectric stack 308 can be formed by one or more thin-film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. As illustrated in Figure 3B, a stepped structure can be formed on the edge of the dielectric stack 308. The stepped structure can be formed by performing multiple so-called "trim etching" cycles on the dielectric layer pairs of the dielectric stack 308 toward the carrier substrate 302. Due to the repeated trim etching cycles applied to the dielectric layer pairs of the dielectric stack 308, the dielectric stack 308 can have one or more inclined edges and upper dielectric layer pairs that are shorter than those at the bottom, as shown in Figure 3B.

[0066] Method 500 proceeds to operation 506, as illustrated in Figure 5, in which a channel structure is formed that extends vertically through the dielectric stack and the packing layer. The channel structure may include a memory film and a semiconductor channel. In some implementations, to form the channel structure, a channel hole is formed that extends vertically through the dielectric stack and the packing layer, stopping at a second stop layer, and the memory film, semiconductor channel, and capping layer are formed sequentially within the channel hole.

[0067] As illustrated in Figure 3B, each channel hole is an opening that extends vertically through the dielectric stack 308 and the packing layer 306, stopping at a second stop layer 304. In some implementations, multiple openings are formed, each opening serving as a location for growing individual channel structures 314 in a later process. In some implementations, the fabrication process for forming the channel holes of the channel structures 314 includes wet etching and / or dry etching (e.g., deep RIE (DRIE)). Etching of the channel holes continues, according to some implementations, until it is stopped by a second stop layer 304 (e.g., silicon oxide or polysilicon). In some implementations, etching conditions (e.g., etching rate and time) can be controlled to ensure that each channel hole reaches and stops at the second stop layer 304 in order to minimize gouging variation between the channel holes and the channel structures 314 formed therein. Depending on the specific etching selectivity, one or more channel holes may extend to a small extent into the second stop layer 304, which will still be seen in this disclosure as being stopped by the second stop layer 304.

[0068] As illustrated in Figure 3B, a memory film comprising a blocking layer 317, a storage layer 316, and a tunneling layer 315, as well as a semiconductor channel 318, are formed sequentially along the sidewall and bottom surfaces of the channel hole in this order. In some implementation configurations, the blocking layer 317, the storage layer 316, and the tunneling layer 315 are first deposited along the sidewall and bottom surfaces of the channel hole in this order using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to form the memory film. The semiconductor channel 318 can then be formed by depositing a semiconductor material (e.g., polysilicon (e.g., undoped polysilicon)) on top of the tunneling layer 315 using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). In several implementation configurations, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer ("SONO" structure) are sequentially deposited to form a blocking layer 317, a storage layer 316, a tunneling layer 315, and a semiconductor channel 318 of the memory film.

[0069] As illustrated in Figure 3B, a capping layer 319 is formed inside and on top of the semiconductor channel 318 to completely or partially fill the channel hole (e.g., with or without an air gap). The capping layer 319 can be formed by depositing a dielectric material (e.g., silicon oxide) using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). The channel plug can then be formed inside the upper portion of the channel hole. In some configurations, a portion of the memory film, semiconductor channel 318, and capping layer 319 on the upper surface of the dielectric stack 308 is removed and planarized by CMP, wet etching, and / or dry etching. The recess can then be formed inside the upper portion of the channel hole by wet etching and / or dry etching the semiconductor channel 318 and portion of the capping layer 319 inside the upper portion of the channel hole. Next, the channel plug can be formed by depositing a semiconductor material (e.g., polysilicon) into the recess by one or more thin-film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof). Thereafter, the channel structure 314 is formed through a dielectric stack 308 and a packing layer 306, according to some implementation configurations, and it stops at a second stop layer 304.

[0070] As illustrated in Figure 3C, the slit 320 is an opening that extends vertically through the dielectric stack 308 and terminates in the packed layer 306. In some implementation configurations, the fabrication process for forming the slit 320 includes wet etching and / or dry etching (e.g., DRIE). Gate replacement is then performed through the slit 320, allowing the dielectric stack 308 to be replaced with the memory stack 330 (shown in Figure 3E).

[0071] As illustrated in Figure 3D, the lateral recesses 322 are initially formed by removing the stack sacrificial layer 312 (shown in Figure 3C) through the slit 320. In some implementations, the stack sacrificial layer 312 is removed by applying an etching solution through the slit 320, creating alternating lateral recesses 322 between the stack dielectric layers 310. The etching solution can include any suitable etching solution that selectively etches the stack sacrificial layer 312 relative to the stack dielectric layers 310.

[0072] As illustrated in Figure 3E, the stacked conductive layer 328 (including the gate electrode and adhesive layer) is deposited through the slit 320 into the lateral recess 322 (shown in Figure 3D). In some configurations, the gate dielectric layer 332 is deposited in the lateral recess 322 before the stacked conductive layer 328, so that the stacked conductive layer 328 is deposited on top of the gate dielectric layer 332. The stacked conductive layer 328 (e.g., a metal layer) can be deposited using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). In some configurations, the gate dielectric layer 332 (e.g., a high-k dielectric layer) is similarly formed along the sidewalls and bottom of the slit 320. This forms a memory stack 330 including alternating stacked conductive layers 328 and stacked dielectric layers 310, which, according to some configurations, replaces the dielectric stack 308 (shown in Figure 3D).

[0073] As illustrated in Figure 3E, an insulating structure 336 is formed that extends vertically through the memory stack 330, terminating at the upper surface of the packing layer 306. The insulating structure 336 is formed by depositing one or more dielectric materials (e.g., silicon oxide) into the slit 320, and it is possible to completely or partially fill the slit 320 (e.g., with or without an air gap) using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). In some implementations, the insulating structure 336 includes a gate dielectric layer 332 (e.g., including a high-k dielectric) and a dielectric capping layer 334 (e.g., including silicon oxide). In some embodiments, the dielectric capping layer 334 is capable of partially filling the slit 320, and a polysilicon core layer 335, as part of the insulating structure 336, is capable of filling the remaining space in the slit 320 and modifying the mechanical properties of the insulating structure 336 (e.g., hardness or stress).

[0074] As illustrated in Figure 3F, after the formation of the insulating structure 336, local contacts (including channel local contacts 344 and word line local contacts 342, as well as peripheral contacts 338 and 340) are formed. Local dielectric layers can be formed on the memory stack 330 by depositing a dielectric material (e.g., silicon oxide or silicon nitride) on the memory stack 330 using one or more thin-film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof). Channel local contacts 344, word line local contacts 342, and peripheral contacts 338 and 340 can be formed by etching the contact openings through the local dielectric layer (and any other ILD layer) using wet etching and / or dry etching (e.g., RIE), followed by filling the contact openings with a conductive material using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0075] As illustrated in Figure 3F, the bonding layer 346 is formed above the channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340. The bonding layer 346 includes bonding contacts electrically connected to the channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340. To form the bonding layer 346, the ILD layer is deposited using one or more thin film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof), and the bonding contacts are formed through the ILD layer by wet etching and / or dry etching (e.g., RIE), followed thereby by one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0076] Method 500 proceeds to operation 508, as illustrated in Figure 5, in which the first and second substrates are bonded in a facing configuration, with the memory stack above the peripheral circuitry. Bonding can include hybrid bonding. As illustrated in Figure 3G, the carrier substrate 302 and the components formed thereon (e.g., the memory stack 330 and the channel structure 314 formed through it) are inverted. According to some implementations, a downward-facing bonding layer 346 is bonded to an upward-facing bonding layer 348, i.e., bonded in a facing configuration, thereby forming a bonding interface 354 between the carrier substrate 302 and the silicon substrate 350. In some implementations, processing steps (e.g., plasma treatment, wet treatment, and / or heat treatment) are applied to the bonding surface before bonding. After bonding, the bonding contacts in bonding layer 346 and bonding contacts in bonding layer 348 are aligned and in contact with each other, so that the memory stack 330 and the channel structure 314 formed through it can be electrically connected to the peripheral circuit 352 and are located above the peripheral circuit 352.

[0077] Method 500 proceeds to operation 510, as illustrated in Figure 5, in operation 510, a portion of the channel structure extending beyond the second substrate and the packing layer is sequentially removed, exposing a portion of the semiconductor channel. The removal can be performed from the back side of the second substrate. As shown in Figure 6, in some mounting configurations, in 602, the second substrate is removed to sequentially remove the second substrate and a portion of the channel structure, stopping at the first stop layer; in 604, the first stop layer is removed, stopping at the second stop layer; and in 606, the second stop layer and a portion of the channel structure are removed, stopping at the packing layer. In some mounting configurations, the removed portion of the channel structure extends into the second stop layer, and the second stop layer and the portion of the channel structure extending into the second stop layer are polished. As shown in Figure 6, in some embodiments, at 608, a portion of the capping layer of the channel structure is etched back to form a recess surrounded by a portion of the semiconductor channel.

[0078] As illustrated in Figure 3H, the carrier substrate 302 (and the pad oxide layer between the carrier substrate 302 and the first stop layer 303, as shown in Figure 3G) is completely removed from the backside until it is stopped by the first stop layer 303 (e.g., a silicon nitride layer). The carrier substrate 302 can be completely removed using CMP, grinding, dry etching, and / or wet etching. In some mounting configurations, the carrier substrate 302 is peeled off. In some mounting configurations where the carrier substrate 302 contains silicon and the first stop layer 303 contains silicon nitride, the carrier substrate 302 can be removed using silicon CMP, which can be stopped automatically when it reaches the first stop layer 303 having a material other than silicon (i.e., acting as a backside CMP stop layer). In some mounting configurations, the carrier substrate 302 (silicon substrate) is removed using wet etching with tetramethylammonium hydroxide (TMAH), which automatically stops when it reaches a first stop layer 303 having a material other than silicon (i.e., it acts as a backside etching stop layer). The first stop layer 303 can ensure the complete removal of the carrier substrate 302 without concerns about thickness uniformity after thinning.

[0079] As shown in Figure 3I, the first and second stop layers 303 and 304 (shown in Figure 3H) can then be similarly completely removed using wet etching with a suitable etching solution (e.g., phosphoric acid and hydrofluoric acid) until they are stopped by a packing layer 306 having a different material (e.g., polysilicon) than the second stop layer 304. As shown in Figure 3I, a portion of the channel structure 314 extending beyond the packing layer 306 is removed so that the upper end of the channel structure 314 is coplanar with the upper surface of the packing layer 306. In some embodiments where a portion of the channel structure 314 extends into the second stop layer 304, the second stop layer 304 and the portion of the channel structure 314 extending into the second stop layer 304 are removed together by polishing (e.g., CMP) until it stops in the packing layer 306. It is understood that if the channel structure 314 does not extend beyond the packed layer 306 into the second stop layer 304, the removal of the upper end of the channel structure 314 may be skipped.

[0080] As illustrated in Figure 3J, a portion of the capping layer 319 is removed to form a recess 321 surrounded by the upper portion of the semiconductor channel 318. For example, a portion of the capping layer 319 of the channel structure 314 can be etched back to form the recess 321, for example, using dry etching and / or wet etching. In some examples, if the upper edge of the capping layer 319 is still covered by the semiconductor channel 318, a portion of the semiconductor channel 318 can be etched first to expose the capping layer 319. Etching of the capping layer 319 can be controlled by controlling the etching time and / or etching rate so that the etching does not continue beyond the source selection gate line (e.g., one or more stacked conductive layers 328 closest to the packing layer 306). Formation of the recess 321 can expose a portion of the semiconductor channel 318 surrounding the recess 321. In some implementations, the upper portion of the semiconductor channel 318 exposed by the recess 321 is doped to increase its conductivity. For example, the gradient ion implantation process can be carried out to dope the upper portion of the semiconductor channel 318 (e.g., including polysilicon) exposed by the recess 321 with any suitable dopant (e.g., an N-type dopant such as P, As, or Sb) to a desired doping concentration.

[0081] Removing a portion of the channel structure 314 from the back side is far less difficult and yields a higher production yield compared to known solutions that use front-side wet etching through an opening (e.g., slit 320 in Figure 3D) through the dielectric stack 308 / memory stack 330 having a high aspect ratio (e.g., greater than 50). By avoiding the problems introduced by the high aspect ratio of slit 320, it is possible to reduce the complexity and cost of fabrication and increase the yield. Vertical scalability (e.g., increasing the level of the dielectric stack 308 / memory stack 330) can also be improved.

[0082] Method 500 proceeds to operation 512, as illustrated in Figure 5, in operation 512, a doped semiconductor layer is formed in contact with the exposed portion of the semiconductor channel. In some implementations, the dopant includes an N-type dopant. In some implementations, as shown in Figure 6, to form a doped semiconductor layer, in 610, a layer of polysilicon is deposited into the recess and on top of the packing layer; in 612, the deposited layer of polysilicon is doped.

[0083] As illustrated in Figure 3K, a doped semiconductor layer 360 is formed in a recess 321 (shown in Figure 3J), which is surrounded and in contact with (and thus surrounded by) an exposed portion of the semiconductor channel 318 and the outside of the recess 321 above the packing layer 306. In some implementation configurations, to form the doped semiconductor layer 360, a semiconductor layer (e.g., polysilicon) is deposited in the recess 321 in contact with an exposed portion of the semiconductor channel 318 and the capping layer 319, and also deposited outside the recess 321 in contact with the packing layer 306, using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). The deposited semiconductor layer can be doped with an N-type dopant (e.g., P, As, or Sb) using ion implantation and / or thermal diffusion. In some implementations, in situ doping with an N-type dopant (e.g., P, As, or Sb) is performed when depositing the semiconductor layer into the recess 321 and on top of the packing layer 306 to form a doped semiconductor layer 360. In some implementations, a CMP process can be performed to remove any excess doped semiconductor layer 360 as needed.

[0084] Method 500 proceeds to operation 514, as illustrated in Figure 5, in which a doped semiconductor layer and a portion of the semiconductor channel in contact with the doped semiconductor layer are locally activated. In some implementations, heat is applied to a confined area having the doped semiconductor layer and portion of the semiconductor channel to activate the dopants in the doped semiconductor layer and portion of the semiconductor channel for local activation. The confined area can be located between the stack structure and the doped semiconductor layer. In some implementations, the doping concentration of the doped semiconductor layer and the doping concentration of the portion of the semiconductor channel in contact with the doped semiconductor layer are set to 10 after activation, respectively.19 cm -3 to 10 21 cm -3 is between.

[0085] As illustrated in FIG. 3L, the doped semiconductor layer 360 and a portion of the semiconductor channel 318 in contact with the doped semiconductor layer 360 are locally activated. In some implementations, heat is applied to a confined area comprising the doped semiconductor layer 360 and a portion of the semiconductor channel 318 to activate dopants therein (e.g., an N-type dopant (e.g., P, As, or Sb), etc.). For example, the confined area may be between the memory stack 330 and the doped semiconductor layer 360 in a vertical direction. Heat may be applied and focused by any suitable technique (e.g., annealing, laser, ultrasound, or any other suitable thermal process, etc.). In some implementations, the confined area, which may be affected by heat during the local activation process, does not extend to and beyond the bonding interface 354 to avoid heating the Cu interconnects used to connect the bonding interface 354 and the peripheral circuit 352. The local activation process is capable of activating doped dopants into the doped semiconductor layer 360 (and the exposed portion of the semiconductor channel 318 if the semiconductor channel 318 is already doped). As a result, the doping concentration of the doped semiconductor layer 360 and the doping concentration of the exposed portion of the semiconductor channel 318 are each 10 after activation 19 cm -3 to 10 21 cm -3It lies between these two points. In some implementations, the local activation process is controlled so that the dopant in the doped semiconductor layer 360 (and, if the semiconductor channel 318 is already doped, the exposed portion of the semiconductor channel 318) can diffuse from the source of the channel structure 314 towards the drain of the channel structure 314, as described above with respect to Figure 2, until it crosses the source selection gate line (e.g., one or more stacked conductive layers 328 closest to the packed layer 306), but without facing the word line. If a portion of the semiconductor channel 318 is not yet doped, the doped semiconductor layer 360 acts as a doping source during the local activation process, allowing the dopant to diffuse from the doped semiconductor layer 360 into the semiconductor channel 318, so that a portion of the semiconductor channel 318 in contact with the doped semiconductor layer 360 can become a doped portion, and so that the doped semiconductor layer 360 and the doped portion of the semiconductor channel 318 can have the same dopant and doping concentration.

[0086] The localized activation process can activate the dopant, allowing it to occupy the silicon lattice, reducing the contact resistance between the doped semiconductor layer 360 and the semiconductor channel 318, and also reducing the sheet resistance of the doped semiconductor layer 360. On the other hand, by confining the heat during the localized activation process to areas without thermal structures, any potential damage to thermal structures (e.g., bonding interface 354 and Cu interconnects used to connect peripheral circuits 352) can be reduced or avoided.

[0087] Method 500 proceeds to operation 516, as illustrated in Figure 5, in operation 516, a source contact is formed in contact with the doped semiconductor layer. As illustrated in Figure 3M, one or more ILD layers 356 are formed on the doped semiconductor layer 360. The ILD layers 356 can be formed by depositing dielectric material on the upper surface of the doped semiconductor layer 360 using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). As illustrated in Figure 3N, a source contact opening 358 can be formed through the ILD layer 356, exposing a portion of the doped semiconductor layer 360. In some configurations, the source contact opening 358 is formed using wet etching and / or dry etching (e.g., RIE).

[0088] As illustrated in Figure 3O, source contacts (as part of the conductive layer 370) are formed in each source contact opening 358 (shown in Figure 3N) on the backside of the packed layer 306. According to some configurations, the source contacts are located above and in contact with the doped semiconductor layer 360. In some configurations, the conductive layer 370 (e.g., Al) is deposited into the source contact openings 358 using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to fill the source contact openings 358. A planarization process (e.g., CMP) can then be performed to remove any excess conductive layer 370.

[0089] As illustrated in Figure 3O, in some implementation configurations, the conductive layer 370 also includes a redistribution layer, which is located above the source contact portion and in contact with the source contact portion. That is, according to some implementation configurations, the conductive layer 370 is not only deposited inside the source contact portion opening 358 as a source contact portion, but is also deposited on the outside of the source contact portion opening 358 on top of the ILD layer 356 as a redistribution layer that electrically connects multiple source contact portions.

[0090] As illustrated in Figure 3O, in some configurations, the conductive layer 370 further includes contact portions extending through the ILD layer 356, the doped semiconductor layer 360, and the packing layer 306. That is, the conductive layer 370 is deposited not only in the source contact opening 358 as a source contact portion, but also in the contact openings 363 and 361 (shown in Figure 3N) as contact portions electrically connected to the peripheral contact portions 338 and 340. As illustrated in Figures 3M and 3N, the contact openings 363 and 361 extending through the spacer layer 371, the ILD layer 356, the doped semiconductor layer 360, and the packing layer 306, respectively, are formed using wet etching and / or dry etching (e.g., RIE). In some configurations, the contact openings 363 and 361 are patterned using lithography so as to be aligned with the peripheral contact portions 338 and 340, respectively. Etching of the contact openings 363 and 361 can be stopped at the upper ends of the peripheral contacts 338 and 340 in order to expose the peripheral contacts 338 and 340. As illustrated in Figure 3N, a spacer 362 is formed from the spacer layer 371 along the side walls of the contact openings 363 and 361 to electrically isolate the doped semiconductor layer 360.

[0091] Figures 4A–4C illustrate a fabrication process for forming another exemplary 3D memory device according to several embodiments of the present disclosure. Examples of 3D memory devices depicted in Figures 4A–4C include the 3D memory device 160 depicted in Figure 1B. Unlike Figure 3J, where the recess 321 is formed by etching back the capping layer 319, as shown in Figure 4A, the upper portion of the semiconductor channel 318 is doped to increase its conductivity without first etching back the capping layer 319 to expose a portion of the semiconductor channel 318. For example, a gradient ion implantation process can be carried out to dope the upper portion of the semiconductor channel 318 (e.g., including polysilicon) to a desired doping concentration with any suitable dopant (e.g., an N-type dopant such as P, As, or Sb).

[0092] In some embodiments, to form a doped semiconductor layer, a layer of polysilicon is deposited on a packed layer, and the deposited polysilicon layer is doped. As shown in Figure 4B, the doped semiconductor layer 360 is formed on the packed layer 306 and on the upper end of the channel structure 314. In some packaging configurations, to form the doped semiconductor layer 360, a semiconductor layer (e.g., polysilicon) is deposited on the packed layer 306 using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). The deposited semiconductor layer can be doped with an N-type dopant (e.g., P, As, or Sb) using ion implantation and / or thermal diffusion. In some packaging configurations, in situ doping of an N-type dopant (e.g., P, As, or Sb) is performed when the semiconductor layer is deposited on the packed layer 306 to form the doped semiconductor layer 360. In some implementation configurations, a CMP process can be performed to remove any excess doped semiconductor layer 360 as needed.

[0093] As shown in Figure 4C, the doped portions of the doped semiconductor layer 360 and semiconductor channel 318 are locally activated. In some implementations, heat is applied to the confined area containing the doped portions of the doped semiconductor layer 360 and semiconductor channel 318, activating the dopants within it (e.g., N-type dopants (e.g., P, As, or Sb)). The local activation process makes it possible to activate the doped dopants within the doped portions of the doped semiconductor layer 360 and semiconductor channel 318. As a result, the doping concentration of the doped semiconductor layer 360 and the doping concentration of the doped portions of the semiconductor channel 318 are increased by 10 after activation, respectively. 19 cm -3 from 10 21 cm -3 It lies between these two states. In some implementations, the local activation process is controlled so that the dopants in the doped semiconductor layer 360 and the doped portion of the semiconductor channel 318 can diffuse from the source of the channel structure 314 to the drain of the channel structure 314, as described above with respect to Figure 2, until they cross the source selection gate line (e.g., one or more stacked conductive layers 328 closest to the packed layer 306), but without facing the word line.

[0094] According to one aspect of the present disclosure, a 3D memory device includes a stack structure comprising alternating conductive and dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer, the doped semiconductor layer comprising a plate and a plug extending from the plate into the channel structure. The channel structure comprises a memory film and a semiconductor channel. The semiconductor channel includes a doped portion, a portion of which extends beyond the stack structure in a first direction. The doped portion of the semiconductor channel surrounds the plug of the doped semiconductor layer.

[0095] In some implementation configurations, the doping concentration of the doped portion of the semiconductor channel and the doping concentration of the doped semiconductor layer are, respectively, 10 19 cm -3 from 10 21 cm -3 It is located between them.

[0096] In some implementations, the doped portion of the semiconductor channel and the doped semiconductor layer each contain N-type doped polysilicon.

[0097] In some implementations, the doped portion of the semiconductor channel and the plug of the doped semiconductor layer extend beyond one of the conductive layers in a second direction opposite to the first direction.

[0098] In some implementations, one of the conductive layers includes a source selection gate line.

[0099] In some implementations, the 3D memory device further includes a packing layer between the stack structure and the doped semiconductor layer plate.

[0100] In some implementation configurations, the packing layer includes polysilicon, a high-k dielectric, or a metal.

[0101] In some implementations, the 3D memory device further includes a source contact portion that is in contact with a doped semiconductor layer.

[0102] In some implementations, the memory film extends beyond the stack structure in a first direction and is in contact with the doped semiconductor layer plate.

[0103] In some implementations, the plugs in the doped semiconductor layer are configured to generate a GIDL-assisted body bias when an erase operation is performed.

[0104] According to another aspect of the present disclosure, a 3D memory device includes a stack structure comprising alternating conductive and dielectric layers, a doped semiconductor layer, and a channel structure extending through the stack structure. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion. The channel structure extends beyond the stack structure in a first direction and is in contact with the doped semiconductor layer. The semiconductor channel includes a doped portion extending beyond one of the conductive layers in a second direction opposite to the first direction.

[0105] In some implementation configurations, the doping concentration of the doped portion of the semiconductor channel and the doping concentration of the doped semiconductor layer are, respectively, 10 19 cm -3 from 10 21 cm -3 It is located between them.

[0106] In some implementations, the doped portion of the semiconductor channel and the doped semiconductor layer each contain N-type doped polysilicon.

[0107] In some implementations, one of the conductive layers includes a source selection gate line.

[0108] In some implementations, a portion of the doped semiconductor channel extends beyond the stack structure in a first direction and is in contact with the doped semiconductor layer.

[0109] In some implementations, the 3D memory device further includes a packing layer between the stack structure and the doped semiconductor layer.

[0110] In some implementation configurations, the packing layer includes polysilicon, a high-k dielectric, or a metal.

[0111] In some implementations, the 3D memory device further includes a source contact portion that is in contact with a doped semiconductor layer.

[0112] In some implementations, the channel structure further includes a capping layer that extends beyond the stack structure in a first direction and is in contact with the doped semiconductor layer.

[0113] In some implementations, the doped semiconductor layer is configured to generate a GIDL-assisted body bias when an erase operation is performed.

[0114] A method for forming a 3D memory device is provided according to yet another aspect of the present disclosure. A packing layer is formed on top of a substrate. A stack structure is formed on top of the packing layer. A channel structure is formed extending through the stack structure and the packing layer. The channel structure includes a memory film and a semiconductor channel. A portion of the channel structure extending beyond the substrate and the packing layer is successively removed to expose a portion of the semiconductor channel. A doped semiconductor layer is formed in contact with the exposed portion of the semiconductor channel. The doped semiconductor layer and the portion of the semiconductor channel in contact with the doped semiconductor layer are locally activated.

[0115] In some implementations, heat is applied to a confined area containing a doped semiconductor layer and a portion of the semiconductor channel to activate the dopants within the doped semiconductor layer and the portion of the semiconductor channel.

[0116] In some implementations, the confined area lies between the stack structure and the doped semiconductor layer.

[0117] In some implementations, the dopant includes an N-type dopant, and after activation, the doping concentration of the doped semiconductor layer and the doping concentration of a portion of the semiconductor channel in contact with the doped semiconductor layer are, respectively, 10 19 cm -3 from 10 21 cm -3 It is located between them.

[0118] In some implementations, the exposed portion of the semiconductor channel is doped before the doped semiconductor layer is formed.

[0119] In some mounting configurations, a first stop layer and a second stop layer are formed sequentially between the substrate and the filler layer.

[0120] In some implementation configurations, the first stop layer comprises silicon oxide or silicon nitride, the second stop layer comprises silicon oxide or polysilicon, and the packing layer comprises polysilicon, a high-k dielectric, or a metal.

[0121] In some implementation configurations, channel holes are formed to extend through the stack structure and packing layer to terminate at a second stop layer in order to form a channel structure, and a memory film, semiconductor channel, and capping layer are sequentially formed within the channel holes.

[0122] In some mounting configurations, to sequentially remove parts of the substrate and memory film, the substrate is removed, stopping at the first stop layer, the first stop layer is removed, stopping at the second stop layer, the second stop layer and part of the channel structure are removed, and stopping at the packing layer.

[0123] In some implementations, the removed portion of the channel structure extends into the second stop layer. In some implementations, the second stop layer and the portion of the channel structure extending into the second stop layer are polished in order to remove the second stop layer and the portion of the channel structure.

[0124] In some implementation configurations, to sequentially remove parts of the substrate and channel structure, a portion of the capping layer of the channel structure is etched back, forming a recess surrounded by a portion of the semiconductor channel.

[0125] In some implementation configurations, to form a doped semiconductor layer, a layer of polysilicon is deposited into the recesses and on top of the packing layer, and the deposited polysilicon layer is doped.

[0126] In some implementation configurations, a layer of polysilicon is deposited on a packed layer to form a doped semiconductor layer, and the deposited polysilicon layer is then doped.

[0127] In some implementation configurations, the doped semiconductor layer is locally activated, and then the source contact area is formed by contact with the doped semiconductor layer.

[0128] According to yet another aspect of the present disclosure, the system includes a 3D memory device configured to store data and a memory controller, the memory controller being coupled to the 3D memory device and configured to control the 3D memory device. The 3D memory device includes a stack structure comprising alternating conductive and dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer, the doped semiconductor layer comprising a plate and a plug extending from the plate into the channel structure. The channel structure comprises a memory film and a semiconductor channel. The semiconductor channel includes a doped portion, the portion of which extends beyond the stack structure in a first direction. The doped portion of the semiconductor channel surrounds the plug of the doped semiconductor layer.

[0129] In some implementations, the system further includes a host, which is coupled to a memory controller and configured to transmit or receive data.

[0130] The foregoing descriptions of specific implementations can be readily modified and / or adapted for various applications. Such adaptations and modifications are therefore intended to fall within the meaning and scope of the equivalents of the disclosed implementations, based on the teachings and guidance presented herein.

[0131] The scope and breadth of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely in accordance with the appended claims and their equivalents. [Explanation of Symbols]

[0132] 100 3D memory devices 101 circuit board 102 First Semiconductor Structure 104 Second Semiconductor Structure 106 Bonding Interface 108 Peripheral Circuits 110 Bonding layer 111 Bonding contact area 112 Bonding layer 113 Bonding contact area 114 Memory Stack 116 Stacked conductive layer 118 Stacked dielectric layer 120 Filled bed 121 Plate 122 Doped semiconductor layer 123 Plug 124-channel structure 126 Memory Film 127 Capping layer 128 semiconductor channels 128a Doped portion 128b Undoped portion 129 Channel Plug 130 Insulating Structure 132 Source contact area 133 Interconnection Layer 134 ILD layer 136 Redistribution Layer 138 Passivation Layer 140 contact pads 142 Contact area 144 Contact area 146 Peripheral contact area 148 Peripheral contact area 150 Channel Local Contact Section 152 Wordline local contact area 160 3D memory devices 201 Source Selection Gate Line 203 Wordline 302 Carrier substrate 303 First stop layer 304 Second stop layer 306 Filled bed 308 Dielectric Stack 310 Stacked dielectric layer 312 stack sacrifice layer 314 channel structure 315 Tunneling layer 316 storage tiers 317 Blocking Layer 318 Semiconductor Channels 319 Capping layer 320 slits 321 Recess 322 Lateral recess 328 Stacked conductive layer 330 memory stack 332 Gate dielectric layer 334 Dielectric capping layer 335 Polysilicon core layer 336 Insulating Structures 338 Peripheral contact area 340 Peripheral contact area 342 Wordline local contact area 344 Channel Local Contact Section 346 Bonding layer 348 Bonding layer 350 silicon substrates 352 Peripheral Circuits 354 Bonding Interface 356 ILD layer 358 Source contact opening 360 doped semiconductor layers 361 Contact opening 362 Spacers 363 Contact opening 370 Conductive layer 371 Spacer layer 700 System 702 memory system 704 3D memory device 706 Memory Controller 708 Host 802 Memory Card 804 Memory card connector 806 SSD 808 SSD connector

Claims

1. A stack structure comprising alternating arrangements of a first dielectric layer and a first conductive layer; In the first direction, the doped semiconductor layer on the stack structure and; A channel structure extending through the stack structure in the first direction, wherein the channel structure includes a memory film and a semiconductor channel surrounded by the memory film, the semiconductor channel includes a doped portion, the doped portion is connected to the doped semiconductor layer and extends through at least one of the first conductive layers; The packing layer between the stack structure and the doped semiconductor layer; Includes, A semiconductor device in which the doped portion extends further through the packed layer and is in contact with the doped semiconductor layer, the packed layer comprising polysilicon, a high dielectric constant (high k) dielectric, or a metal.

2. The semiconductor device according to claim 1, wherein the semiconductor channel further includes a first portion, the doped portion is between the first portion and the doped semiconductor layer, and the doping concentration of the doped portion of the semiconductor channel is higher than the doping concentration of the first portion of the semiconductor channel.

3. The doping concentration of the doped portion of the semiconductor channel and the doping concentration of the doped semiconductor layer are each 10 １９ cm －３ and 10 ２１ cm －３ A semiconductor device according to claim 1, which is between the above.

4. The semiconductor device according to claim 1, further comprising a source contact portion in contact with the doped semiconductor layer, wherein the doped semiconductor layer is between the source contact portion and the stack structure.

5. The first direction further includes a second dielectric layer and a second conductive layer on the doped semiconductor layer, wherein the second dielectric layer is between the second conductive layer and the doped semiconductor layer, and the source contact portion extends through the second dielectric layer and is in further contact with the second conductive layer. The semiconductor device according to claim 4, wherein the second conductive layer and the source contact portion are made of the same material.

6. The semiconductor device according to claim 5, further comprising a peripheral contact portion connected to the second conductive layer, wherein the peripheral contact portion extends beyond the stack structure in the first direction.

7. The semiconductor device according to claim 1, further comprising peripheral circuits, wherein the peripheral circuits are coupled to the stack structure, and the stack structure is located between the peripheral circuits and the semiconductor layer.

8. The semiconductor device according to claim 1, wherein the doped semiconductor layer includes a plate and a plug, the plate is on the stack structure and the plug, and the plug extends into the channel structure and is in contact with the doped portion.

9. The semiconductor device according to claim 8, wherein the plug extends beyond at least one of the first conductive layers and is surrounded by the memory film or the doped portion.

10. A stack structure comprising alternating arrangements of a first dielectric layer and a first conductive layer; A channel structure extending through the stack structure in a first direction, wherein the channel structure includes a memory film and a semiconductor channel surrounded by the memory film; A doped semiconductor layer comprising a plate and a plug, wherein the plate is on the stack structure and the plug in the first direction, and the plug extends into the channel structure and is in contact with the semiconductor channel; Semiconductor devices, including those mentioned above.

11. The semiconductor device according to claim 10, wherein the plug extends through at least one of the first conductive layers.

12. The semiconductor device according to claim 11, wherein the plug is surrounded by the memory film or the semiconductor channel.

13. The semiconductor device according to claim 10, further comprising a packing layer between the stack structure and the plate of the doped semiconductor layer, wherein the plug extends further through the packing layer, and the packing layer comprises polysilicon, a high dielectric constant (high k) dielectric, or a metal.

14. The semiconductor device according to claim 10, wherein the semiconductor channel includes a doped portion that is in contact with the plug.

15. The semiconductor device according to claim 14, wherein the doped portion extends through at least one of the first conductive layers.

16. A source contact portion in contact with the doped semiconductor layer, wherein the doped semiconductor layer is between the source contact portion and the stack structure, In the first direction, the second dielectric layer and the second conductive layer are on the doped semiconductor layer, It further includes, The second dielectric layer is located between the second conductive layer and the doped semiconductor layer, and the source contact portion extends through the second dielectric layer and is in further contact with the second conductive layer. The semiconductor device according to claim 10, wherein the second conductive layer and the source contact portion are made of the same material.

17. The semiconductor device according to claim 16, further comprising a peripheral contact portion connected to the second conductive layer, wherein the peripheral contact portion extends beyond the stack structure in the first direction.

18. The semiconductor device according to claim 10, further comprising a peripheral circuit, wherein the peripheral circuit is coupled to the stack structure, and the stack structure is between the peripheral circuit and the semiconductor layer.

19. A method for forming a semiconductor device, The step of forming a packed layer; The steps include: forming a stack structure on the packing layer; A step of forming a channel structure extending through the stack structure and the packed layer, wherein the channel structure includes a memory film and a semiconductor channel surrounded by the memory film, the semiconductor channel includes a doped portion, and the doped portion extends through at least one of the conductive layers; A step of forming a doped semiconductor layer, wherein the packed layer is between the doped semiconductor layer and the stack structure, and the doped portion is in contact with the doped semiconductor layer or the packed layer; Methods that include...

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