Semiconductor device and method for manufacturing same

Abstract

An SiC substrate (10) is doped with vanadium. A high electron mobility transistor (20) is formed on the SiC substrate (10). The SiC substrate (10) includes a first substrate (1) and a second substrate (2) formed on the first substrate (1). The vanadium concentration of the first substrate (1) is 1×1018cm-3 or more. The vanadium concentration of the second substrate (2) at an interface between the second substrate (2) and the high electron mobility transistor (20) is 1×1017cm-3 or less.

Description

Semiconductor device and manufacturing method thereof

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof.

[0002] In high electron mobility transistors (HEMTs), SiC substrates are used that are doped with dopants such as vanadium to introduce defects that provide semi-insulating properties (see, for example, Patent Document 1).

[0003] Japan Special Publication No. 2022-519825

[0004] In the HEMT manufacturing process, after the semiconductor layer is deposited on the substrate, the amount of warpage of the substrate is small when the substrate is thick. However, when the substrate is thinned, the amount of warpage of the substrate increases to an inappropriate level. Doping a SiC substrate with vanadium improves the elastic modulus, thereby reducing the amount of warpage of the substrate. However, increasing the vanadium concentration can cause the problem of current collapse.

[0005] The present disclosure has been made to solve the above-mentioned problems, and its object is to provide a semiconductor device and a manufacturing method thereof that can suppress current collapse while reducing the amount of warping of the substrate.

[0006] A semiconductor device according to the present disclosure includes a vanadium-doped SiC substrate and a high electron mobility transistor formed on the SiC substrate, the SiC substrate having a first substrate and a second substrate formed on the first substrate, and the vanadium concentration of the first substrate is 1×10 １８ cm －３ or more, and the vanadium concentration of the second substrate at the interface between the second substrate and the high electron mobility transistor is 1×10 １７ cm －３ The present invention is characterized by the following:

[0007] In the present disclosure, the vanadium concentration of the second substrate at the interface between the second substrate and the high electron mobility transistor is 1×10 １７ cm －３This makes it possible to suppress current collapse. In addition, the vanadium concentration of the second substrate on the high electron mobility transistor side is reduced, but the vanadium concentration of the first substrate is set to 1×10 or less. １８ cm －３ By doing so, the amount of warping of the substrate can be reduced.

[0008] It is a cross-sectional view showing a semiconductor device according to embodiment 1. It is a diagram showing the vanadium concentration of a SiC substrate according to embodiment 1. It is a diagram showing the vanadium concentration of a SiC substrate according to embodiment 2. It is a diagram comparing substrate warpage and current collapse between embodiment 1 and embodiment 2.

[0009] A semiconductor device and a manufacturing method thereof according to an embodiment will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and repeated description may be omitted.

[0010] 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. A SiC substrate 10 is doped with vanadium. A GaN-HEMT 20, which is a high electron mobility transistor, is formed on the SiC substrate 10. The SiC substrate 10 has a first substrate 1 and a second substrate 2 formed on the first substrate 1.

[0011] The GaN-HEMT 20 has a nucleation layer 3, a high resistance layer 4, a channel layer 5, and an electron supply layer 6 stacked in this order on a second substrate 2. The nucleation layer 3 is made of Al ｘ１ Ga ｙ１ In １－ｘ１－ｙ１ The high resistance layer 4 is made of AlN (0≦x1, y1≦1) and has a thickness of 5 to 100 nm. ｘ２ Ga ｙ２ In １－ｘ２－ｙ２ N (0≦x2, y2≦1) and has a thickness of 100 to 1000 nm. The high resistance layer 4 is doped with Fe, C, Mn, etc. The impurity concentration of the high resistance layer 4 is 1E+17 to 1E+19 cm －３ The channel layer 5 is Al ｘ３ Ga ｙ３ In １－ｘ３－ｙ３ The electron supply layer 6 is made of AlN (0≦x3, y3≦1) and has a thickness of 100 to 1000 nm. ｘ４ Gaｙ４ In １－ｘ４－ｙ４ N (0≦x4, y4≦1) and has a thickness of 1 to 50 nm. A gate electrode 7, a source electrode 8, and a drain electrode 9 are formed on the electron supply layer 6.

[0012] Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. First substrate 1 is manufactured by sublimation. Next, second substrate 2 is manufactured on first substrate 1 by CVD. In the CVD method, SiCl is used as a silicon source. ４ , SiH ４ , SiH ３ Cl, SiH ２ Cl ２ , SiHCl ３ , Si ２ H ６ , Si ３ H ８ , SiH ３ (CH ３ ), SiCl ３ (CH ３ ) and CH as a carbon source ４ , C ３ H ８ etc., as a vanadium source, VCl ３ , V[N(CH ３ ) ２ ] ４ etc., N as a carrier gas ２ , H ２ , Ar, He, etc. are used. The pressure is 5 to 100 kPa, and the temperature is 1000 to 1800°C.

[0013] Next, a nucleation layer 3, a channel layer 5, and an electron supply layer 6 are laminated in this order on the second substrate 2, and a gate electrode 7, a source electrode 8, and a drain electrode 9 are formed on the electron supply layer 6 to form the GaN-HEMT 20. After the GaN-HEMT 20 is formed, the first substrate 1 in wafer form is ground and polished from the backside to be thinned. The wafer is then divided into individual chips.

[0014] The thickness of the first substrate 1 is 300 to 500 μm before thinning and 10 to 50 μm after thinning. The thickness of the second substrate 2 is 10 to 50 μm. Therefore, the total thickness of the SiC substrate 10 before thinning is 310 to 550 μm; if it is thinner than this, it is prone to warping during processing, and if it is thicker, it becomes costly. The total thickness of the SiC substrate 10 after thinning is 20 to 100 μm.

[0015] 2 is a diagram showing the vanadium concentration of the SiC substrate according to the first embodiment. The vanadium concentration of the first substrate 1 is 1×10 １８ cm －３ From 1 x 10 １９ cm －３ On the other hand, the vanadium concentration of the second substrate 2 is constant at 0 to 1×10 １７ cm －３ In this way, the vanadium concentration of the SiC substrate 10 varies in the thickness direction, but the average vanadium concentration of the SiC substrate 10 is 1×10 １７ ~1 x 10 １９ cm －３ is.

[0016] The amount of warpage h of a wafer in which a semiconductor layer is epitaxially grown on a substrate is expressed by the following formula: where t is the film thickness of the substrate, t is the film thickness of the semiconductor layer, E is the elastic modulus of the substrate, E is the elastic modulus of the semiconductor layer, R is the wafer diameter, and ε is the in-plane strain. From this formula, it can be seen that the amount of warpage h can be reduced by increasing the elastic modulus E of the substrate.

[0017] Since the bond strength between vanadium and carbon is stronger than the bond strength between silicon and carbon, doping with vanadium increases the elastic modulus of the SiC substrate 10. Table 1 shows the results of theoretical calculations of the vanadium concentration and warpage of the substrate of the semiconductor device according to the first embodiment after thinning. When the vanadium concentration of the first substrate 1 is 1×10 １８ cm －３ It can be seen that the amount of warpage of the substrate is reduced by the above.

[0018] As described above, in this embodiment, the vanadium concentration of the second substrate 2 at the interface between the second substrate 2 and the GaN-HEMT 20 is set to 1×10１７ cm －３ This makes it possible to suppress current collapse. The vanadium concentration of the second substrate 2 at the interface is set to 1×10 or less. １６ cm －３ The current collapse can be further suppressed by the following.

[0019] In addition, the vanadium concentration in the second substrate 2 on the GaN-HEMT 20 side is reduced, but the vanadium concentration in the first substrate 1 is reduced to 1×10 １８ cm －３ or more, the average vanadium concentration in the entire SiC substrate 10 is 1×10 １７ ~1 x 10 １９ cm －３ This makes it possible to reduce the amount of warping of the substrate.

[0020] Furthermore, by manufacturing the second substrate 2 on the GaN-HEMT 20 side by the CVD method, defects such as threading dislocations in the second substrate 2 and the epitaxial layer of the GaN-HEMT 20 formed thereon can be suppressed.

[0021] Second Embodiment A semiconductor device according to a second embodiment differs from that according to the first embodiment in the way in which the vanadium concentration of the SiC substrate 10 varies in the thickness direction. FIG. 3 is a diagram showing the vanadium concentration of the SiC substrate according to the second embodiment. The vanadium concentration of the first substrate 1 is 1×10 １８ cm －３ From 1 x 10 １９ cm －３ The vanadium concentration of the second substrate 2 is constant at a constant value. On the other hand, the vanadium concentration of the second substrate 2 is equal to the vanadium concentration of the first substrate 1 at the interface between the first substrate 1 and the second substrate 2, and decreases continuously toward the GaN-HEMT 20. The change in the vanadium concentration of the second substrate 2 is not limited to a linear change as in pattern A, but may also change in a curved manner as in patterns B and C. Pattern B improves substrate warpage more than pattern A, and pattern C improves current collapse more than pattern A. The second substrate 2 is manufactured by a CVD method while reducing the amount of vanadium source gas.

[0022] Table 2 shows the results of theoretical calculations of the vanadium concentration and the amount of warpage of the substrate of the semiconductor device according to the second embodiment after thinning.

[0023] As in the first embodiment, the vanadium concentration of the second substrate 2 at the interface between the second substrate 2 and the GaN-HEMT 20 is set to 1×10 １７ cm －３ This makes it possible to suppress current collapse. In addition, the vanadium concentration of the first substrate 1 is set to 1×10 or less. １８ cm －３ By setting the average vanadium concentration of the SiC substrate 10 to 1×10 or more, １７ ~1 x 10 １９ cm －３ This makes it possible to reduce the amount of warping of the substrate.

[0024] 4 is a diagram comparing the substrate warpage and current collapse between the first embodiment and the second embodiment. When attempting to obtain the same current collapse, the average vanadium concentration of the Si substrate is higher in the second embodiment than in the first embodiment. Therefore, the second embodiment can reduce the substrate warpage.

[0025] Furthermore, in the second embodiment, the vanadium concentration in the second substrate 2 is continuously changed, so that defects in the second substrate 2 and the epitaxial layer of the GaN-HEMT 20 can be reduced more than in the first embodiment.

[0026] Since the polytypes of commonly used SiC substrates are 4H-SiC or 6H-SiC, the polytype of the first substrate 1 in the first and second embodiments is set to 4H-SiC or 6H-SiC in consideration of cost. On the other hand, it is preferable that the polytype of the second substrate 2 on the GaN-HEMT side is set to 3C-SiC, which has high thermal conductivity. This can improve heat dissipation. 3C-SiC can be manufactured by changing CVD conditions such as adjusting the carrier gas flow rate or lowering the growth temperature.

[0027] 1 First substrate, 2 Second substrate, 3 Nucleation layer, 4 High resistance layer, 5 Channel layer, 6 Electron supply layer, 7 Gate electrode, 8 Source electrode, 9 Drain electrode, 10 SiC substrate, 20 GaN-HEMT (High Electron Mobility Transistor)

Claims

1. a vanadium-doped SiC substrate; a high electron mobility transistor formed on the SiC substrate; The SiC substrate has a first substrate and a second substrate formed on the first substrate, The vanadium concentration of the first substrate is 1×10 １８ cm －３ That's all. The vanadium concentration of the second substrate at the interface between the second substrate and the high electron mobility transistor is 1×10 １７ cm －３ A semiconductor device characterized in that:

2. The vanadium concentration of the second substrate at the interface between the second substrate and the high electron mobility transistor is 1×10 １６ cm －３ 2. The semiconductor device according to claim 1, wherein:

3. The average vanadium concentration of the SiC substrate is 1×10 １７ ~1×10 １９ cm －３ 3. The semiconductor device according to claim 1, wherein

4. The vanadium concentration of the first substrate is 1×10 １８ ~1×10 １９ cm －３ 3. The semiconductor device according to claim 1, wherein

5. 3. The semiconductor device according to claim 1, wherein the vanadium concentration of the second substrate is equal to the vanadium concentration of the first substrate at the interface between the first substrate and the second substrate, and continuously decreases toward the high electron mobility transistor.

6. the polytype of the first substrate is 4H—SiC or 6H—SiC; 3. The semiconductor device according to claim 1, wherein the polytype of the second substrate is 3C-SiC.

7. A method for manufacturing the semiconductor device according to claim 1 or 2, comprising the steps of: A method for manufacturing a semiconductor device, comprising the steps of: manufacturing the second substrate by a CVD method.